Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	12677	1			T44	2		T71	4080		T15	2
alert[0x1]	6786	1			T6	713		T40	1		T15	1
alert[0x2]	8804	1			T39	13		T71	518		T15	1
alert[0x3]	8873	1			T15	1		T22	6		T277	1
alert[0x4]	4467	1			T3	1		T71	91		T48	1262
alert[0x5]	6174	1			T6	28		T47	15		T278	1
alert[0x6]	1584	1			T13	2		T6	1		T20	11
alert[0x7]	9140	1			T39	2		T44	1		T47	3
alert[0x8]	3738	1			T48	273		T22	57		T80	341
alert[0x9]	5697	1			T6	1		T191	1		T22	4
alert[0xa]	8353	1			T3	1		T14	1		T44	5
alert[0xb]	2265	1			T14	1		T71	49		T15	1
alert[0xc]	6412	1			T3	1		T71	19		T48	6
alert[0xd]	3009	1			T6	79		T48	35		T279	1
alert[0xe]	4093	1			T71	31		T47	164		T73	10
alert[0xf]	7982	1			T6	162		T224	35		T50	26
alert[0x10]	2735	1			T14	1		T71	159		T268	37
alert[0x11]	6947	1			T6	35		T21	14		T22	14
alert[0x12]	6438	1			T6	15		T14	1		T71	135
alert[0x13]	18121	1			T6	2		T278	1		T224	46
alert[0x14]	3655	1			T20	3		T44	1		T277	1
alert[0x15]	2851	1			T12	1		T20	2		T14	1
alert[0x16]	5594	1			T6	1		T14	1		T71	23
alert[0x17]	8086	1			T15	1		T21	49		T48	281
alert[0x18]	11540	1			T23	1		T280	1		T224	88
alert[0x19]	7968	1			T3	1		T71	28		T21	195
alert[0x1a]	3751	1			T21	355		T48	70		T22	1
alert[0x1b]	8506	1			T14	1		T21	14		T48	23
alert[0x1c]	9183	1			T44	236		T15	1		T21	13
alert[0x1d]	4568	1			T71	375		T21	55		T22	65
alert[0x1e]	5755	1			T14	2		T44	1		T15	1
alert[0x1f]	14966	1			T20	6		T71	25		T278	2
alert[0x20]	8080	1			T71	291		T47	17		T191	1
alert[0x21]	13299	1			T3	1		T71	363		T22	3
alert[0x22]	4857	1			T48	551		T224	32		T50	32
alert[0x23]	4696	1			T71	22		T15	2		T21	116
alert[0x24]	3981	1			T21	106		T47	34		T48	59
alert[0x25]	4401	1			T3	1		T20	2		T71	84
alert[0x26]	5255	1			T6	14		T21	42		T224	278
alert[0x27]	6825	1			T3	1		T6	1		T21	60
alert[0x28]	8205	1			T40	8		T44	2		T71	594
alert[0x29]	6628	1			T6	1		T21	8		T47	1547
alert[0x2a]	3996	1			T3	1		T6	2		T15	1
alert[0x2b]	4221	1			T71	781		T48	17		T277	1
alert[0x2c]	4042	1			T20	3		T71	78		T47	140
alert[0x2d]	4832	1			T20	25		T47	275		T48	13
alert[0x2e]	10166	1			T21	38		T47	11		T48	1425
alert[0x2f]	7499	1			T6	79		T20	4		T40	2
alert[0x30]	7597	1			T6	388		T71	811		T224	322
alert[0x31]	4433	1			T6	1		T47	261		T48	78
alert[0x32]	9682	1			T71	1326		T21	327		T48	5
alert[0x33]	3716	1			T13	18		T71	97		T278	1
alert[0x34]	6556	1			T12	1		T20	1		T15	1
alert[0x35]	9031	1			T6	3		T71	88		T191	1
alert[0x36]	6689	1			T6	5		T71	145		T48	20
alert[0x37]	13899	1			T14	1		T47	235		T268	2
alert[0x38]	8098	1			T21	16		T47	83		T48	26
alert[0x39]	4191	1			T6	7		T14	1		T48	144
alert[0x3a]	8874	1			T3	2		T6	206		T15	1
alert[0x3b]	5016	1			T6	15		T39	2		T44	10
alert[0x3c]	9813	1			T20	1		T71	45		T48	185
alert[0x3d]	5893	1			T71	89		T47	62		T191	1
alert[0x3e]	4298	1			T20	6		T44	3		T71	16
alert[0x3f]	5741	1			T6	3		T21	3		T47	3
alert[0x40]	2960	1			T6	24		T71	12		T15	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	89134	1			T12	2		T13	1		T6	109
class_i[0x1]	147517	1			T3	9		T6	27		T20	9
class_i[0x2]	31872	1			T3	1		T6	59		T20	41
class_i[0x3]	169665	1			T13	19		T6	1591		T40	8

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

437503

1

T12

2

T13

20

T6

1786

alert_ping_fail

685

1

T3

10

T14

13

T15

18

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	12666	1			T44	2		T71	4080		T21	1304
alert_integrity_fail	alert[0x1]	6774	1			T6	713		T40	1		T35	124
alert_integrity_fail	alert[0x2]	8794	1			T39	13		T71	518		T224	35
alert_integrity_fail	alert[0x3]	8866	1			T22	6		T26	7		T281	127
alert_integrity_fail	alert[0x4]	4462	1			T71	91		T48	1262		T50	36
alert_integrity_fail	alert[0x5]	6157	1			T6	28		T47	15		T79	2
alert_integrity_fail	alert[0x6]	1568	1			T13	2		T6	1		T20	11
alert_integrity_fail	alert[0x7]	9127	1			T39	2		T44	1		T47	3
alert_integrity_fail	alert[0x8]	3731	1			T48	273		T22	57		T80	341
alert_integrity_fail	alert[0x9]	5685	1			T6	1		T22	4		T224	140
alert_integrity_fail	alert[0xa]	8334	1			T44	5		T21	174		T47	52
alert_integrity_fail	alert[0xb]	2255	1			T71	49		T224	529		T50	1
alert_integrity_fail	alert[0xc]	6401	1			T71	19		T48	6		T22	34
alert_integrity_fail	alert[0xd]	3001	1			T6	79		T48	35		T26	347
alert_integrity_fail	alert[0xe]	4080	1			T71	31		T47	164		T73	10
alert_integrity_fail	alert[0xf]	7975	1			T6	162		T224	35		T50	26
alert_integrity_fail	alert[0x10]	2726	1			T71	159		T268	37		T224	21
alert_integrity_fail	alert[0x11]	6941	1			T6	35		T21	14		T22	14
alert_integrity_fail	alert[0x12]	6427	1			T6	15		T71	135		T47	20
alert_integrity_fail	alert[0x13]	18106	1			T6	2		T224	46		T26	375
alert_integrity_fail	alert[0x14]	3642	1			T20	3		T44	1		T224	682
alert_integrity_fail	alert[0x15]	2840	1			T12	1		T20	2		T224	10
alert_integrity_fail	alert[0x16]	5585	1			T6	1		T71	23		T48	42
alert_integrity_fail	alert[0x17]	8078	1			T21	49		T48	281		T268	2
alert_integrity_fail	alert[0x18]	11530	1			T224	88		T26	9		T35	171
alert_integrity_fail	alert[0x19]	7957	1			T71	28		T21	195		T47	157
alert_integrity_fail	alert[0x1a]	3744	1			T21	355		T48	70		T22	1
alert_integrity_fail	alert[0x1b]	8495	1			T21	14		T48	23		T50	26
alert_integrity_fail	alert[0x1c]	9170	1			T44	236		T21	13		T48	180
alert_integrity_fail	alert[0x1d]	4560	1			T71	375		T21	55		T22	65
alert_integrity_fail	alert[0x1e]	5741	1			T44	1		T21	34		T50	12
alert_integrity_fail	alert[0x1f]	14952	1			T20	6		T71	25		T73	51
alert_integrity_fail	alert[0x20]	8068	1			T71	291		T47	17		T80	4963
alert_integrity_fail	alert[0x21]	13291	1			T71	363		T22	3		T224	9
alert_integrity_fail	alert[0x22]	4850	1			T48	551		T224	32		T50	32
alert_integrity_fail	alert[0x23]	4686	1			T71	22		T21	116		T47	1
alert_integrity_fail	alert[0x24]	3975	1			T21	106		T47	34		T48	59
alert_integrity_fail	alert[0x25]	4389	1			T20	2		T71	84		T48	17
alert_integrity_fail	alert[0x26]	5251	1			T6	14		T21	42		T224	278
alert_integrity_fail	alert[0x27]	6818	1			T6	1		T21	60		T47	138
alert_integrity_fail	alert[0x28]	8194	1			T40	8		T44	2		T71	594
alert_integrity_fail	alert[0x29]	6621	1			T6	1		T21	8		T47	1547
alert_integrity_fail	alert[0x2a]	3984	1			T6	2		T47	1		T48	122
alert_integrity_fail	alert[0x2b]	4207	1			T71	781		T48	17		T224	45
alert_integrity_fail	alert[0x2c]	4028	1			T20	3		T71	78		T47	140
alert_integrity_fail	alert[0x2d]	4814	1			T20	25		T47	275		T48	13
alert_integrity_fail	alert[0x2e]	10161	1			T21	38		T47	11		T48	1425
alert_integrity_fail	alert[0x2f]	7490	1			T6	79		T20	4		T40	2
alert_integrity_fail	alert[0x30]	7584	1			T6	388		T71	811		T224	322
alert_integrity_fail	alert[0x31]	4418	1			T6	1		T47	261		T48	78
alert_integrity_fail	alert[0x32]	9675	1			T71	1326		T21	327		T48	5
alert_integrity_fail	alert[0x33]	3708	1			T13	18		T71	97		T224	385
alert_integrity_fail	alert[0x34]	6542	1			T12	1		T20	1		T80	570
alert_integrity_fail	alert[0x35]	9019	1			T6	3		T71	88		T224	1
alert_integrity_fail	alert[0x36]	6680	1			T6	5		T71	145		T48	20
alert_integrity_fail	alert[0x37]	13887	1			T47	235		T268	2		T73	8
alert_integrity_fail	alert[0x38]	8087	1			T21	16		T47	83		T48	26
alert_integrity_fail	alert[0x39]	4180	1			T6	7		T48	144		T224	46
alert_integrity_fail	alert[0x3a]	8861	1			T6	206		T48	140		T224	144
alert_integrity_fail	alert[0x3b]	5009	1			T6	15		T39	2		T44	10
alert_integrity_fail	alert[0x3c]	9802	1			T20	1		T71	45		T48	185
alert_integrity_fail	alert[0x3d]	5884	1			T71	89		T47	62		T50	62
alert_integrity_fail	alert[0x3e]	4282	1			T20	6		T44	3		T71	16
alert_integrity_fail	alert[0x3f]	5734	1			T6	3		T21	3		T47	3
alert_integrity_fail	alert[0x40]	2954	1			T6	24		T71	12		T48	97
alert_ping_fail	alert[0x0]	11	1			T15	2		T278	1		T282	1
alert_ping_fail	alert[0x1]	12	1			T15	1		T32	1		T283	1
alert_ping_fail	alert[0x2]	10	1			T15	1		T277	1		T23	1
alert_ping_fail	alert[0x3]	7	1			T15	1		T277	1		T284	1
alert_ping_fail	alert[0x4]	5	1			T3	1		T278	1		T285	1
alert_ping_fail	alert[0x5]	17	1			T278	1		T23	1		T280	1
alert_ping_fail	alert[0x6]	16	1			T14	1		T110	1		T97	1
alert_ping_fail	alert[0x7]	13	1			T191	2		T277	1		T280	1
alert_ping_fail	alert[0x8]	7	1			T286	1		T110	1		T97	1
alert_ping_fail	alert[0x9]	12	1			T191	1		T277	1		T286	1
alert_ping_fail	alert[0xa]	19	1			T3	1		T14	1		T280	1
alert_ping_fail	alert[0xb]	10	1			T14	1		T15	1		T277	1
alert_ping_fail	alert[0xc]	11	1			T3	1		T191	1		T277	1
alert_ping_fail	alert[0xd]	8	1			T279	1		T283	1		T287	1
alert_ping_fail	alert[0xe]	13	1			T23	1		T280	1		T286	1
alert_ping_fail	alert[0xf]	7	1			T279	1		T32	1		T283	1
alert_ping_fail	alert[0x10]	9	1			T14	1		T23	1		T287	2
alert_ping_fail	alert[0x11]	6	1			T277	1		T23	1		T97	1
alert_ping_fail	alert[0x12]	11	1			T14	1		T191	1		T278	1
alert_ping_fail	alert[0x13]	15	1			T278	1		T273	1		T285	1
alert_ping_fail	alert[0x14]	13	1			T277	1		T280	1		T288	1
alert_ping_fail	alert[0x15]	11	1			T14	1		T15	1		T191	1
alert_ping_fail	alert[0x16]	9	1			T14	1		T191	2		T276	1
alert_ping_fail	alert[0x17]	8	1			T15	1		T280	1		T32	1
alert_ping_fail	alert[0x18]	10	1			T23	1		T280	1		T282	1
alert_ping_fail	alert[0x19]	11	1			T3	1		T23	1		T32	1
alert_ping_fail	alert[0x1a]	7	1			T277	1		T280	1		T286	1
alert_ping_fail	alert[0x1b]	11	1			T14	1		T278	1		T277	1
alert_ping_fail	alert[0x1c]	13	1			T15	1		T277	1		T23	2
alert_ping_fail	alert[0x1d]	8	1			T23	1		T286	1		T283	2
alert_ping_fail	alert[0x1e]	14	1			T14	2		T15	1		T289	1
alert_ping_fail	alert[0x1f]	14	1			T278	2		T272	2		T288	1
alert_ping_fail	alert[0x20]	12	1			T191	1		T23	1		T286	1
alert_ping_fail	alert[0x21]	8	1			T3	1		T290	1		T291	2
alert_ping_fail	alert[0x22]	7	1			T279	1		T32	1		T291	1
alert_ping_fail	alert[0x23]	10	1			T15	2		T278	1		T277	1
alert_ping_fail	alert[0x24]	6	1			T23	1		T283	1		T292	1
alert_ping_fail	alert[0x25]	12	1			T3	1		T15	1		T23	1
alert_ping_fail	alert[0x26]	4	1			T292	1		T293	1		T294	1
alert_ping_fail	alert[0x27]	7	1			T3	1		T32	1		T295	2
alert_ping_fail	alert[0x28]	11	1			T191	1		T280	1		T286	1
alert_ping_fail	alert[0x29]	7	1			T191	1		T291	1		T292	1
alert_ping_fail	alert[0x2a]	12	1			T3	1		T15	1		T32	1
alert_ping_fail	alert[0x2b]	14	1			T277	1		T279	1		T286	1
alert_ping_fail	alert[0x2c]	14	1			T23	2		T289	1		T283	1
alert_ping_fail	alert[0x2d]	18	1			T290	1		T296	1		T292	1
alert_ping_fail	alert[0x2e]	5	1			T275	1		T297	1		T288	1
alert_ping_fail	alert[0x2f]	9	1			T14	1		T277	1		T283	1
alert_ping_fail	alert[0x30]	13	1			T289	1		T279	1		T297	1
alert_ping_fail	alert[0x31]	15	1			T286	1		T283	1		T291	1
alert_ping_fail	alert[0x32]	7	1			T191	1		T298	1		T284	1
alert_ping_fail	alert[0x33]	8	1			T278	1		T277	1		T23	1
alert_ping_fail	alert[0x34]	14	1			T15	1		T278	1		T23	1
alert_ping_fail	alert[0x35]	12	1			T191	1		T280	1		T289	1
alert_ping_fail	alert[0x36]	9	1			T280	1		T32	1		T290	1
alert_ping_fail	alert[0x37]	12	1			T14	1		T299	1		T298	1
alert_ping_fail	alert[0x38]	11	1			T23	1		T283	2		T297	1
alert_ping_fail	alert[0x39]	11	1			T14	1		T191	1		T278	1
alert_ping_fail	alert[0x3a]	13	1			T3	2		T15	1		T277	1
alert_ping_fail	alert[0x3b]	7	1			T15	1		T191	1		T279	1
alert_ping_fail	alert[0x3c]	11	1			T280	1		T291	3		T300	1
alert_ping_fail	alert[0x3d]	9	1			T191	1		T280	1		T288	1
alert_ping_fail	alert[0x3e]	16	1			T277	1		T23	1		T32	2
alert_ping_fail	alert[0x3f]	7	1			T278	1		T288	1		T262	1
alert_ping_fail	alert[0x40]	6	1			T15	1		T191	1		T286	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	88952	1			T12	2		T13	1		T6	109
alert_integrity_fail	class_i[0x1]	147372	1			T6	27		T20	9		T39	13
alert_integrity_fail	class_i[0x2]	31692	1			T6	59		T20	41		T39	4
alert_integrity_fail	class_i[0x3]	169487	1			T13	19		T6	1591		T40	8
alert_ping_fail	class_i[0x0]	182	1			T14	12		T15	3		T191	2
alert_ping_fail	class_i[0x1]	145	1			T3	9		T14	1		T15	1
alert_ping_fail	class_i[0x2]	180	1			T3	1		T191	2		T278	1
alert_ping_fail	class_i[0x3]	178	1			T15	14		T278	12		T277	2