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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.63 99.99 98.72 92.67 100.00 100.00 99.38 99.64


Total test records in report: 826
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T764 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2799067870 Jun 09 12:26:37 PM PDT 24 Jun 09 12:26:43 PM PDT 24 63086955 ps
T159 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3683412895 Jun 09 12:26:22 PM PDT 24 Jun 09 12:36:38 PM PDT 24 17184094098 ps
T765 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1033913465 Jun 09 12:26:49 PM PDT 24 Jun 09 12:26:51 PM PDT 24 12205686 ps
T766 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3672523186 Jun 09 12:26:30 PM PDT 24 Jun 09 12:26:32 PM PDT 24 11013481 ps
T767 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2648309845 Jun 09 12:26:59 PM PDT 24 Jun 09 12:27:02 PM PDT 24 36465928 ps
T768 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1263201190 Jun 09 12:26:23 PM PDT 24 Jun 09 12:26:25 PM PDT 24 12305460 ps
T160 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4177393455 Jun 09 12:26:48 PM PDT 24 Jun 09 12:46:18 PM PDT 24 68313939286 ps
T769 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.335704531 Jun 09 12:26:54 PM PDT 24 Jun 09 12:26:56 PM PDT 24 18364828 ps
T770 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3648872769 Jun 09 12:26:13 PM PDT 24 Jun 09 12:26:16 PM PDT 24 9649043 ps
T771 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1072340383 Jun 09 12:26:13 PM PDT 24 Jun 09 12:26:25 PM PDT 24 626551538 ps
T339 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.870642798 Jun 09 12:26:41 PM PDT 24 Jun 09 12:34:22 PM PDT 24 5988344776 ps
T772 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3269360124 Jun 09 12:26:14 PM PDT 24 Jun 09 12:26:23 PM PDT 24 123991794 ps
T773 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1727204502 Jun 09 12:26:14 PM PDT 24 Jun 09 12:30:54 PM PDT 24 4658484515 ps
T162 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.30081580 Jun 09 12:26:13 PM PDT 24 Jun 09 12:36:58 PM PDT 24 4838707917 ps
T774 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.282694728 Jun 09 12:26:29 PM PDT 24 Jun 09 12:26:35 PM PDT 24 130716568 ps
T775 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.37920245 Jun 09 12:26:54 PM PDT 24 Jun 09 12:27:01 PM PDT 24 97995849 ps
T776 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.4200162558 Jun 09 12:26:15 PM PDT 24 Jun 09 12:26:21 PM PDT 24 263253892 ps
T777 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2672776502 Jun 09 12:26:15 PM PDT 24 Jun 09 12:26:21 PM PDT 24 112357916 ps
T778 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2271912218 Jun 09 12:26:15 PM PDT 24 Jun 09 12:26:36 PM PDT 24 2117061310 ps
T779 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3513981342 Jun 09 12:26:49 PM PDT 24 Jun 09 12:26:57 PM PDT 24 83918107 ps
T780 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1845541994 Jun 09 12:26:52 PM PDT 24 Jun 09 12:26:54 PM PDT 24 23831776 ps
T781 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1508649232 Jun 09 12:26:44 PM PDT 24 Jun 09 12:26:51 PM PDT 24 185519149 ps
T782 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.803044855 Jun 09 12:26:20 PM PDT 24 Jun 09 12:35:21 PM PDT 24 7752636939 ps
T783 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.877258123 Jun 09 12:27:01 PM PDT 24 Jun 09 12:27:03 PM PDT 24 12295567 ps
T182 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1711120679 Jun 09 12:26:20 PM PDT 24 Jun 09 12:26:27 PM PDT 24 110001762 ps
T784 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.127378679 Jun 09 12:26:40 PM PDT 24 Jun 09 12:30:00 PM PDT 24 1722408007 ps
T785 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1046701927 Jun 09 12:26:55 PM PDT 24 Jun 09 12:27:03 PM PDT 24 319593231 ps
T786 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3530965693 Jun 09 12:26:46 PM PDT 24 Jun 09 12:26:51 PM PDT 24 63047917 ps
T166 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2943433183 Jun 09 12:26:13 PM PDT 24 Jun 09 12:30:46 PM PDT 24 17259304073 ps
T787 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2822100408 Jun 09 12:26:48 PM PDT 24 Jun 09 12:26:50 PM PDT 24 6403367 ps
T165 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3151221176 Jun 09 12:26:39 PM PDT 24 Jun 09 12:28:12 PM PDT 24 7379722018 ps
T788 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.4223681808 Jun 09 12:26:49 PM PDT 24 Jun 09 12:26:59 PM PDT 24 473275496 ps
T789 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3033033972 Jun 09 12:26:14 PM PDT 24 Jun 09 12:26:20 PM PDT 24 131831590 ps
T790 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1131755636 Jun 09 12:26:53 PM PDT 24 Jun 09 12:26:54 PM PDT 24 17086787 ps
T791 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3620019915 Jun 09 12:27:04 PM PDT 24 Jun 09 12:27:07 PM PDT 24 36184721 ps
T792 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.850580605 Jun 09 12:26:59 PM PDT 24 Jun 09 12:27:29 PM PDT 24 473248236 ps
T793 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.365927697 Jun 09 12:26:56 PM PDT 24 Jun 09 12:26:58 PM PDT 24 67875753 ps
T794 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.637621865 Jun 09 12:26:15 PM PDT 24 Jun 09 12:26:22 PM PDT 24 183152732 ps
T795 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3983002464 Jun 09 12:26:48 PM PDT 24 Jun 09 12:26:56 PM PDT 24 77396870 ps
T796 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.343810724 Jun 09 12:26:57 PM PDT 24 Jun 09 12:26:59 PM PDT 24 25674277 ps
T183 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2978401575 Jun 09 12:26:35 PM PDT 24 Jun 09 12:26:37 PM PDT 24 157946659 ps
T338 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.671838699 Jun 09 12:26:50 PM PDT 24 Jun 09 12:32:16 PM PDT 24 43619437376 ps
T797 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.549424206 Jun 09 12:26:57 PM PDT 24 Jun 09 12:27:01 PM PDT 24 127211226 ps
T798 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.789505444 Jun 09 12:26:17 PM PDT 24 Jun 09 12:26:31 PM PDT 24 624571242 ps
T799 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2294027282 Jun 09 12:26:50 PM PDT 24 Jun 09 12:27:02 PM PDT 24 90656808 ps
T800 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2164280664 Jun 09 12:26:11 PM PDT 24 Jun 09 12:35:30 PM PDT 24 17703260647 ps
T801 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2089340709 Jun 09 12:26:57 PM PDT 24 Jun 09 12:26:59 PM PDT 24 12137358 ps
T802 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.913408891 Jun 09 12:26:16 PM PDT 24 Jun 09 12:26:22 PM PDT 24 195269317 ps
T803 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2805420532 Jun 09 12:26:55 PM PDT 24 Jun 09 12:26:57 PM PDT 24 19005941 ps
T804 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3874054150 Jun 09 12:26:58 PM PDT 24 Jun 09 12:27:00 PM PDT 24 10814679 ps
T805 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.4056940196 Jun 09 12:26:43 PM PDT 24 Jun 09 12:26:48 PM PDT 24 42781765 ps
T806 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.843599530 Jun 09 12:26:10 PM PDT 24 Jun 09 12:30:18 PM PDT 24 4543198635 ps
T807 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3304370329 Jun 09 12:26:17 PM PDT 24 Jun 09 12:26:26 PM PDT 24 153211384 ps
T178 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1002415657 Jun 09 12:26:51 PM PDT 24 Jun 09 12:26:55 PM PDT 24 36726180 ps
T808 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1402071971 Jun 09 12:27:01 PM PDT 24 Jun 09 12:27:03 PM PDT 24 18661267 ps
T809 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3946082070 Jun 09 12:26:14 PM PDT 24 Jun 09 12:26:39 PM PDT 24 766138573 ps
T810 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.165425828 Jun 09 12:26:34 PM PDT 24 Jun 09 12:27:12 PM PDT 24 502736911 ps
T811 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2814480222 Jun 09 12:28:19 PM PDT 24 Jun 09 12:28:21 PM PDT 24 15335212 ps
T812 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2942786344 Jun 09 12:26:49 PM PDT 24 Jun 09 12:26:58 PM PDT 24 358176610 ps
T813 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3844746372 Jun 09 12:26:11 PM PDT 24 Jun 09 12:26:13 PM PDT 24 10257841 ps
T814 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1199302872 Jun 09 12:26:57 PM PDT 24 Jun 09 12:27:02 PM PDT 24 50841323 ps
T815 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.814723088 Jun 09 12:26:16 PM PDT 24 Jun 09 12:26:21 PM PDT 24 217214576 ps
T816 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1588495304 Jun 09 12:26:42 PM PDT 24 Jun 09 12:26:54 PM PDT 24 103347812 ps
T817 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.4129264311 Jun 09 12:26:51 PM PDT 24 Jun 09 12:26:54 PM PDT 24 10792349 ps
T818 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2555900370 Jun 09 12:26:15 PM PDT 24 Jun 09 12:26:20 PM PDT 24 68701778 ps
T819 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3618821096 Jun 09 12:26:36 PM PDT 24 Jun 09 12:26:46 PM PDT 24 68864840 ps
T820 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2063862269 Jun 09 12:27:03 PM PDT 24 Jun 09 12:27:22 PM PDT 24 602996401 ps
T821 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1306422301 Jun 09 12:26:12 PM PDT 24 Jun 09 12:26:15 PM PDT 24 16961487 ps
T174 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3720205415 Jun 09 12:26:13 PM PDT 24 Jun 09 12:26:20 PM PDT 24 107750828 ps
T822 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2695984059 Jun 09 12:26:41 PM PDT 24 Jun 09 12:27:00 PM PDT 24 1079185825 ps
T823 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.470581073 Jun 09 12:26:38 PM PDT 24 Jun 09 12:26:44 PM PDT 24 111954642 ps
T824 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3160376426 Jun 09 12:26:59 PM PDT 24 Jun 09 12:27:01 PM PDT 24 8036146 ps
T825 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1877453204 Jun 09 12:26:44 PM PDT 24 Jun 09 12:27:08 PM PDT 24 174604396 ps
T826 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3520167322 Jun 09 12:26:46 PM PDT 24 Jun 09 12:26:48 PM PDT 24 12192523 ps
T177 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2724469167 Jun 09 12:26:54 PM PDT 24 Jun 09 12:26:57 PM PDT 24 36048842 ps
T164 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3378479812 Jun 09 12:26:39 PM PDT 24 Jun 09 12:31:23 PM PDT 24 9654695211 ps

Test location /workspace/coverage/default/2.alert_handler_entropy.116587438
Short name T13
Test name
Test status
Simulation time 12278618162 ps
CPU time 1329.88 seconds
Started Jun 09 12:37:35 PM PDT 24
Finished Jun 09 12:59:46 PM PDT 24
Peak memory 284972 kb
Host smart-c35d00bb-7379-4f7c-a878-6c67a58767ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116587438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.116587438
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.3516104400
Short name T6
Test name
Test status
Simulation time 157410004043 ps
CPU time 2326.82 seconds
Started Jun 09 12:38:30 PM PDT 24
Finished Jun 09 01:17:17 PM PDT 24
Peak memory 289592 kb
Host smart-5d792ee1-b521-42cc-9974-f9e9c361bd68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516104400 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.3516104400
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.5264289
Short name T21
Test name
Test status
Simulation time 225435062262 ps
CPU time 4521.91 seconds
Started Jun 09 12:38:09 PM PDT 24
Finished Jun 09 01:53:32 PM PDT 24
Peak memory 299616 kb
Host smart-7ee2a28f-e775-4d89-87a8-716cacbf5636
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5264289 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.5264289
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.579599136
Short name T8
Test name
Test status
Simulation time 613173701 ps
CPU time 12.7 seconds
Started Jun 09 12:37:35 PM PDT 24
Finished Jun 09 12:37:48 PM PDT 24
Peak memory 277508 kb
Host smart-b449fc34-2a17-463f-b751-c92d15a33340
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=579599136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.579599136
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2119095442
Short name T230
Test name
Test status
Simulation time 4151183699 ps
CPU time 38.43 seconds
Started Jun 09 12:26:53 PM PDT 24
Finished Jun 09 12:27:32 PM PDT 24
Peak memory 237632 kb
Host smart-5d3a3ec5-a81b-4e4b-a962-572aee2eb5ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2119095442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2119095442
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1072283667
Short name T5
Test name
Test status
Simulation time 866790096 ps
CPU time 11.1 seconds
Started Jun 09 12:37:39 PM PDT 24
Finished Jun 09 12:37:51 PM PDT 24
Peak memory 248700 kb
Host smart-19240e70-5887-452e-97b5-48c0bd7a61f3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1072283667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1072283667
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2473690008
Short name T110
Test name
Test status
Simulation time 119153379907 ps
CPU time 2319.96 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 01:16:25 PM PDT 24
Peak memory 289172 kb
Host smart-e317dad3-03ff-4ab8-a1c8-e7a38cfc707a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473690008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2473690008
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2971624469
Short name T108
Test name
Test status
Simulation time 870197800940 ps
CPU time 3008.91 seconds
Started Jun 09 12:37:41 PM PDT 24
Finished Jun 09 01:27:52 PM PDT 24
Peak memory 289680 kb
Host smart-a5a22d1c-adf6-4993-a4d0-6c86c17adde2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971624469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2971624469
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1196650544
Short name T133
Test name
Test status
Simulation time 1706598995 ps
CPU time 202.38 seconds
Started Jun 09 12:27:11 PM PDT 24
Finished Jun 09 12:30:34 PM PDT 24
Peak memory 272568 kb
Host smart-61442eb2-535d-4455-8181-d04dc9cee23c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1196650544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1196650544
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1128221864
Short name T641
Test name
Test status
Simulation time 21110003995 ps
CPU time 1993.37 seconds
Started Jun 09 12:38:37 PM PDT 24
Finished Jun 09 01:11:51 PM PDT 24
Peak memory 302164 kb
Host smart-6e812c26-1500-4f94-ab70-c930f5becc25
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128221864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1128221864
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1828426135
Short name T144
Test name
Test status
Simulation time 40740363032 ps
CPU time 1220.4 seconds
Started Jun 09 12:26:27 PM PDT 24
Finished Jun 09 12:46:48 PM PDT 24
Peak memory 272736 kb
Host smart-97dc020f-02f2-4c41-b5d3-3600577cdf08
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828426135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1828426135
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.3668485264
Short name T22
Test name
Test status
Simulation time 7711293960 ps
CPU time 518.24 seconds
Started Jun 09 12:37:40 PM PDT 24
Finished Jun 09 12:46:19 PM PDT 24
Peak memory 267172 kb
Host smart-95ed9f37-d622-44f2-829a-7ccb81f1a032
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668485264 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3668485264
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3913720057
Short name T134
Test name
Test status
Simulation time 7222373235 ps
CPU time 399.54 seconds
Started Jun 09 12:26:23 PM PDT 24
Finished Jun 09 12:33:03 PM PDT 24
Peak memory 273012 kb
Host smart-64063d7f-3670-428a-af04-265e2c0c217a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3913720057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3913720057
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2447722709
Short name T224
Test name
Test status
Simulation time 136713990515 ps
CPU time 1118.79 seconds
Started Jun 09 12:37:38 PM PDT 24
Finished Jun 09 12:56:18 PM PDT 24
Peak memory 288856 kb
Host smart-92de1137-611c-47c8-b212-8829974c955a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447722709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2447722709
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.200695845
Short name T140
Test name
Test status
Simulation time 18574373944 ps
CPU time 559.52 seconds
Started Jun 09 12:26:41 PM PDT 24
Finished Jun 09 12:36:01 PM PDT 24
Peak memory 265096 kb
Host smart-5a262621-505a-47ee-984c-c737d42bdb3f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200695845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.200695845
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3976261774
Short name T15
Test name
Test status
Simulation time 11335038315 ps
CPU time 444.57 seconds
Started Jun 09 12:37:37 PM PDT 24
Finished Jun 09 12:45:02 PM PDT 24
Peak memory 247992 kb
Host smart-d1018d0d-7fc2-45dd-8381-fe401d538a70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976261774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3976261774
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1470049407
Short name T303
Test name
Test status
Simulation time 199480598484 ps
CPU time 2682.38 seconds
Started Jun 09 12:37:40 PM PDT 24
Finished Jun 09 01:22:23 PM PDT 24
Peak memory 287672 kb
Host smart-6bc89675-9300-4214-b757-44f69db5b76e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470049407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1470049407
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2541172299
Short name T335
Test name
Test status
Simulation time 21211570 ps
CPU time 1.43 seconds
Started Jun 09 12:27:00 PM PDT 24
Finished Jun 09 12:27:02 PM PDT 24
Peak memory 236560 kb
Host smart-6646bf6e-3019-4189-a823-7a443a7d2024
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2541172299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2541172299
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1610962049
Short name T47
Test name
Test status
Simulation time 115235175560 ps
CPU time 3334.72 seconds
Started Jun 09 12:38:47 PM PDT 24
Finished Jun 09 01:34:22 PM PDT 24
Peak memory 306028 kb
Host smart-401d4fe7-5389-448d-8803-2fe9b79913c3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610962049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1610962049
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3396867564
Short name T276
Test name
Test status
Simulation time 19889241550 ps
CPU time 1227.42 seconds
Started Jun 09 12:37:40 PM PDT 24
Finished Jun 09 12:58:09 PM PDT 24
Peak memory 271992 kb
Host smart-71d7174e-c2d7-4c42-b854-1cf2b5691bc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396867564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3396867564
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.733167659
Short name T146
Test name
Test status
Simulation time 15722664568 ps
CPU time 1047.64 seconds
Started Jun 09 12:26:36 PM PDT 24
Finished Jun 09 12:44:04 PM PDT 24
Peak memory 264948 kb
Host smart-48adaf85-4663-4960-8c9a-d9f4b8c9209c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733167659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.733167659
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.4169809808
Short name T23
Test name
Test status
Simulation time 24335630922 ps
CPU time 486.48 seconds
Started Jun 09 12:37:44 PM PDT 24
Finished Jun 09 12:45:52 PM PDT 24
Peak memory 255232 kb
Host smart-8981e257-e36e-4444-8c65-1b78c7d5b5f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169809808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.4169809808
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1174011530
Short name T138
Test name
Test status
Simulation time 1635335196 ps
CPU time 199.1 seconds
Started Jun 09 12:26:35 PM PDT 24
Finished Jun 09 12:29:55 PM PDT 24
Peak memory 264908 kb
Host smart-3e41283a-262b-4153-a663-e61ad37bf790
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1174011530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1174011530
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.3311070877
Short name T55
Test name
Test status
Simulation time 157058411791 ps
CPU time 2435.76 seconds
Started Jun 09 12:38:20 PM PDT 24
Finished Jun 09 01:18:56 PM PDT 24
Peak memory 289432 kb
Host smart-118b31a9-2b65-4161-b22f-ecd4d3109a89
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311070877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.3311070877
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3523895120
Short name T191
Test name
Test status
Simulation time 48177083106 ps
CPU time 482.83 seconds
Started Jun 09 12:37:34 PM PDT 24
Finished Jun 09 12:45:37 PM PDT 24
Peak memory 248044 kb
Host smart-eb23bb27-c573-4546-9832-1b59fd9ed8d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523895120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3523895120
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.90858578
Short name T161
Test name
Test status
Simulation time 4327271179 ps
CPU time 580.55 seconds
Started Jun 09 12:26:53 PM PDT 24
Finished Jun 09 12:36:35 PM PDT 24
Peak memory 271912 kb
Host smart-ccfab055-f965-4c95-be1d-b4b78a211ab8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90858578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.90858578
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1309442610
Short name T310
Test name
Test status
Simulation time 356121114659 ps
CPU time 2065.46 seconds
Started Jun 09 12:38:23 PM PDT 24
Finished Jun 09 01:12:49 PM PDT 24
Peak memory 286192 kb
Host smart-b9cf7c7c-a030-4ca4-b662-06fc48cc21b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309442610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1309442610
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.764957424
Short name T302
Test name
Test status
Simulation time 82792044153 ps
CPU time 2277.53 seconds
Started Jun 09 12:38:47 PM PDT 24
Finished Jun 09 01:16:45 PM PDT 24
Peak memory 281540 kb
Host smart-99b89e4f-b553-4b49-b2c2-1840e51ba569
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764957424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.764957424
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.5721209
Short name T238
Test name
Test status
Simulation time 326204887198 ps
CPU time 4785.51 seconds
Started Jun 09 12:37:59 PM PDT 24
Finished Jun 09 01:57:45 PM PDT 24
Peak memory 314368 kb
Host smart-a8e907fd-51ff-4631-917f-cdae1e719697
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5721209 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.5721209
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1753975045
Short name T50
Test name
Test status
Simulation time 36813432792 ps
CPU time 1970.35 seconds
Started Jun 09 12:37:56 PM PDT 24
Finished Jun 09 01:10:47 PM PDT 24
Peak memory 282420 kb
Host smart-b874b681-fa14-4c89-8501-b3214bb765d4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753975045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1753975045
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.939573787
Short name T131
Test name
Test status
Simulation time 50823013812 ps
CPU time 468.62 seconds
Started Jun 09 12:26:15 PM PDT 24
Finished Jun 09 12:34:05 PM PDT 24
Peak memory 265188 kb
Host smart-6e5c3c4e-2f62-4df9-a322-41befbbff2da
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939573787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.939573787
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1079222308
Short name T252
Test name
Test status
Simulation time 33216782565 ps
CPU time 1928.98 seconds
Started Jun 09 12:38:19 PM PDT 24
Finished Jun 09 01:10:29 PM PDT 24
Peak memory 288680 kb
Host smart-741cde56-ab64-4fcc-81ac-9b8a9645fce3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079222308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1079222308
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.236345996
Short name T99
Test name
Test status
Simulation time 156899982733 ps
CPU time 2235.39 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 01:14:59 PM PDT 24
Peak memory 281600 kb
Host smart-0401d1dc-cea0-49b8-ad74-04875d08f720
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236345996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.236345996
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.26312008
Short name T298
Test name
Test status
Simulation time 10873334404 ps
CPU time 449.95 seconds
Started Jun 09 12:38:21 PM PDT 24
Finished Jun 09 12:45:51 PM PDT 24
Peak memory 254952 kb
Host smart-1886af56-574a-4aac-8458-f4a85fa8e29d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26312008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.26312008
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4177393455
Short name T160
Test name
Test status
Simulation time 68313939286 ps
CPU time 1169.56 seconds
Started Jun 09 12:26:48 PM PDT 24
Finished Jun 09 12:46:18 PM PDT 24
Peak memory 265120 kb
Host smart-e057d351-1712-4d58-b300-cceb9c8b765b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177393455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.4177393455
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3842675347
Short name T332
Test name
Test status
Simulation time 12726135 ps
CPU time 1.43 seconds
Started Jun 09 12:26:56 PM PDT 24
Finished Jun 09 12:26:59 PM PDT 24
Peak memory 236564 kb
Host smart-8325663e-ba2f-4228-8815-ec8e00261717
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3842675347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3842675347
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1807222989
Short name T278
Test name
Test status
Simulation time 21120676061 ps
CPU time 433.12 seconds
Started Jun 09 12:38:12 PM PDT 24
Finished Jun 09 12:45:26 PM PDT 24
Peak memory 248144 kb
Host smart-8b847e9f-87f5-464e-82d7-d40230a1d03a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807222989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1807222989
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1207958269
Short name T96
Test name
Test status
Simulation time 212883709687 ps
CPU time 4133.8 seconds
Started Jun 09 12:37:39 PM PDT 24
Finished Jun 09 01:46:34 PM PDT 24
Peak memory 321040 kb
Host smart-a218f847-98e0-46ba-a713-fd2a8dbb247c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207958269 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1207958269
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3182057013
Short name T127
Test name
Test status
Simulation time 81730742356 ps
CPU time 2585.89 seconds
Started Jun 09 12:38:25 PM PDT 24
Finished Jun 09 01:21:32 PM PDT 24
Peak memory 285524 kb
Host smart-aef1083c-4cbc-4184-ac3e-a13280439144
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182057013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3182057013
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1626657057
Short name T156
Test name
Test status
Simulation time 5131099090 ps
CPU time 336.83 seconds
Started Jun 09 12:26:43 PM PDT 24
Finished Jun 09 12:32:20 PM PDT 24
Peak memory 264960 kb
Host smart-c0202161-3e30-4b21-95e1-9ccbb856ee99
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1626657057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1626657057
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.30081580
Short name T162
Test name
Test status
Simulation time 4838707917 ps
CPU time 643.33 seconds
Started Jun 09 12:26:13 PM PDT 24
Finished Jun 09 12:36:58 PM PDT 24
Peak memory 272280 kb
Host smart-9435a296-3cbf-4c65-ba15-4a3003c4531c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30081580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.30081580
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.110703498
Short name T272
Test name
Test status
Simulation time 75305598821 ps
CPU time 1505.79 seconds
Started Jun 09 12:37:45 PM PDT 24
Finished Jun 09 01:02:52 PM PDT 24
Peak memory 288220 kb
Host smart-bd3fb69d-7788-468e-b4ef-ff7de3355d05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110703498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.110703498
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2297184896
Short name T263
Test name
Test status
Simulation time 10159892096 ps
CPU time 1015.58 seconds
Started Jun 09 12:38:59 PM PDT 24
Finished Jun 09 12:55:55 PM PDT 24
Peak memory 283904 kb
Host smart-2e560470-0ac6-4acb-ac32-278c4305f16d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297184896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2297184896
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.4040381490
Short name T122
Test name
Test status
Simulation time 46691621662 ps
CPU time 2953.9 seconds
Started Jun 09 12:38:27 PM PDT 24
Finished Jun 09 01:27:41 PM PDT 24
Peak memory 321868 kb
Host smart-f56bbd62-c1bc-4df0-abd5-4540f201fa93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040381490 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.4040381490
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1389100126
Short name T121
Test name
Test status
Simulation time 58801095967 ps
CPU time 1370.35 seconds
Started Jun 09 12:37:46 PM PDT 24
Finished Jun 09 01:00:38 PM PDT 24
Peak memory 289068 kb
Host smart-2e95d175-fe5e-46f5-9636-ee0aac482c2b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389100126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1389100126
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1711120679
Short name T182
Test name
Test status
Simulation time 110001762 ps
CPU time 5.98 seconds
Started Jun 09 12:26:20 PM PDT 24
Finished Jun 09 12:26:27 PM PDT 24
Peak memory 235600 kb
Host smart-185251ee-202a-4050-853c-02461e4b4568
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1711120679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1711120679
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.395363847
Short name T125
Test name
Test status
Simulation time 82494648385 ps
CPU time 8058.14 seconds
Started Jun 09 12:37:35 PM PDT 24
Finished Jun 09 02:51:55 PM PDT 24
Peak memory 393680 kb
Host smart-b153bbd2-4f90-4cc9-a33e-2f4383a095a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395363847 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.395363847
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2795184787
Short name T296
Test name
Test status
Simulation time 41485268605 ps
CPU time 2180.62 seconds
Started Jun 09 12:38:14 PM PDT 24
Finished Jun 09 01:14:36 PM PDT 24
Peak memory 282408 kb
Host smart-92854fcc-3386-4f42-a1aa-9e5b8535a91f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795184787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2795184787
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1774739861
Short name T32
Test name
Test status
Simulation time 19695131388 ps
CPU time 421.59 seconds
Started Jun 09 12:38:38 PM PDT 24
Finished Jun 09 12:45:40 PM PDT 24
Peak memory 248400 kb
Host smart-5d839f20-9c72-4e1c-8d1d-9826f1eed1b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774739861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1774739861
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2113497072
Short name T57
Test name
Test status
Simulation time 122982153342 ps
CPU time 3966.41 seconds
Started Jun 09 12:38:38 PM PDT 24
Finished Jun 09 01:44:45 PM PDT 24
Peak memory 302532 kb
Host smart-0e03cd34-a029-4c04-9e21-93322d77ca55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113497072 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2113497072
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.3431385611
Short name T80
Test name
Test status
Simulation time 74458935276 ps
CPU time 2124.99 seconds
Started Jun 09 12:38:36 PM PDT 24
Finished Jun 09 01:14:01 PM PDT 24
Peak memory 305576 kb
Host smart-b8e425b7-0727-4a8d-88ad-6297d56cb823
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431385611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.3431385611
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3271213260
Short name T179
Test name
Test status
Simulation time 599654689 ps
CPU time 38.46 seconds
Started Jun 09 12:26:34 PM PDT 24
Finished Jun 09 12:27:13 PM PDT 24
Peak memory 239936 kb
Host smart-eeff3acf-703b-416b-8ac0-515a9ffdfd58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3271213260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3271213260
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1334528019
Short name T147
Test name
Test status
Simulation time 3434475258 ps
CPU time 103.4 seconds
Started Jun 09 12:26:46 PM PDT 24
Finished Jun 09 12:28:30 PM PDT 24
Peak memory 264980 kb
Host smart-7f1b9ffa-d235-439b-9117-5f5c9f7b3dfa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1334528019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1334528019
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.496643209
Short name T218
Test name
Test status
Simulation time 25547407 ps
CPU time 2.7 seconds
Started Jun 09 12:37:35 PM PDT 24
Finished Jun 09 12:37:39 PM PDT 24
Peak memory 256992 kb
Host smart-84449a9a-57b2-44ad-b876-32c3288a9f5d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=496643209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.496643209
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3636989749
Short name T214
Test name
Test status
Simulation time 42795426 ps
CPU time 3.16 seconds
Started Jun 09 12:37:37 PM PDT 24
Finished Jun 09 12:37:41 PM PDT 24
Peak memory 248864 kb
Host smart-4aadea79-bbbd-4342-b051-f5981b178da3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3636989749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3636989749
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2099237621
Short name T210
Test name
Test status
Simulation time 66814274 ps
CPU time 3.08 seconds
Started Jun 09 12:37:44 PM PDT 24
Finished Jun 09 12:37:48 PM PDT 24
Peak memory 248864 kb
Host smart-3e0747e9-990f-4fad-8cfa-6911a70c495b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2099237621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2099237621
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2073626047
Short name T217
Test name
Test status
Simulation time 89320163 ps
CPU time 3.43 seconds
Started Jun 09 12:37:58 PM PDT 24
Finished Jun 09 12:38:02 PM PDT 24
Peak memory 248784 kb
Host smart-55fe7d85-5fff-4ef5-a4e4-68e12b9e4a2d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2073626047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2073626047
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1707013251
Short name T261
Test name
Test status
Simulation time 17361348927 ps
CPU time 1445.47 seconds
Started Jun 09 12:37:37 PM PDT 24
Finished Jun 09 01:01:44 PM PDT 24
Peak memory 289660 kb
Host smart-b99ee9d2-5d15-4d48-834a-61d63580b7b0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707013251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1707013251
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2001553623
Short name T267
Test name
Test status
Simulation time 32785644824 ps
CPU time 1390.35 seconds
Started Jun 09 12:38:12 PM PDT 24
Finished Jun 09 01:01:23 PM PDT 24
Peak memory 289236 kb
Host smart-8cafb5e2-f45b-4285-be17-1dc07d0799c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001553623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2001553623
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2056599392
Short name T294
Test name
Test status
Simulation time 20831634167 ps
CPU time 392.32 seconds
Started Jun 09 12:38:17 PM PDT 24
Finished Jun 09 12:44:50 PM PDT 24
Peak memory 248188 kb
Host smart-dbe270d9-13d0-4550-a37f-f7a73194fcfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056599392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2056599392
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3466644946
Short name T245
Test name
Test status
Simulation time 33966290223 ps
CPU time 1731.57 seconds
Started Jun 09 12:38:16 PM PDT 24
Finished Jun 09 01:07:09 PM PDT 24
Peak memory 273272 kb
Host smart-00090e38-6cdc-4d62-accf-da3eb03f62d9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466644946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3466644946
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3278468141
Short name T256
Test name
Test status
Simulation time 58729389591 ps
CPU time 1820.8 seconds
Started Jun 09 12:38:57 PM PDT 24
Finished Jun 09 01:09:19 PM PDT 24
Peak memory 272868 kb
Host smart-97227d3d-bb76-4a24-8ac6-7f5e513cc7b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278468141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3278468141
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2985090174
Short name T671
Test name
Test status
Simulation time 10933001718 ps
CPU time 672.17 seconds
Started Jun 09 12:37:59 PM PDT 24
Finished Jun 09 12:49:11 PM PDT 24
Peak memory 272864 kb
Host smart-11150b2a-f8d2-428a-b2ab-b928463101ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985090174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2985090174
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2898714898
Short name T135
Test name
Test status
Simulation time 7426909809 ps
CPU time 157.26 seconds
Started Jun 09 12:26:17 PM PDT 24
Finished Jun 09 12:28:55 PM PDT 24
Peak memory 264984 kb
Host smart-7758ac1c-2877-4c0b-a4ba-3f4dfd16ec1e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2898714898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2898714898
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3858027110
Short name T139
Test name
Test status
Simulation time 7594661422 ps
CPU time 140.2 seconds
Started Jun 09 12:26:16 PM PDT 24
Finished Jun 09 12:28:37 PM PDT 24
Peak memory 265080 kb
Host smart-55119c50-ae83-4394-9649-3993e52ca5b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3858027110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3858027110
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2157534376
Short name T12
Test name
Test status
Simulation time 652429185 ps
CPU time 34.76 seconds
Started Jun 09 12:37:36 PM PDT 24
Finished Jun 09 12:38:12 PM PDT 24
Peak memory 255404 kb
Host smart-8c60c3dd-5477-4a45-ba3f-2c9796f1df6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21575
34376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2157534376
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.843325696
Short name T229
Test name
Test status
Simulation time 40113533 ps
CPU time 1.34 seconds
Started Jun 09 12:26:12 PM PDT 24
Finished Jun 09 12:26:14 PM PDT 24
Peak memory 236548 kb
Host smart-4a723cc3-b6dc-4eb3-a38d-d69bb4c265c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=843325696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.843325696
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1639204759
Short name T299
Test name
Test status
Simulation time 8373892760 ps
CPU time 342.07 seconds
Started Jun 09 12:37:32 PM PDT 24
Finished Jun 09 12:43:15 PM PDT 24
Peak memory 248420 kb
Host smart-b56386b8-f659-43a5-819d-67bc4a869e16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639204759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1639204759
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.2853131299
Short name T102
Test name
Test status
Simulation time 96114631984 ps
CPU time 8302.3 seconds
Started Jun 09 12:37:29 PM PDT 24
Finished Jun 09 02:55:53 PM PDT 24
Peak memory 403128 kb
Host smart-23f75da1-0e2d-4e05-8e3a-6aee366007bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853131299 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.2853131299
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.909913820
Short name T251
Test name
Test status
Simulation time 31636012941 ps
CPU time 1223.63 seconds
Started Jun 09 12:38:11 PM PDT 24
Finished Jun 09 12:58:36 PM PDT 24
Peak memory 288732 kb
Host smart-eb2a7a51-bb71-4904-9590-fe3e0478549f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909913820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.909913820
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2415415688
Short name T306
Test name
Test status
Simulation time 55998474216 ps
CPU time 1193.25 seconds
Started Jun 09 12:37:46 PM PDT 24
Finished Jun 09 12:57:40 PM PDT 24
Peak memory 273264 kb
Host smart-6fd5d182-54d2-49ba-b7cf-f252ba54cad5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415415688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2415415688
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2588663877
Short name T54
Test name
Test status
Simulation time 513198753 ps
CPU time 56.5 seconds
Started Jun 09 12:37:46 PM PDT 24
Finished Jun 09 12:38:43 PM PDT 24
Peak memory 248564 kb
Host smart-11e7b004-16e9-4dbf-a37d-196305e0c9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25886
63877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2588663877
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3553303831
Short name T237
Test name
Test status
Simulation time 141691708749 ps
CPU time 1366.23 seconds
Started Jun 09 12:38:12 PM PDT 24
Finished Jun 09 01:00:59 PM PDT 24
Peak memory 297884 kb
Host smart-fb9f3bb3-683e-4370-838f-9524b7d5a83a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553303831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3553303831
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2715642370
Short name T82
Test name
Test status
Simulation time 200745336 ps
CPU time 24.37 seconds
Started Jun 09 12:38:15 PM PDT 24
Finished Jun 09 12:38:40 PM PDT 24
Peak memory 256968 kb
Host smart-a30f30b3-a188-4419-8944-a91e79573671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27156
42370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2715642370
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2149880607
Short name T324
Test name
Test status
Simulation time 146757540566 ps
CPU time 2114.3 seconds
Started Jun 09 12:38:28 PM PDT 24
Finished Jun 09 01:13:42 PM PDT 24
Peak memory 289224 kb
Host smart-928401bf-62ac-4961-aa24-2fa272dcfdf9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149880607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2149880607
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.587125149
Short name T242
Test name
Test status
Simulation time 1329128954 ps
CPU time 23.57 seconds
Started Jun 09 12:38:32 PM PDT 24
Finished Jun 09 12:38:56 PM PDT 24
Peak memory 255432 kb
Host smart-cddb2049-91e3-4eda-a909-e2f521f9f5f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58712
5149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.587125149
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.671736586
Short name T246
Test name
Test status
Simulation time 28529950443 ps
CPU time 371.64 seconds
Started Jun 09 12:38:35 PM PDT 24
Finished Jun 09 12:44:47 PM PDT 24
Peak memory 256884 kb
Host smart-13359903-89e8-434c-96d3-b2338627947f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671736586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.671736586
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1382821568
Short name T114
Test name
Test status
Simulation time 125384664180 ps
CPU time 1825.37 seconds
Started Jun 09 12:38:59 PM PDT 24
Finished Jun 09 01:09:25 PM PDT 24
Peak memory 301236 kb
Host smart-6577436c-3a94-43de-b962-73f4f1752d1b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382821568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1382821568
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3151221176
Short name T165
Test name
Test status
Simulation time 7379722018 ps
CPU time 92.6 seconds
Started Jun 09 12:26:39 PM PDT 24
Finished Jun 09 12:28:12 PM PDT 24
Peak memory 264848 kb
Host smart-f9b02710-5218-4c33-976c-f9a6acc20922
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3151221176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3151221176
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.625225232
Short name T167
Test name
Test status
Simulation time 119561887 ps
CPU time 4.25 seconds
Started Jun 09 12:26:21 PM PDT 24
Finished Jun 09 12:26:31 PM PDT 24
Peak memory 236448 kb
Host smart-36b27d61-f9b8-42f6-a186-e9b4307045b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=625225232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.625225232
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2512560430
Short name T180
Test name
Test status
Simulation time 37592969 ps
CPU time 3.26 seconds
Started Jun 09 12:26:15 PM PDT 24
Finished Jun 09 12:26:20 PM PDT 24
Peak memory 236544 kb
Host smart-d94b17d7-cbc4-4a4c-823e-f3d243cbf6e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2512560430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2512560430
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2943433183
Short name T166
Test name
Test status
Simulation time 17259304073 ps
CPU time 271.41 seconds
Started Jun 09 12:26:13 PM PDT 24
Finished Jun 09 12:30:46 PM PDT 24
Peak memory 264956 kb
Host smart-afb80510-378d-4bdc-8081-2084c892673e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2943433183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2943433183
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3720205415
Short name T174
Test name
Test status
Simulation time 107750828 ps
CPU time 5.8 seconds
Started Jun 09 12:26:13 PM PDT 24
Finished Jun 09 12:26:20 PM PDT 24
Peak memory 235600 kb
Host smart-63154107-03d8-42e9-bbbf-41c659fb2ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3720205415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3720205415
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1754346005
Short name T173
Test name
Test status
Simulation time 4909583905 ps
CPU time 66.83 seconds
Started Jun 09 12:26:51 PM PDT 24
Finished Jun 09 12:27:58 PM PDT 24
Peak memory 245980 kb
Host smart-38215cb0-fb35-40a9-bdcf-653c2d79531a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1754346005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1754346005
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1002415657
Short name T178
Test name
Test status
Simulation time 36726180 ps
CPU time 2.87 seconds
Started Jun 09 12:26:51 PM PDT 24
Finished Jun 09 12:26:55 PM PDT 24
Peak memory 236512 kb
Host smart-9b1f552f-6a9e-495b-b298-881f05d94958
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1002415657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1002415657
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1842584101
Short name T187
Test name
Test status
Simulation time 128949749 ps
CPU time 2.87 seconds
Started Jun 09 12:26:15 PM PDT 24
Finished Jun 09 12:26:19 PM PDT 24
Peak memory 236536 kb
Host smart-89d92927-4d10-4ed5-988b-1438c4e07729
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1842584101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1842584101
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3692786822
Short name T175
Test name
Test status
Simulation time 3679920199 ps
CPU time 67.18 seconds
Started Jun 09 12:26:48 PM PDT 24
Finished Jun 09 12:27:56 PM PDT 24
Peak memory 248228 kb
Host smart-19706633-e1a3-4c67-945a-3a264f1d10b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3692786822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3692786822
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3165992849
Short name T168
Test name
Test status
Simulation time 371354171 ps
CPU time 4.18 seconds
Started Jun 09 12:26:35 PM PDT 24
Finished Jun 09 12:26:40 PM PDT 24
Peak memory 236528 kb
Host smart-2958f404-c03e-414e-a83e-a19adf3191a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3165992849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3165992849
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1402173774
Short name T137
Test name
Test status
Simulation time 2231691278 ps
CPU time 213.49 seconds
Started Jun 09 12:26:34 PM PDT 24
Finished Jun 09 12:30:08 PM PDT 24
Peak memory 271584 kb
Host smart-ebf1049e-9c6c-463c-9385-8e71c18de680
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1402173774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1402173774
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2724469167
Short name T177
Test name
Test status
Simulation time 36048842 ps
CPU time 2.25 seconds
Started Jun 09 12:26:54 PM PDT 24
Finished Jun 09 12:26:57 PM PDT 24
Peak memory 236380 kb
Host smart-dc1b289a-8811-47da-9916-1efb190570e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2724469167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2724469167
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3913112242
Short name T176
Test name
Test status
Simulation time 92408409 ps
CPU time 2.42 seconds
Started Jun 09 12:26:52 PM PDT 24
Finished Jun 09 12:26:55 PM PDT 24
Peak memory 236608 kb
Host smart-fdef119d-7272-4e67-8e30-cb0945a78755
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3913112242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3913112242
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2978401575
Short name T183
Test name
Test status
Simulation time 157946659 ps
CPU time 2.17 seconds
Started Jun 09 12:26:35 PM PDT 24
Finished Jun 09 12:26:37 PM PDT 24
Peak memory 236388 kb
Host smart-9a94de9c-bc67-4c58-b997-bea53068deb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2978401575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2978401575
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2099899938
Short name T169
Test name
Test status
Simulation time 2461418488 ps
CPU time 38.23 seconds
Started Jun 09 12:26:14 PM PDT 24
Finished Jun 09 12:26:54 PM PDT 24
Peak memory 239936 kb
Host smart-f9506aee-f266-450c-9e89-9f1a8d0cc82a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2099899938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2099899938
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1123371111
Short name T186
Test name
Test status
Simulation time 4163419276 ps
CPU time 151.26 seconds
Started Jun 09 12:26:10 PM PDT 24
Finished Jun 09 12:28:42 PM PDT 24
Peak memory 238320 kb
Host smart-fa7476da-0ea6-4fc7-a992-803366eddbe4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1123371111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1123371111
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.843599530
Short name T806
Test name
Test status
Simulation time 4543198635 ps
CPU time 248.39 seconds
Started Jun 09 12:26:10 PM PDT 24
Finished Jun 09 12:30:18 PM PDT 24
Peak memory 236572 kb
Host smart-3aec6055-eb10-4450-a24c-795a138a34ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=843599530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.843599530
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1632677397
Short name T713
Test name
Test status
Simulation time 225162735 ps
CPU time 5.16 seconds
Started Jun 09 12:26:16 PM PDT 24
Finished Jun 09 12:26:22 PM PDT 24
Peak memory 239960 kb
Host smart-d38db6e6-304b-406c-964e-083efee29eeb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1632677397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1632677397
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2672507655
Short name T341
Test name
Test status
Simulation time 1071172705 ps
CPU time 6.14 seconds
Started Jun 09 12:26:10 PM PDT 24
Finished Jun 09 12:26:17 PM PDT 24
Peak memory 239980 kb
Host smart-e6a90733-d4de-4b20-ae65-6c2d261d36c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672507655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2672507655
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2555900370
Short name T818
Test name
Test status
Simulation time 68701778 ps
CPU time 3.19 seconds
Started Jun 09 12:26:15 PM PDT 24
Finished Jun 09 12:26:20 PM PDT 24
Peak memory 236372 kb
Host smart-b7318a62-5fb5-4937-9e42-81fc57f31d2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2555900370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2555900370
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3844746372
Short name T813
Test name
Test status
Simulation time 10257841 ps
CPU time 1.25 seconds
Started Jun 09 12:26:11 PM PDT 24
Finished Jun 09 12:26:13 PM PDT 24
Peak memory 234572 kb
Host smart-524cf2a3-8f86-42e0-9de3-bb26c634754e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3844746372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3844746372
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3770819107
Short name T743
Test name
Test status
Simulation time 526994947 ps
CPU time 11.16 seconds
Started Jun 09 12:26:12 PM PDT 24
Finished Jun 09 12:26:25 PM PDT 24
Peak memory 248160 kb
Host smart-9de1011c-ff6a-48e4-92e2-8ac4e7493e48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3770819107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3770819107
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3112312285
Short name T143
Test name
Test status
Simulation time 3588658654 ps
CPU time 86.67 seconds
Started Jun 09 12:26:13 PM PDT 24
Finished Jun 09 12:27:41 PM PDT 24
Peak memory 256784 kb
Host smart-1abfaefd-e3ef-4207-bf81-660d8be4503e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3112312285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3112312285
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.803044855
Short name T782
Test name
Test status
Simulation time 7752636939 ps
CPU time 541.1 seconds
Started Jun 09 12:26:20 PM PDT 24
Finished Jun 09 12:35:21 PM PDT 24
Peak memory 264988 kb
Host smart-21d7e8fb-394c-426f-b76e-aa346d1ac2df
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803044855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.803044855
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.4200162558
Short name T776
Test name
Test status
Simulation time 263253892 ps
CPU time 4.96 seconds
Started Jun 09 12:26:15 PM PDT 24
Finished Jun 09 12:26:21 PM PDT 24
Peak memory 247884 kb
Host smart-0bdf2eda-30d5-4366-b12d-846d0656f0c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4200162558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.4200162558
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.23757848
Short name T751
Test name
Test status
Simulation time 52873828 ps
CPU time 2.64 seconds
Started Jun 09 12:26:08 PM PDT 24
Finished Jun 09 12:26:11 PM PDT 24
Peak memory 236532 kb
Host smart-572f6c79-6cf9-40f4-8d1a-9621d162028e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=23757848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.23757848
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.848395312
Short name T185
Test name
Test status
Simulation time 1654966114 ps
CPU time 119.15 seconds
Started Jun 09 12:26:15 PM PDT 24
Finished Jun 09 12:28:16 PM PDT 24
Peak memory 236528 kb
Host smart-6acd3e98-94a9-4a91-ad08-49ef4511f5f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=848395312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.848395312
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2945962358
Short name T755
Test name
Test status
Simulation time 95038981209 ps
CPU time 384.56 seconds
Started Jun 09 12:26:13 PM PDT 24
Finished Jun 09 12:32:39 PM PDT 24
Peak memory 236468 kb
Host smart-57a39c3e-4438-4b24-a8cb-6075c75a7143
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2945962358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2945962358
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.637621865
Short name T794
Test name
Test status
Simulation time 183152732 ps
CPU time 5.84 seconds
Started Jun 09 12:26:15 PM PDT 24
Finished Jun 09 12:26:22 PM PDT 24
Peak memory 239968 kb
Host smart-36cd1262-7d7f-444e-992c-9d9bf84338c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=637621865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.637621865
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3164400772
Short name T726
Test name
Test status
Simulation time 847927944 ps
CPU time 6.7 seconds
Started Jun 09 12:26:09 PM PDT 24
Finished Jun 09 12:26:22 PM PDT 24
Peak memory 239996 kb
Host smart-9b22b74e-e6fd-4f0e-ab02-9e19d7f5301c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164400772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3164400772
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1978791294
Short name T184
Test name
Test status
Simulation time 71943721 ps
CPU time 3.24 seconds
Started Jun 09 12:26:13 PM PDT 24
Finished Jun 09 12:26:18 PM PDT 24
Peak memory 239188 kb
Host smart-45a0e60f-8de0-4c4a-a2fb-e5a1af19e3c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1978791294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1978791294
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3648872769
Short name T770
Test name
Test status
Simulation time 9649043 ps
CPU time 1.48 seconds
Started Jun 09 12:26:13 PM PDT 24
Finished Jun 09 12:26:16 PM PDT 24
Peak memory 235616 kb
Host smart-32b24b6a-4ad8-4c59-9d3d-023cc9cb362c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3648872769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3648872769
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3490105398
Short name T744
Test name
Test status
Simulation time 1646195966 ps
CPU time 21.58 seconds
Started Jun 09 12:26:11 PM PDT 24
Finished Jun 09 12:26:34 PM PDT 24
Peak memory 248168 kb
Host smart-ef0cde0c-cdbd-468f-a1f9-6754328b07eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3490105398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3490105398
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1030951054
Short name T136
Test name
Test status
Simulation time 13640161103 ps
CPU time 435.95 seconds
Started Jun 09 12:26:13 PM PDT 24
Finished Jun 09 12:33:30 PM PDT 24
Peak memory 264916 kb
Host smart-e49d4a86-de6d-4c0f-b3db-8b3fac10831f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030951054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1030951054
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.562593980
Short name T712
Test name
Test status
Simulation time 52783242 ps
CPU time 6.73 seconds
Started Jun 09 12:26:22 PM PDT 24
Finished Jun 09 12:26:29 PM PDT 24
Peak memory 248148 kb
Host smart-c31ae327-03fa-4b62-a5bc-2f03862167fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=562593980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.562593980
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.967220438
Short name T227
Test name
Test status
Simulation time 157085786 ps
CPU time 11.17 seconds
Started Jun 09 12:26:25 PM PDT 24
Finished Jun 09 12:26:36 PM PDT 24
Peak memory 252708 kb
Host smart-466e1945-9e2b-4f0f-8e1b-b49ff28fa983
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967220438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.967220438
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1573372767
Short name T228
Test name
Test status
Simulation time 65874392 ps
CPU time 4.85 seconds
Started Jun 09 12:26:52 PM PDT 24
Finished Jun 09 12:26:57 PM PDT 24
Peak memory 236524 kb
Host smart-3f2e8078-53c1-4f39-aa34-ae69cb0be21c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1573372767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1573372767
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3520167322
Short name T826
Test name
Test status
Simulation time 12192523 ps
CPU time 1.39 seconds
Started Jun 09 12:26:46 PM PDT 24
Finished Jun 09 12:26:48 PM PDT 24
Peak memory 236544 kb
Host smart-1c85aad8-38a0-4ca8-baa8-cdbf5635426a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3520167322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3520167322
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3178922838
Short name T750
Test name
Test status
Simulation time 337301770 ps
CPU time 21.27 seconds
Started Jun 09 12:26:39 PM PDT 24
Finished Jun 09 12:27:01 PM PDT 24
Peak memory 248064 kb
Host smart-949af571-60d0-4233-8b16-059b0de0f1e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3178922838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3178922838
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1521068687
Short name T709
Test name
Test status
Simulation time 1164582901 ps
CPU time 15.15 seconds
Started Jun 09 12:26:38 PM PDT 24
Finished Jun 09 12:26:54 PM PDT 24
Peak memory 247664 kb
Host smart-c7fb8c7c-afd2-4b7d-acb3-ca4926303166
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1521068687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1521068687
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3550446007
Short name T721
Test name
Test status
Simulation time 29841474 ps
CPU time 4.6 seconds
Started Jun 09 12:26:38 PM PDT 24
Finished Jun 09 12:26:42 PM PDT 24
Peak memory 240016 kb
Host smart-7ef6be95-3813-4ea7-912b-bc1f023da673
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550446007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3550446007
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1060414661
Short name T733
Test name
Test status
Simulation time 48762985 ps
CPU time 5.16 seconds
Started Jun 09 12:26:43 PM PDT 24
Finished Jun 09 12:26:48 PM PDT 24
Peak memory 236524 kb
Host smart-20221e43-29c9-479c-a3d2-dc74031edf48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1060414661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1060414661
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3672523186
Short name T766
Test name
Test status
Simulation time 11013481 ps
CPU time 1.38 seconds
Started Jun 09 12:26:30 PM PDT 24
Finished Jun 09 12:26:32 PM PDT 24
Peak memory 234608 kb
Host smart-a9f52197-25da-41d0-a57f-e58474272c12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3672523186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3672523186
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1060909437
Short name T763
Test name
Test status
Simulation time 690896378 ps
CPU time 41.8 seconds
Started Jun 09 12:26:42 PM PDT 24
Finished Jun 09 12:27:24 PM PDT 24
Peak memory 244728 kb
Host smart-e83e92dc-be88-4fd3-9f30-314a105dcfef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1060909437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1060909437
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2299766221
Short name T157
Test name
Test status
Simulation time 9398813856 ps
CPU time 182.47 seconds
Started Jun 09 12:26:46 PM PDT 24
Finished Jun 09 12:29:48 PM PDT 24
Peak memory 264972 kb
Host smart-546cb317-40ed-4322-8f86-df1c52190b02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2299766221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2299766221
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.870642798
Short name T339
Test name
Test status
Simulation time 5988344776 ps
CPU time 460.64 seconds
Started Jun 09 12:26:41 PM PDT 24
Finished Jun 09 12:34:22 PM PDT 24
Peak memory 265124 kb
Host smart-f34432f9-2aa4-43e3-9009-657bc8318ca5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870642798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.870642798
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1541237641
Short name T741
Test name
Test status
Simulation time 785703721 ps
CPU time 11.75 seconds
Started Jun 09 12:26:49 PM PDT 24
Finished Jun 09 12:27:01 PM PDT 24
Peak memory 252944 kb
Host smart-d08bb946-795c-471c-9827-157b612a87f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1541237641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1541237641
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3513981342
Short name T779
Test name
Test status
Simulation time 83918107 ps
CPU time 7.08 seconds
Started Jun 09 12:26:49 PM PDT 24
Finished Jun 09 12:26:57 PM PDT 24
Peak memory 240004 kb
Host smart-7ffd1aa8-d8bb-4299-9809-c0cf63b36451
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513981342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3513981342
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3403326847
Short name T200
Test name
Test status
Simulation time 63774062 ps
CPU time 3.48 seconds
Started Jun 09 12:26:43 PM PDT 24
Finished Jun 09 12:26:47 PM PDT 24
Peak memory 235588 kb
Host smart-bf389cb9-83a4-4072-95c6-085c5c1e7ec1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3403326847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3403326847
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2729772674
Short name T719
Test name
Test status
Simulation time 6371808 ps
CPU time 1.45 seconds
Started Jun 09 12:26:42 PM PDT 24
Finished Jun 09 12:26:44 PM PDT 24
Peak memory 235632 kb
Host smart-11b1021b-7335-4d58-b852-194a4dd44ef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2729772674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2729772674
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2294027282
Short name T799
Test name
Test status
Simulation time 90656808 ps
CPU time 11.45 seconds
Started Jun 09 12:26:50 PM PDT 24
Finished Jun 09 12:27:02 PM PDT 24
Peak memory 239908 kb
Host smart-1c55f547-0e4a-4451-b1ce-78cda072aa4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2294027282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2294027282
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3331469214
Short name T155
Test name
Test status
Simulation time 6104678589 ps
CPU time 690.83 seconds
Started Jun 09 12:26:38 PM PDT 24
Finished Jun 09 12:38:09 PM PDT 24
Peak memory 264968 kb
Host smart-bb529d8d-3028-43e7-a9a1-ea262ead4285
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331469214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3331469214
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1588495304
Short name T816
Test name
Test status
Simulation time 103347812 ps
CPU time 10.63 seconds
Started Jun 09 12:26:42 PM PDT 24
Finished Jun 09 12:26:54 PM PDT 24
Peak memory 253016 kb
Host smart-5ddddecf-7fae-42b8-a60c-a36099542411
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1588495304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1588495304
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2533490268
Short name T715
Test name
Test status
Simulation time 157167008 ps
CPU time 5.48 seconds
Started Jun 09 12:27:00 PM PDT 24
Finished Jun 09 12:27:06 PM PDT 24
Peak memory 239364 kb
Host smart-f4b0c25a-80ff-4c6f-9815-94388327dd5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533490268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2533490268
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1508649232
Short name T781
Test name
Test status
Simulation time 185519149 ps
CPU time 7.06 seconds
Started Jun 09 12:26:44 PM PDT 24
Finished Jun 09 12:26:51 PM PDT 24
Peak memory 235588 kb
Host smart-059653fe-802d-48a3-b3fe-11159ebb75bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1508649232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1508649232
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1262247994
Short name T739
Test name
Test status
Simulation time 16142826 ps
CPU time 1.29 seconds
Started Jun 09 12:26:58 PM PDT 24
Finished Jun 09 12:27:00 PM PDT 24
Peak memory 236540 kb
Host smart-1f697b01-24f6-4a2f-b442-3a11aac38d66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1262247994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1262247994
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1475013938
Short name T742
Test name
Test status
Simulation time 179512022 ps
CPU time 18.41 seconds
Started Jun 09 12:26:58 PM PDT 24
Finished Jun 09 12:27:17 PM PDT 24
Peak memory 248152 kb
Host smart-7a5a07fd-ef8c-41b7-bf12-45c5d02a5490
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1475013938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1475013938
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.273893749
Short name T723
Test name
Test status
Simulation time 36671537 ps
CPU time 4.74 seconds
Started Jun 09 12:26:45 PM PDT 24
Finished Jun 09 12:26:50 PM PDT 24
Peak memory 248544 kb
Host smart-33f4ae55-d21e-4cc9-9da8-eda154fbe71e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=273893749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.273893749
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.114965106
Short name T752
Test name
Test status
Simulation time 518187587 ps
CPU time 8.84 seconds
Started Jun 09 12:26:44 PM PDT 24
Finished Jun 09 12:26:53 PM PDT 24
Peak memory 240020 kb
Host smart-848e9e1b-4c7d-4dcf-bc45-7a7e7d5c0be3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114965106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.alert_handler_csr_mem_rw_with_rand_reset.114965106
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.4223681808
Short name T788
Test name
Test status
Simulation time 473275496 ps
CPU time 8.71 seconds
Started Jun 09 12:26:49 PM PDT 24
Finished Jun 09 12:26:59 PM PDT 24
Peak memory 236524 kb
Host smart-ea95da2d-c400-4c46-8abb-397d599e8542
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4223681808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.4223681808
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1033913465
Short name T765
Test name
Test status
Simulation time 12205686 ps
CPU time 1.5 seconds
Started Jun 09 12:26:49 PM PDT 24
Finished Jun 09 12:26:51 PM PDT 24
Peak memory 235640 kb
Host smart-ff3277b7-9ce0-495c-862b-865d6c0e75fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1033913465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1033913465
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.257946248
Short name T724
Test name
Test status
Simulation time 507079609 ps
CPU time 16.87 seconds
Started Jun 09 12:27:02 PM PDT 24
Finished Jun 09 12:27:19 PM PDT 24
Peak memory 244732 kb
Host smart-9a45f1bb-524d-482e-845d-f474514e5791
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=257946248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.257946248
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.451772997
Short name T150
Test name
Test status
Simulation time 5087846036 ps
CPU time 96.79 seconds
Started Jun 09 12:26:49 PM PDT 24
Finished Jun 09 12:28:26 PM PDT 24
Peak memory 265720 kb
Host smart-2abb01e6-1eb0-4672-8618-248f876891e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=451772997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.451772997
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1787051875
Short name T152
Test name
Test status
Simulation time 4387346880 ps
CPU time 306.66 seconds
Started Jun 09 12:26:56 PM PDT 24
Finished Jun 09 12:32:03 PM PDT 24
Peak memory 265084 kb
Host smart-12ca9db0-fd4b-475f-95bc-1e715f90fca7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787051875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1787051875
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.4065112827
Short name T720
Test name
Test status
Simulation time 211330914 ps
CPU time 9.42 seconds
Started Jun 09 12:26:48 PM PDT 24
Finished Jun 09 12:26:58 PM PDT 24
Peak memory 248240 kb
Host smart-57647926-2153-4246-98ba-20c278535606
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4065112827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.4065112827
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.225678000
Short name T231
Test name
Test status
Simulation time 317597494 ps
CPU time 41.98 seconds
Started Jun 09 12:26:54 PM PDT 24
Finished Jun 09 12:27:37 PM PDT 24
Peak memory 244724 kb
Host smart-948c215a-e825-4d52-9cb3-70fca059bc04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=225678000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.225678000
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.37920245
Short name T775
Test name
Test status
Simulation time 97995849 ps
CPU time 6.76 seconds
Started Jun 09 12:26:54 PM PDT 24
Finished Jun 09 12:27:01 PM PDT 24
Peak memory 238972 kb
Host smart-2f1ed3be-0878-4b3e-8b6b-221f0f12be75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37920245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.alert_handler_csr_mem_rw_with_rand_reset.37920245
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2010829662
Short name T710
Test name
Test status
Simulation time 273725573 ps
CPU time 5.26 seconds
Started Jun 09 12:26:50 PM PDT 24
Finished Jun 09 12:26:56 PM PDT 24
Peak memory 236524 kb
Host smart-5d071d8b-3502-4bce-8e59-ec479a433953
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2010829662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2010829662
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2938901438
Short name T331
Test name
Test status
Simulation time 23947575 ps
CPU time 1.31 seconds
Started Jun 09 12:26:45 PM PDT 24
Finished Jun 09 12:26:46 PM PDT 24
Peak memory 236560 kb
Host smart-bfdc34f2-894b-4fee-b75b-19814f40f8ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2938901438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2938901438
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1273482329
Short name T746
Test name
Test status
Simulation time 417439772 ps
CPU time 12.65 seconds
Started Jun 09 12:26:56 PM PDT 24
Finished Jun 09 12:27:10 PM PDT 24
Peak memory 244736 kb
Host smart-b199ea53-80d3-4acf-8c2c-29d821e14854
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1273482329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1273482329
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.671838699
Short name T338
Test name
Test status
Simulation time 43619437376 ps
CPU time 325.91 seconds
Started Jun 09 12:26:50 PM PDT 24
Finished Jun 09 12:32:16 PM PDT 24
Peak memory 265128 kb
Host smart-71023645-c28e-4aff-a533-9bb194e4e197
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671838699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.671838699
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1046701927
Short name T785
Test name
Test status
Simulation time 319593231 ps
CPU time 7.26 seconds
Started Jun 09 12:26:55 PM PDT 24
Finished Jun 09 12:27:03 PM PDT 24
Peak memory 247800 kb
Host smart-bd68b291-92dd-4fbf-a4d4-9fde7495a534
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1046701927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1046701927
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2648309845
Short name T767
Test name
Test status
Simulation time 36465928 ps
CPU time 2.23 seconds
Started Jun 09 12:26:59 PM PDT 24
Finished Jun 09 12:27:02 PM PDT 24
Peak memory 236576 kb
Host smart-f76624fa-c5de-495f-a6bf-d5b9d4b8a3a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2648309845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2648309845
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.596773710
Short name T748
Test name
Test status
Simulation time 242281773 ps
CPU time 9.56 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:18 PM PDT 24
Peak memory 242068 kb
Host smart-933b6872-0e36-4f4b-889b-effafa1cb102
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596773710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.596773710
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1199302872
Short name T814
Test name
Test status
Simulation time 50841323 ps
CPU time 4.42 seconds
Started Jun 09 12:26:57 PM PDT 24
Finished Jun 09 12:27:02 PM PDT 24
Peak memory 236524 kb
Host smart-285c9625-eee4-4490-96a8-ca286dcbb30d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1199302872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1199302872
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2822100408
Short name T787
Test name
Test status
Simulation time 6403367 ps
CPU time 1.38 seconds
Started Jun 09 12:26:48 PM PDT 24
Finished Jun 09 12:26:50 PM PDT 24
Peak memory 234528 kb
Host smart-cdcbf91e-5632-459a-9710-26358dbd715f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2822100408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2822100408
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.165425828
Short name T810
Test name
Test status
Simulation time 502736911 ps
CPU time 37.31 seconds
Started Jun 09 12:26:34 PM PDT 24
Finished Jun 09 12:27:12 PM PDT 24
Peak memory 244744 kb
Host smart-6bc16590-d695-421f-aff9-490cd0048a82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=165425828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.165425828
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3232365558
Short name T141
Test name
Test status
Simulation time 9917407763 ps
CPU time 179.49 seconds
Started Jun 09 12:26:51 PM PDT 24
Finished Jun 09 12:29:51 PM PDT 24
Peak memory 264944 kb
Host smart-b301c46f-0fd4-4455-b45d-80ed64a6fbfe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3232365558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3232365558
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2557071716
Short name T148
Test name
Test status
Simulation time 9315244245 ps
CPU time 261.66 seconds
Started Jun 09 12:26:56 PM PDT 24
Finished Jun 09 12:31:18 PM PDT 24
Peak memory 264968 kb
Host smart-1a3eb1b7-ee33-429b-9c12-5ee68971d41b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557071716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2557071716
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2527472799
Short name T707
Test name
Test status
Simulation time 167776830 ps
CPU time 10.09 seconds
Started Jun 09 12:26:55 PM PDT 24
Finished Jun 09 12:27:06 PM PDT 24
Peak memory 247768 kb
Host smart-5070ddaa-9900-47f6-9252-f64a585c3138
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2527472799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2527472799
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3691041472
Short name T340
Test name
Test status
Simulation time 604593446 ps
CPU time 13.1 seconds
Started Jun 09 12:27:08 PM PDT 24
Finished Jun 09 12:27:23 PM PDT 24
Peak memory 252288 kb
Host smart-8be50ea8-8efe-4b0e-abc0-a3b4275fe90c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691041472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3691041472
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3285770146
Short name T199
Test name
Test status
Simulation time 251331826 ps
CPU time 5.36 seconds
Started Jun 09 12:26:55 PM PDT 24
Finished Jun 09 12:27:01 PM PDT 24
Peak memory 236524 kb
Host smart-3e074202-800f-4311-9446-4b5e223b285f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3285770146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3285770146
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.4129264311
Short name T817
Test name
Test status
Simulation time 10792349 ps
CPU time 1.61 seconds
Started Jun 09 12:26:51 PM PDT 24
Finished Jun 09 12:26:54 PM PDT 24
Peak memory 235632 kb
Host smart-f8979a09-a2cb-491a-9129-d29c1db355bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4129264311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.4129264311
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2063862269
Short name T820
Test name
Test status
Simulation time 602996401 ps
CPU time 17.75 seconds
Started Jun 09 12:27:03 PM PDT 24
Finished Jun 09 12:27:22 PM PDT 24
Peak memory 243792 kb
Host smart-223d6899-70c9-4ae5-9bd4-8df848aca5aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2063862269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2063862269
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3983002464
Short name T795
Test name
Test status
Simulation time 77396870 ps
CPU time 8.04 seconds
Started Jun 09 12:26:48 PM PDT 24
Finished Jun 09 12:26:56 PM PDT 24
Peak memory 248192 kb
Host smart-fae8a2d4-0a49-417b-840e-c36cb695b4c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3983002464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3983002464
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1524171979
Short name T757
Test name
Test status
Simulation time 221094130 ps
CPU time 8.02 seconds
Started Jun 09 12:26:57 PM PDT 24
Finished Jun 09 12:27:06 PM PDT 24
Peak memory 237292 kb
Host smart-151dfa69-5015-4c00-a556-e2ea1ac90558
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524171979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1524171979
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.4912228
Short name T732
Test name
Test status
Simulation time 165162609 ps
CPU time 3.21 seconds
Started Jun 09 12:26:54 PM PDT 24
Finished Jun 09 12:26:57 PM PDT 24
Peak memory 239704 kb
Host smart-a883afcb-f66c-4555-9fd6-f764f4b9187a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4912228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.4912228
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1696708496
Short name T716
Test name
Test status
Simulation time 10481306 ps
CPU time 1.29 seconds
Started Jun 09 12:26:54 PM PDT 24
Finished Jun 09 12:26:56 PM PDT 24
Peak memory 234596 kb
Host smart-d1d5511c-ffb8-452a-b645-eb4b1c2e9f9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1696708496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1696708496
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.850580605
Short name T792
Test name
Test status
Simulation time 473248236 ps
CPU time 29.51 seconds
Started Jun 09 12:26:59 PM PDT 24
Finished Jun 09 12:27:29 PM PDT 24
Peak memory 243772 kb
Host smart-8615d46b-f468-4ebc-815f-c3a4be645e16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=850580605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.850580605
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3686551375
Short name T158
Test name
Test status
Simulation time 7415295681 ps
CPU time 124.49 seconds
Started Jun 09 12:26:50 PM PDT 24
Finished Jun 09 12:28:55 PM PDT 24
Peak memory 264956 kb
Host smart-854aa7ee-05cb-4dad-824f-886019b5cd91
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3686551375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3686551375
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3245464585
Short name T708
Test name
Test status
Simulation time 140368507 ps
CPU time 5.69 seconds
Started Jun 09 12:26:49 PM PDT 24
Finished Jun 09 12:26:55 PM PDT 24
Peak memory 247776 kb
Host smart-10cd9511-3067-4cd2-968c-f264df5f09a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3245464585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3245464585
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.549424206
Short name T797
Test name
Test status
Simulation time 127211226 ps
CPU time 3.41 seconds
Started Jun 09 12:26:57 PM PDT 24
Finished Jun 09 12:27:01 PM PDT 24
Peak memory 239660 kb
Host smart-12255bec-9e73-4edf-89a2-cc5b10ae0267
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549424206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.549424206
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2931647478
Short name T760
Test name
Test status
Simulation time 31181830 ps
CPU time 3.29 seconds
Started Jun 09 12:26:48 PM PDT 24
Finished Jun 09 12:26:52 PM PDT 24
Peak memory 236524 kb
Host smart-d6d52366-7957-4618-a23f-f0f4df220e25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2931647478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2931647478
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1001161371
Short name T740
Test name
Test status
Simulation time 341078892 ps
CPU time 11.74 seconds
Started Jun 09 12:26:53 PM PDT 24
Finished Jun 09 12:27:06 PM PDT 24
Peak memory 243800 kb
Host smart-ff2e5de9-c94c-45ac-860c-c1912a6f4148
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1001161371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1001161371
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.4039247971
Short name T142
Test name
Test status
Simulation time 7929516693 ps
CPU time 468.84 seconds
Started Jun 09 12:26:56 PM PDT 24
Finished Jun 09 12:34:46 PM PDT 24
Peak memory 268836 kb
Host smart-ee219861-294f-4d34-a2cd-217db47a5f31
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039247971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.4039247971
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2942786344
Short name T812
Test name
Test status
Simulation time 358176610 ps
CPU time 9.23 seconds
Started Jun 09 12:26:49 PM PDT 24
Finished Jun 09 12:26:58 PM PDT 24
Peak memory 248228 kb
Host smart-4e983780-bd1b-4316-97c6-300e234e5210
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2942786344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2942786344
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1727204502
Short name T773
Test name
Test status
Simulation time 4658484515 ps
CPU time 278.68 seconds
Started Jun 09 12:26:14 PM PDT 24
Finished Jun 09 12:30:54 PM PDT 24
Peak memory 240028 kb
Host smart-b2497b19-92f3-42b6-a722-fa64601e0e85
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1727204502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1727204502
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1113447058
Short name T226
Test name
Test status
Simulation time 29657014380 ps
CPU time 406.65 seconds
Started Jun 09 12:26:16 PM PDT 24
Finished Jun 09 12:33:03 PM PDT 24
Peak memory 235664 kb
Host smart-0af94527-72df-456f-8569-78f426f16d82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1113447058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1113447058
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3966364334
Short name T711
Test name
Test status
Simulation time 104118960 ps
CPU time 8.72 seconds
Started Jun 09 12:26:10 PM PDT 24
Finished Jun 09 12:26:19 PM PDT 24
Peak memory 240040 kb
Host smart-35ffbfb2-68b0-437a-a2ce-bae5dbccaa7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3966364334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3966364334
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.470581073
Short name T823
Test name
Test status
Simulation time 111954642 ps
CPU time 5.73 seconds
Started Jun 09 12:26:38 PM PDT 24
Finished Jun 09 12:26:44 PM PDT 24
Peak memory 240008 kb
Host smart-434304ae-91f3-4870-b7e0-09ea19bea0a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470581073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.alert_handler_csr_mem_rw_with_rand_reset.470581073
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.814723088
Short name T815
Test name
Test status
Simulation time 217214576 ps
CPU time 4.71 seconds
Started Jun 09 12:26:16 PM PDT 24
Finished Jun 09 12:26:21 PM PDT 24
Peak memory 235592 kb
Host smart-79029311-bc62-4267-8bdf-130178c8d4f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=814723088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.814723088
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3285458916
Short name T198
Test name
Test status
Simulation time 647602740 ps
CPU time 31.66 seconds
Started Jun 09 12:26:41 PM PDT 24
Finished Jun 09 12:27:13 PM PDT 24
Peak memory 248112 kb
Host smart-23adefab-eaac-4ac9-a969-3fd1a9b4e9d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3285458916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3285458916
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3405833651
Short name T145
Test name
Test status
Simulation time 9503125609 ps
CPU time 97.14 seconds
Started Jun 09 12:26:14 PM PDT 24
Finished Jun 09 12:27:52 PM PDT 24
Peak memory 256784 kb
Host smart-5fa66666-9b91-45e8-b691-c145ef2f7965
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3405833651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3405833651
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2164280664
Short name T800
Test name
Test status
Simulation time 17703260647 ps
CPU time 557.1 seconds
Started Jun 09 12:26:11 PM PDT 24
Finished Jun 09 12:35:30 PM PDT 24
Peak memory 264988 kb
Host smart-fadf6313-43b1-4c7d-b0ee-22c25ca27cfc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164280664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2164280664
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2519000088
Short name T738
Test name
Test status
Simulation time 167910334 ps
CPU time 5.61 seconds
Started Jun 09 12:26:40 PM PDT 24
Finished Jun 09 12:26:46 PM PDT 24
Peak memory 248176 kb
Host smart-495670d5-6096-4c86-89cb-f475a36c4335
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2519000088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2519000088
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1131755636
Short name T790
Test name
Test status
Simulation time 17086787 ps
CPU time 1.27 seconds
Started Jun 09 12:26:53 PM PDT 24
Finished Jun 09 12:26:54 PM PDT 24
Peak memory 235624 kb
Host smart-ece036c3-ed4b-46a1-aefe-ced0d307919e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1131755636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1131755636
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1628502133
Short name T171
Test name
Test status
Simulation time 19852856 ps
CPU time 1.37 seconds
Started Jun 09 12:26:51 PM PDT 24
Finished Jun 09 12:26:54 PM PDT 24
Peak memory 236540 kb
Host smart-8cd8f33f-de40-4be9-b0c3-743269e24bec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1628502133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1628502133
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.343810724
Short name T796
Test name
Test status
Simulation time 25674277 ps
CPU time 1.44 seconds
Started Jun 09 12:26:57 PM PDT 24
Finished Jun 09 12:26:59 PM PDT 24
Peak memory 235592 kb
Host smart-22ce3fb6-5424-49ec-a465-9aa469ad1dda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=343810724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.343810724
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1402071971
Short name T808
Test name
Test status
Simulation time 18661267 ps
CPU time 1.34 seconds
Started Jun 09 12:27:01 PM PDT 24
Finished Jun 09 12:27:03 PM PDT 24
Peak memory 236556 kb
Host smart-f55a61a4-b954-4925-a97e-17481e935207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1402071971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1402071971
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2865397022
Short name T758
Test name
Test status
Simulation time 24253705 ps
CPU time 2.01 seconds
Started Jun 09 12:26:51 PM PDT 24
Finished Jun 09 12:26:54 PM PDT 24
Peak memory 235632 kb
Host smart-aee82cbe-f53e-437c-8ce1-f340a1461d01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2865397022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2865397022
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.365927697
Short name T793
Test name
Test status
Simulation time 67875753 ps
CPU time 1.36 seconds
Started Jun 09 12:26:56 PM PDT 24
Finished Jun 09 12:26:58 PM PDT 24
Peak memory 236388 kb
Host smart-37f21a5a-4b42-4483-b550-7e0dba1e0703
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=365927697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.365927697
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3200751314
Short name T329
Test name
Test status
Simulation time 11011435 ps
CPU time 1.3 seconds
Started Jun 09 12:26:55 PM PDT 24
Finished Jun 09 12:26:57 PM PDT 24
Peak memory 235632 kb
Host smart-16704d1d-9071-42c4-985c-2c13dcd18feb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3200751314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3200751314
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2079835030
Short name T731
Test name
Test status
Simulation time 21349916 ps
CPU time 1.52 seconds
Started Jun 09 12:27:02 PM PDT 24
Finished Jun 09 12:27:05 PM PDT 24
Peak memory 235624 kb
Host smart-4e8d5a50-4038-4974-ae03-000f9d8ef6ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2079835030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2079835030
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2089340709
Short name T801
Test name
Test status
Simulation time 12137358 ps
CPU time 1.37 seconds
Started Jun 09 12:26:57 PM PDT 24
Finished Jun 09 12:26:59 PM PDT 24
Peak memory 234616 kb
Host smart-579d502d-88d4-4b9d-87db-d0fedaf1ab0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2089340709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2089340709
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3230654284
Short name T727
Test name
Test status
Simulation time 9746240 ps
CPU time 1.3 seconds
Started Jun 09 12:27:03 PM PDT 24
Finished Jun 09 12:27:05 PM PDT 24
Peak memory 236560 kb
Host smart-412febe6-df2d-4029-9772-cfdd96419821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3230654284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3230654284
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2280567002
Short name T197
Test name
Test status
Simulation time 1921531211 ps
CPU time 109.3 seconds
Started Jun 09 12:26:22 PM PDT 24
Finished Jun 09 12:28:12 PM PDT 24
Peak memory 239868 kb
Host smart-44a9809b-7641-4e69-8fe4-2523712dbcbf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2280567002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2280567002
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.790416620
Short name T195
Test name
Test status
Simulation time 17841478301 ps
CPU time 253.79 seconds
Started Jun 09 12:26:32 PM PDT 24
Finished Jun 09 12:30:46 PM PDT 24
Peak memory 240016 kb
Host smart-79361901-7dd5-4c4f-88ff-89d7482653f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=790416620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.790416620
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1467206077
Short name T759
Test name
Test status
Simulation time 125897422 ps
CPU time 3.27 seconds
Started Jun 09 12:26:21 PM PDT 24
Finished Jun 09 12:26:34 PM PDT 24
Peak memory 239856 kb
Host smart-0f02919d-4a79-45e0-8c37-674f23371135
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1467206077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1467206077
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.282694728
Short name T774
Test name
Test status
Simulation time 130716568 ps
CPU time 5.55 seconds
Started Jun 09 12:26:29 PM PDT 24
Finished Jun 09 12:26:35 PM PDT 24
Peak memory 251136 kb
Host smart-974c2226-25f1-4f8c-ae92-dc7a8c4cc3c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282694728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.alert_handler_csr_mem_rw_with_rand_reset.282694728
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.4056940196
Short name T805
Test name
Test status
Simulation time 42781765 ps
CPU time 5.09 seconds
Started Jun 09 12:26:43 PM PDT 24
Finished Jun 09 12:26:48 PM PDT 24
Peak memory 235600 kb
Host smart-4c21a627-72d3-4857-a887-3d9850668184
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4056940196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.4056940196
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.4081169167
Short name T761
Test name
Test status
Simulation time 8654705 ps
CPU time 1.45 seconds
Started Jun 09 12:26:16 PM PDT 24
Finished Jun 09 12:26:18 PM PDT 24
Peak memory 236544 kb
Host smart-21186db8-b861-46fa-8931-3a1c2651d80a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4081169167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.4081169167
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1931198297
Short name T196
Test name
Test status
Simulation time 255404156 ps
CPU time 18.53 seconds
Started Jun 09 12:26:31 PM PDT 24
Finished Jun 09 12:26:50 PM PDT 24
Peak memory 239852 kb
Host smart-e42f4204-31a3-4e26-b861-99c67d7f1fb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1931198297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1931198297
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1072340383
Short name T771
Test name
Test status
Simulation time 626551538 ps
CPU time 10.25 seconds
Started Jun 09 12:26:13 PM PDT 24
Finished Jun 09 12:26:25 PM PDT 24
Peak memory 248220 kb
Host smart-b4273a5b-9b04-4411-a9fa-8033a0a4e3aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1072340383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1072340383
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.335704531
Short name T769
Test name
Test status
Simulation time 18364828 ps
CPU time 1.39 seconds
Started Jun 09 12:26:54 PM PDT 24
Finished Jun 09 12:26:56 PM PDT 24
Peak memory 234568 kb
Host smart-f082e307-8236-4f0b-92ea-863435754646
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=335704531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.335704531
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3389074134
Short name T730
Test name
Test status
Simulation time 6274065 ps
CPU time 1.38 seconds
Started Jun 09 12:27:01 PM PDT 24
Finished Jun 09 12:27:03 PM PDT 24
Peak memory 234592 kb
Host smart-b448e747-f738-4282-9dda-58a74ef9fc52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3389074134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3389074134
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.995464364
Short name T749
Test name
Test status
Simulation time 12251305 ps
CPU time 1.68 seconds
Started Jun 09 12:26:50 PM PDT 24
Finished Jun 09 12:26:52 PM PDT 24
Peak memory 235616 kb
Host smart-4e3fda69-c286-43a9-8c52-ac04cd4de3a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=995464364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.995464364
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1845541994
Short name T780
Test name
Test status
Simulation time 23831776 ps
CPU time 1.84 seconds
Started Jun 09 12:26:52 PM PDT 24
Finished Jun 09 12:26:54 PM PDT 24
Peak memory 235600 kb
Host smart-013f3762-bc9e-49cb-99ea-9302db5d1bfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1845541994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1845541994
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.4161118901
Short name T333
Test name
Test status
Simulation time 10259617 ps
CPU time 1.55 seconds
Started Jun 09 12:27:00 PM PDT 24
Finished Jun 09 12:27:02 PM PDT 24
Peak memory 235612 kb
Host smart-d171acfc-bb4e-4530-af66-88f2ffdc7a76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4161118901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.4161118901
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2581912990
Short name T735
Test name
Test status
Simulation time 7293919 ps
CPU time 1.39 seconds
Started Jun 09 12:27:01 PM PDT 24
Finished Jun 09 12:27:03 PM PDT 24
Peak memory 236568 kb
Host smart-e14fe245-0424-4b7b-b87e-898ee8f0a7e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2581912990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2581912990
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.4276564149
Short name T753
Test name
Test status
Simulation time 11205052 ps
CPU time 1.35 seconds
Started Jun 09 12:26:54 PM PDT 24
Finished Jun 09 12:26:56 PM PDT 24
Peak memory 234616 kb
Host smart-ac82c45b-f91d-4442-9c82-4ff69deacd4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4276564149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.4276564149
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.74519681
Short name T334
Test name
Test status
Simulation time 33456558 ps
CPU time 1.24 seconds
Started Jun 09 12:26:49 PM PDT 24
Finished Jun 09 12:26:51 PM PDT 24
Peak memory 236528 kb
Host smart-f1d102ed-b930-4b6b-b6b3-6b27d967aed1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=74519681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.74519681
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2805420532
Short name T803
Test name
Test status
Simulation time 19005941 ps
CPU time 1.49 seconds
Started Jun 09 12:26:55 PM PDT 24
Finished Jun 09 12:26:57 PM PDT 24
Peak memory 236560 kb
Host smart-cd835597-2f81-4051-b11a-7e5586c03a40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2805420532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2805420532
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.184859931
Short name T194
Test name
Test status
Simulation time 13653629949 ps
CPU time 239.27 seconds
Started Jun 09 12:26:20 PM PDT 24
Finished Jun 09 12:30:19 PM PDT 24
Peak memory 240020 kb
Host smart-0cb628bb-3b85-48f4-9820-e4c9a6e61a6b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=184859931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.184859931
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.127378679
Short name T784
Test name
Test status
Simulation time 1722408007 ps
CPU time 199.28 seconds
Started Jun 09 12:26:40 PM PDT 24
Finished Jun 09 12:30:00 PM PDT 24
Peak memory 236440 kb
Host smart-ee1aa64b-65ca-476e-9215-ff915ad3bc1b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=127378679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.127378679
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3327181790
Short name T734
Test name
Test status
Simulation time 54548111 ps
CPU time 4.95 seconds
Started Jun 09 12:26:18 PM PDT 24
Finished Jun 09 12:26:24 PM PDT 24
Peak memory 239964 kb
Host smart-43714d08-2579-4b36-87cc-8b734af48f33
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3327181790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3327181790
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2672776502
Short name T777
Test name
Test status
Simulation time 112357916 ps
CPU time 4.5 seconds
Started Jun 09 12:26:15 PM PDT 24
Finished Jun 09 12:26:21 PM PDT 24
Peak memory 240120 kb
Host smart-ad07c900-4add-4cd7-af73-7324593c4a50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672776502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2672776502
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2799067870
Short name T764
Test name
Test status
Simulation time 63086955 ps
CPU time 5.53 seconds
Started Jun 09 12:26:37 PM PDT 24
Finished Jun 09 12:26:43 PM PDT 24
Peak memory 239864 kb
Host smart-3db212d2-359b-45eb-bfca-73b06d333569
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2799067870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2799067870
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1263201190
Short name T768
Test name
Test status
Simulation time 12305460 ps
CPU time 1.37 seconds
Started Jun 09 12:26:23 PM PDT 24
Finished Jun 09 12:26:25 PM PDT 24
Peak memory 236544 kb
Host smart-fa079d99-a4cd-41ad-b0b1-43fb0754a4d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1263201190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1263201190
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.254629832
Short name T728
Test name
Test status
Simulation time 1115364318 ps
CPU time 19.35 seconds
Started Jun 09 12:26:12 PM PDT 24
Finished Jun 09 12:26:33 PM PDT 24
Peak memory 244728 kb
Host smart-907415ce-c398-43f6-86f3-e62689cf6c6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=254629832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.254629832
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3418690543
Short name T132
Test name
Test status
Simulation time 50792867761 ps
CPU time 927.42 seconds
Started Jun 09 12:26:17 PM PDT 24
Finished Jun 09 12:41:44 PM PDT 24
Peak memory 265200 kb
Host smart-eeeb7927-caba-45c6-8e64-6b0ed0f6e75d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418690543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3418690543
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1162798416
Short name T717
Test name
Test status
Simulation time 297430083 ps
CPU time 10.23 seconds
Started Jun 09 12:26:19 PM PDT 24
Finished Jun 09 12:26:29 PM PDT 24
Peak memory 248224 kb
Host smart-3d3adf05-46d3-44c6-9d32-2ab6d08a8bd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1162798416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1162798416
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3160376426
Short name T824
Test name
Test status
Simulation time 8036146 ps
CPU time 1.34 seconds
Started Jun 09 12:26:59 PM PDT 24
Finished Jun 09 12:27:01 PM PDT 24
Peak memory 235652 kb
Host smart-d0015014-5cfe-443d-ab08-52e94dcf00ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3160376426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3160376426
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3620019915
Short name T791
Test name
Test status
Simulation time 36184721 ps
CPU time 1.48 seconds
Started Jun 09 12:27:04 PM PDT 24
Finished Jun 09 12:27:07 PM PDT 24
Peak memory 236536 kb
Host smart-e54a8057-fa75-46cd-834c-9e6982f9cbea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3620019915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3620019915
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2259807417
Short name T336
Test name
Test status
Simulation time 7715881 ps
CPU time 1.31 seconds
Started Jun 09 12:26:50 PM PDT 24
Finished Jun 09 12:26:52 PM PDT 24
Peak memory 236560 kb
Host smart-80a5183c-728b-4a4b-b951-fd0820c88748
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2259807417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2259807417
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.877258123
Short name T783
Test name
Test status
Simulation time 12295567 ps
CPU time 1.27 seconds
Started Jun 09 12:27:01 PM PDT 24
Finished Jun 09 12:27:03 PM PDT 24
Peak memory 235604 kb
Host smart-e3eeaebe-3732-4286-af24-4cf25dc985eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=877258123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.877258123
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2975530742
Short name T172
Test name
Test status
Simulation time 11423602 ps
CPU time 1.53 seconds
Started Jun 09 12:27:03 PM PDT 24
Finished Jun 09 12:27:06 PM PDT 24
Peak memory 236504 kb
Host smart-5f4e0cca-f6d1-46a4-9e5e-b5e6acfeac80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2975530742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2975530742
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3554622350
Short name T170
Test name
Test status
Simulation time 7977034 ps
CPU time 1.34 seconds
Started Jun 09 12:27:03 PM PDT 24
Finished Jun 09 12:27:05 PM PDT 24
Peak memory 236560 kb
Host smart-a4fac183-f369-4b9b-a7ec-c22af3beb99d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3554622350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3554622350
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2814480222
Short name T811
Test name
Test status
Simulation time 15335212 ps
CPU time 1.25 seconds
Started Jun 09 12:28:19 PM PDT 24
Finished Jun 09 12:28:21 PM PDT 24
Peak memory 235528 kb
Host smart-dcfbd752-97dc-41b4-b41a-83e0f17f85e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2814480222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2814480222
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3874054150
Short name T804
Test name
Test status
Simulation time 10814679 ps
CPU time 1.32 seconds
Started Jun 09 12:26:58 PM PDT 24
Finished Jun 09 12:27:00 PM PDT 24
Peak memory 236544 kb
Host smart-88543f6b-6594-4722-8d38-fd9885d0e4b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3874054150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3874054150
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3452137569
Short name T745
Test name
Test status
Simulation time 7324638 ps
CPU time 1.44 seconds
Started Jun 09 12:26:57 PM PDT 24
Finished Jun 09 12:27:00 PM PDT 24
Peak memory 234576 kb
Host smart-cebabe60-936d-4312-8712-7223d88bdf8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3452137569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3452137569
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2083611086
Short name T756
Test name
Test status
Simulation time 9059654 ps
CPU time 1.2 seconds
Started Jun 09 12:26:55 PM PDT 24
Finished Jun 09 12:26:56 PM PDT 24
Peak memory 236540 kb
Host smart-abe4b930-0b91-4a5a-81f0-3ad21e329b98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2083611086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2083611086
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1306969653
Short name T714
Test name
Test status
Simulation time 75733846 ps
CPU time 5.2 seconds
Started Jun 09 12:26:14 PM PDT 24
Finished Jun 09 12:26:20 PM PDT 24
Peak memory 237612 kb
Host smart-162962dd-dd7d-4e5f-a605-3b1d12d4ee62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306969653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1306969653
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.936050373
Short name T718
Test name
Test status
Simulation time 35569492 ps
CPU time 5.47 seconds
Started Jun 09 12:26:43 PM PDT 24
Finished Jun 09 12:26:49 PM PDT 24
Peak memory 236528 kb
Host smart-56adf785-aab1-46c7-a0b8-300237145531
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=936050373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.936050373
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1306422301
Short name T821
Test name
Test status
Simulation time 16961487 ps
CPU time 1.62 seconds
Started Jun 09 12:26:12 PM PDT 24
Finished Jun 09 12:26:15 PM PDT 24
Peak memory 235616 kb
Host smart-83c6ea87-519f-4f70-9a50-d02813cafd36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1306422301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1306422301
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1877453204
Short name T825
Test name
Test status
Simulation time 174604396 ps
CPU time 23.13 seconds
Started Jun 09 12:26:44 PM PDT 24
Finished Jun 09 12:27:08 PM PDT 24
Peak memory 244744 kb
Host smart-d6892a00-5e92-41f3-a93a-95ed6a71f67e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1877453204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.1877453204
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3853376746
Short name T151
Test name
Test status
Simulation time 3563028436 ps
CPU time 176 seconds
Started Jun 09 12:26:11 PM PDT 24
Finished Jun 09 12:29:08 PM PDT 24
Peak memory 264908 kb
Host smart-2d31c6d5-a2b6-42b5-ad3b-c3c9781552d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3853376746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3853376746
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.739999922
Short name T705
Test name
Test status
Simulation time 285133775 ps
CPU time 6.9 seconds
Started Jun 09 12:26:32 PM PDT 24
Finished Jun 09 12:26:39 PM PDT 24
Peak memory 247620 kb
Host smart-552e88d1-4e8f-4d99-9334-2d27815a15fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=739999922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.739999922
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.728555960
Short name T725
Test name
Test status
Simulation time 67291310 ps
CPU time 9.46 seconds
Started Jun 09 12:26:32 PM PDT 24
Finished Jun 09 12:26:41 PM PDT 24
Peak memory 253984 kb
Host smart-d7910d50-66a3-45c3-8e0d-8a6611d1d0d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728555960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.alert_handler_csr_mem_rw_with_rand_reset.728555960
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3530965693
Short name T786
Test name
Test status
Simulation time 63047917 ps
CPU time 4.78 seconds
Started Jun 09 12:26:46 PM PDT 24
Finished Jun 09 12:26:51 PM PDT 24
Peak memory 239296 kb
Host smart-24363116-76f7-468c-ac11-b848d3cb6c4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3530965693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3530965693
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1179807025
Short name T330
Test name
Test status
Simulation time 10422649 ps
CPU time 1.5 seconds
Started Jun 09 12:26:21 PM PDT 24
Finished Jun 09 12:26:23 PM PDT 24
Peak memory 235640 kb
Host smart-6fa3bb76-f03d-4745-9ac4-9d399ef420bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1179807025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1179807025
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2480680699
Short name T722
Test name
Test status
Simulation time 709144935 ps
CPU time 36.31 seconds
Started Jun 09 12:26:12 PM PDT 24
Finished Jun 09 12:26:50 PM PDT 24
Peak memory 248160 kb
Host smart-0a8c7d57-f0be-41f9-b851-859cf54fdbb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2480680699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2480680699
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.715897463
Short name T149
Test name
Test status
Simulation time 1544731076 ps
CPU time 155.54 seconds
Started Jun 09 12:26:14 PM PDT 24
Finished Jun 09 12:28:51 PM PDT 24
Peak memory 265856 kb
Host smart-49736f3c-d005-4dca-894d-1b9d66312df6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=715897463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.715897463
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1527701359
Short name T154
Test name
Test status
Simulation time 23912928997 ps
CPU time 457.83 seconds
Started Jun 09 12:26:14 PM PDT 24
Finished Jun 09 12:33:53 PM PDT 24
Peak memory 268524 kb
Host smart-61fd69cb-2dd3-4345-aff0-3b7a4cc2a102
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527701359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1527701359
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.215001136
Short name T729
Test name
Test status
Simulation time 439146351 ps
CPU time 26.91 seconds
Started Jun 09 12:26:09 PM PDT 24
Finished Jun 09 12:26:36 PM PDT 24
Peak memory 248160 kb
Host smart-fc6e1218-161d-4b2c-85ca-98114bfc03ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=215001136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.215001136
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.282325740
Short name T181
Test name
Test status
Simulation time 128558445 ps
CPU time 2.1 seconds
Started Jun 09 12:26:09 PM PDT 24
Finished Jun 09 12:26:12 PM PDT 24
Peak memory 236440 kb
Host smart-d3277237-fe7d-4a09-aac3-cf15656bd4c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=282325740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.282325740
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3033033972
Short name T789
Test name
Test status
Simulation time 131831590 ps
CPU time 4.67 seconds
Started Jun 09 12:26:14 PM PDT 24
Finished Jun 09 12:26:20 PM PDT 24
Peak memory 255616 kb
Host smart-6725823f-f3cc-4dfd-837d-5e2d03eb11d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033033972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3033033972
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1305654823
Short name T747
Test name
Test status
Simulation time 64026047 ps
CPU time 3.16 seconds
Started Jun 09 12:26:15 PM PDT 24
Finished Jun 09 12:26:19 PM PDT 24
Peak memory 236528 kb
Host smart-a4d2a5b6-618d-42a7-9c9c-57d5e5d62f3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1305654823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1305654823
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3129793134
Short name T736
Test name
Test status
Simulation time 8893441 ps
CPU time 1.52 seconds
Started Jun 09 12:26:45 PM PDT 24
Finished Jun 09 12:26:47 PM PDT 24
Peak memory 236544 kb
Host smart-123ed320-08f2-48b3-ac8e-4aa19da19be5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3129793134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3129793134
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2271912218
Short name T778
Test name
Test status
Simulation time 2117061310 ps
CPU time 19.63 seconds
Started Jun 09 12:26:15 PM PDT 24
Finished Jun 09 12:26:36 PM PDT 24
Peak memory 243756 kb
Host smart-3be511f3-2ba0-4837-91eb-fcbe0e2760d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2271912218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2271912218
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1002732154
Short name T153
Test name
Test status
Simulation time 2853803370 ps
CPU time 84.02 seconds
Started Jun 09 12:26:26 PM PDT 24
Finished Jun 09 12:27:50 PM PDT 24
Peak memory 264960 kb
Host smart-7be8cec7-2c16-4d45-be85-b979177dfdab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1002732154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1002732154
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3618821096
Short name T819
Test name
Test status
Simulation time 68864840 ps
CPU time 9.33 seconds
Started Jun 09 12:26:36 PM PDT 24
Finished Jun 09 12:26:46 PM PDT 24
Peak memory 248396 kb
Host smart-8b2bf078-e52d-4312-a9de-fc7946b07150
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3618821096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3618821096
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3269360124
Short name T772
Test name
Test status
Simulation time 123991794 ps
CPU time 7.97 seconds
Started Jun 09 12:26:14 PM PDT 24
Finished Jun 09 12:26:23 PM PDT 24
Peak memory 250676 kb
Host smart-a24131b2-9fa1-4fbb-873b-43edd61662a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269360124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3269360124
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2888523560
Short name T737
Test name
Test status
Simulation time 196549873 ps
CPU time 9.07 seconds
Started Jun 09 12:26:14 PM PDT 24
Finished Jun 09 12:26:25 PM PDT 24
Peak memory 236536 kb
Host smart-5f2d6341-f668-452f-8f1c-9668031ac298
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2888523560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2888523560
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2399606768
Short name T754
Test name
Test status
Simulation time 10241699 ps
CPU time 1.57 seconds
Started Jun 09 12:26:12 PM PDT 24
Finished Jun 09 12:26:15 PM PDT 24
Peak memory 236544 kb
Host smart-594fbe74-cb6a-4d00-b89d-77607ed08e24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2399606768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2399606768
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2695984059
Short name T822
Test name
Test status
Simulation time 1079185825 ps
CPU time 18.42 seconds
Started Jun 09 12:26:41 PM PDT 24
Finished Jun 09 12:27:00 PM PDT 24
Peak memory 240196 kb
Host smart-726a78d1-1a3e-4cfc-9d2b-a3fe1af00195
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2695984059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2695984059
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3378479812
Short name T164
Test name
Test status
Simulation time 9654695211 ps
CPU time 283.49 seconds
Started Jun 09 12:26:39 PM PDT 24
Finished Jun 09 12:31:23 PM PDT 24
Peak memory 266316 kb
Host smart-d78e119a-ce74-4010-b6c7-44bf23baf84b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3378479812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3378479812
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3683412895
Short name T159
Test name
Test status
Simulation time 17184094098 ps
CPU time 616.03 seconds
Started Jun 09 12:26:22 PM PDT 24
Finished Jun 09 12:36:38 PM PDT 24
Peak memory 264984 kb
Host smart-e7cecf57-0ba2-4f85-b115-62af3c0d71cd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683412895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3683412895
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.913408891
Short name T802
Test name
Test status
Simulation time 195269317 ps
CPU time 5.39 seconds
Started Jun 09 12:26:16 PM PDT 24
Finished Jun 09 12:26:22 PM PDT 24
Peak memory 251372 kb
Host smart-14c2bdc8-243b-49aa-809e-07fab7fbd129
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=913408891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.913408891
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3304370329
Short name T807
Test name
Test status
Simulation time 153211384 ps
CPU time 8.1 seconds
Started Jun 09 12:26:17 PM PDT 24
Finished Jun 09 12:26:26 PM PDT 24
Peak memory 239572 kb
Host smart-9ca655e5-a771-4516-9539-556335f66370
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304370329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3304370329
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1692564717
Short name T706
Test name
Test status
Simulation time 60077534 ps
CPU time 4.68 seconds
Started Jun 09 12:26:22 PM PDT 24
Finished Jun 09 12:26:27 PM PDT 24
Peak memory 239296 kb
Host smart-ace7d06b-57d7-4651-b26d-e463b99941f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1692564717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1692564717
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1884264081
Short name T762
Test name
Test status
Simulation time 14205981 ps
CPU time 1.48 seconds
Started Jun 09 12:26:27 PM PDT 24
Finished Jun 09 12:26:29 PM PDT 24
Peak memory 235604 kb
Host smart-1905b480-967f-4674-a6dd-14c1fb1546bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1884264081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1884264081
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3946082070
Short name T809
Test name
Test status
Simulation time 766138573 ps
CPU time 23.12 seconds
Started Jun 09 12:26:14 PM PDT 24
Finished Jun 09 12:26:39 PM PDT 24
Peak memory 244712 kb
Host smart-84c760c0-5c88-42e4-a884-51f4674a9cd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3946082070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.3946082070
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2602987441
Short name T163
Test name
Test status
Simulation time 11860734919 ps
CPU time 864.32 seconds
Started Jun 09 12:26:26 PM PDT 24
Finished Jun 09 12:40:50 PM PDT 24
Peak memory 272912 kb
Host smart-67314f11-98e1-4750-91f2-4bed814e2209
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602987441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2602987441
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.789505444
Short name T798
Test name
Test status
Simulation time 624571242 ps
CPU time 13.43 seconds
Started Jun 09 12:26:17 PM PDT 24
Finished Jun 09 12:26:31 PM PDT 24
Peak memory 256384 kb
Host smart-d6798818-8685-4197-b338-db55d79c5754
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=789505444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.789505444
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1851620535
Short name T201
Test name
Test status
Simulation time 189797029 ps
CPU time 3.33 seconds
Started Jun 09 12:26:16 PM PDT 24
Finished Jun 09 12:26:20 PM PDT 24
Peak memory 235596 kb
Host smart-ec6f28fb-7cda-4bbf-8a76-a3fc58bd7f93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1851620535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1851620535
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3063161771
Short name T617
Test name
Test status
Simulation time 44526022661 ps
CPU time 1052.93 seconds
Started Jun 09 12:37:35 PM PDT 24
Finished Jun 09 12:55:08 PM PDT 24
Peak memory 273240 kb
Host smart-3fb1bdb1-d5f0-4b7f-93ff-3c08a5038a02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063161771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3063161771
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.214810200
Short name T446
Test name
Test status
Simulation time 5963754565 ps
CPU time 342.12 seconds
Started Jun 09 12:37:44 PM PDT 24
Finished Jun 09 12:43:30 PM PDT 24
Peak memory 251000 kb
Host smart-f3484d9d-e619-4c16-b5f8-6a8ffe8cfd42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21481
0200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.214810200
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3669747553
Short name T509
Test name
Test status
Simulation time 420060369 ps
CPU time 41.12 seconds
Started Jun 09 12:37:36 PM PDT 24
Finished Jun 09 12:38:18 PM PDT 24
Peak memory 255704 kb
Host smart-147ebfad-0f5b-45d7-9c34-34e4e55da2e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36697
47553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3669747553
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2444655231
Short name T269
Test name
Test status
Simulation time 27727206996 ps
CPU time 1127.41 seconds
Started Jun 09 12:37:35 PM PDT 24
Finished Jun 09 12:56:23 PM PDT 24
Peak memory 288612 kb
Host smart-fb50f431-6578-42ea-9a69-febb3d691dd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444655231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2444655231
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1258461764
Short name T547
Test name
Test status
Simulation time 90603878978 ps
CPU time 1308.94 seconds
Started Jun 09 12:37:40 PM PDT 24
Finished Jun 09 12:59:30 PM PDT 24
Peak memory 267252 kb
Host smart-a73c03f5-7cc4-4955-bb2c-22f7a02a0053
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258461764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1258461764
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3237825438
Short name T360
Test name
Test status
Simulation time 2038181949 ps
CPU time 65.63 seconds
Started Jun 09 12:37:32 PM PDT 24
Finished Jun 09 12:38:38 PM PDT 24
Peak memory 255956 kb
Host smart-4ac3b444-2894-4ce5-a032-14766005b0a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32378
25438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3237825438
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3650909113
Short name T651
Test name
Test status
Simulation time 839309862 ps
CPU time 50.07 seconds
Started Jun 09 12:37:37 PM PDT 24
Finished Jun 09 12:38:28 PM PDT 24
Peak memory 256780 kb
Host smart-ae785115-454e-4c77-be08-8ba26fea28cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36509
09113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3650909113
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2668161544
Short name T351
Test name
Test status
Simulation time 29505834 ps
CPU time 3.84 seconds
Started Jun 09 12:37:36 PM PDT 24
Finished Jun 09 12:37:40 PM PDT 24
Peak memory 239308 kb
Host smart-416bdac8-7b5a-4697-8087-43751607bcf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26681
61544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2668161544
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.175084869
Short name T505
Test name
Test status
Simulation time 293007156 ps
CPU time 9.41 seconds
Started Jun 09 12:37:36 PM PDT 24
Finished Jun 09 12:37:47 PM PDT 24
Peak memory 248700 kb
Host smart-fd0da5b5-be87-461b-a1dd-1a11a1f7f415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17508
4869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.175084869
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3176731173
Short name T644
Test name
Test status
Simulation time 220365462858 ps
CPU time 3077.66 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 01:29:07 PM PDT 24
Peak memory 297240 kb
Host smart-5c7f4c28-30cc-4af9-8c38-d414a3910e1f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176731173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3176731173
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3255652829
Short name T44
Test name
Test status
Simulation time 18495676055 ps
CPU time 616.64 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 12:48:02 PM PDT 24
Peak memory 265120 kb
Host smart-f007ce01-757b-46fb-a8fa-fa1012b912c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255652829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3255652829
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.605659335
Short name T193
Test name
Test status
Simulation time 3635354195 ps
CPU time 12.56 seconds
Started Jun 09 12:37:36 PM PDT 24
Finished Jun 09 12:37:49 PM PDT 24
Peak memory 248756 kb
Host smart-78ea675f-8826-4963-a2b5-fb3a42f927a4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=605659335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.605659335
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.619001606
Short name T564
Test name
Test status
Simulation time 7588304508 ps
CPU time 170.44 seconds
Started Jun 09 12:37:41 PM PDT 24
Finished Jun 09 12:40:33 PM PDT 24
Peak memory 251368 kb
Host smart-dcee192e-aa06-461d-a5c9-bbf6c43963bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61900
1606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.619001606
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.997899955
Short name T432
Test name
Test status
Simulation time 228166500 ps
CPU time 25.4 seconds
Started Jun 09 12:37:38 PM PDT 24
Finished Jun 09 12:38:04 PM PDT 24
Peak memory 248852 kb
Host smart-f3ebb633-1feb-498e-a436-3d5650257376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99789
9955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.997899955
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1726072116
Short name T657
Test name
Test status
Simulation time 18116940311 ps
CPU time 1482.89 seconds
Started Jun 09 12:37:37 PM PDT 24
Finished Jun 09 01:02:21 PM PDT 24
Peak memory 289036 kb
Host smart-46a70f03-b059-4c00-9752-f8e7a479d06a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726072116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1726072116
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2851769600
Short name T485
Test name
Test status
Simulation time 21659060470 ps
CPU time 201.62 seconds
Started Jun 09 12:37:34 PM PDT 24
Finished Jun 09 12:40:56 PM PDT 24
Peak memory 248536 kb
Host smart-f666cda9-cfe4-40ad-988d-3db80a48c35d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851769600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2851769600
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1844352933
Short name T397
Test name
Test status
Simulation time 845630971 ps
CPU time 27.62 seconds
Started Jun 09 12:37:33 PM PDT 24
Finished Jun 09 12:38:01 PM PDT 24
Peak memory 256864 kb
Host smart-36068495-be1e-4dee-8156-61a425e85f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18443
52933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1844352933
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2025873580
Short name T106
Test name
Test status
Simulation time 178408736 ps
CPU time 4.1 seconds
Started Jun 09 12:37:35 PM PDT 24
Finished Jun 09 12:37:40 PM PDT 24
Peak memory 251740 kb
Host smart-e018b347-7b4c-4013-afff-03a90e6f8b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20258
73580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2025873580
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1788786475
Short name T29
Test name
Test status
Simulation time 356529492 ps
CPU time 19.47 seconds
Started Jun 09 12:37:36 PM PDT 24
Finished Jun 09 12:37:56 PM PDT 24
Peak memory 277248 kb
Host smart-75f16807-e5af-4b9f-ae30-b803934b8b02
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1788786475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1788786475
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2455489606
Short name T27
Test name
Test status
Simulation time 376178832 ps
CPU time 12.28 seconds
Started Jun 09 12:37:39 PM PDT 24
Finished Jun 09 12:37:52 PM PDT 24
Peak memory 248828 kb
Host smart-91897cc6-33ea-43c7-9980-b174633ca9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24554
89606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2455489606
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2327625168
Short name T625
Test name
Test status
Simulation time 181166674435 ps
CPU time 2698.86 seconds
Started Jun 09 12:37:33 PM PDT 24
Finished Jun 09 01:22:32 PM PDT 24
Peak memory 289024 kb
Host smart-0c6dbe32-8d6a-4cf7-b2ac-23e9e43aca95
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327625168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2327625168
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1971246287
Short name T35
Test name
Test status
Simulation time 75729340192 ps
CPU time 1965.43 seconds
Started Jun 09 12:37:44 PM PDT 24
Finished Jun 09 01:10:30 PM PDT 24
Peak memory 282572 kb
Host smart-eee1a7ba-6cde-4e4b-90d4-1687dc829499
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971246287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1971246287
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.578811127
Short name T410
Test name
Test status
Simulation time 670179416 ps
CPU time 15.21 seconds
Started Jun 09 12:37:46 PM PDT 24
Finished Jun 09 12:38:03 PM PDT 24
Peak memory 248640 kb
Host smart-e50726c8-4712-4f34-ab49-757a4d2e2458
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=578811127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.578811127
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.521760895
Short name T355
Test name
Test status
Simulation time 20255149034 ps
CPU time 267.57 seconds
Started Jun 09 12:37:45 PM PDT 24
Finished Jun 09 12:42:13 PM PDT 24
Peak memory 256908 kb
Host smart-0b9a5912-4a6a-4cfa-b098-f904ce0d23a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52176
0895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.521760895
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2592326021
Short name T540
Test name
Test status
Simulation time 636633858 ps
CPU time 14.15 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 12:37:58 PM PDT 24
Peak memory 255684 kb
Host smart-11838164-9ddd-4805-97f8-7f40d5f9bb68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25923
26021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2592326021
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2154159915
Short name T313
Test name
Test status
Simulation time 8345342208 ps
CPU time 780.14 seconds
Started Jun 09 12:37:45 PM PDT 24
Finished Jun 09 12:50:46 PM PDT 24
Peak memory 265204 kb
Host smart-22215e07-e1b1-4fdc-a4cd-72f9b843a15c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154159915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2154159915
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2412410935
Short name T393
Test name
Test status
Simulation time 213744102386 ps
CPU time 1983.09 seconds
Started Jun 09 12:37:59 PM PDT 24
Finished Jun 09 01:11:03 PM PDT 24
Peak memory 285892 kb
Host smart-1ee63c93-e18f-4406-bd7e-cd8e85205cea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412410935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2412410935
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1907483689
Short name T288
Test name
Test status
Simulation time 9490428367 ps
CPU time 378.07 seconds
Started Jun 09 12:37:37 PM PDT 24
Finished Jun 09 12:43:56 PM PDT 24
Peak memory 254188 kb
Host smart-fe1c667d-2e4a-4f68-adf6-a67650fe65c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907483689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1907483689
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.743354929
Short name T516
Test name
Test status
Simulation time 438788909 ps
CPU time 26.32 seconds
Started Jun 09 12:37:32 PM PDT 24
Finished Jun 09 12:37:58 PM PDT 24
Peak memory 248696 kb
Host smart-dc9f0a2a-0350-49d0-bec7-718dcf162d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74335
4929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.743354929
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3479937177
Short name T501
Test name
Test status
Simulation time 704161163 ps
CPU time 42.75 seconds
Started Jun 09 12:37:44 PM PDT 24
Finished Jun 09 12:38:28 PM PDT 24
Peak memory 256776 kb
Host smart-61a4e48d-4c72-45f2-8b74-d55fc7182a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34799
37177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3479937177
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.386651782
Short name T356
Test name
Test status
Simulation time 898570141 ps
CPU time 28.03 seconds
Started Jun 09 12:37:47 PM PDT 24
Finished Jun 09 12:38:16 PM PDT 24
Peak memory 248252 kb
Host smart-6db030e1-cd7a-482e-9b2a-0def8be62ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38665
1782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.386651782
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1898602597
Short name T1
Test name
Test status
Simulation time 3363447938 ps
CPU time 40.26 seconds
Started Jun 09 12:37:35 PM PDT 24
Finished Jun 09 12:38:16 PM PDT 24
Peak memory 256944 kb
Host smart-9f8ef2f2-3e6b-40e9-9429-793a669b30c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18986
02597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1898602597
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.3793558698
Short name T73
Test name
Test status
Simulation time 32967866600 ps
CPU time 655.58 seconds
Started Jun 09 12:37:38 PM PDT 24
Finished Jun 09 12:48:34 PM PDT 24
Peak memory 267940 kb
Host smart-2c8d5794-4b95-4ea5-bd6f-12aca994ddd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793558698 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.3793558698
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2634333949
Short name T572
Test name
Test status
Simulation time 19143592296 ps
CPU time 1471.72 seconds
Started Jun 09 12:37:38 PM PDT 24
Finished Jun 09 01:02:10 PM PDT 24
Peak memory 289464 kb
Host smart-014e34ed-3b66-4abf-97db-a2dc822e89c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634333949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2634333949
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.314716143
Short name T688
Test name
Test status
Simulation time 1053765643 ps
CPU time 45.66 seconds
Started Jun 09 12:37:45 PM PDT 24
Finished Jun 09 12:38:32 PM PDT 24
Peak memory 248724 kb
Host smart-69a030e8-5b63-4b6b-9ede-d3fe0235817f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=314716143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.314716143
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3965956647
Short name T679
Test name
Test status
Simulation time 9194577650 ps
CPU time 132.02 seconds
Started Jun 09 12:37:38 PM PDT 24
Finished Jun 09 12:39:51 PM PDT 24
Peak memory 249284 kb
Host smart-bfb4df32-05f4-4946-8fcd-7c56e5ef8efc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39659
56647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3965956647
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3086845670
Short name T613
Test name
Test status
Simulation time 1440625213 ps
CPU time 40.27 seconds
Started Jun 09 12:37:50 PM PDT 24
Finished Jun 09 12:38:31 PM PDT 24
Peak memory 248632 kb
Host smart-60d6f70a-ae53-4241-934b-270d8fbed3bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30868
45670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3086845670
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.944846665
Short name T273
Test name
Test status
Simulation time 53557912466 ps
CPU time 1147.83 seconds
Started Jun 09 12:37:46 PM PDT 24
Finished Jun 09 12:56:55 PM PDT 24
Peak memory 271940 kb
Host smart-6148ad3f-06a2-48c1-82e1-626cfcd2d374
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944846665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.944846665
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.692370974
Short name T444
Test name
Test status
Simulation time 136721843994 ps
CPU time 1635.88 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 01:05:00 PM PDT 24
Peak memory 269236 kb
Host smart-86696e52-bb95-48aa-871b-2bc3897c60c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692370974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.692370974
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.566506481
Short name T282
Test name
Test status
Simulation time 8762553032 ps
CPU time 91.63 seconds
Started Jun 09 12:37:37 PM PDT 24
Finished Jun 09 12:39:09 PM PDT 24
Peak memory 248132 kb
Host smart-50130802-f2c5-48df-a287-c84239fb9292
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566506481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.566506481
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.626484747
Short name T620
Test name
Test status
Simulation time 773625759 ps
CPU time 38.47 seconds
Started Jun 09 12:37:45 PM PDT 24
Finished Jun 09 12:38:24 PM PDT 24
Peak memory 248824 kb
Host smart-5b9fe41b-11bf-4f1d-af04-315c0ba81af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62648
4747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.626484747
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3803010079
Short name T378
Test name
Test status
Simulation time 335610750 ps
CPU time 12.86 seconds
Started Jun 09 12:38:06 PM PDT 24
Finished Jun 09 12:38:20 PM PDT 24
Peak memory 254108 kb
Host smart-fabc2108-f1df-46bf-95dc-773859b8e475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38030
10079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3803010079
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.74826917
Short name T243
Test name
Test status
Simulation time 1387843179 ps
CPU time 22.39 seconds
Started Jun 09 12:37:37 PM PDT 24
Finished Jun 09 12:38:00 PM PDT 24
Peak memory 255476 kb
Host smart-b8b89c0d-49c9-4802-80fd-c5363846827e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74826
917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.74826917
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.4110158147
Short name T507
Test name
Test status
Simulation time 226451878 ps
CPU time 7 seconds
Started Jun 09 12:37:34 PM PDT 24
Finished Jun 09 12:37:41 PM PDT 24
Peak memory 254120 kb
Host smart-78140e3a-4a3b-4591-935d-2f45f0308e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41101
58147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.4110158147
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2635864412
Short name T458
Test name
Test status
Simulation time 262746877253 ps
CPU time 3302.21 seconds
Started Jun 09 12:37:48 PM PDT 24
Finished Jun 09 01:32:56 PM PDT 24
Peak memory 289452 kb
Host smart-0b3869d2-72bf-40ae-b77b-b26596aa010f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635864412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2635864412
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.168527147
Short name T206
Test name
Test status
Simulation time 323853273 ps
CPU time 3.23 seconds
Started Jun 09 12:37:38 PM PDT 24
Finished Jun 09 12:37:42 PM PDT 24
Peak memory 248804 kb
Host smart-d662565a-be7f-41d0-b7e1-f4319ce5a44a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=168527147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.168527147
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1429365346
Short name T349
Test name
Test status
Simulation time 3880388609 ps
CPU time 44.46 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 12:38:30 PM PDT 24
Peak memory 248756 kb
Host smart-5d706273-9e04-41ae-97e0-e994be2d62a1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1429365346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1429365346
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2627025958
Short name T543
Test name
Test status
Simulation time 2619802757 ps
CPU time 36.29 seconds
Started Jun 09 12:38:08 PM PDT 24
Finished Jun 09 12:38:45 PM PDT 24
Peak memory 256204 kb
Host smart-0626b7d0-3f60-42d8-b7fb-2a1141973814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26270
25958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2627025958
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2855862299
Short name T552
Test name
Test status
Simulation time 202323194 ps
CPU time 5.84 seconds
Started Jun 09 12:37:49 PM PDT 24
Finished Jun 09 12:37:55 PM PDT 24
Peak memory 247384 kb
Host smart-e05bb1d0-39d6-4c64-977c-ae5b6a05d7ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28558
62299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2855862299
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3234852690
Short name T656
Test name
Test status
Simulation time 74669490214 ps
CPU time 1540.27 seconds
Started Jun 09 12:37:46 PM PDT 24
Finished Jun 09 01:03:28 PM PDT 24
Peak memory 273380 kb
Host smart-a2442bfb-d40d-4e90-81e4-2c9c143779c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234852690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3234852690
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1914624793
Short name T357
Test name
Test status
Simulation time 28216904044 ps
CPU time 1553.3 seconds
Started Jun 09 12:37:41 PM PDT 24
Finished Jun 09 01:03:36 PM PDT 24
Peak memory 272704 kb
Host smart-0f63c527-afdb-45bd-aec0-52087e5f1fdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914624793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1914624793
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1379544533
Short name T297
Test name
Test status
Simulation time 25904585443 ps
CPU time 303.02 seconds
Started Jun 09 12:37:49 PM PDT 24
Finished Jun 09 12:42:52 PM PDT 24
Peak memory 248368 kb
Host smart-5e04a656-1ef4-4729-9616-58635e236b9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379544533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1379544533
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.800535542
Short name T265
Test name
Test status
Simulation time 128704353 ps
CPU time 10.18 seconds
Started Jun 09 12:37:39 PM PDT 24
Finished Jun 09 12:37:50 PM PDT 24
Peak memory 254356 kb
Host smart-7db80e2f-809e-418a-86c4-c3bb9db00d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80053
5542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.800535542
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3612711315
Short name T358
Test name
Test status
Simulation time 875147020 ps
CPU time 55.35 seconds
Started Jun 09 12:37:40 PM PDT 24
Finished Jun 09 12:38:36 PM PDT 24
Peak memory 248772 kb
Host smart-945babf0-34bb-4ea3-96ae-33abc2f18e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36127
11315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3612711315
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2445510984
Short name T39
Test name
Test status
Simulation time 949454146 ps
CPU time 27.74 seconds
Started Jun 09 12:37:38 PM PDT 24
Finished Jun 09 12:38:07 PM PDT 24
Peak memory 248676 kb
Host smart-f6940c57-7277-48d7-98c9-f3b24a180366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24455
10984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2445510984
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2134044114
Short name T479
Test name
Test status
Simulation time 905163477 ps
CPU time 33 seconds
Started Jun 09 12:38:04 PM PDT 24
Finished Jun 09 12:38:37 PM PDT 24
Peak memory 256700 kb
Host smart-dc572bb4-58e1-42ba-afe7-5d47d15e896c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21340
44114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2134044114
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1545976201
Short name T696
Test name
Test status
Simulation time 1418590773 ps
CPU time 27.93 seconds
Started Jun 09 12:37:33 PM PDT 24
Finished Jun 09 12:38:01 PM PDT 24
Peak memory 255448 kb
Host smart-d4d9a01a-5e79-4dc7-b2b2-10f1c635251d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545976201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1545976201
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.270583518
Short name T215
Test name
Test status
Simulation time 15218247 ps
CPU time 2.37 seconds
Started Jun 09 12:37:38 PM PDT 24
Finished Jun 09 12:37:42 PM PDT 24
Peak memory 248856 kb
Host smart-98253361-6074-49d0-a408-06512fdf0a79
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=270583518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.270583518
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2774030967
Short name T635
Test name
Test status
Simulation time 11273877563 ps
CPU time 1042.82 seconds
Started Jun 09 12:37:36 PM PDT 24
Finished Jun 09 12:55:00 PM PDT 24
Peak memory 281824 kb
Host smart-ef89c8de-f0dc-4ab9-93f3-72f42b9684e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774030967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2774030967
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3955751449
Short name T66
Test name
Test status
Simulation time 169424754 ps
CPU time 10.07 seconds
Started Jun 09 12:38:06 PM PDT 24
Finished Jun 09 12:38:16 PM PDT 24
Peak memory 251508 kb
Host smart-c2225034-8c6e-4750-ba96-14ae2cb1aab0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3955751449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3955751449
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.4026614633
Short name T116
Test name
Test status
Simulation time 912846074 ps
CPU time 52.5 seconds
Started Jun 09 12:37:53 PM PDT 24
Finished Jun 09 12:38:46 PM PDT 24
Peak memory 256148 kb
Host smart-cb3d9440-0fd6-4d96-b443-bc5ed3a42d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40266
14633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.4026614633
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1039472186
Short name T46
Test name
Test status
Simulation time 208208171 ps
CPU time 11.03 seconds
Started Jun 09 12:37:33 PM PDT 24
Finished Jun 09 12:37:44 PM PDT 24
Peak memory 248644 kb
Host smart-23c9ffff-0967-48a9-a8d9-9d15ba6060c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10394
72186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1039472186
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2659844968
Short name T328
Test name
Test status
Simulation time 131017312477 ps
CPU time 1440.05 seconds
Started Jun 09 12:37:45 PM PDT 24
Finished Jun 09 01:01:48 PM PDT 24
Peak memory 288952 kb
Host smart-9d0e1941-bcd3-4729-a1f9-e34f38b2b8df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659844968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2659844968
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.4083184717
Short name T257
Test name
Test status
Simulation time 178137778369 ps
CPU time 2517.1 seconds
Started Jun 09 12:37:39 PM PDT 24
Finished Jun 09 01:19:37 PM PDT 24
Peak memory 289104 kb
Host smart-0edde64b-c3d0-42c3-bbe8-360ea9248bfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083184717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.4083184717
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1919086953
Short name T574
Test name
Test status
Simulation time 36152320300 ps
CPU time 378.21 seconds
Started Jun 09 12:37:47 PM PDT 24
Finished Jun 09 12:44:06 PM PDT 24
Peak memory 255212 kb
Host smart-c7b97f9c-aada-4701-bde4-4d3efc2458d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919086953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1919086953
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2242352192
Short name T49
Test name
Test status
Simulation time 1554403509 ps
CPU time 36.67 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 12:38:20 PM PDT 24
Peak memory 255980 kb
Host smart-94d35316-46cc-4a1d-b248-ac24e1fc677b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22423
52192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2242352192
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.886982238
Short name T398
Test name
Test status
Simulation time 1543379253 ps
CPU time 22.2 seconds
Started Jun 09 12:37:38 PM PDT 24
Finished Jun 09 12:38:01 PM PDT 24
Peak memory 248624 kb
Host smart-1ce0f858-be9a-43f1-abcf-ce21243b589a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88698
2238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.886982238
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.571034383
Short name T78
Test name
Test status
Simulation time 1203755019 ps
CPU time 34.09 seconds
Started Jun 09 12:37:46 PM PDT 24
Finished Jun 09 12:38:21 PM PDT 24
Peak memory 255180 kb
Host smart-3dade6f6-f8e6-4d43-9ea5-90ccefa55a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57103
4383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.571034383
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1634839439
Short name T618
Test name
Test status
Simulation time 327670135 ps
CPU time 13.2 seconds
Started Jun 09 12:37:45 PM PDT 24
Finished Jun 09 12:38:01 PM PDT 24
Peak memory 248700 kb
Host smart-30a6ea56-6e1a-4c6b-ad5b-f81656407bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16348
39439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1634839439
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3657156678
Short name T548
Test name
Test status
Simulation time 110239598012 ps
CPU time 3075.45 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 01:29:00 PM PDT 24
Peak memory 297364 kb
Host smart-17fadd8a-26c8-4816-9d42-406726511fdd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657156678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3657156678
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3706034274
Short name T216
Test name
Test status
Simulation time 802120319 ps
CPU time 4.14 seconds
Started Jun 09 12:37:47 PM PDT 24
Finished Jun 09 12:37:52 PM PDT 24
Peak memory 248816 kb
Host smart-883958b5-405b-4f79-8432-41ac4a2cca5d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3706034274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3706034274
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2409112372
Short name T663
Test name
Test status
Simulation time 8796820100 ps
CPU time 885.71 seconds
Started Jun 09 12:37:41 PM PDT 24
Finished Jun 09 12:52:27 PM PDT 24
Peak memory 269180 kb
Host smart-f3396542-20e1-4e7f-9088-53b5261b732e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409112372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2409112372
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.518481703
Short name T565
Test name
Test status
Simulation time 683915957 ps
CPU time 30.48 seconds
Started Jun 09 12:37:39 PM PDT 24
Finished Jun 09 12:38:10 PM PDT 24
Peak memory 248628 kb
Host smart-94fa673f-5a96-4aa2-aedd-bdf3e99097fa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=518481703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.518481703
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.6591539
Short name T119
Test name
Test status
Simulation time 881494009 ps
CPU time 80.18 seconds
Started Jun 09 12:37:47 PM PDT 24
Finished Jun 09 12:39:08 PM PDT 24
Peak memory 248800 kb
Host smart-911b2577-609a-4372-9367-ccfa913d4197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65915
39 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.6591539
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2315095783
Short name T584
Test name
Test status
Simulation time 381025275 ps
CPU time 28.06 seconds
Started Jun 09 12:37:41 PM PDT 24
Finished Jun 09 12:38:10 PM PDT 24
Peak memory 255012 kb
Host smart-d027c6bf-6861-412d-872e-69d9d3d07630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23150
95783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2315095783
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.697845973
Short name T698
Test name
Test status
Simulation time 18087637523 ps
CPU time 1336.47 seconds
Started Jun 09 12:37:39 PM PDT 24
Finished Jun 09 12:59:56 PM PDT 24
Peak memory 289004 kb
Host smart-8c50e1c9-2d3f-4a34-a8e5-1003114e51eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697845973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.697845973
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3473980303
Short name T623
Test name
Test status
Simulation time 31115354099 ps
CPU time 321.87 seconds
Started Jun 09 12:37:36 PM PDT 24
Finished Jun 09 12:42:59 PM PDT 24
Peak memory 248312 kb
Host smart-5ae43c69-52dd-4cbd-ad3f-7897215f53f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473980303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3473980303
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3889900322
Short name T424
Test name
Test status
Simulation time 479595350 ps
CPU time 19.31 seconds
Started Jun 09 12:37:46 PM PDT 24
Finished Jun 09 12:38:06 PM PDT 24
Peak memory 248704 kb
Host smart-aa7e29de-4718-4a6a-ba9d-80183e7cb595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38899
00322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3889900322
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1721408942
Short name T415
Test name
Test status
Simulation time 309257846 ps
CPU time 26.91 seconds
Started Jun 09 12:37:51 PM PDT 24
Finished Jun 09 12:38:18 PM PDT 24
Peak memory 255476 kb
Host smart-cfdc9f5c-dfc9-4276-b9ba-3dd57e61a4a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17214
08942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1721408942
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3090579699
Short name T248
Test name
Test status
Simulation time 309499589 ps
CPU time 17.98 seconds
Started Jun 09 12:38:06 PM PDT 24
Finished Jun 09 12:38:24 PM PDT 24
Peak memory 248536 kb
Host smart-463e25e3-ec11-4714-9b22-156cf5924a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30905
79699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3090579699
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3676276682
Short name T697
Test name
Test status
Simulation time 2661665201 ps
CPU time 28.36 seconds
Started Jun 09 12:37:49 PM PDT 24
Finished Jun 09 12:38:18 PM PDT 24
Peak memory 256576 kb
Host smart-a9902321-eb15-4140-b466-1e835aec8e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36762
76682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3676276682
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.2999508683
Short name T554
Test name
Test status
Simulation time 291920355482 ps
CPU time 3597.17 seconds
Started Jun 09 12:38:06 PM PDT 24
Finished Jun 09 01:38:05 PM PDT 24
Peak memory 297524 kb
Host smart-06af5ece-649b-4429-ac8e-213596be9d9f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999508683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.2999508683
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.3369080799
Short name T92
Test name
Test status
Simulation time 13682720009 ps
CPU time 947.6 seconds
Started Jun 09 12:37:47 PM PDT 24
Finished Jun 09 12:53:36 PM PDT 24
Peak memory 268564 kb
Host smart-cc24986f-6e5f-4424-ba9b-5595c521e92c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369080799 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.3369080799
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2635673935
Short name T208
Test name
Test status
Simulation time 58245992 ps
CPU time 2.89 seconds
Started Jun 09 12:37:40 PM PDT 24
Finished Jun 09 12:37:43 PM PDT 24
Peak memory 248816 kb
Host smart-55713934-02e4-4aae-9232-2673f1f19ae2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2635673935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2635673935
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.4197834679
Short name T477
Test name
Test status
Simulation time 17042480608 ps
CPU time 639.05 seconds
Started Jun 09 12:37:49 PM PDT 24
Finished Jun 09 12:48:29 PM PDT 24
Peak memory 267188 kb
Host smart-b8deef76-8c3f-4ee8-b4db-6443471d6e4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197834679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.4197834679
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.605943979
Short name T337
Test name
Test status
Simulation time 271126762 ps
CPU time 11.54 seconds
Started Jun 09 12:37:44 PM PDT 24
Finished Jun 09 12:37:57 PM PDT 24
Peak memory 248664 kb
Host smart-8bc4ded0-443a-4bcb-8ae6-3afe752dd438
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=605943979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.605943979
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.4274876243
Short name T130
Test name
Test status
Simulation time 5673024164 ps
CPU time 242.05 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 12:41:45 PM PDT 24
Peak memory 256916 kb
Host smart-c478674e-3e07-4b18-a79a-c9dd883a79f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42748
76243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.4274876243
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.4069352536
Short name T525
Test name
Test status
Simulation time 424976328 ps
CPU time 9.79 seconds
Started Jun 09 12:37:48 PM PDT 24
Finished Jun 09 12:37:58 PM PDT 24
Peak memory 253748 kb
Host smart-38fdb65b-7930-459e-8c52-e06fa672b7cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40693
52536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.4069352536
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.4128279030
Short name T578
Test name
Test status
Simulation time 17833207787 ps
CPU time 834.48 seconds
Started Jun 09 12:37:59 PM PDT 24
Finished Jun 09 12:51:53 PM PDT 24
Peak memory 272552 kb
Host smart-45798801-d6e1-4b59-beed-b07260ccd990
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128279030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.4128279030
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2815349989
Short name T284
Test name
Test status
Simulation time 23248944153 ps
CPU time 480.1 seconds
Started Jun 09 12:37:34 PM PDT 24
Finished Jun 09 12:45:35 PM PDT 24
Peak memory 248348 kb
Host smart-da419057-50db-44ec-b146-14422c79b1aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815349989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2815349989
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.122854128
Short name T33
Test name
Test status
Simulation time 8357854951 ps
CPU time 55.4 seconds
Started Jun 09 12:37:41 PM PDT 24
Finished Jun 09 12:38:38 PM PDT 24
Peak memory 256340 kb
Host smart-d7eeb688-f116-47f9-b110-57d6d69dc5ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12285
4128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.122854128
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.27411653
Short name T434
Test name
Test status
Simulation time 1730554075 ps
CPU time 50.98 seconds
Started Jun 09 12:37:58 PM PDT 24
Finished Jun 09 12:38:50 PM PDT 24
Peak memory 256848 kb
Host smart-c6925f75-60d2-4576-8a7c-ce5a44eabf8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27411
653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.27411653
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3034470748
Short name T79
Test name
Test status
Simulation time 1094048947 ps
CPU time 37.93 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 12:38:21 PM PDT 24
Peak memory 255440 kb
Host smart-cd804dfe-48d2-4ae1-8304-966d7f4ab270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30344
70748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3034470748
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3297878826
Short name T581
Test name
Test status
Simulation time 435052264 ps
CPU time 7.89 seconds
Started Jun 09 12:37:44 PM PDT 24
Finished Jun 09 12:37:53 PM PDT 24
Peak memory 254032 kb
Host smart-5575c4db-1c5c-4ce5-be41-c505d260b5f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32978
78826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3297878826
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2444133678
Short name T527
Test name
Test status
Simulation time 19716974731 ps
CPU time 179.6 seconds
Started Jun 09 12:37:45 PM PDT 24
Finished Jun 09 12:40:46 PM PDT 24
Peak memory 256940 kb
Host smart-89982a22-55c2-4288-8462-6d37112ce1f8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444133678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2444133678
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1379148767
Short name T212
Test name
Test status
Simulation time 44378199 ps
CPU time 3.9 seconds
Started Jun 09 12:38:01 PM PDT 24
Finished Jun 09 12:38:05 PM PDT 24
Peak memory 248788 kb
Host smart-1e12955f-ef2d-4bb5-90de-5351c4c5ed7c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1379148767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1379148767
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1291054632
Short name T685
Test name
Test status
Simulation time 1092566902 ps
CPU time 14.22 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 12:37:58 PM PDT 24
Peak memory 248688 kb
Host smart-e362ea2c-a377-4674-9efb-51bad6b15eb3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1291054632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1291054632
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2646791077
Short name T391
Test name
Test status
Simulation time 162405023 ps
CPU time 13.13 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 12:37:57 PM PDT 24
Peak memory 255152 kb
Host smart-dc9a2e73-bba9-49ba-99c6-1f41fbcf74cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26467
91077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2646791077
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3498160924
Short name T408
Test name
Test status
Simulation time 606857429 ps
CPU time 22.22 seconds
Started Jun 09 12:37:44 PM PDT 24
Finished Jun 09 12:38:08 PM PDT 24
Peak memory 255612 kb
Host smart-d74bec30-322c-4f26-b515-b4ff72067d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34981
60924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3498160924
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.1714942433
Short name T315
Test name
Test status
Simulation time 42294110067 ps
CPU time 891.2 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 12:52:35 PM PDT 24
Peak memory 273384 kb
Host smart-2394b7e8-f96d-4f8a-b091-f72dbfbd74c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714942433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.1714942433
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2735139713
Short name T461
Test name
Test status
Simulation time 34946593821 ps
CPU time 1105.07 seconds
Started Jun 09 12:37:47 PM PDT 24
Finished Jun 09 12:56:13 PM PDT 24
Peak memory 265180 kb
Host smart-3c9082ad-2b2d-409d-a41c-d72b7867cd89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735139713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2735139713
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1861932626
Short name T590
Test name
Test status
Simulation time 5176230065 ps
CPU time 112.6 seconds
Started Jun 09 12:37:57 PM PDT 24
Finished Jun 09 12:39:50 PM PDT 24
Peak memory 254784 kb
Host smart-95e9837c-f52a-4e3a-88a2-e4af92dce82f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861932626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1861932626
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.4263864785
Short name T439
Test name
Test status
Simulation time 1029716513 ps
CPU time 36.53 seconds
Started Jun 09 12:37:47 PM PDT 24
Finished Jun 09 12:38:24 PM PDT 24
Peak memory 256868 kb
Host smart-77a6d210-e296-4f3d-8ee2-5cb0bc5b0acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42638
64785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.4263864785
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1948754035
Short name T515
Test name
Test status
Simulation time 120363261 ps
CPU time 7.86 seconds
Started Jun 09 12:37:54 PM PDT 24
Finished Jun 09 12:38:02 PM PDT 24
Peak memory 247620 kb
Host smart-4409536d-e875-4ac5-9357-75d0fe5cd220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19487
54035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1948754035
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1804794694
Short name T452
Test name
Test status
Simulation time 576082278 ps
CPU time 14.41 seconds
Started Jun 09 12:37:39 PM PDT 24
Finished Jun 09 12:37:54 PM PDT 24
Peak memory 247948 kb
Host smart-682dd723-44b7-45e9-9484-0712150fb183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18047
94694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1804794694
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.581058250
Short name T482
Test name
Test status
Simulation time 57040457 ps
CPU time 4.55 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 12:37:49 PM PDT 24
Peak memory 248688 kb
Host smart-024b7c00-5b88-4ce7-a849-5110fc02352b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58105
8250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.581058250
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2338810764
Short name T85
Test name
Test status
Simulation time 4985467189 ps
CPU time 143.79 seconds
Started Jun 09 12:37:36 PM PDT 24
Finished Jun 09 12:40:01 PM PDT 24
Peak memory 256940 kb
Host smart-75cc9230-eeff-47c6-a090-d27d16dc495f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338810764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2338810764
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2849578115
Short name T204
Test name
Test status
Simulation time 72483414 ps
CPU time 3.46 seconds
Started Jun 09 12:37:39 PM PDT 24
Finished Jun 09 12:37:43 PM PDT 24
Peak memory 248804 kb
Host smart-3979f83e-3145-43e7-b169-7cdbfc47e9ae
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2849578115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2849578115
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3539561374
Short name T506
Test name
Test status
Simulation time 395303010251 ps
CPU time 3265.45 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 01:32:08 PM PDT 24
Peak memory 289036 kb
Host smart-2ba00769-1a05-481a-8783-6116c8c486c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539561374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3539561374
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1823848498
Short name T664
Test name
Test status
Simulation time 144912250 ps
CPU time 8.76 seconds
Started Jun 09 12:37:44 PM PDT 24
Finished Jun 09 12:37:56 PM PDT 24
Peak memory 240452 kb
Host smart-e26149ea-014d-4e92-ae43-ffb724697bb8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1823848498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1823848498
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.3555621197
Short name T120
Test name
Test status
Simulation time 92452060459 ps
CPU time 298.44 seconds
Started Jun 09 12:37:44 PM PDT 24
Finished Jun 09 12:42:44 PM PDT 24
Peak memory 256888 kb
Host smart-74e0e883-5fc7-4def-9c37-f330f31bcdef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35556
21197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3555621197
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.74120321
Short name T607
Test name
Test status
Simulation time 229085347 ps
CPU time 10.94 seconds
Started Jun 09 12:37:44 PM PDT 24
Finished Jun 09 12:37:56 PM PDT 24
Peak memory 254724 kb
Host smart-1e8c854f-a77e-4a9a-bf49-7661e5968d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74120
321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.74120321
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2166122741
Short name T327
Test name
Test status
Simulation time 150766345094 ps
CPU time 2286.36 seconds
Started Jun 09 12:37:47 PM PDT 24
Finished Jun 09 01:15:54 PM PDT 24
Peak memory 281536 kb
Host smart-79050e13-a16f-4782-b16a-f459ed955a00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166122741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2166122741
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3283132757
Short name T570
Test name
Test status
Simulation time 118001777651 ps
CPU time 1841.14 seconds
Started Jun 09 12:37:39 PM PDT 24
Finished Jun 09 01:08:21 PM PDT 24
Peak memory 282556 kb
Host smart-22bc6390-9641-40e9-8f27-58acc12ebbd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283132757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3283132757
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.75582988
Short name T285
Test name
Test status
Simulation time 4886775770 ps
CPU time 192.29 seconds
Started Jun 09 12:37:49 PM PDT 24
Finished Jun 09 12:41:01 PM PDT 24
Peak memory 255328 kb
Host smart-1bed78d3-4e63-4490-97ff-4b5438e26142
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75582988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.75582988
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.2264922951
Short name T474
Test name
Test status
Simulation time 1044653924 ps
CPU time 31.62 seconds
Started Jun 09 12:38:09 PM PDT 24
Finished Jun 09 12:38:41 PM PDT 24
Peak memory 256828 kb
Host smart-ad6e9f56-3bba-43f4-b4c1-ba8063a087dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22649
22951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2264922951
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.4094321922
Short name T497
Test name
Test status
Simulation time 589076970 ps
CPU time 31.08 seconds
Started Jun 09 12:37:56 PM PDT 24
Finished Jun 09 12:38:32 PM PDT 24
Peak memory 256584 kb
Host smart-bf09d4ea-571b-41a5-bb6d-74ae17e79540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40943
21922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.4094321922
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.206165082
Short name T587
Test name
Test status
Simulation time 871296945 ps
CPU time 20.84 seconds
Started Jun 09 12:37:52 PM PDT 24
Finished Jun 09 12:38:13 PM PDT 24
Peak memory 255068 kb
Host smart-6835e997-3358-4e6b-a3a1-7e1b2d9b71c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20616
5082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.206165082
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3724656369
Short name T442
Test name
Test status
Simulation time 1405244081 ps
CPU time 34.74 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 12:38:19 PM PDT 24
Peak memory 248708 kb
Host smart-570bb0a4-35ba-4dfb-978e-2dc5e94272b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37246
56369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3724656369
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.38962102
Short name T64
Test name
Test status
Simulation time 135510222 ps
CPU time 3.58 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 12:37:48 PM PDT 24
Peak memory 248888 kb
Host smart-5ece455f-7a0e-4bca-be1d-5739cc65f474
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=38962102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.38962102
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1527615655
Short name T281
Test name
Test status
Simulation time 10924337650 ps
CPU time 941.84 seconds
Started Jun 09 12:37:50 PM PDT 24
Finished Jun 09 12:53:32 PM PDT 24
Peak memory 268560 kb
Host smart-a0366c5c-85d5-4956-8a53-6773f91a476d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527615655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1527615655
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.391898747
Short name T456
Test name
Test status
Simulation time 706750463 ps
CPU time 18.22 seconds
Started Jun 09 12:38:04 PM PDT 24
Finished Jun 09 12:38:22 PM PDT 24
Peak memory 248708 kb
Host smart-44b72c1e-e039-449e-817c-5b5f80ddd9c4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=391898747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.391898747
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1348174952
Short name T575
Test name
Test status
Simulation time 13021864500 ps
CPU time 174.94 seconds
Started Jun 09 12:37:38 PM PDT 24
Finished Jun 09 12:40:34 PM PDT 24
Peak memory 256892 kb
Host smart-61a4b704-2203-4ff4-a96d-0ccaee26d774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13481
74952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1348174952
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.574331897
Short name T440
Test name
Test status
Simulation time 33125274 ps
CPU time 3.26 seconds
Started Jun 09 12:37:39 PM PDT 24
Finished Jun 09 12:37:43 PM PDT 24
Peak memory 240428 kb
Host smart-b8ee2fd3-d450-4388-9e3a-fe7b04334a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57433
1897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.574331897
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2450476995
Short name T321
Test name
Test status
Simulation time 38117524288 ps
CPU time 1051.7 seconds
Started Jun 09 12:37:45 PM PDT 24
Finished Jun 09 12:55:18 PM PDT 24
Peak memory 288636 kb
Host smart-0dfeb589-ad74-4278-8f52-66245067c6ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450476995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2450476995
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.449045657
Short name T670
Test name
Test status
Simulation time 186142761921 ps
CPU time 2627.01 seconds
Started Jun 09 12:37:44 PM PDT 24
Finished Jun 09 01:21:33 PM PDT 24
Peak memory 289060 kb
Host smart-e45885f6-4e03-4ab6-9826-f2c9c6e55c8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449045657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.449045657
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.583833902
Short name T489
Test name
Test status
Simulation time 19012477245 ps
CPU time 359.42 seconds
Started Jun 09 12:37:45 PM PDT 24
Finished Jun 09 12:43:45 PM PDT 24
Peak memory 247964 kb
Host smart-cc648ff0-131e-4ac4-afef-6d745d4a0349
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583833902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.583833902
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2819726714
Short name T674
Test name
Test status
Simulation time 2436880591 ps
CPU time 40.69 seconds
Started Jun 09 12:37:48 PM PDT 24
Finished Jun 09 12:38:29 PM PDT 24
Peak memory 256948 kb
Host smart-7c29f49c-b38a-4d0e-a869-ddebaae9ffef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28197
26714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2819726714
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3548233842
Short name T38
Test name
Test status
Simulation time 1903527846 ps
CPU time 32.33 seconds
Started Jun 09 12:37:41 PM PDT 24
Finished Jun 09 12:38:15 PM PDT 24
Peak memory 255392 kb
Host smart-ceb82255-11cb-40d8-93a4-b914272f8fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35482
33842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3548233842
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2970434760
Short name T84
Test name
Test status
Simulation time 1272399873 ps
CPU time 26.69 seconds
Started Jun 09 12:37:50 PM PDT 24
Finished Jun 09 12:38:17 PM PDT 24
Peak memory 247164 kb
Host smart-a0a290a6-af6a-4905-8ab0-beb75914b293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29704
34760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2970434760
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1777024281
Short name T394
Test name
Test status
Simulation time 1877060300 ps
CPU time 32.91 seconds
Started Jun 09 12:38:09 PM PDT 24
Finished Jun 09 12:38:42 PM PDT 24
Peak memory 248620 kb
Host smart-8d9fc735-f3f0-47f6-8fb9-f5e230886d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17770
24281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1777024281
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3311743780
Short name T59
Test name
Test status
Simulation time 234226427297 ps
CPU time 3323.96 seconds
Started Jun 09 12:37:39 PM PDT 24
Finished Jun 09 01:33:04 PM PDT 24
Peak memory 297688 kb
Host smart-319498d3-4da7-43fb-b377-b22e7fc85f2f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311743780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3311743780
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.441586248
Short name T205
Test name
Test status
Simulation time 153471801 ps
CPU time 3.32 seconds
Started Jun 09 12:37:50 PM PDT 24
Finished Jun 09 12:37:54 PM PDT 24
Peak memory 248784 kb
Host smart-be6fe90d-f4be-45fe-b8df-79434bad53f6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=441586248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.441586248
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1370382383
Short name T52
Test name
Test status
Simulation time 84702956486 ps
CPU time 1350.67 seconds
Started Jun 09 12:38:10 PM PDT 24
Finished Jun 09 01:00:41 PM PDT 24
Peak memory 269216 kb
Host smart-fe8bddc3-18e4-46bb-a087-82a96e46a2c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370382383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1370382383
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1371024856
Short name T388
Test name
Test status
Simulation time 3418548650 ps
CPU time 25.94 seconds
Started Jun 09 12:38:11 PM PDT 24
Finished Jun 09 12:38:38 PM PDT 24
Peak memory 248768 kb
Host smart-83a17b2e-aa87-482e-a458-de037726a462
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1371024856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1371024856
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1980332290
Short name T493
Test name
Test status
Simulation time 864570107 ps
CPU time 53.15 seconds
Started Jun 09 12:38:07 PM PDT 24
Finished Jun 09 12:39:01 PM PDT 24
Peak memory 256844 kb
Host smart-63e7cffb-7d7a-42d0-a390-f9fa45e94588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19803
32290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1980332290
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.654508118
Short name T476
Test name
Test status
Simulation time 784283410 ps
CPU time 35.46 seconds
Started Jun 09 12:38:02 PM PDT 24
Finished Jun 09 12:38:37 PM PDT 24
Peak memory 256836 kb
Host smart-3ea0cbda-ffa7-4804-817e-d54e67cf1165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65450
8118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.654508118
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2341297719
Short name T275
Test name
Test status
Simulation time 56529568924 ps
CPU time 1198.16 seconds
Started Jun 09 12:38:14 PM PDT 24
Finished Jun 09 12:58:13 PM PDT 24
Peak memory 272416 kb
Host smart-0a9cf53c-116f-43b6-9891-7da47919de43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341297719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2341297719
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1181954885
Short name T25
Test name
Test status
Simulation time 29673447025 ps
CPU time 750.82 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 12:50:14 PM PDT 24
Peak memory 272480 kb
Host smart-416952df-76cf-40ef-827a-e9044259f843
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181954885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1181954885
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3727033269
Short name T14
Test name
Test status
Simulation time 8143646113 ps
CPU time 321.9 seconds
Started Jun 09 12:38:14 PM PDT 24
Finished Jun 09 12:43:37 PM PDT 24
Peak memory 247052 kb
Host smart-f54821ad-9a97-4f82-ab36-da1028cb5ac8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727033269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3727033269
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1818968919
Short name T425
Test name
Test status
Simulation time 61605325 ps
CPU time 7.49 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 12:37:52 PM PDT 24
Peak memory 248644 kb
Host smart-5e5ea3f0-07bd-47c7-bd7b-2749035197a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18189
68919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1818968919
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3705047537
Short name T101
Test name
Test status
Simulation time 309221124 ps
CPU time 17.63 seconds
Started Jun 09 12:37:59 PM PDT 24
Finished Jun 09 12:38:17 PM PDT 24
Peak memory 254720 kb
Host smart-15cb595b-3b6e-4326-9bc7-6309cb566c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37050
47537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3705047537
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2067155647
Short name T250
Test name
Test status
Simulation time 1126858380 ps
CPU time 30.22 seconds
Started Jun 09 12:38:07 PM PDT 24
Finished Jun 09 12:38:38 PM PDT 24
Peak memory 248712 kb
Host smart-b088bd49-187f-4798-92e1-26019c06501e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20671
55647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2067155647
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2593487908
Short name T555
Test name
Test status
Simulation time 1690602617 ps
CPU time 34.25 seconds
Started Jun 09 12:38:09 PM PDT 24
Finished Jun 09 12:38:44 PM PDT 24
Peak memory 256172 kb
Host smart-331d8bf6-854e-445e-abae-74b3cdf19dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25934
87908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2593487908
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.4015713856
Short name T655
Test name
Test status
Simulation time 7331074948 ps
CPU time 191.93 seconds
Started Jun 09 12:38:03 PM PDT 24
Finished Jun 09 12:41:15 PM PDT 24
Peak memory 253356 kb
Host smart-4395d2aa-f594-41d6-bb9c-a3272e7e5a69
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015713856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.4015713856
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.4145732011
Short name T235
Test name
Test status
Simulation time 86318114305 ps
CPU time 2689.2 seconds
Started Jun 09 12:38:07 PM PDT 24
Finished Jun 09 01:22:57 PM PDT 24
Peak memory 319416 kb
Host smart-e0908d7e-8fc3-4e3a-b513-cd953a78a2ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145732011 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.4145732011
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.328552966
Short name T209
Test name
Test status
Simulation time 133674259 ps
CPU time 3.03 seconds
Started Jun 09 12:37:44 PM PDT 24
Finished Jun 09 12:37:48 PM PDT 24
Peak memory 248884 kb
Host smart-e37efe6a-0020-44f1-b57f-3b772c51e389
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=328552966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.328552966
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.4106234121
Short name T4
Test name
Test status
Simulation time 919606083 ps
CPU time 13.1 seconds
Started Jun 09 12:37:27 PM PDT 24
Finished Jun 09 12:37:41 PM PDT 24
Peak memory 248716 kb
Host smart-2016cbac-240b-4b0c-a914-ab50668f70ff
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4106234121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.4106234121
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3259653246
Short name T192
Test name
Test status
Simulation time 3223622692 ps
CPU time 133.02 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 12:39:56 PM PDT 24
Peak memory 250280 kb
Host smart-a7285d76-3d6c-4a85-b0e2-523eff7acc58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32596
53246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3259653246
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3728189079
Short name T220
Test name
Test status
Simulation time 1191517263 ps
CPU time 36.28 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 12:38:20 PM PDT 24
Peak memory 255728 kb
Host smart-63cd65c9-8962-460b-8436-56d18567330d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37281
89079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3728189079
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3120407437
Short name T675
Test name
Test status
Simulation time 35499566676 ps
CPU time 1007.97 seconds
Started Jun 09 12:37:37 PM PDT 24
Finished Jun 09 12:54:32 PM PDT 24
Peak memory 271772 kb
Host smart-f15be643-0709-48cf-bd0b-d1480327c315
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120407437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3120407437
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2513770837
Short name T407
Test name
Test status
Simulation time 47485755108 ps
CPU time 1375.63 seconds
Started Jun 09 12:37:37 PM PDT 24
Finished Jun 09 01:00:33 PM PDT 24
Peak memory 286792 kb
Host smart-85fe2918-7991-467f-ac92-9ae00978c7a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513770837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2513770837
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3907544082
Short name T354
Test name
Test status
Simulation time 4051680292 ps
CPU time 24.49 seconds
Started Jun 09 12:37:44 PM PDT 24
Finished Jun 09 12:38:10 PM PDT 24
Peak memory 248668 kb
Host smart-a4c50782-b371-4b63-a8c3-4c176030769c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39075
44082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3907544082
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2633978578
Short name T533
Test name
Test status
Simulation time 423002734 ps
CPU time 30.58 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 12:38:15 PM PDT 24
Peak memory 255768 kb
Host smart-d51f7cbb-4b38-4a4d-9e6c-7d50aed074b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26339
78578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2633978578
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2174408568
Short name T7
Test name
Test status
Simulation time 1580486432 ps
CPU time 22.42 seconds
Started Jun 09 12:37:34 PM PDT 24
Finished Jun 09 12:37:57 PM PDT 24
Peak memory 278616 kb
Host smart-c6ead900-eb89-4c86-a93a-34244b3805d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2174408568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2174408568
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3279073947
Short name T219
Test name
Test status
Simulation time 9619059806 ps
CPU time 57.48 seconds
Started Jun 09 12:37:36 PM PDT 24
Finished Jun 09 12:38:35 PM PDT 24
Peak memory 256868 kb
Host smart-51eab801-eceb-44b1-804c-c6b3b691c5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32790
73947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3279073947
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.4220388592
Short name T342
Test name
Test status
Simulation time 2762641653 ps
CPU time 39.85 seconds
Started Jun 09 12:37:39 PM PDT 24
Finished Jun 09 12:38:20 PM PDT 24
Peak memory 256300 kb
Host smart-3420b3b1-2e51-4636-8c32-bf1f1f5a8830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42203
88592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.4220388592
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1003482129
Short name T611
Test name
Test status
Simulation time 9417923101 ps
CPU time 407.69 seconds
Started Jun 09 12:37:36 PM PDT 24
Finished Jun 09 12:44:24 PM PDT 24
Peak memory 265172 kb
Host smart-c8e31caf-c23e-4c76-8f69-5be95dae7095
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003482129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1003482129
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.4018046828
Short name T427
Test name
Test status
Simulation time 118416612001 ps
CPU time 3152.97 seconds
Started Jun 09 12:37:36 PM PDT 24
Finished Jun 09 01:30:10 PM PDT 24
Peak memory 289608 kb
Host smart-aed6adfb-263c-4230-be1f-e2855679e5f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018046828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.4018046828
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3378011097
Short name T699
Test name
Test status
Simulation time 2132543418 ps
CPU time 136.22 seconds
Started Jun 09 12:37:56 PM PDT 24
Finished Jun 09 12:40:13 PM PDT 24
Peak memory 256892 kb
Host smart-4727c91e-bbbb-48e7-a2cd-8da7e00d44e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33780
11097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3378011097
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.2032135441
Short name T405
Test name
Test status
Simulation time 665038014 ps
CPU time 12.66 seconds
Started Jun 09 12:37:53 PM PDT 24
Finished Jun 09 12:38:06 PM PDT 24
Peak memory 252676 kb
Host smart-58871a90-bf5d-41c1-bf4c-6990a9d58aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20321
35441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2032135441
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1017309281
Short name T317
Test name
Test status
Simulation time 47780732284 ps
CPU time 2559.57 seconds
Started Jun 09 12:37:45 PM PDT 24
Finished Jun 09 01:20:26 PM PDT 24
Peak memory 281548 kb
Host smart-0b117d42-e0de-43f1-a7c7-dccd8239c74b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017309281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1017309281
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2826315977
Short name T669
Test name
Test status
Simulation time 53194839289 ps
CPU time 1694.48 seconds
Started Jun 09 12:37:47 PM PDT 24
Finished Jun 09 01:06:03 PM PDT 24
Peak memory 272772 kb
Host smart-61d4b48b-9150-4906-a361-f530f7e6a900
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826315977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2826315977
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1173656923
Short name T569
Test name
Test status
Simulation time 19068273890 ps
CPU time 200.3 seconds
Started Jun 09 12:37:57 PM PDT 24
Finished Jun 09 12:41:18 PM PDT 24
Peak memory 248192 kb
Host smart-ca0e4151-2745-4864-82f2-4b2fa0aca32c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173656923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1173656923
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3951810730
Short name T86
Test name
Test status
Simulation time 926920274 ps
CPU time 13.24 seconds
Started Jun 09 12:37:35 PM PDT 24
Finished Jun 09 12:37:49 PM PDT 24
Peak memory 248712 kb
Host smart-27646ea7-0c62-4517-9abd-e505d9f70689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39518
10730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3951810730
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.58021880
Short name T94
Test name
Test status
Simulation time 943649082 ps
CPU time 33.77 seconds
Started Jun 09 12:37:46 PM PDT 24
Finished Jun 09 12:38:21 PM PDT 24
Peak memory 256784 kb
Host smart-afe559c0-4fd6-42cb-b5a8-8a28c7d10af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58021
880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.58021880
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.75351841
Short name T689
Test name
Test status
Simulation time 1688296355 ps
CPU time 56.03 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 12:38:40 PM PDT 24
Peak memory 248596 kb
Host smart-f3d61ee7-80f2-43d8-b1e0-1b69b162cceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75351
841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.75351841
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.327054336
Short name T512
Test name
Test status
Simulation time 1096335301 ps
CPU time 61.11 seconds
Started Jun 09 12:37:40 PM PDT 24
Finished Jun 09 12:38:42 PM PDT 24
Peak memory 248700 kb
Host smart-acdfee6a-7ea7-4e82-8c18-60407aa0d349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32705
4336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.327054336
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3875789519
Short name T353
Test name
Test status
Simulation time 2511039021 ps
CPU time 66.89 seconds
Started Jun 09 12:38:07 PM PDT 24
Finished Jun 09 12:39:14 PM PDT 24
Peak memory 256768 kb
Host smart-96a209e2-5b9a-448a-afb9-0fb962c4eef8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875789519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3875789519
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.293418535
Short name T513
Test name
Test status
Simulation time 8596566431 ps
CPU time 685.69 seconds
Started Jun 09 12:37:51 PM PDT 24
Finished Jun 09 12:49:17 PM PDT 24
Peak memory 265144 kb
Host smart-dec2089a-ecf0-42bb-983c-efeb007a8f03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293418535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.293418535
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.473428100
Short name T438
Test name
Test status
Simulation time 4273308145 ps
CPU time 121.73 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 12:39:46 PM PDT 24
Peak memory 256836 kb
Host smart-572e7db6-34df-4405-9f43-89ad636c7e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47342
8100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.473428100
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.2825768896
Short name T549
Test name
Test status
Simulation time 685559732 ps
CPU time 36.94 seconds
Started Jun 09 12:37:44 PM PDT 24
Finished Jun 09 12:38:22 PM PDT 24
Peak memory 255620 kb
Host smart-2c5a71db-a653-41e4-94f7-b48425154c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28257
68896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2825768896
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.4006192832
Short name T322
Test name
Test status
Simulation time 21672086786 ps
CPU time 1577.48 seconds
Started Jun 09 12:38:04 PM PDT 24
Finished Jun 09 01:04:22 PM PDT 24
Peak memory 289416 kb
Host smart-fe282a93-062b-4cde-9ca9-46c743851c1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006192832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.4006192832
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1732903400
Short name T596
Test name
Test status
Simulation time 31161447514 ps
CPU time 1772.65 seconds
Started Jun 09 12:38:09 PM PDT 24
Finished Jun 09 01:07:43 PM PDT 24
Peak memory 284772 kb
Host smart-6f0f86af-9277-4d35-8892-1a0b78bd7fc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732903400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1732903400
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1031042453
Short name T300
Test name
Test status
Simulation time 3398889370 ps
CPU time 129.3 seconds
Started Jun 09 12:37:54 PM PDT 24
Finished Jun 09 12:40:04 PM PDT 24
Peak memory 248316 kb
Host smart-4b00ffad-3f7f-464d-ab15-4a27f2aebb7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031042453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1031042453
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2537821797
Short name T484
Test name
Test status
Simulation time 1117919383 ps
CPU time 56.77 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 12:38:43 PM PDT 24
Peak memory 248640 kb
Host smart-d088498d-a48b-4de1-9027-56c91992d964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25378
21797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2537821797
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.28239594
Short name T428
Test name
Test status
Simulation time 1054468191 ps
CPU time 35.12 seconds
Started Jun 09 12:38:07 PM PDT 24
Finished Jun 09 12:38:42 PM PDT 24
Peak memory 247616 kb
Host smart-ef3257f7-2fb7-43b7-933c-0280472b06d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28239
594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.28239594
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1437242061
Short name T687
Test name
Test status
Simulation time 685534032 ps
CPU time 4.46 seconds
Started Jun 09 12:38:14 PM PDT 24
Finished Jun 09 12:38:19 PM PDT 24
Peak memory 240572 kb
Host smart-afc52a81-4a88-4765-9896-114ddb7d5003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14372
42061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1437242061
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.148596306
Short name T701
Test name
Test status
Simulation time 244453213685 ps
CPU time 3646.45 seconds
Started Jun 09 12:38:15 PM PDT 24
Finished Jun 09 01:39:02 PM PDT 24
Peak memory 298020 kb
Host smart-eb2bd563-8de7-490d-ba88-4a6ef7464f7b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148596306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_han
dler_stress_all.148596306
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1292171790
Short name T61
Test name
Test status
Simulation time 716169916800 ps
CPU time 2542.85 seconds
Started Jun 09 12:38:08 PM PDT 24
Finished Jun 09 01:20:32 PM PDT 24
Peak memory 288884 kb
Host smart-ef77d7b6-5f47-42c7-ac25-516e8f1514d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292171790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1292171790
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3721596066
Short name T419
Test name
Test status
Simulation time 8799261047 ps
CPU time 231.11 seconds
Started Jun 09 12:37:45 PM PDT 24
Finished Jun 09 12:41:38 PM PDT 24
Peak memory 249736 kb
Host smart-e6872560-2921-4f22-b819-0c481a11015a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37215
96066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3721596066
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.1175766129
Short name T447
Test name
Test status
Simulation time 716941147 ps
CPU time 45.4 seconds
Started Jun 09 12:38:00 PM PDT 24
Finished Jun 09 12:38:46 PM PDT 24
Peak memory 255400 kb
Host smart-ff903cdf-eeab-457c-b28c-bbb07e4a022d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11757
66129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1175766129
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1364009213
Short name T312
Test name
Test status
Simulation time 106194922658 ps
CPU time 1432.64 seconds
Started Jun 09 12:37:47 PM PDT 24
Finished Jun 09 01:01:41 PM PDT 24
Peak memory 269132 kb
Host smart-2d8c61bf-958a-47be-8ad3-6e8654f9eeeb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364009213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1364009213
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3406718101
Short name T286
Test name
Test status
Simulation time 45729558755 ps
CPU time 468.96 seconds
Started Jun 09 12:37:41 PM PDT 24
Finished Jun 09 12:45:31 PM PDT 24
Peak memory 248544 kb
Host smart-dd05529b-6021-468b-ad00-3f1aa62766f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406718101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3406718101
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.671831439
Short name T401
Test name
Test status
Simulation time 646113873 ps
CPU time 21.34 seconds
Started Jun 09 12:37:52 PM PDT 24
Finished Jun 09 12:38:13 PM PDT 24
Peak memory 255900 kb
Host smart-d832ecc5-e6c8-4dc6-af55-f66f9b6ef5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67183
1439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.671831439
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.407944484
Short name T11
Test name
Test status
Simulation time 399062251 ps
CPU time 27.46 seconds
Started Jun 09 12:37:45 PM PDT 24
Finished Jun 09 12:38:15 PM PDT 24
Peak memory 248896 kb
Host smart-d5f50e1b-f6e1-4f6a-b234-90babab5be13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40794
4484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.407944484
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3888272074
Short name T236
Test name
Test status
Simulation time 544630822 ps
CPU time 19.49 seconds
Started Jun 09 12:37:41 PM PDT 24
Finished Jun 09 12:38:01 PM PDT 24
Peak memory 255388 kb
Host smart-51282ed6-7126-4183-8690-fe5db3deb777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38882
72074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3888272074
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.348210779
Short name T350
Test name
Test status
Simulation time 1938139772 ps
CPU time 55.37 seconds
Started Jun 09 12:37:52 PM PDT 24
Finished Jun 09 12:38:48 PM PDT 24
Peak memory 256824 kb
Host smart-dcd0c3e3-1d96-422c-8d68-8ed549c8877a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34821
0779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.348210779
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.578987459
Short name T387
Test name
Test status
Simulation time 3778734764 ps
CPU time 45.85 seconds
Started Jun 09 12:37:53 PM PDT 24
Finished Jun 09 12:38:39 PM PDT 24
Peak memory 256932 kb
Host smart-68e1e212-2986-4386-af42-3aa211fc6f7b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578987459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.578987459
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2312092198
Short name T417
Test name
Test status
Simulation time 119656406817 ps
CPU time 2470.1 seconds
Started Jun 09 12:38:11 PM PDT 24
Finished Jun 09 01:19:22 PM PDT 24
Peak memory 288980 kb
Host smart-fef6e8fc-a3be-4f1c-9a29-c73c12dd97d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312092198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2312092198
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.567162453
Short name T592
Test name
Test status
Simulation time 4342999700 ps
CPU time 230.53 seconds
Started Jun 09 12:38:11 PM PDT 24
Finished Jun 09 12:42:02 PM PDT 24
Peak memory 256872 kb
Host smart-2c6f1eaa-c2ed-4fc0-b47a-e29866b2ba8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56716
2453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.567162453
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2448854623
Short name T691
Test name
Test status
Simulation time 2418126786 ps
CPU time 38.34 seconds
Started Jun 09 12:38:10 PM PDT 24
Finished Jun 09 12:38:49 PM PDT 24
Peak memory 248808 kb
Host smart-9843f9ad-343d-4df1-9cca-3147b4ca850e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24488
54623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2448854623
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.123489579
Short name T118
Test name
Test status
Simulation time 34431289934 ps
CPU time 1513.67 seconds
Started Jun 09 12:38:02 PM PDT 24
Finished Jun 09 01:03:16 PM PDT 24
Peak memory 289324 kb
Host smart-23095a24-a7b5-47dc-8cec-48d3386f291f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123489579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.123489579
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3458213370
Short name T658
Test name
Test status
Simulation time 93372433458 ps
CPU time 1146.35 seconds
Started Jun 09 12:38:13 PM PDT 24
Finished Jun 09 12:57:20 PM PDT 24
Peak memory 272968 kb
Host smart-ef1414d5-0178-47d0-b815-aef02b8ed3b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458213370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3458213370
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3905458325
Short name T295
Test name
Test status
Simulation time 5825025028 ps
CPU time 227.38 seconds
Started Jun 09 12:38:08 PM PDT 24
Finished Jun 09 12:41:56 PM PDT 24
Peak memory 248248 kb
Host smart-c6a892db-87a3-4fa1-bbb0-a6d228a49c38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905458325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3905458325
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2477047587
Short name T385
Test name
Test status
Simulation time 395046972 ps
CPU time 16.76 seconds
Started Jun 09 12:37:39 PM PDT 24
Finished Jun 09 12:37:56 PM PDT 24
Peak memory 248632 kb
Host smart-8e3487ee-3b21-4557-beb8-85373931bf40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24770
47587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2477047587
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3758839339
Short name T475
Test name
Test status
Simulation time 125320862 ps
CPU time 8.69 seconds
Started Jun 09 12:38:06 PM PDT 24
Finished Jun 09 12:38:16 PM PDT 24
Peak memory 253160 kb
Host smart-b3d6e3b3-32fb-4d71-9c95-507c31c8c162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37588
39339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3758839339
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3408658331
Short name T81
Test name
Test status
Simulation time 2787687641 ps
CPU time 27.76 seconds
Started Jun 09 12:38:11 PM PDT 24
Finished Jun 09 12:38:39 PM PDT 24
Peak memory 256828 kb
Host smart-c232933f-9488-45e7-9849-e8fdfa10d9bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34086
58331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3408658331
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1695744762
Short name T379
Test name
Test status
Simulation time 1337680424 ps
CPU time 30.18 seconds
Started Jun 09 12:38:06 PM PDT 24
Finished Jun 09 12:38:37 PM PDT 24
Peak memory 248696 kb
Host smart-26cf0900-8424-4b76-b34f-32e9f645c534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16957
44762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1695744762
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.1243667605
Short name T103
Test name
Test status
Simulation time 101456818730 ps
CPU time 1020 seconds
Started Jun 09 12:38:05 PM PDT 24
Finished Jun 09 12:55:06 PM PDT 24
Peak memory 281816 kb
Host smart-ecfdab6f-aa1e-43d0-a5e0-e447640d0ee7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243667605 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.1243667605
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.395513196
Short name T496
Test name
Test status
Simulation time 60619694537 ps
CPU time 1541.84 seconds
Started Jun 09 12:37:59 PM PDT 24
Finished Jun 09 01:03:42 PM PDT 24
Peak memory 288996 kb
Host smart-15f85303-87c5-470f-8e79-3183252510ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395513196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.395513196
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.895028987
Short name T362
Test name
Test status
Simulation time 1209475108 ps
CPU time 103.28 seconds
Started Jun 09 12:37:58 PM PDT 24
Finished Jun 09 12:39:42 PM PDT 24
Peak memory 250128 kb
Host smart-ccae1f0f-4dca-4859-99b1-c574582c46dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89502
8987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.895028987
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1482815192
Short name T403
Test name
Test status
Simulation time 207808987 ps
CPU time 13.78 seconds
Started Jun 09 12:37:48 PM PDT 24
Finished Jun 09 12:38:07 PM PDT 24
Peak memory 252544 kb
Host smart-1ef9abd1-68b8-49fe-9174-b27ae01e25aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14828
15192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1482815192
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1915834293
Short name T404
Test name
Test status
Simulation time 22686383435 ps
CPU time 1225.79 seconds
Started Jun 09 12:38:00 PM PDT 24
Finished Jun 09 12:58:26 PM PDT 24
Peak memory 272560 kb
Host smart-8de39053-7fb4-48dd-9951-32ae419996bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915834293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1915834293
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.4136665759
Short name T546
Test name
Test status
Simulation time 3241354437 ps
CPU time 112.66 seconds
Started Jun 09 12:38:09 PM PDT 24
Finished Jun 09 12:40:02 PM PDT 24
Peak memory 248320 kb
Host smart-d976deed-97af-434d-bde2-6bf299fbe401
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136665759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.4136665759
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2427673486
Short name T10
Test name
Test status
Simulation time 25776111 ps
CPU time 3.47 seconds
Started Jun 09 12:38:07 PM PDT 24
Finished Jun 09 12:38:11 PM PDT 24
Peak memory 240440 kb
Host smart-8bb5191a-2124-4cd1-b14f-ea0355bf2af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24276
73486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2427673486
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2091917815
Short name T421
Test name
Test status
Simulation time 772014657 ps
CPU time 43.76 seconds
Started Jun 09 12:37:46 PM PDT 24
Finished Jun 09 12:38:31 PM PDT 24
Peak memory 248560 kb
Host smart-d96758b6-d205-4c1f-a591-2c772895adfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20919
17815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2091917815
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.284719349
Short name T667
Test name
Test status
Simulation time 184076874 ps
CPU time 18.61 seconds
Started Jun 09 12:38:05 PM PDT 24
Finished Jun 09 12:38:24 PM PDT 24
Peak memory 247688 kb
Host smart-c96bebf8-f44b-4de7-87ac-6d95bd0a2d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28471
9349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.284719349
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3288632683
Short name T74
Test name
Test status
Simulation time 343437892 ps
CPU time 12.32 seconds
Started Jun 09 12:38:00 PM PDT 24
Finished Jun 09 12:38:13 PM PDT 24
Peak memory 248624 kb
Host smart-b38c7599-2dcf-41e9-bba4-73f44b191af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32886
32683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3288632683
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3824393879
Short name T634
Test name
Test status
Simulation time 31033276000 ps
CPU time 711.4 seconds
Started Jun 09 12:37:46 PM PDT 24
Finished Jun 09 12:49:39 PM PDT 24
Peak memory 273292 kb
Host smart-64321ed8-3019-4936-873e-8bd9810087c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824393879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3824393879
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.489106159
Short name T459
Test name
Test status
Simulation time 243410236 ps
CPU time 20.33 seconds
Started Jun 09 12:38:02 PM PDT 24
Finished Jun 09 12:38:23 PM PDT 24
Peak memory 248864 kb
Host smart-d9621547-7323-4f08-a4de-6c5ae3c9480b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48910
6159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.489106159
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3538812528
Short name T524
Test name
Test status
Simulation time 179719723 ps
CPU time 7.12 seconds
Started Jun 09 12:38:07 PM PDT 24
Finished Jun 09 12:38:14 PM PDT 24
Peak memory 253152 kb
Host smart-12986d2f-597f-46ef-a35e-af9d78822828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35388
12528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3538812528
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2538212770
Short name T325
Test name
Test status
Simulation time 12942609450 ps
CPU time 1068.01 seconds
Started Jun 09 12:38:13 PM PDT 24
Finished Jun 09 12:56:02 PM PDT 24
Peak memory 273328 kb
Host smart-0bf015a5-286b-4eb3-8c5c-1b17631acfec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538212770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2538212770
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2486186561
Short name T316
Test name
Test status
Simulation time 22636375443 ps
CPU time 615.73 seconds
Started Jun 09 12:38:06 PM PDT 24
Finished Jun 09 12:48:23 PM PDT 24
Peak memory 265116 kb
Host smart-cd7ba17e-45a7-4b35-9187-e53fd5b308ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486186561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2486186561
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2919379497
Short name T279
Test name
Test status
Simulation time 41290986173 ps
CPU time 233.07 seconds
Started Jun 09 12:38:06 PM PDT 24
Finished Jun 09 12:42:00 PM PDT 24
Peak memory 254788 kb
Host smart-f43e8c63-c2c7-42e8-9114-ec69ea3b9d51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919379497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2919379497
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1565002875
Short name T363
Test name
Test status
Simulation time 241396198 ps
CPU time 22.59 seconds
Started Jun 09 12:38:07 PM PDT 24
Finished Jun 09 12:38:30 PM PDT 24
Peak memory 248888 kb
Host smart-bd906482-582c-472f-971b-a60f5da72f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15650
02875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1565002875
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2067827871
Short name T566
Test name
Test status
Simulation time 1774527187 ps
CPU time 44.35 seconds
Started Jun 09 12:38:06 PM PDT 24
Finished Jun 09 12:38:51 PM PDT 24
Peak memory 248640 kb
Host smart-87c9218b-f70c-4ccb-aa82-2099dea29eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20678
27871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2067827871
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1165517968
Short name T472
Test name
Test status
Simulation time 1388468927 ps
CPU time 40.28 seconds
Started Jun 09 12:38:02 PM PDT 24
Finished Jun 09 12:38:42 PM PDT 24
Peak memory 256432 kb
Host smart-7dc5182d-7052-430e-9e8d-11c9fc971c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11655
17968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1165517968
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2832186216
Short name T695
Test name
Test status
Simulation time 252843915 ps
CPU time 27.21 seconds
Started Jun 09 12:38:05 PM PDT 24
Finished Jun 09 12:38:33 PM PDT 24
Peak memory 248692 kb
Host smart-ca2ceee2-1625-40b7-a429-c4518ba32d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28321
86216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2832186216
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.473185829
Short name T451
Test name
Test status
Simulation time 50871729989 ps
CPU time 1276.83 seconds
Started Jun 09 12:37:59 PM PDT 24
Finished Jun 09 12:59:16 PM PDT 24
Peak memory 289388 kb
Host smart-b2e5d158-b958-4aa5-9af0-74adc9ef00fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473185829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.473185829
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.837881708
Short name T48
Test name
Test status
Simulation time 142531606055 ps
CPU time 5982.03 seconds
Started Jun 09 12:38:04 PM PDT 24
Finished Jun 09 02:17:47 PM PDT 24
Peak memory 354436 kb
Host smart-e63ff636-cbd5-48a7-a099-2db0bb17aa7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837881708 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.837881708
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.4000653115
Short name T123
Test name
Test status
Simulation time 17304310096 ps
CPU time 181.28 seconds
Started Jun 09 12:38:00 PM PDT 24
Finished Jun 09 12:41:01 PM PDT 24
Peak memory 250744 kb
Host smart-d268ad36-c260-4e85-a299-2e599f660029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40006
53115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.4000653115
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.356856568
Short name T526
Test name
Test status
Simulation time 201190777 ps
CPU time 14.12 seconds
Started Jun 09 12:38:01 PM PDT 24
Finished Jun 09 12:38:16 PM PDT 24
Peak memory 254340 kb
Host smart-21cd4647-15d2-40fd-80bb-1bdb599df6ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35685
6568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.356856568
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.211339297
Short name T318
Test name
Test status
Simulation time 96352744629 ps
CPU time 1170.52 seconds
Started Jun 09 12:38:08 PM PDT 24
Finished Jun 09 12:57:40 PM PDT 24
Peak memory 265160 kb
Host smart-5d48b2d2-a55b-49e3-bef4-fe9ed38461c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211339297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.211339297
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.979362253
Short name T680
Test name
Test status
Simulation time 52510051655 ps
CPU time 1932.49 seconds
Started Jun 09 12:38:03 PM PDT 24
Finished Jun 09 01:10:16 PM PDT 24
Peak memory 273320 kb
Host smart-54c01067-ec56-4825-ad92-8e11607b5cf3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979362253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.979362253
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1751637904
Short name T291
Test name
Test status
Simulation time 30780102289 ps
CPU time 604.94 seconds
Started Jun 09 12:38:06 PM PDT 24
Finished Jun 09 12:48:12 PM PDT 24
Peak memory 247340 kb
Host smart-81158dfe-5344-4cb7-9b23-99a54810c087
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751637904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1751637904
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.409136247
Short name T582
Test name
Test status
Simulation time 203650320 ps
CPU time 18.54 seconds
Started Jun 09 12:38:08 PM PDT 24
Finished Jun 09 12:38:27 PM PDT 24
Peak memory 248712 kb
Host smart-cead5b8f-77a6-422f-ab91-3c308dfb55cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40913
6247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.409136247
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.1964439892
Short name T390
Test name
Test status
Simulation time 60867924 ps
CPU time 9 seconds
Started Jun 09 12:37:53 PM PDT 24
Finished Jun 09 12:38:02 PM PDT 24
Peak memory 248716 kb
Host smart-a1b0aab9-e402-4488-b223-c91adf53dcd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19644
39892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1964439892
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3411370079
Short name T502
Test name
Test status
Simulation time 380208692 ps
CPU time 12.94 seconds
Started Jun 09 12:38:04 PM PDT 24
Finished Jun 09 12:38:17 PM PDT 24
Peak memory 254724 kb
Host smart-0cbbae11-59ed-491b-9765-cd3ccf573b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34113
70079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3411370079
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.859051825
Short name T429
Test name
Test status
Simulation time 117752734 ps
CPU time 13.13 seconds
Started Jun 09 12:37:48 PM PDT 24
Finished Jun 09 12:38:02 PM PDT 24
Peak memory 248880 kb
Host smart-d977d7c1-872f-40c7-af00-cd21c7602b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85905
1825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.859051825
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2401020285
Short name T222
Test name
Test status
Simulation time 29915867620 ps
CPU time 1885.77 seconds
Started Jun 09 12:38:13 PM PDT 24
Finished Jun 09 01:09:39 PM PDT 24
Peak memory 288592 kb
Host smart-6c51b142-cf7e-4e66-9b08-03fc1d54453b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401020285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2401020285
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.347125743
Short name T189
Test name
Test status
Simulation time 70830368666 ps
CPU time 1805.2 seconds
Started Jun 09 12:38:12 PM PDT 24
Finished Jun 09 01:08:18 PM PDT 24
Peak memory 298244 kb
Host smart-06a942e0-6798-4812-b619-ad3396dfbbee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347125743 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.347125743
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.128532766
Short name T602
Test name
Test status
Simulation time 87033878200 ps
CPU time 2748.96 seconds
Started Jun 09 12:38:05 PM PDT 24
Finished Jun 09 01:23:55 PM PDT 24
Peak memory 289236 kb
Host smart-51016742-a34b-4185-95b6-ad2eb8430414
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128532766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.128532766
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.4205943277
Short name T371
Test name
Test status
Simulation time 6110291832 ps
CPU time 133.42 seconds
Started Jun 09 12:38:09 PM PDT 24
Finished Jun 09 12:40:23 PM PDT 24
Peak memory 256912 kb
Host smart-5ca138e4-190a-4363-979e-2704c100c567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42059
43277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.4205943277
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3741044645
Short name T541
Test name
Test status
Simulation time 883324618 ps
CPU time 52.33 seconds
Started Jun 09 12:38:18 PM PDT 24
Finished Jun 09 12:39:11 PM PDT 24
Peak memory 255820 kb
Host smart-40abc877-74b8-4720-87c2-c0c663e92b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37410
44645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3741044645
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.37035429
Short name T544
Test name
Test status
Simulation time 81736681267 ps
CPU time 980.26 seconds
Started Jun 09 12:38:11 PM PDT 24
Finished Jun 09 12:54:32 PM PDT 24
Peak memory 265096 kb
Host smart-74ae7f02-852c-4fd2-8982-3c72cd52836d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37035429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.37035429
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3798420866
Short name T18
Test name
Test status
Simulation time 11771584389 ps
CPU time 1134.96 seconds
Started Jun 09 12:38:03 PM PDT 24
Finished Jun 09 12:56:58 PM PDT 24
Peak memory 273048 kb
Host smart-63c3f29f-4589-44a6-9547-04b670ab98eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798420866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3798420866
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1371137239
Short name T672
Test name
Test status
Simulation time 39549451473 ps
CPU time 412.31 seconds
Started Jun 09 12:38:14 PM PDT 24
Finished Jun 09 12:45:07 PM PDT 24
Peak memory 254712 kb
Host smart-10dfc14a-a6e3-488b-9bdc-f955cd257a81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371137239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1371137239
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2866608929
Short name T542
Test name
Test status
Simulation time 1740029833 ps
CPU time 27.93 seconds
Started Jun 09 12:38:12 PM PDT 24
Finished Jun 09 12:38:40 PM PDT 24
Peak memory 256228 kb
Host smart-a5988cfb-114b-4598-b4f8-c7d4458ada18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28666
08929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2866608929
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.978256273
Short name T368
Test name
Test status
Simulation time 3095651682 ps
CPU time 45.77 seconds
Started Jun 09 12:38:25 PM PDT 24
Finished Jun 09 12:39:12 PM PDT 24
Peak memory 256912 kb
Host smart-fb46ddd4-83e1-41e8-89aa-c7b126b4cd65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97825
6273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.978256273
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1892314709
Short name T117
Test name
Test status
Simulation time 181763426 ps
CPU time 22.1 seconds
Started Jun 09 12:38:14 PM PDT 24
Finished Jun 09 12:38:37 PM PDT 24
Peak memory 248740 kb
Host smart-9a3e5fb7-98d2-4a40-9024-2812d915c1a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18923
14709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1892314709
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2569980082
Short name T31
Test name
Test status
Simulation time 3617658891 ps
CPU time 22.98 seconds
Started Jun 09 12:38:15 PM PDT 24
Finished Jun 09 12:38:39 PM PDT 24
Peak memory 255960 kb
Host smart-3f339698-8c95-4d27-86b4-998c294f88ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25699
80082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2569980082
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.4124722220
Short name T443
Test name
Test status
Simulation time 10358553457 ps
CPU time 442.21 seconds
Started Jun 09 12:38:07 PM PDT 24
Finished Jun 09 12:45:29 PM PDT 24
Peak memory 265132 kb
Host smart-c61bd3fc-393d-4b42-a22f-ba8d42d2020b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124722220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.4124722220
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2733008881
Short name T426
Test name
Test status
Simulation time 43876358976 ps
CPU time 2556.79 seconds
Started Jun 09 12:38:18 PM PDT 24
Finished Jun 09 01:20:56 PM PDT 24
Peak memory 287416 kb
Host smart-d427acb4-9180-4e14-97d5-f528cb0a6ba1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733008881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2733008881
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1032087975
Short name T529
Test name
Test status
Simulation time 1483579264 ps
CPU time 92.64 seconds
Started Jun 09 12:38:12 PM PDT 24
Finished Jun 09 12:39:45 PM PDT 24
Peak memory 256484 kb
Host smart-264005f3-44de-40c0-8399-154cdc78fa03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10320
87975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1032087975
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.519234505
Short name T483
Test name
Test status
Simulation time 600775558 ps
CPU time 32.32 seconds
Started Jun 09 12:38:13 PM PDT 24
Finished Jun 09 12:38:45 PM PDT 24
Peak memory 254564 kb
Host smart-76d1dba2-fccc-4531-8f80-1356b1867649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51923
4505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.519234505
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1689812817
Short name T311
Test name
Test status
Simulation time 35751865669 ps
CPU time 1536.79 seconds
Started Jun 09 12:38:14 PM PDT 24
Finished Jun 09 01:03:51 PM PDT 24
Peak memory 286700 kb
Host smart-c6772277-850b-45a6-ba8d-47bde825907e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689812817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1689812817
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3948915177
Short name T466
Test name
Test status
Simulation time 382890834099 ps
CPU time 1355.35 seconds
Started Jun 09 12:38:14 PM PDT 24
Finished Jun 09 01:00:50 PM PDT 24
Peak memory 272792 kb
Host smart-8d09bf64-5365-4da3-ad48-983c0ae0e4d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948915177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3948915177
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2031622402
Short name T573
Test name
Test status
Simulation time 447319371 ps
CPU time 21.33 seconds
Started Jun 09 12:38:11 PM PDT 24
Finished Jun 09 12:38:33 PM PDT 24
Peak memory 256280 kb
Host smart-1ebfc94d-044e-43d8-8e64-0055ec1b6ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20316
22402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2031622402
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.569146051
Short name T406
Test name
Test status
Simulation time 2506279976 ps
CPU time 22.75 seconds
Started Jun 09 12:38:14 PM PDT 24
Finished Jun 09 12:38:37 PM PDT 24
Peak memory 248784 kb
Host smart-1a420eaa-e226-467e-85b4-c39d8ba27dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56914
6051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.569146051
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.489399926
Short name T412
Test name
Test status
Simulation time 257732218 ps
CPU time 4.64 seconds
Started Jun 09 12:38:14 PM PDT 24
Finished Jun 09 12:38:20 PM PDT 24
Peak memory 240512 kb
Host smart-b5c84c4c-858b-4a11-973c-338c3333ee4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48939
9926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.489399926
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3695330462
Short name T499
Test name
Test status
Simulation time 4447792672 ps
CPU time 59.79 seconds
Started Jun 09 12:38:11 PM PDT 24
Finished Jun 09 12:39:12 PM PDT 24
Peak memory 248680 kb
Host smart-d704fdf9-2f88-4cc3-a9ee-0fd54f2d93c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36953
30462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3695330462
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2089482569
Short name T654
Test name
Test status
Simulation time 548808781 ps
CPU time 44.75 seconds
Started Jun 09 12:38:18 PM PDT 24
Finished Jun 09 12:39:03 PM PDT 24
Peak memory 256500 kb
Host smart-104518d2-b208-49c8-a5e1-e9fc0503763f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089482569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2089482569
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3508788014
Short name T534
Test name
Test status
Simulation time 55713173752 ps
CPU time 3005.99 seconds
Started Jun 09 12:38:15 PM PDT 24
Finished Jun 09 01:28:22 PM PDT 24
Peak memory 289428 kb
Host smart-d63f207c-f17c-413f-814b-8409cf355509
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508788014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3508788014
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.323331263
Short name T128
Test name
Test status
Simulation time 902391302 ps
CPU time 38.83 seconds
Started Jun 09 12:38:13 PM PDT 24
Finished Jun 09 12:38:53 PM PDT 24
Peak memory 249116 kb
Host smart-ed983c56-03e6-4a35-bca0-22915057789d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32333
1263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.323331263
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2015464500
Short name T448
Test name
Test status
Simulation time 6532769164 ps
CPU time 41.82 seconds
Started Jun 09 12:38:13 PM PDT 24
Finished Jun 09 12:38:55 PM PDT 24
Peak memory 255564 kb
Host smart-68bd2f09-7707-454e-9e3f-dbafb74f82eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20154
64500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2015464500
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1725852626
Short name T308
Test name
Test status
Simulation time 136192074059 ps
CPU time 1135.44 seconds
Started Jun 09 12:38:11 PM PDT 24
Finished Jun 09 12:57:08 PM PDT 24
Peak memory 265092 kb
Host smart-14a1be54-4625-4f7e-86c9-baebbb96cdba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725852626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1725852626
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3078535975
Short name T19
Test name
Test status
Simulation time 69813625931 ps
CPU time 2323.11 seconds
Started Jun 09 12:38:15 PM PDT 24
Finished Jun 09 01:16:59 PM PDT 24
Peak memory 281504 kb
Host smart-3dfb539e-3168-48a9-91df-cfd4ffe50786
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078535975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3078535975
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2659434357
Short name T642
Test name
Test status
Simulation time 66754128836 ps
CPU time 561.4 seconds
Started Jun 09 12:38:12 PM PDT 24
Finished Jun 09 12:47:34 PM PDT 24
Peak memory 254744 kb
Host smart-0e603426-159e-4989-adc2-9c2197bd65b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659434357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2659434357
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2498280431
Short name T480
Test name
Test status
Simulation time 4147974284 ps
CPU time 67.39 seconds
Started Jun 09 12:38:02 PM PDT 24
Finished Jun 09 12:39:10 PM PDT 24
Peak memory 256440 kb
Host smart-39a76ac7-0d02-4f64-84f3-aa3627c6e6ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24982
80431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2498280431
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1019286210
Short name T45
Test name
Test status
Simulation time 2949082618 ps
CPU time 46.26 seconds
Started Jun 09 12:38:18 PM PDT 24
Finished Jun 09 12:39:05 PM PDT 24
Peak memory 248760 kb
Host smart-9007320e-7aaa-4a5a-97b9-8bf2a48f7204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10192
86210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1019286210
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3869620108
Short name T416
Test name
Test status
Simulation time 596128905 ps
CPU time 42.18 seconds
Started Jun 09 12:38:13 PM PDT 24
Finished Jun 09 12:38:56 PM PDT 24
Peak memory 256796 kb
Host smart-e552fff7-db76-405d-9ccd-ce3b548ec109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38696
20108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3869620108
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2958717936
Short name T450
Test name
Test status
Simulation time 1950139110 ps
CPU time 30.83 seconds
Started Jun 09 12:38:07 PM PDT 24
Finished Jun 09 12:38:38 PM PDT 24
Peak memory 256800 kb
Host smart-a5ac9ae8-9475-47c0-aad6-d84917a1038a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29587
17936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2958717936
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1771331812
Short name T577
Test name
Test status
Simulation time 21510620182 ps
CPU time 1740.69 seconds
Started Jun 09 12:38:12 PM PDT 24
Finished Jun 09 01:07:14 PM PDT 24
Peak memory 304192 kb
Host smart-ebea791c-e48c-4cf9-8f77-c7123f44e189
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771331812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1771331812
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2036290461
Short name T207
Test name
Test status
Simulation time 173196104 ps
CPU time 3.78 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 12:37:47 PM PDT 24
Peak memory 248856 kb
Host smart-bf7bbb43-7514-4a96-b26e-dedb83dd9a0b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2036290461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2036290461
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1448440438
Short name T455
Test name
Test status
Simulation time 62380729692 ps
CPU time 2251 seconds
Started Jun 09 12:37:38 PM PDT 24
Finished Jun 09 01:15:10 PM PDT 24
Peak memory 288712 kb
Host smart-af74b161-ab9e-4d54-bfd1-5435e92e0e94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448440438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1448440438
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3836679094
Short name T449
Test name
Test status
Simulation time 1956415257 ps
CPU time 41.86 seconds
Started Jun 09 12:37:41 PM PDT 24
Finished Jun 09 12:38:24 PM PDT 24
Peak memory 240516 kb
Host smart-70d6d4cc-fe81-4bb5-8378-6654fc1bd781
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3836679094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3836679094
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2144078721
Short name T601
Test name
Test status
Simulation time 848179856 ps
CPU time 47.09 seconds
Started Jun 09 12:37:36 PM PDT 24
Finished Jun 09 12:38:23 PM PDT 24
Peak memory 256472 kb
Host smart-30737367-5549-44e9-95d2-0c7402595b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21440
78721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2144078721
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3667872252
Short name T631
Test name
Test status
Simulation time 1199491451 ps
CPU time 42.84 seconds
Started Jun 09 12:38:02 PM PDT 24
Finished Jun 09 12:38:46 PM PDT 24
Peak memory 248640 kb
Host smart-860215b7-a6e7-4cdf-ba90-c0e9589ffecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36678
72252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3667872252
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1525425060
Short name T305
Test name
Test status
Simulation time 58937943484 ps
CPU time 961.93 seconds
Started Jun 09 12:37:41 PM PDT 24
Finished Jun 09 12:53:44 PM PDT 24
Peak memory 273260 kb
Host smart-b92d37b5-426b-4587-8849-02cc95feac4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525425060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1525425060
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2030737119
Short name T454
Test name
Test status
Simulation time 37155366959 ps
CPU time 2254.3 seconds
Started Jun 09 12:37:36 PM PDT 24
Finished Jun 09 01:15:12 PM PDT 24
Peak memory 288760 kb
Host smart-665f529c-80a7-40d3-ab97-80cd78535c8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030737119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2030737119
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2049186153
Short name T396
Test name
Test status
Simulation time 628501061 ps
CPU time 34.44 seconds
Started Jun 09 12:37:30 PM PDT 24
Finished Jun 09 12:38:05 PM PDT 24
Peak memory 255964 kb
Host smart-be8cb4b5-c7e2-4268-a5cb-d4a0b6f1d810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20491
86153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2049186153
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.3970817734
Short name T562
Test name
Test status
Simulation time 711903688 ps
CPU time 45.05 seconds
Started Jun 09 12:37:37 PM PDT 24
Finished Jun 09 12:38:23 PM PDT 24
Peak memory 255696 kb
Host smart-380249dc-e7ab-4def-86de-49895aee1e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39708
17734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3970817734
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1759876196
Short name T9
Test name
Test status
Simulation time 474167879 ps
CPU time 26.16 seconds
Started Jun 09 12:37:34 PM PDT 24
Finished Jun 09 12:38:00 PM PDT 24
Peak memory 278012 kb
Host smart-3249c9d2-6f30-4417-9ef4-2faaafb2aefd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1759876196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1759876196
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3063782939
Short name T232
Test name
Test status
Simulation time 555102926 ps
CPU time 37.19 seconds
Started Jun 09 12:37:40 PM PDT 24
Finished Jun 09 12:38:18 PM PDT 24
Peak memory 247628 kb
Host smart-8e738ce7-6a6d-456e-b3ed-6dfff7f5a183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30637
82939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3063782939
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3334323778
Short name T491
Test name
Test status
Simulation time 1367798228 ps
CPU time 71.11 seconds
Started Jun 09 12:37:36 PM PDT 24
Finished Jun 09 12:38:48 PM PDT 24
Peak memory 248628 kb
Host smart-df0544c4-08be-4e1d-8184-05e0d999b6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33343
23778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3334323778
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3982373923
Short name T700
Test name
Test status
Simulation time 29942956336 ps
CPU time 1137.76 seconds
Started Jun 09 12:38:21 PM PDT 24
Finished Jun 09 12:57:19 PM PDT 24
Peak memory 289524 kb
Host smart-9a2f1714-3a96-4c25-8036-af9a709d51b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982373923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3982373923
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.420763971
Short name T530
Test name
Test status
Simulation time 1083024219 ps
CPU time 67.93 seconds
Started Jun 09 12:38:07 PM PDT 24
Finished Jun 09 12:39:15 PM PDT 24
Peak memory 249080 kb
Host smart-c87d5b60-2c49-4a46-b22d-7745cb70fd8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42076
3971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.420763971
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.88105133
Short name T369
Test name
Test status
Simulation time 616910955 ps
CPU time 35.31 seconds
Started Jun 09 12:38:13 PM PDT 24
Finished Jun 09 12:38:49 PM PDT 24
Peak memory 254888 kb
Host smart-1ed69240-c532-45aa-85e1-bfb50629f72a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88105
133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.88105133
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.1967291975
Short name T643
Test name
Test status
Simulation time 34256254608 ps
CPU time 1947.16 seconds
Started Jun 09 12:38:26 PM PDT 24
Finished Jun 09 01:10:53 PM PDT 24
Peak memory 286608 kb
Host smart-2745aa99-b366-4758-926b-8f0c35a0fb3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967291975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1967291975
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.937407196
Short name T42
Test name
Test status
Simulation time 4197382296 ps
CPU time 30.72 seconds
Started Jun 09 12:38:18 PM PDT 24
Finished Jun 09 12:38:49 PM PDT 24
Peak memory 256080 kb
Host smart-4f02719d-e44f-4b38-9e56-e27a56a2fce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93740
7196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.937407196
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.4004294456
Short name T260
Test name
Test status
Simulation time 307415221 ps
CPU time 18.47 seconds
Started Jun 09 12:38:10 PM PDT 24
Finished Jun 09 12:38:29 PM PDT 24
Peak memory 248644 kb
Host smart-aacd6e07-c629-4ae6-8cbc-dd9e383f37f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40042
94456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.4004294456
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.2438125785
Short name T580
Test name
Test status
Simulation time 1171272513 ps
CPU time 34.13 seconds
Started Jun 09 12:38:13 PM PDT 24
Finished Jun 09 12:38:47 PM PDT 24
Peak memory 247764 kb
Host smart-a85a4cf1-a6d6-4425-b6a6-b82ce7567284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24381
25785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2438125785
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.494642774
Short name T41
Test name
Test status
Simulation time 773935436 ps
CPU time 16.8 seconds
Started Jun 09 12:38:14 PM PDT 24
Finished Jun 09 12:38:31 PM PDT 24
Peak memory 248708 kb
Host smart-d4f4a80d-6ec1-4d2e-91c3-6ef775a50dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49464
2774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.494642774
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2331843804
Short name T693
Test name
Test status
Simulation time 62391348740 ps
CPU time 3046.17 seconds
Started Jun 09 12:38:22 PM PDT 24
Finished Jun 09 01:29:09 PM PDT 24
Peak memory 305920 kb
Host smart-1602f8e3-7bb8-43ed-8ca3-9db4fc3917e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331843804 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2331843804
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1113666512
Short name T26
Test name
Test status
Simulation time 206855419123 ps
CPU time 2587.82 seconds
Started Jun 09 12:38:31 PM PDT 24
Finished Jun 09 01:21:39 PM PDT 24
Peak memory 289180 kb
Host smart-242a9d94-d855-4338-93c1-4eeb319af071
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113666512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1113666512
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.4243842964
Short name T348
Test name
Test status
Simulation time 1873473424 ps
CPU time 45.77 seconds
Started Jun 09 12:38:16 PM PDT 24
Finished Jun 09 12:39:03 PM PDT 24
Peak memory 248568 kb
Host smart-721e4f39-fc4e-4a26-a3b1-9470cf253216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42438
42964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.4243842964
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2697909342
Short name T704
Test name
Test status
Simulation time 274162636 ps
CPU time 5.54 seconds
Started Jun 09 12:38:14 PM PDT 24
Finished Jun 09 12:38:20 PM PDT 24
Peak memory 239500 kb
Host smart-012006a2-d74b-4a17-bacb-b75533002f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26979
09342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2697909342
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.612186316
Short name T320
Test name
Test status
Simulation time 481072587401 ps
CPU time 1493.71 seconds
Started Jun 09 12:38:15 PM PDT 24
Finished Jun 09 01:03:09 PM PDT 24
Peak memory 268208 kb
Host smart-aa068f2c-4591-4668-947c-cd20829eb27b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612186316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.612186316
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1148892041
Short name T266
Test name
Test status
Simulation time 44209700589 ps
CPU time 1379.89 seconds
Started Jun 09 12:38:15 PM PDT 24
Finished Jun 09 01:01:15 PM PDT 24
Peak memory 271272 kb
Host smart-239f7fb2-eb2c-4117-973c-dad2e401cd43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148892041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1148892041
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1002444121
Short name T650
Test name
Test status
Simulation time 43152893880 ps
CPU time 471.02 seconds
Started Jun 09 12:38:20 PM PDT 24
Finished Jun 09 12:46:11 PM PDT 24
Peak memory 248436 kb
Host smart-85ec5a47-a5c5-42e1-8dc8-397fc8c4defd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002444121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1002444121
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2377475599
Short name T399
Test name
Test status
Simulation time 315942264 ps
CPU time 32.33 seconds
Started Jun 09 12:38:17 PM PDT 24
Finished Jun 09 12:38:49 PM PDT 24
Peak memory 248644 kb
Host smart-fd4ba0cf-df25-49f3-9069-57fe592b5a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23774
75599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2377475599
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2847306729
Short name T492
Test name
Test status
Simulation time 52986330 ps
CPU time 4.99 seconds
Started Jun 09 12:38:10 PM PDT 24
Finished Jun 09 12:38:16 PM PDT 24
Peak memory 239152 kb
Host smart-2d43f6ea-beef-4ce1-837c-9831aa0b4626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28473
06729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2847306729
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.643933237
Short name T681
Test name
Test status
Simulation time 16791384 ps
CPU time 2.95 seconds
Started Jun 09 12:38:18 PM PDT 24
Finished Jun 09 12:38:22 PM PDT 24
Peak memory 240520 kb
Host smart-240bf227-d234-44ae-a6a3-e6220a3e3c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64393
3237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.643933237
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3359877879
Short name T606
Test name
Test status
Simulation time 95442386284 ps
CPU time 1149.64 seconds
Started Jun 09 12:38:23 PM PDT 24
Finished Jun 09 12:57:33 PM PDT 24
Peak memory 289428 kb
Host smart-576965c1-4d21-4e9a-89e5-4ff53bfa7f55
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359877879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3359877879
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1072980714
Short name T435
Test name
Test status
Simulation time 79745527964 ps
CPU time 3734.26 seconds
Started Jun 09 12:38:14 PM PDT 24
Finished Jun 09 01:40:29 PM PDT 24
Peak memory 337000 kb
Host smart-9bb7ce5c-4b53-4694-b775-81086d43fb92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072980714 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1072980714
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.613172950
Short name T460
Test name
Test status
Simulation time 25657283923 ps
CPU time 1728.36 seconds
Started Jun 09 12:38:25 PM PDT 24
Finished Jun 09 01:07:14 PM PDT 24
Peak memory 272680 kb
Host smart-be73e696-5f80-4d3c-b56b-750f38891394
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613172950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.613172950
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3865469478
Short name T604
Test name
Test status
Simulation time 6463393785 ps
CPU time 148.23 seconds
Started Jun 09 12:38:19 PM PDT 24
Finished Jun 09 12:40:48 PM PDT 24
Peak memory 256952 kb
Host smart-0ab11723-1b55-46a2-9253-27af2e4c292b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38654
69478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3865469478
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.3533405978
Short name T508
Test name
Test status
Simulation time 2067695147 ps
CPU time 36.66 seconds
Started Jun 09 12:38:13 PM PDT 24
Finished Jun 09 12:38:50 PM PDT 24
Peak memory 254824 kb
Host smart-c9518b73-85fa-478f-8843-11626d2cb10e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35334
05978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3533405978
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.206060708
Short name T694
Test name
Test status
Simulation time 26594487702 ps
CPU time 1463.5 seconds
Started Jun 09 12:38:23 PM PDT 24
Finished Jun 09 01:02:47 PM PDT 24
Peak memory 288780 kb
Host smart-c4f5bf3f-26b4-4b90-a3a8-ff726115b6cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206060708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.206060708
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3818637285
Short name T221
Test name
Test status
Simulation time 15080478618 ps
CPU time 1375.05 seconds
Started Jun 09 12:38:17 PM PDT 24
Finished Jun 09 01:01:13 PM PDT 24
Peak memory 281460 kb
Host smart-e7df27df-1045-4e14-87b6-a5a165b9bc7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818637285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3818637285
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.4029132260
Short name T3
Test name
Test status
Simulation time 7459844145 ps
CPU time 303.46 seconds
Started Jun 09 12:38:16 PM PDT 24
Finished Jun 09 12:43:20 PM PDT 24
Peak memory 247392 kb
Host smart-48bfac9b-090a-49cf-be89-82656f5008da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029132260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.4029132260
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.373264485
Short name T660
Test name
Test status
Simulation time 64117843 ps
CPU time 6.87 seconds
Started Jun 09 12:38:15 PM PDT 24
Finished Jun 09 12:38:23 PM PDT 24
Peak memory 253392 kb
Host smart-acf7cd28-44bc-4e3a-8934-253bf87673fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37326
4485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.373264485
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3503539785
Short name T579
Test name
Test status
Simulation time 3719850467 ps
CPU time 53.05 seconds
Started Jun 09 12:38:15 PM PDT 24
Finished Jun 09 12:39:08 PM PDT 24
Peak memory 255832 kb
Host smart-f10e4651-d48e-408b-8e00-fed35a58141e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35035
39785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3503539785
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.4274759153
Short name T364
Test name
Test status
Simulation time 109399866 ps
CPU time 14.46 seconds
Started Jun 09 12:38:17 PM PDT 24
Finished Jun 09 12:38:31 PM PDT 24
Peak memory 256832 kb
Host smart-89247876-af2a-485c-8060-da6d638682e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42747
59153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.4274759153
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.363558862
Short name T347
Test name
Test status
Simulation time 782370067 ps
CPU time 46.85 seconds
Started Jun 09 12:38:14 PM PDT 24
Finished Jun 09 12:39:02 PM PDT 24
Peak memory 256872 kb
Host smart-fdc480d4-d1bd-435b-afbf-085444e3fd20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36355
8862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.363558862
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.556526734
Short name T244
Test name
Test status
Simulation time 101440998004 ps
CPU time 1703.05 seconds
Started Jun 09 12:38:22 PM PDT 24
Finished Jun 09 01:06:45 PM PDT 24
Peak memory 273404 kb
Host smart-77374a61-8b47-4e4f-9904-f9ef107690a4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556526734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.556526734
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.1926191094
Short name T639
Test name
Test status
Simulation time 80137444194 ps
CPU time 1649.99 seconds
Started Jun 09 12:38:19 PM PDT 24
Finished Jun 09 01:05:50 PM PDT 24
Peak memory 289848 kb
Host smart-c09ce1c5-abbd-4493-b8ee-10d9f625368c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926191094 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.1926191094
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3161065140
Short name T637
Test name
Test status
Simulation time 112232563541 ps
CPU time 1502.94 seconds
Started Jun 09 12:38:17 PM PDT 24
Finished Jun 09 01:03:20 PM PDT 24
Peak memory 288856 kb
Host smart-adb1ed05-82d4-41f6-8516-62c59ddf76f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161065140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3161065140
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1205972392
Short name T68
Test name
Test status
Simulation time 2516575526 ps
CPU time 33.08 seconds
Started Jun 09 12:38:19 PM PDT 24
Finished Jun 09 12:38:53 PM PDT 24
Peak memory 256800 kb
Host smart-606e1ae4-db46-4f8c-85df-58c3081eaa79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12059
72392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1205972392
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2041087546
Short name T361
Test name
Test status
Simulation time 216870924 ps
CPU time 6.56 seconds
Started Jun 09 12:38:16 PM PDT 24
Finished Jun 09 12:38:23 PM PDT 24
Peak memory 252140 kb
Host smart-7315ad52-6c07-4de6-bee2-011fbffaa95b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20410
87546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2041087546
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2204958041
Short name T678
Test name
Test status
Simulation time 83423003593 ps
CPU time 2149.42 seconds
Started Jun 09 12:38:18 PM PDT 24
Finished Jun 09 01:14:08 PM PDT 24
Peak memory 281460 kb
Host smart-49a5e8e0-a276-4ca6-849c-02588e8e7404
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204958041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2204958041
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3184894508
Short name T301
Test name
Test status
Simulation time 228813651729 ps
CPU time 2159.45 seconds
Started Jun 09 12:38:21 PM PDT 24
Finished Jun 09 01:14:21 PM PDT 24
Peak memory 273364 kb
Host smart-0dc2f52e-a8e1-4329-bf0c-10ed74b252a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184894508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3184894508
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3650056602
Short name T270
Test name
Test status
Simulation time 1189176202 ps
CPU time 69.96 seconds
Started Jun 09 12:38:21 PM PDT 24
Finished Jun 09 12:39:31 PM PDT 24
Peak memory 248652 kb
Host smart-618d3449-59f0-4a7a-a21e-5bc1db958c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36500
56602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3650056602
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3583639445
Short name T630
Test name
Test status
Simulation time 1652195231 ps
CPU time 34.68 seconds
Started Jun 09 12:38:18 PM PDT 24
Finished Jun 09 12:38:54 PM PDT 24
Peak memory 256792 kb
Host smart-14cdadf0-28e6-4281-a44b-a2256ebf53bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35836
39445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3583639445
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2379624537
Short name T374
Test name
Test status
Simulation time 167621503 ps
CPU time 20.91 seconds
Started Jun 09 12:38:26 PM PDT 24
Finished Jun 09 12:38:47 PM PDT 24
Peak memory 247528 kb
Host smart-44ff7715-da8c-4888-bf0c-90b8300e2b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23796
24537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2379624537
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2564867295
Short name T626
Test name
Test status
Simulation time 329388807 ps
CPU time 24.64 seconds
Started Jun 09 12:38:18 PM PDT 24
Finished Jun 09 12:38:44 PM PDT 24
Peak memory 248640 kb
Host smart-f853a8d2-9e17-4bd6-a47c-a338894090f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25648
67295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2564867295
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.718178972
Short name T692
Test name
Test status
Simulation time 259173955643 ps
CPU time 4234.96 seconds
Started Jun 09 12:38:23 PM PDT 24
Finished Jun 09 01:48:59 PM PDT 24
Peak memory 336632 kb
Host smart-f87f757f-b6b2-478f-96de-d47a3f5d4a17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718178972 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.718178972
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1959272055
Short name T605
Test name
Test status
Simulation time 26302216699 ps
CPU time 1220.82 seconds
Started Jun 09 12:38:21 PM PDT 24
Finished Jun 09 12:58:42 PM PDT 24
Peak memory 285432 kb
Host smart-2884143d-660d-46e2-ad86-c5a5bc71e831
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959272055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1959272055
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1423032859
Short name T659
Test name
Test status
Simulation time 772861876 ps
CPU time 37.73 seconds
Started Jun 09 12:38:37 PM PDT 24
Finished Jun 09 12:39:15 PM PDT 24
Peak memory 256804 kb
Host smart-ca90fa67-ce41-4501-9754-4c89aa54c31f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14230
32859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1423032859
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2927641141
Short name T498
Test name
Test status
Simulation time 1852404100 ps
CPU time 31.76 seconds
Started Jun 09 12:38:31 PM PDT 24
Finished Jun 09 12:39:03 PM PDT 24
Peak memory 255132 kb
Host smart-3209104d-fcb1-4ff1-ac08-f74e272f3259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29276
41141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2927641141
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1332680543
Short name T653
Test name
Test status
Simulation time 26841277390 ps
CPU time 1715.01 seconds
Started Jun 09 12:38:23 PM PDT 24
Finished Jun 09 01:06:58 PM PDT 24
Peak memory 271304 kb
Host smart-83e5acf5-1c48-4ec4-9f0f-1d28ffa935be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332680543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1332680543
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1005072923
Short name T280
Test name
Test status
Simulation time 11948629346 ps
CPU time 476.54 seconds
Started Jun 09 12:38:22 PM PDT 24
Finished Jun 09 12:46:19 PM PDT 24
Peak memory 248232 kb
Host smart-e925c62e-e74e-48bc-b33e-f135fbf6afbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005072923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1005072923
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2906148198
Short name T486
Test name
Test status
Simulation time 365247226 ps
CPU time 11.12 seconds
Started Jun 09 12:38:24 PM PDT 24
Finished Jun 09 12:38:36 PM PDT 24
Peak memory 248988 kb
Host smart-30384850-b6ce-49de-9953-6e207acf8565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29061
48198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2906148198
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3961375795
Short name T76
Test name
Test status
Simulation time 1881766816 ps
CPU time 23.52 seconds
Started Jun 09 12:38:22 PM PDT 24
Finished Jun 09 12:38:46 PM PDT 24
Peak memory 256288 kb
Host smart-3b68c60c-c140-4f79-b475-62ec57b0ad5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39613
75795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3961375795
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1607736156
Short name T105
Test name
Test status
Simulation time 803591793 ps
CPU time 21.81 seconds
Started Jun 09 12:38:22 PM PDT 24
Finished Jun 09 12:38:44 PM PDT 24
Peak memory 247616 kb
Host smart-c5467545-6c22-4ecd-bdfc-42211398d82f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16077
36156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1607736156
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1827975830
Short name T413
Test name
Test status
Simulation time 1258210605 ps
CPU time 28.47 seconds
Started Jun 09 12:38:19 PM PDT 24
Finished Jun 09 12:38:48 PM PDT 24
Peak memory 256884 kb
Host smart-5a7f3ba1-c431-466f-a965-5b5d18f97676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18279
75830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1827975830
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1811142534
Short name T124
Test name
Test status
Simulation time 43033873906 ps
CPU time 1346.22 seconds
Started Jun 09 12:38:26 PM PDT 24
Finished Jun 09 01:00:53 PM PDT 24
Peak memory 272972 kb
Host smart-2758fca6-7fa9-4920-862d-f0387d479c05
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811142534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1811142534
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.139112287
Short name T71
Test name
Test status
Simulation time 36501540577 ps
CPU time 995.06 seconds
Started Jun 09 12:38:27 PM PDT 24
Finished Jun 09 12:55:02 PM PDT 24
Peak memory 270324 kb
Host smart-9253aa33-508b-49e8-a778-d3c485e52966
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139112287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.139112287
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1278625935
Short name T65
Test name
Test status
Simulation time 217453694 ps
CPU time 26.84 seconds
Started Jun 09 12:38:25 PM PDT 24
Finished Jun 09 12:38:53 PM PDT 24
Peak memory 256244 kb
Host smart-e536973f-a31f-4561-918f-f4d5edb4057b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12786
25935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1278625935
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.4107514169
Short name T612
Test name
Test status
Simulation time 1547683696 ps
CPU time 51.77 seconds
Started Jun 09 12:38:24 PM PDT 24
Finished Jun 09 12:39:16 PM PDT 24
Peak memory 248652 kb
Host smart-3751ebda-7227-4a24-b337-6695e45ef638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41075
14169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.4107514169
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1865695336
Short name T271
Test name
Test status
Simulation time 27330838159 ps
CPU time 987.53 seconds
Started Jun 09 12:38:22 PM PDT 24
Finished Jun 09 12:54:50 PM PDT 24
Peak memory 273396 kb
Host smart-0c873884-a3db-4247-b550-f1c1f0e0f6ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865695336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1865695336
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1880951245
Short name T366
Test name
Test status
Simulation time 117111972500 ps
CPU time 1649.93 seconds
Started Jun 09 12:38:26 PM PDT 24
Finished Jun 09 01:05:57 PM PDT 24
Peak memory 273276 kb
Host smart-9e178ec7-986a-4ce6-808f-7740609fca77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880951245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1880951245
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2938935369
Short name T504
Test name
Test status
Simulation time 9310869155 ps
CPU time 198.77 seconds
Started Jun 09 12:38:27 PM PDT 24
Finished Jun 09 12:41:46 PM PDT 24
Peak memory 247320 kb
Host smart-ee368307-0486-4fc1-ae4e-3ba30ff58086
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938935369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2938935369
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.453794969
Short name T30
Test name
Test status
Simulation time 942761181 ps
CPU time 31.66 seconds
Started Jun 09 12:38:24 PM PDT 24
Finished Jun 09 12:38:56 PM PDT 24
Peak memory 248652 kb
Host smart-18a2bbba-c394-4d61-8ae2-880e6a10ba49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45379
4969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.453794969
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.918334490
Short name T647
Test name
Test status
Simulation time 501168373 ps
CPU time 30.35 seconds
Started Jun 09 12:38:25 PM PDT 24
Finished Jun 09 12:38:56 PM PDT 24
Peak memory 255636 kb
Host smart-d4fc5eac-578e-4cac-a1ac-733f138a1fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91833
4490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.918334490
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3349683168
Short name T702
Test name
Test status
Simulation time 690845916 ps
CPU time 24.43 seconds
Started Jun 09 12:38:24 PM PDT 24
Finished Jun 09 12:38:48 PM PDT 24
Peak memory 248572 kb
Host smart-4524acfd-44ee-4512-85d4-225920a0bcbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33496
83168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3349683168
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1705008415
Short name T457
Test name
Test status
Simulation time 547337490 ps
CPU time 35.51 seconds
Started Jun 09 12:38:22 PM PDT 24
Finished Jun 09 12:38:58 PM PDT 24
Peak memory 248704 kb
Host smart-694ecdb6-1339-44e1-b1f7-263f697227f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17050
08415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1705008415
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.592984559
Short name T20
Test name
Test status
Simulation time 5177981930 ps
CPU time 322.18 seconds
Started Jun 09 12:38:33 PM PDT 24
Finished Jun 09 12:43:56 PM PDT 24
Peak memory 256952 kb
Host smart-9a3c51d3-16fa-444e-840f-dce0a5ea5553
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592984559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.592984559
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3215073857
Short name T89
Test name
Test status
Simulation time 550489889706 ps
CPU time 5944.44 seconds
Started Jun 09 12:38:33 PM PDT 24
Finished Jun 09 02:17:38 PM PDT 24
Peak memory 322032 kb
Host smart-630a58e1-a0d7-495f-bd65-289a453ef6db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215073857 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3215073857
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.4049975011
Short name T619
Test name
Test status
Simulation time 156928743210 ps
CPU time 2349 seconds
Started Jun 09 12:38:28 PM PDT 24
Finished Jun 09 01:17:37 PM PDT 24
Peak memory 288600 kb
Host smart-ce9a8db9-e846-46a0-b109-84dd9475bc13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049975011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.4049975011
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1111036186
Short name T595
Test name
Test status
Simulation time 23804200961 ps
CPU time 332.67 seconds
Started Jun 09 12:38:31 PM PDT 24
Finished Jun 09 12:44:04 PM PDT 24
Peak memory 256516 kb
Host smart-78dc396a-20e4-4a05-a523-a82710d84770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11110
36186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1111036186
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3362730107
Short name T545
Test name
Test status
Simulation time 1918008294 ps
CPU time 33.16 seconds
Started Jun 09 12:38:30 PM PDT 24
Finished Jun 09 12:39:04 PM PDT 24
Peak memory 254844 kb
Host smart-19e37614-c310-48e1-ba58-4dce0f9bbe7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33627
30107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3362730107
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.852649707
Short name T414
Test name
Test status
Simulation time 25660978576 ps
CPU time 1071.2 seconds
Started Jun 09 12:38:22 PM PDT 24
Finished Jun 09 12:56:14 PM PDT 24
Peak memory 287164 kb
Host smart-c1234842-7e3a-4823-8557-59acadcf32d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852649707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.852649707
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3721369559
Short name T290
Test name
Test status
Simulation time 4507090652 ps
CPU time 184.05 seconds
Started Jun 09 12:38:32 PM PDT 24
Finished Jun 09 12:41:36 PM PDT 24
Peak memory 247888 kb
Host smart-afe2a49a-0488-4b92-a0c3-2232258116f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721369559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3721369559
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2902485128
Short name T437
Test name
Test status
Simulation time 1306759451 ps
CPU time 36.74 seconds
Started Jun 09 12:38:23 PM PDT 24
Finished Jun 09 12:39:00 PM PDT 24
Peak memory 248648 kb
Host smart-2b79e17f-8cfe-4445-b6f2-f419c1672c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29024
85128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2902485128
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3774642835
Short name T636
Test name
Test status
Simulation time 791887067 ps
CPU time 14.14 seconds
Started Jun 09 12:38:22 PM PDT 24
Finished Jun 09 12:38:36 PM PDT 24
Peak memory 249084 kb
Host smart-6262d98e-7172-4fda-b517-5566c0f9f1ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37746
42835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3774642835
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2631466989
Short name T431
Test name
Test status
Simulation time 353600909 ps
CPU time 5.62 seconds
Started Jun 09 12:38:29 PM PDT 24
Finished Jun 09 12:38:35 PM PDT 24
Peak memory 240408 kb
Host smart-f15e6e3b-cd88-4c53-8dbe-15182f65053d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26314
66989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2631466989
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3883922580
Short name T583
Test name
Test status
Simulation time 7672638423 ps
CPU time 734.44 seconds
Started Jun 09 12:38:25 PM PDT 24
Finished Jun 09 12:50:40 PM PDT 24
Peak memory 273156 kb
Host smart-40730f2d-2c87-4212-a901-457c0ae96a5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883922580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3883922580
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1712632351
Short name T381
Test name
Test status
Simulation time 1449691019 ps
CPU time 33.41 seconds
Started Jun 09 12:38:37 PM PDT 24
Finished Jun 09 12:39:11 PM PDT 24
Peak memory 256436 kb
Host smart-0a35c4cc-a264-42cf-8446-284750786eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17126
32351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1712632351
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1524762390
Short name T556
Test name
Test status
Simulation time 1446055308 ps
CPU time 41.86 seconds
Started Jun 09 12:38:38 PM PDT 24
Finished Jun 09 12:39:20 PM PDT 24
Peak memory 256796 kb
Host smart-ce5fb902-8c1c-4dd4-b697-d8534a37da62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15247
62390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1524762390
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1137779596
Short name T17
Test name
Test status
Simulation time 15532854602 ps
CPU time 1379.62 seconds
Started Jun 09 12:38:24 PM PDT 24
Finished Jun 09 01:01:24 PM PDT 24
Peak memory 285556 kb
Host smart-22c95f0b-e6aa-4ceb-8e0f-a5d2826074a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137779596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1137779596
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2084146886
Short name T616
Test name
Test status
Simulation time 14623672960 ps
CPU time 142.37 seconds
Started Jun 09 12:38:36 PM PDT 24
Finished Jun 09 12:40:58 PM PDT 24
Peak memory 248032 kb
Host smart-ed1ea54b-619b-4169-995e-11749f3b4bf2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084146886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2084146886
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3586550969
Short name T588
Test name
Test status
Simulation time 1148703391 ps
CPU time 69.47 seconds
Started Jun 09 12:38:36 PM PDT 24
Finished Jun 09 12:39:46 PM PDT 24
Peak memory 256188 kb
Host smart-2680e539-7e73-461f-87b8-07f0f80a80ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35865
50969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3586550969
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2035838769
Short name T633
Test name
Test status
Simulation time 209744578 ps
CPU time 13.27 seconds
Started Jun 09 12:38:37 PM PDT 24
Finished Jun 09 12:38:51 PM PDT 24
Peak memory 252128 kb
Host smart-57746631-7d4d-4fd6-9578-0934d80b2054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20358
38769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2035838769
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1094922837
Short name T268
Test name
Test status
Simulation time 407614570 ps
CPU time 32.13 seconds
Started Jun 09 12:38:35 PM PDT 24
Finished Jun 09 12:39:07 PM PDT 24
Peak memory 247392 kb
Host smart-b01bd9bc-42d6-410c-8c31-f61f05e396df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10949
22837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1094922837
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.804786186
Short name T614
Test name
Test status
Simulation time 2902004849 ps
CPU time 47.03 seconds
Started Jun 09 12:38:35 PM PDT 24
Finished Jun 09 12:39:22 PM PDT 24
Peak memory 256936 kb
Host smart-90fb0b00-faf3-4f90-8ce7-820f3fa3766d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80478
6186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.804786186
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2822328210
Short name T62
Test name
Test status
Simulation time 85177745241 ps
CPU time 2472.28 seconds
Started Jun 09 12:38:28 PM PDT 24
Finished Jun 09 01:19:40 PM PDT 24
Peak memory 289680 kb
Host smart-770b5eb3-f91b-4b84-b5a0-bbcf16440772
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822328210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2822328210
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.269987033
Short name T83
Test name
Test status
Simulation time 32030867059 ps
CPU time 1911.2 seconds
Started Jun 09 12:38:31 PM PDT 24
Finished Jun 09 01:10:23 PM PDT 24
Peak memory 289368 kb
Host smart-4ae8e912-de0f-4e98-ac95-e91c91c0248b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269987033 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.269987033
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.1206836452
Short name T100
Test name
Test status
Simulation time 47948354504 ps
CPU time 2500.22 seconds
Started Jun 09 12:38:29 PM PDT 24
Finished Jun 09 01:20:10 PM PDT 24
Peak memory 288952 kb
Host smart-25621f2f-f60a-452a-9cad-ab24d74f38cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206836452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1206836452
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.930238563
Short name T576
Test name
Test status
Simulation time 2484893127 ps
CPU time 76.51 seconds
Started Jun 09 12:38:29 PM PDT 24
Finished Jun 09 12:39:46 PM PDT 24
Peak memory 256856 kb
Host smart-16ca53e7-9391-4e76-a197-ddefbb526691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93023
8563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.930238563
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.872826095
Short name T77
Test name
Test status
Simulation time 1498309081 ps
CPU time 29.99 seconds
Started Jun 09 12:38:31 PM PDT 24
Finished Jun 09 12:39:02 PM PDT 24
Peak memory 255676 kb
Host smart-70ea4cf0-2f39-49fb-b2dd-d7f1c65af927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87282
6095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.872826095
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3686815391
Short name T307
Test name
Test status
Simulation time 21480846519 ps
CPU time 1185.84 seconds
Started Jun 09 12:38:31 PM PDT 24
Finished Jun 09 12:58:18 PM PDT 24
Peak memory 273336 kb
Host smart-a92b8c66-7bfa-482f-82b1-26b838dc98f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686815391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3686815391
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1050559565
Short name T523
Test name
Test status
Simulation time 100024623397 ps
CPU time 1840.01 seconds
Started Jun 09 12:38:36 PM PDT 24
Finished Jun 09 01:09:16 PM PDT 24
Peak memory 273328 kb
Host smart-027ec319-d3e6-4fb1-8abf-acbed2f319c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050559565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1050559565
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.763793568
Short name T97
Test name
Test status
Simulation time 11020999573 ps
CPU time 458.93 seconds
Started Jun 09 12:38:30 PM PDT 24
Finished Jun 09 12:46:09 PM PDT 24
Peak memory 247984 kb
Host smart-021b7c50-c673-48ea-9e3a-c78939e15458
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763793568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.763793568
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2836944303
Short name T597
Test name
Test status
Simulation time 462832242 ps
CPU time 35.84 seconds
Started Jun 09 12:38:35 PM PDT 24
Finished Jun 09 12:39:11 PM PDT 24
Peak memory 248712 kb
Host smart-df1e4201-58e9-4b5d-86d1-871bc4d5cbaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28369
44303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2836944303
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1706258887
Short name T531
Test name
Test status
Simulation time 402468396 ps
CPU time 9.66 seconds
Started Jun 09 12:38:26 PM PDT 24
Finished Jun 09 12:38:36 PM PDT 24
Peak memory 251928 kb
Host smart-684ee815-1ee1-48e7-860d-27649d9f15f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17062
58887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1706258887
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.333480159
Short name T240
Test name
Test status
Simulation time 1753713514 ps
CPU time 54.62 seconds
Started Jun 09 12:38:35 PM PDT 24
Finished Jun 09 12:39:30 PM PDT 24
Peak memory 255692 kb
Host smart-66aeff4b-2913-4a72-876f-2a7b63f777cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33348
0159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.333480159
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2422086943
Short name T488
Test name
Test status
Simulation time 499204993 ps
CPU time 6.26 seconds
Started Jun 09 12:38:26 PM PDT 24
Finished Jun 09 12:38:32 PM PDT 24
Peak memory 240428 kb
Host smart-1483c115-6c8d-44b4-9fa9-1f8139a43022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24220
86943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2422086943
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3622784211
Short name T255
Test name
Test status
Simulation time 9927033263 ps
CPU time 809.4 seconds
Started Jun 09 12:38:30 PM PDT 24
Finished Jun 09 12:52:00 PM PDT 24
Peak memory 267188 kb
Host smart-1872c532-31aa-489f-a4b8-0be391ea5cb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622784211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3622784211
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2377269448
Short name T586
Test name
Test status
Simulation time 516167557 ps
CPU time 27.89 seconds
Started Jun 09 12:38:34 PM PDT 24
Finished Jun 09 12:39:02 PM PDT 24
Peak memory 256796 kb
Host smart-ae6a77f6-9ec3-469a-8839-f7e73308729f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23772
69448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2377269448
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.895602674
Short name T34
Test name
Test status
Simulation time 1583716347 ps
CPU time 47.89 seconds
Started Jun 09 12:38:36 PM PDT 24
Finished Jun 09 12:39:24 PM PDT 24
Peak memory 254864 kb
Host smart-8d5fefa9-c409-4779-ae2e-ce8db60cf389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89560
2674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.895602674
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3652761997
Short name T274
Test name
Test status
Simulation time 80532292852 ps
CPU time 859.84 seconds
Started Jun 09 12:38:29 PM PDT 24
Finished Jun 09 12:52:49 PM PDT 24
Peak memory 273340 kb
Host smart-5a134eff-a86a-46a4-891c-5bd2e0bf3f4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652761997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3652761997
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.807746452
Short name T677
Test name
Test status
Simulation time 259100751649 ps
CPU time 1728.42 seconds
Started Jun 09 12:38:30 PM PDT 24
Finished Jun 09 01:07:18 PM PDT 24
Peak memory 273320 kb
Host smart-944e7235-411d-48eb-bd35-90d44f7dba51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807746452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.807746452
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.4125147019
Short name T557
Test name
Test status
Simulation time 52871451507 ps
CPU time 579.14 seconds
Started Jun 09 12:38:30 PM PDT 24
Finished Jun 09 12:48:09 PM PDT 24
Peak memory 248420 kb
Host smart-e87bb600-6a9c-4f7d-8fd0-85b7ac194fd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125147019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.4125147019
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1094415852
Short name T467
Test name
Test status
Simulation time 269858179 ps
CPU time 16.83 seconds
Started Jun 09 12:38:30 PM PDT 24
Finished Jun 09 12:38:47 PM PDT 24
Peak memory 249072 kb
Host smart-607df5d9-c76a-44cb-9ba1-19875bbfd37b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10944
15852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1094415852
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.3238952161
Short name T389
Test name
Test status
Simulation time 8341260288 ps
CPU time 49.13 seconds
Started Jun 09 12:38:30 PM PDT 24
Finished Jun 09 12:39:19 PM PDT 24
Peak memory 256360 kb
Host smart-f17868e2-f728-4627-a5dd-aca97d834014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32389
52161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3238952161
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2067295408
Short name T376
Test name
Test status
Simulation time 1090332995 ps
CPU time 21.21 seconds
Started Jun 09 12:38:29 PM PDT 24
Finished Jun 09 12:38:51 PM PDT 24
Peak memory 254508 kb
Host smart-4b99930b-f2d3-4d79-a2d2-d1ceed02fc58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20672
95408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2067295408
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2275600925
Short name T430
Test name
Test status
Simulation time 520280117 ps
CPU time 26.68 seconds
Started Jun 09 12:38:30 PM PDT 24
Finished Jun 09 12:38:57 PM PDT 24
Peak memory 248616 kb
Host smart-0941a304-9ac8-4f2f-a044-f84bf648f39f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22756
00925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2275600925
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.667796369
Short name T203
Test name
Test status
Simulation time 61852478 ps
CPU time 2.6 seconds
Started Jun 09 12:37:41 PM PDT 24
Finished Jun 09 12:37:45 PM PDT 24
Peak memory 248848 kb
Host smart-57b4ec64-39b2-4d76-9ce3-11666f2f1e21
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=667796369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.667796369
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2127749717
Short name T112
Test name
Test status
Simulation time 14275440076 ps
CPU time 737.45 seconds
Started Jun 09 12:37:36 PM PDT 24
Finished Jun 09 12:49:55 PM PDT 24
Peak memory 273300 kb
Host smart-5d14a19f-24c4-448e-83ff-097bb219e431
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127749717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2127749717
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.4223689772
Short name T538
Test name
Test status
Simulation time 462724766 ps
CPU time 20.5 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 12:38:05 PM PDT 24
Peak memory 248708 kb
Host smart-ba72baf5-b7f9-4f40-8493-dc6839b4f771
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4223689772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.4223689772
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2201640407
Short name T373
Test name
Test status
Simulation time 7326942595 ps
CPU time 133.29 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 12:39:59 PM PDT 24
Peak memory 256852 kb
Host smart-7953fd28-e5a5-441f-9277-3f811efb0c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22016
40407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2201640407
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1118529381
Short name T494
Test name
Test status
Simulation time 435424750 ps
CPU time 24.94 seconds
Started Jun 09 12:38:07 PM PDT 24
Finished Jun 09 12:38:33 PM PDT 24
Peak memory 255712 kb
Host smart-6b2abce8-a009-4c49-b7dc-b3b1c1c82a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11185
29381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1118529381
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.4203295903
Short name T567
Test name
Test status
Simulation time 65710096532 ps
CPU time 1793.98 seconds
Started Jun 09 12:37:41 PM PDT 24
Finished Jun 09 01:07:36 PM PDT 24
Peak memory 273340 kb
Host smart-4826b875-bf13-4ede-bf75-60382107d7a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203295903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.4203295903
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2202931718
Short name T264
Test name
Test status
Simulation time 68343442522 ps
CPU time 1671.12 seconds
Started Jun 09 12:37:37 PM PDT 24
Finished Jun 09 01:05:30 PM PDT 24
Peak memory 283184 kb
Host smart-89a3ee78-155d-4a10-ade1-602ba276aa6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202931718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2202931718
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.445999637
Short name T345
Test name
Test status
Simulation time 672561940 ps
CPU time 22.65 seconds
Started Jun 09 12:37:36 PM PDT 24
Finished Jun 09 12:37:59 PM PDT 24
Peak memory 248608 kb
Host smart-e3e3e940-2e4c-4506-8f85-5e73e7adb392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44599
9637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.445999637
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1775303995
Short name T359
Test name
Test status
Simulation time 2060088069 ps
CPU time 27.14 seconds
Started Jun 09 12:37:33 PM PDT 24
Finished Jun 09 12:38:01 PM PDT 24
Peak memory 256056 kb
Host smart-f81b658e-d931-40af-a1e8-c664fa0a4c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17753
03995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1775303995
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.371776081
Short name T28
Test name
Test status
Simulation time 625588797 ps
CPU time 27.77 seconds
Started Jun 09 12:37:34 PM PDT 24
Finished Jun 09 12:38:03 PM PDT 24
Peak memory 270268 kb
Host smart-3030a287-107a-4e28-969a-d3b1d4eaccd3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=371776081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.371776081
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.523416611
Short name T239
Test name
Test status
Simulation time 1558234563 ps
CPU time 29.47 seconds
Started Jun 09 12:37:36 PM PDT 24
Finished Jun 09 12:38:06 PM PDT 24
Peak memory 248684 kb
Host smart-e07f3546-e285-4d6c-87ca-4697688c5370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52341
6611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.523416611
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1661968498
Short name T594
Test name
Test status
Simulation time 160526372 ps
CPU time 11.5 seconds
Started Jun 09 12:37:40 PM PDT 24
Finished Jun 09 12:37:53 PM PDT 24
Peak memory 248696 kb
Host smart-94675a36-4001-474e-8235-5fe1d419da0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16619
68498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1661968498
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1203910502
Short name T676
Test name
Test status
Simulation time 20149981694 ps
CPU time 1775.08 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 01:07:18 PM PDT 24
Peak memory 289240 kb
Host smart-6f7417bd-399a-48c1-a09a-7d936c31b784
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203910502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1203910502
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3539403721
Short name T411
Test name
Test status
Simulation time 10340417529 ps
CPU time 819.87 seconds
Started Jun 09 12:38:41 PM PDT 24
Finished Jun 09 12:52:21 PM PDT 24
Peak memory 272956 kb
Host smart-050ed506-707a-4ac1-a863-54bb7bb485d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539403721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3539403721
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1494204158
Short name T537
Test name
Test status
Simulation time 2983296999 ps
CPU time 205.73 seconds
Started Jun 09 12:38:36 PM PDT 24
Finished Jun 09 12:42:02 PM PDT 24
Peak memory 256756 kb
Host smart-d13c6a86-4b66-4623-b94d-2cd21043dbcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14942
04158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1494204158
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1583457768
Short name T532
Test name
Test status
Simulation time 488175459 ps
CPU time 24.06 seconds
Started Jun 09 12:38:42 PM PDT 24
Finished Jun 09 12:39:06 PM PDT 24
Peak memory 255872 kb
Host smart-e64ba5f4-247b-4ea2-aeb9-3ae007273214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15834
57768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1583457768
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3871031429
Short name T72
Test name
Test status
Simulation time 42495627648 ps
CPU time 844.27 seconds
Started Jun 09 12:38:33 PM PDT 24
Finished Jun 09 12:52:38 PM PDT 24
Peak memory 273096 kb
Host smart-a82b25ae-6a7f-4f43-b1ae-47362f2bfb67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871031429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3871031429
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3863284582
Short name T539
Test name
Test status
Simulation time 65137067548 ps
CPU time 1373.35 seconds
Started Jun 09 12:38:38 PM PDT 24
Finished Jun 09 01:01:32 PM PDT 24
Peak memory 288820 kb
Host smart-fd0f401c-119a-4f39-ac2c-06347ef891be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863284582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3863284582
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2772420173
Short name T277
Test name
Test status
Simulation time 40365405492 ps
CPU time 472.09 seconds
Started Jun 09 12:38:40 PM PDT 24
Finished Jun 09 12:46:33 PM PDT 24
Peak memory 248164 kb
Host smart-e635d475-9c37-4e64-881b-741105e75377
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772420173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2772420173
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1817047899
Short name T382
Test name
Test status
Simulation time 540281988 ps
CPU time 36.32 seconds
Started Jun 09 12:38:41 PM PDT 24
Finished Jun 09 12:39:18 PM PDT 24
Peak memory 248632 kb
Host smart-28e0966c-2241-4df1-9cc7-756aac1f2739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18170
47899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1817047899
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2206603244
Short name T422
Test name
Test status
Simulation time 543770841 ps
CPU time 23.13 seconds
Started Jun 09 12:38:36 PM PDT 24
Finished Jun 09 12:38:59 PM PDT 24
Peak memory 254964 kb
Host smart-cd2f6434-c1f0-4910-945e-dcbb8a712f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22066
03244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2206603244
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3157057814
Short name T662
Test name
Test status
Simulation time 99842021 ps
CPU time 11.63 seconds
Started Jun 09 12:38:36 PM PDT 24
Finished Jun 09 12:38:48 PM PDT 24
Peak memory 248764 kb
Host smart-7ff1b30a-dc4d-4729-81bf-17de02c04bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31570
57814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3157057814
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2105792487
Short name T468
Test name
Test status
Simulation time 1373457283 ps
CPU time 77.29 seconds
Started Jun 09 12:38:35 PM PDT 24
Finished Jun 09 12:39:53 PM PDT 24
Peak memory 248704 kb
Host smart-f1ea3c5f-0841-4563-a807-14ea8ec7262b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21057
92487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2105792487
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.3452889910
Short name T241
Test name
Test status
Simulation time 71998453328 ps
CPU time 1150.44 seconds
Started Jun 09 12:38:40 PM PDT 24
Finished Jun 09 12:57:51 PM PDT 24
Peak memory 281652 kb
Host smart-9e684f10-bd6a-4320-997c-0e3c3c0a7bde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452889910 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.3452889910
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2258040678
Short name T384
Test name
Test status
Simulation time 72349538962 ps
CPU time 1610.82 seconds
Started Jun 09 12:38:36 PM PDT 24
Finished Jun 09 01:05:28 PM PDT 24
Peak memory 289028 kb
Host smart-b152d0d1-af78-424c-a8dc-23c4863dacfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258040678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2258040678
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3161619520
Short name T37
Test name
Test status
Simulation time 16735981952 ps
CPU time 259.57 seconds
Started Jun 09 12:38:35 PM PDT 24
Finished Jun 09 12:42:55 PM PDT 24
Peak memory 250832 kb
Host smart-62272195-fc5b-48bd-a1e1-256b9f91f4ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31616
19520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3161619520
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.500356858
Short name T682
Test name
Test status
Simulation time 859960880 ps
CPU time 16.96 seconds
Started Jun 09 12:38:34 PM PDT 24
Finished Jun 09 12:38:51 PM PDT 24
Peak memory 254692 kb
Host smart-cfb86232-6bc6-4394-99e7-fdfa7f8bd2aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50035
6858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.500356858
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2809451535
Short name T93
Test name
Test status
Simulation time 134438933695 ps
CPU time 674.43 seconds
Started Jun 09 12:38:41 PM PDT 24
Finished Jun 09 12:49:56 PM PDT 24
Peak memory 265180 kb
Host smart-2338a821-bb83-43ed-90ec-d26e95c61f11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809451535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2809451535
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.627478641
Short name T535
Test name
Test status
Simulation time 224431118921 ps
CPU time 1469.58 seconds
Started Jun 09 12:38:43 PM PDT 24
Finished Jun 09 01:03:13 PM PDT 24
Peak memory 273352 kb
Host smart-9652def8-fb46-4f9d-8454-08012f3abbd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627478641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.627478641
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3839302692
Short name T289
Test name
Test status
Simulation time 3079433606 ps
CPU time 122.08 seconds
Started Jun 09 12:38:35 PM PDT 24
Finished Jun 09 12:40:38 PM PDT 24
Peak memory 253604 kb
Host smart-9548cd32-dba2-4b9a-a100-9cf7b7c10006
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839302692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3839302692
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3356294976
Short name T259
Test name
Test status
Simulation time 3402804701 ps
CPU time 51.38 seconds
Started Jun 09 12:38:36 PM PDT 24
Finished Jun 09 12:39:28 PM PDT 24
Peak memory 256944 kb
Host smart-8e2566c4-0616-4689-826b-3d3cb3a048f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33562
94976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3356294976
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2388314455
Short name T58
Test name
Test status
Simulation time 1412699591 ps
CPU time 32.88 seconds
Started Jun 09 12:38:35 PM PDT 24
Finished Jun 09 12:39:09 PM PDT 24
Peak memory 256788 kb
Host smart-92ea3cf4-3473-4aa1-ac38-844b41f412fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23883
14455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2388314455
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1626643455
Short name T40
Test name
Test status
Simulation time 409315199 ps
CPU time 13.36 seconds
Started Jun 09 12:38:36 PM PDT 24
Finished Jun 09 12:38:50 PM PDT 24
Peak memory 248604 kb
Host smart-5078ffed-c44e-4609-b0df-eea9da9b6f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16266
43455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1626643455
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2826837602
Short name T420
Test name
Test status
Simulation time 54669369 ps
CPU time 6.14 seconds
Started Jun 09 12:38:41 PM PDT 24
Finished Jun 09 12:38:48 PM PDT 24
Peak memory 248644 kb
Host smart-67c66079-bfc4-452e-9b03-8746ceebf338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28268
37602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2826837602
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2749774091
Short name T624
Test name
Test status
Simulation time 35170915163 ps
CPU time 1371.75 seconds
Started Jun 09 12:38:39 PM PDT 24
Finished Jun 09 01:01:31 PM PDT 24
Peak memory 289828 kb
Host smart-f8ed85f1-ccec-44cf-be51-f92c459d3bca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749774091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2749774091
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.2901892624
Short name T16
Test name
Test status
Simulation time 57701543374 ps
CPU time 3145.45 seconds
Started Jun 09 12:38:41 PM PDT 24
Finished Jun 09 01:31:07 PM PDT 24
Peak memory 288884 kb
Host smart-362740a9-e28a-463d-8c6a-665998c5068e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901892624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.2901892624
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1840935295
Short name T500
Test name
Test status
Simulation time 604051128 ps
CPU time 35.84 seconds
Started Jun 09 12:38:40 PM PDT 24
Finished Jun 09 12:39:17 PM PDT 24
Peak memory 256392 kb
Host smart-fcd602c7-710e-4066-bf24-3a6aeb8becdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18409
35295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1840935295
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.438977912
Short name T632
Test name
Test status
Simulation time 652372128 ps
CPU time 22.26 seconds
Started Jun 09 12:38:41 PM PDT 24
Finished Jun 09 12:39:04 PM PDT 24
Peak memory 248640 kb
Host smart-c9ef4117-61a5-4388-a97a-3f5478d4d9b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43897
7912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.438977912
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2453363003
Short name T309
Test name
Test status
Simulation time 171504669743 ps
CPU time 956.91 seconds
Started Jun 09 12:38:39 PM PDT 24
Finished Jun 09 12:54:36 PM PDT 24
Peak memory 269304 kb
Host smart-ae72a80e-842b-4d36-bcfc-057ce41d5b32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453363003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2453363003
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3061834995
Short name T375
Test name
Test status
Simulation time 34047401399 ps
CPU time 1048.9 seconds
Started Jun 09 12:38:41 PM PDT 24
Finished Jun 09 12:56:11 PM PDT 24
Peak memory 266176 kb
Host smart-f5437757-07a3-43de-924c-ab186df3437e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061834995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3061834995
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3461360622
Short name T553
Test name
Test status
Simulation time 468507762 ps
CPU time 17.24 seconds
Started Jun 09 12:38:42 PM PDT 24
Finished Jun 09 12:39:00 PM PDT 24
Peak memory 256632 kb
Host smart-ccad85c3-a0da-4ee6-a7cd-263fbe4fa993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34613
60622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3461360622
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3963286781
Short name T88
Test name
Test status
Simulation time 438750225 ps
CPU time 32.5 seconds
Started Jun 09 12:38:40 PM PDT 24
Finished Jun 09 12:39:13 PM PDT 24
Peak memory 255016 kb
Host smart-ac887412-61b3-4a08-a1ac-f4b125122755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39632
86781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3963286781
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3801370394
Short name T610
Test name
Test status
Simulation time 818927284 ps
CPU time 46.44 seconds
Started Jun 09 12:38:40 PM PDT 24
Finished Jun 09 12:39:26 PM PDT 24
Peak memory 255664 kb
Host smart-216c92c6-8488-42b1-b211-65c0a678335e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38013
70394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3801370394
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3828310795
Short name T377
Test name
Test status
Simulation time 345756050 ps
CPU time 35.49 seconds
Started Jun 09 12:38:39 PM PDT 24
Finished Jun 09 12:39:15 PM PDT 24
Peak memory 248664 kb
Host smart-56eb86b7-eb37-4e3a-8d77-46f03961294f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38283
10795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3828310795
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2169195398
Short name T109
Test name
Test status
Simulation time 196675911305 ps
CPU time 2504.83 seconds
Started Jun 09 12:38:43 PM PDT 24
Finished Jun 09 01:20:29 PM PDT 24
Peak memory 287172 kb
Host smart-b0503153-0b51-4944-9c3e-d7bce795fecb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169195398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2169195398
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.466743994
Short name T247
Test name
Test status
Simulation time 65798691495 ps
CPU time 2812.95 seconds
Started Jun 09 12:38:44 PM PDT 24
Finished Jun 09 01:25:38 PM PDT 24
Peak memory 297436 kb
Host smart-9a086dfc-4ebf-44f5-a02a-67d6225aab0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466743994 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.466743994
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.185545898
Short name T571
Test name
Test status
Simulation time 102456085650 ps
CPU time 1833.66 seconds
Started Jun 09 12:38:47 PM PDT 24
Finished Jun 09 01:09:21 PM PDT 24
Peak memory 283828 kb
Host smart-cca05c2f-6483-4e41-b218-a4b15e8302e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185545898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.185545898
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1227890077
Short name T585
Test name
Test status
Simulation time 13159727809 ps
CPU time 182.96 seconds
Started Jun 09 12:38:38 PM PDT 24
Finished Jun 09 12:41:41 PM PDT 24
Peak memory 256876 kb
Host smart-675fc2cd-5761-4658-bab8-300e16e5af35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12278
90077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1227890077
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2226398499
Short name T418
Test name
Test status
Simulation time 458607368 ps
CPU time 26.33 seconds
Started Jun 09 12:38:37 PM PDT 24
Finished Jun 09 12:39:04 PM PDT 24
Peak memory 254020 kb
Host smart-8272534f-e429-4272-ae2b-f032759b7ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22263
98499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2226398499
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.2767950072
Short name T599
Test name
Test status
Simulation time 17158592759 ps
CPU time 1069.76 seconds
Started Jun 09 12:38:44 PM PDT 24
Finished Jun 09 12:56:34 PM PDT 24
Peak memory 265168 kb
Host smart-b2184ef3-f4b3-4159-a6fe-d6d1339bb33a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767950072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2767950072
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3356610177
Short name T69
Test name
Test status
Simulation time 30655464314 ps
CPU time 2063.09 seconds
Started Jun 09 12:38:48 PM PDT 24
Finished Jun 09 01:13:12 PM PDT 24
Peak memory 282544 kb
Host smart-736080fc-c71f-4262-90f1-7ec4d047de7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356610177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3356610177
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.605922939
Short name T292
Test name
Test status
Simulation time 13340437424 ps
CPU time 529.25 seconds
Started Jun 09 12:38:44 PM PDT 24
Finished Jun 09 12:47:33 PM PDT 24
Peak memory 248320 kb
Host smart-bb587542-345b-45e2-86d0-343bfc4744fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605922939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.605922939
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2307124034
Short name T63
Test name
Test status
Simulation time 1017463356 ps
CPU time 34.37 seconds
Started Jun 09 12:38:42 PM PDT 24
Finished Jun 09 12:39:17 PM PDT 24
Peak memory 248704 kb
Host smart-eeeb13a3-c7d3-43a6-ae24-d04faac0f0d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23071
24034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2307124034
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1755566279
Short name T495
Test name
Test status
Simulation time 4928658952 ps
CPU time 64.12 seconds
Started Jun 09 12:38:43 PM PDT 24
Finished Jun 09 12:39:47 PM PDT 24
Peak memory 255756 kb
Host smart-94843487-6c0a-477c-926f-27bc4df71f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17555
66279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1755566279
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1160264016
Short name T487
Test name
Test status
Simulation time 922304779 ps
CPU time 26.37 seconds
Started Jun 09 12:38:44 PM PDT 24
Finished Jun 09 12:39:10 PM PDT 24
Peak memory 247316 kb
Host smart-b83ad2cd-9ba0-45f3-938a-2e8dd30d1194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11602
64016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1160264016
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3178820357
Short name T392
Test name
Test status
Simulation time 77315033 ps
CPU time 10.24 seconds
Started Jun 09 12:38:43 PM PDT 24
Finished Jun 09 12:38:54 PM PDT 24
Peak memory 256892 kb
Host smart-584cf2b5-63b0-424d-8421-84d477efcfa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31788
20357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3178820357
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.3874498448
Short name T225
Test name
Test status
Simulation time 124717932057 ps
CPU time 1935.29 seconds
Started Jun 09 12:38:45 PM PDT 24
Finished Jun 09 01:11:01 PM PDT 24
Peak memory 289448 kb
Host smart-f1894f85-2bea-4b7c-893f-6312ecd43705
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874498448 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.3874498448
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3971475717
Short name T478
Test name
Test status
Simulation time 35217453393 ps
CPU time 1929.41 seconds
Started Jun 09 12:38:48 PM PDT 24
Finished Jun 09 01:10:58 PM PDT 24
Peak memory 282288 kb
Host smart-693d9db2-1303-4ae7-8475-7cf69747fd4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971475717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3971475717
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3436859083
Short name T503
Test name
Test status
Simulation time 188251413 ps
CPU time 6.13 seconds
Started Jun 09 12:38:49 PM PDT 24
Finished Jun 09 12:38:55 PM PDT 24
Peak memory 248812 kb
Host smart-97f484dd-a7b0-44f7-83b2-0d8d4c66c8e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34368
59083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3436859083
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2406078085
Short name T367
Test name
Test status
Simulation time 230594431 ps
CPU time 18.44 seconds
Started Jun 09 12:38:50 PM PDT 24
Finished Jun 09 12:39:08 PM PDT 24
Peak memory 255492 kb
Host smart-e04ef8a9-22e0-4ce8-92d4-b78f758a5872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24060
78085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2406078085
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.861277483
Short name T649
Test name
Test status
Simulation time 66480458353 ps
CPU time 1263.43 seconds
Started Jun 09 12:38:58 PM PDT 24
Finished Jun 09 01:00:02 PM PDT 24
Peak memory 265128 kb
Host smart-32d5b325-152a-4431-99e9-df78b1398b6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861277483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.861277483
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3190622625
Short name T560
Test name
Test status
Simulation time 19237615739 ps
CPU time 197.01 seconds
Started Jun 09 12:38:50 PM PDT 24
Finished Jun 09 12:42:07 PM PDT 24
Peak memory 248692 kb
Host smart-c7fb6099-bba6-4377-9b6f-d54b793f1099
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190622625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3190622625
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.4163369270
Short name T473
Test name
Test status
Simulation time 45852718 ps
CPU time 5.73 seconds
Started Jun 09 12:38:44 PM PDT 24
Finished Jun 09 12:38:51 PM PDT 24
Peak memory 248632 kb
Host smart-c19b650a-c8a1-4653-a748-8773dca7413a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41633
69270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.4163369270
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.159123182
Short name T190
Test name
Test status
Simulation time 18749998 ps
CPU time 3.38 seconds
Started Jun 09 12:38:44 PM PDT 24
Finished Jun 09 12:38:48 PM PDT 24
Peak memory 239320 kb
Host smart-d7689c86-36e1-4ccc-bd3b-709b6f5140ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15912
3182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.159123182
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2340477989
Short name T627
Test name
Test status
Simulation time 693572050 ps
CPU time 13.14 seconds
Started Jun 09 12:38:52 PM PDT 24
Finished Jun 09 12:39:06 PM PDT 24
Peak memory 253416 kb
Host smart-7176e648-4ff3-4f1f-8f05-c1080d237021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23404
77989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2340477989
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1651786140
Short name T561
Test name
Test status
Simulation time 999352861 ps
CPU time 35.62 seconds
Started Jun 09 12:38:48 PM PDT 24
Finished Jun 09 12:39:24 PM PDT 24
Peak memory 256044 kb
Host smart-755c4b4d-128c-4375-a5c5-1ad3804f2647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16517
86140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1651786140
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.296762051
Short name T395
Test name
Test status
Simulation time 80097910245 ps
CPU time 2646.41 seconds
Started Jun 09 12:38:52 PM PDT 24
Finished Jun 09 01:22:59 PM PDT 24
Peak memory 289692 kb
Host smart-7ea3d313-c105-4103-be78-f411d6dbdd68
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296762051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.296762051
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.195486838
Short name T254
Test name
Test status
Simulation time 41374722307 ps
CPU time 1366.35 seconds
Started Jun 09 12:38:56 PM PDT 24
Finished Jun 09 01:01:43 PM PDT 24
Peak memory 265168 kb
Host smart-d548f473-4cf8-4974-b926-9ade9f52580b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195486838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.195486838
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3021654461
Short name T517
Test name
Test status
Simulation time 514773010 ps
CPU time 47.5 seconds
Started Jun 09 12:38:52 PM PDT 24
Finished Jun 09 12:39:40 PM PDT 24
Peak memory 256700 kb
Host smart-f058789c-98ff-4913-9cf5-e41b6b934203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30216
54461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3021654461
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1008583189
Short name T661
Test name
Test status
Simulation time 738988748 ps
CPU time 37.99 seconds
Started Jun 09 12:38:54 PM PDT 24
Finished Jun 09 12:39:32 PM PDT 24
Peak memory 248804 kb
Host smart-6e8297db-edd1-4fcc-8687-3f5c0366f458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10085
83189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1008583189
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3651684751
Short name T223
Test name
Test status
Simulation time 152660693842 ps
CPU time 2119.15 seconds
Started Jun 09 12:38:51 PM PDT 24
Finished Jun 09 01:14:11 PM PDT 24
Peak memory 281472 kb
Host smart-535cd526-e569-442a-b96b-9481dde6ae63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651684751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3651684751
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2381996675
Short name T445
Test name
Test status
Simulation time 85675336719 ps
CPU time 1462.35 seconds
Started Jun 09 12:38:54 PM PDT 24
Finished Jun 09 01:03:17 PM PDT 24
Peak memory 273256 kb
Host smart-ce2b92e6-6a9a-403d-8bf5-159b9816a572
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381996675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2381996675
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.920663676
Short name T622
Test name
Test status
Simulation time 24830860569 ps
CPU time 246.68 seconds
Started Jun 09 12:38:51 PM PDT 24
Finished Jun 09 12:42:58 PM PDT 24
Peak memory 254640 kb
Host smart-ecef136c-f632-4d06-829d-b5f9a19779ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920663676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.920663676
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2240200756
Short name T490
Test name
Test status
Simulation time 534140414 ps
CPU time 18.09 seconds
Started Jun 09 12:38:52 PM PDT 24
Finished Jun 09 12:39:10 PM PDT 24
Peak memory 255864 kb
Host smart-c34f09f1-509a-440d-a5c4-203eafcceb3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22402
00756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2240200756
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.2050781984
Short name T550
Test name
Test status
Simulation time 1197168738 ps
CPU time 18 seconds
Started Jun 09 12:38:54 PM PDT 24
Finished Jun 09 12:39:12 PM PDT 24
Peak memory 256440 kb
Host smart-665a4cdb-103f-41c9-9abe-813a94df66dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20507
81984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2050781984
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1983703468
Short name T249
Test name
Test status
Simulation time 2520474642 ps
CPU time 46.51 seconds
Started Jun 09 12:38:56 PM PDT 24
Finished Jun 09 12:39:43 PM PDT 24
Peak memory 248736 kb
Host smart-fb1c9ce4-79b0-4410-8a97-d58acd56d41c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19837
03468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1983703468
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2662185258
Short name T344
Test name
Test status
Simulation time 67821462 ps
CPU time 4.86 seconds
Started Jun 09 12:38:54 PM PDT 24
Finished Jun 09 12:38:59 PM PDT 24
Peak memory 240480 kb
Host smart-0774b461-4691-416e-904f-c7e4d66dd1fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26621
85258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2662185258
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.765343790
Short name T638
Test name
Test status
Simulation time 119431044927 ps
CPU time 2213.47 seconds
Started Jun 09 12:38:59 PM PDT 24
Finished Jun 09 01:15:53 PM PDT 24
Peak memory 288936 kb
Host smart-51fc1239-269f-4a27-859b-8fd978de530f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765343790 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.765343790
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.846182316
Short name T56
Test name
Test status
Simulation time 19732547507 ps
CPU time 1006.2 seconds
Started Jun 09 12:38:53 PM PDT 24
Finished Jun 09 12:55:39 PM PDT 24
Peak memory 273232 kb
Host smart-92951fd7-2e31-4a51-9163-9480290d3e65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846182316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.846182316
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.493546522
Short name T521
Test name
Test status
Simulation time 1344128397 ps
CPU time 116.61 seconds
Started Jun 09 12:38:54 PM PDT 24
Finished Jun 09 12:40:51 PM PDT 24
Peak memory 256684 kb
Host smart-50b9d18f-c33e-4803-8885-01409469a184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49354
6522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.493546522
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.4095772687
Short name T465
Test name
Test status
Simulation time 2277564085 ps
CPU time 33.61 seconds
Started Jun 09 12:38:55 PM PDT 24
Finished Jun 09 12:39:29 PM PDT 24
Peak memory 255040 kb
Host smart-8b8db95b-cff7-4946-9f23-4b8a54c88222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40957
72687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.4095772687
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.842239256
Short name T326
Test name
Test status
Simulation time 13364346737 ps
CPU time 744.6 seconds
Started Jun 09 12:38:56 PM PDT 24
Finished Jun 09 12:51:21 PM PDT 24
Peak memory 265152 kb
Host smart-522e8b35-5c3b-470d-9e01-6b82ef5f88c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842239256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.842239256
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.605438008
Short name T409
Test name
Test status
Simulation time 9341457639 ps
CPU time 1060.05 seconds
Started Jun 09 12:38:58 PM PDT 24
Finished Jun 09 12:56:38 PM PDT 24
Peak memory 270556 kb
Host smart-b573a073-033a-404f-8388-50b44123e4a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605438008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.605438008
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.4285799050
Short name T563
Test name
Test status
Simulation time 18525746195 ps
CPU time 196.99 seconds
Started Jun 09 12:38:55 PM PDT 24
Finished Jun 09 12:42:13 PM PDT 24
Peak memory 248124 kb
Host smart-eb820a07-bfc3-441b-b31c-7a0eafaaa3a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285799050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.4285799050
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.920926820
Short name T2
Test name
Test status
Simulation time 3376883769 ps
CPU time 50.71 seconds
Started Jun 09 12:38:54 PM PDT 24
Finished Jun 09 12:39:45 PM PDT 24
Peak memory 256876 kb
Host smart-7ee02823-62c0-492a-89d1-a16aca14a5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92092
6820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.920926820
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3036125478
Short name T370
Test name
Test status
Simulation time 1845098564 ps
CPU time 53.49 seconds
Started Jun 09 12:38:57 PM PDT 24
Finished Jun 09 12:39:51 PM PDT 24
Peak memory 248640 kb
Host smart-489dcdd4-f9e2-4d62-b364-78ad8422e79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30361
25478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3036125478
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3835879809
Short name T234
Test name
Test status
Simulation time 910409282 ps
CPU time 17.6 seconds
Started Jun 09 12:38:57 PM PDT 24
Finished Jun 09 12:39:15 PM PDT 24
Peak memory 255488 kb
Host smart-aed190c0-363f-4c56-9eec-e5fdda638bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38358
79809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3835879809
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.885220649
Short name T343
Test name
Test status
Simulation time 108595536 ps
CPU time 4.62 seconds
Started Jun 09 12:38:54 PM PDT 24
Finished Jun 09 12:38:59 PM PDT 24
Peak memory 240428 kb
Host smart-429cc94b-8810-4cc5-984e-28ec3562fa1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88522
0649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.885220649
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.3523022123
Short name T188
Test name
Test status
Simulation time 56600856906 ps
CPU time 916.56 seconds
Started Jun 09 12:38:58 PM PDT 24
Finished Jun 09 12:54:15 PM PDT 24
Peak memory 273260 kb
Host smart-d9c32c0b-e2be-4826-906d-fc45a7f84ea6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523022123 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.3523022123
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2366199221
Short name T665
Test name
Test status
Simulation time 66641104500 ps
CPU time 1417.21 seconds
Started Jun 09 12:38:59 PM PDT 24
Finished Jun 09 01:02:36 PM PDT 24
Peak memory 288244 kb
Host smart-8e7c4141-3fb7-4a64-98f9-bab7b360cf3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366199221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2366199221
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.822975539
Short name T433
Test name
Test status
Simulation time 5558539868 ps
CPU time 181.24 seconds
Started Jun 09 12:38:54 PM PDT 24
Finished Jun 09 12:41:56 PM PDT 24
Peak memory 256916 kb
Host smart-a7bf413c-82d8-4e85-91f5-4d540f016940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82297
5539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.822975539
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3003987003
Short name T380
Test name
Test status
Simulation time 7768390555 ps
CPU time 52.37 seconds
Started Jun 09 12:38:56 PM PDT 24
Finished Jun 09 12:39:48 PM PDT 24
Peak memory 249020 kb
Host smart-41d0790e-3223-4e52-a70d-ac895db2e339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30039
87003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3003987003
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2301619774
Short name T319
Test name
Test status
Simulation time 40117341662 ps
CPU time 1150.71 seconds
Started Jun 09 12:38:58 PM PDT 24
Finished Jun 09 12:58:09 PM PDT 24
Peak memory 272408 kb
Host smart-75a70812-bfb1-4e40-bd30-9116b5cb5567
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301619774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2301619774
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2732718148
Short name T703
Test name
Test status
Simulation time 91718125648 ps
CPU time 1347.75 seconds
Started Jun 09 12:38:59 PM PDT 24
Finished Jun 09 01:01:27 PM PDT 24
Peak memory 272704 kb
Host smart-23f6d404-d489-4613-b69e-bfbfeba39a2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732718148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2732718148
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3586849264
Short name T690
Test name
Test status
Simulation time 14380992331 ps
CPU time 544.1 seconds
Started Jun 09 12:38:57 PM PDT 24
Finished Jun 09 12:48:02 PM PDT 24
Peak memory 254444 kb
Host smart-db5d1b48-b5e5-46c7-963d-4c2d5a39493b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586849264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3586849264
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1457876255
Short name T514
Test name
Test status
Simulation time 2231592480 ps
CPU time 73.12 seconds
Started Jun 09 12:38:56 PM PDT 24
Finished Jun 09 12:40:09 PM PDT 24
Peak memory 256108 kb
Host smart-98f59cac-0a91-477d-89c3-244044281789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14578
76255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1457876255
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2729334531
Short name T609
Test name
Test status
Simulation time 4064610937 ps
CPU time 14.09 seconds
Started Jun 09 12:38:55 PM PDT 24
Finished Jun 09 12:39:09 PM PDT 24
Peak memory 253196 kb
Host smart-528da56b-e15f-4b6f-952f-1733a65bd030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27293
34531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2729334531
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1817160871
Short name T481
Test name
Test status
Simulation time 2430263271 ps
CPU time 48.57 seconds
Started Jun 09 12:38:59 PM PDT 24
Finished Jun 09 12:39:48 PM PDT 24
Peak memory 256812 kb
Host smart-fb860ce0-523c-4f66-92fd-28a6c076931c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18171
60871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1817160871
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1188765668
Short name T518
Test name
Test status
Simulation time 249878052 ps
CPU time 15 seconds
Started Jun 09 12:38:54 PM PDT 24
Finished Jun 09 12:39:09 PM PDT 24
Peak memory 255668 kb
Host smart-04e2050a-2000-4295-8236-95c81c88f0f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11887
65668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1188765668
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.4079410841
Short name T558
Test name
Test status
Simulation time 502679821 ps
CPU time 9.25 seconds
Started Jun 09 12:39:00 PM PDT 24
Finished Jun 09 12:39:09 PM PDT 24
Peak memory 248208 kb
Host smart-d3de605e-dbb1-4bfa-91b7-6c2392193b94
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079410841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.4079410841
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3314231643
Short name T598
Test name
Test status
Simulation time 61834608271 ps
CPU time 2020.33 seconds
Started Jun 09 12:38:57 PM PDT 24
Finished Jun 09 01:12:38 PM PDT 24
Peak memory 288728 kb
Host smart-b298dd8f-7215-40b3-8f32-ffe55be1d230
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314231643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3314231643
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1017285134
Short name T126
Test name
Test status
Simulation time 35578084285 ps
CPU time 148.33 seconds
Started Jun 09 12:38:58 PM PDT 24
Finished Jun 09 12:41:26 PM PDT 24
Peak memory 256932 kb
Host smart-fb310045-abcd-476f-80d1-151cf8197d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10172
85134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1017285134
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2716782803
Short name T463
Test name
Test status
Simulation time 656037993 ps
CPU time 28.04 seconds
Started Jun 09 12:38:58 PM PDT 24
Finished Jun 09 12:39:27 PM PDT 24
Peak memory 255632 kb
Host smart-914b5f7f-7980-48d1-8ed8-3a490fc3b068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27167
82803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2716782803
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.69557982
Short name T87
Test name
Test status
Simulation time 20485553799 ps
CPU time 1367.39 seconds
Started Jun 09 12:39:05 PM PDT 24
Finished Jun 09 01:01:53 PM PDT 24
Peak memory 272748 kb
Host smart-75ffa2ef-94d1-469d-9688-ad7b6b83daa3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69557982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.69557982
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3158277206
Short name T287
Test name
Test status
Simulation time 21183990467 ps
CPU time 450.66 seconds
Started Jun 09 12:38:59 PM PDT 24
Finished Jun 09 12:46:30 PM PDT 24
Peak memory 247908 kb
Host smart-b39eff3d-a725-41e5-9880-3c50939302b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158277206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3158277206
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.651150345
Short name T36
Test name
Test status
Simulation time 2813417404 ps
CPU time 49.96 seconds
Started Jun 09 12:38:58 PM PDT 24
Finished Jun 09 12:39:49 PM PDT 24
Peak memory 255964 kb
Host smart-a2cbb1ec-02fd-48a0-96a8-44fe0a4068db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65115
0345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.651150345
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2674626863
Short name T372
Test name
Test status
Simulation time 1532295473 ps
CPU time 48.2 seconds
Started Jun 09 12:38:58 PM PDT 24
Finished Jun 09 12:39:47 PM PDT 24
Peak memory 255504 kb
Host smart-a6aca6c7-05f2-4f3d-9e0d-5cc39adf44a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26746
26863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2674626863
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3329978722
Short name T684
Test name
Test status
Simulation time 1157153513 ps
CPU time 15.68 seconds
Started Jun 09 12:38:57 PM PDT 24
Finished Jun 09 12:39:13 PM PDT 24
Peak memory 248868 kb
Host smart-56c09204-57cc-4b30-a3bc-55dabddc8503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33299
78722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3329978722
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3923082001
Short name T352
Test name
Test status
Simulation time 55443909 ps
CPU time 6.6 seconds
Started Jun 09 12:38:58 PM PDT 24
Finished Jun 09 12:39:05 PM PDT 24
Peak memory 256856 kb
Host smart-b4210fc6-239d-414d-9134-849bfabcad73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39230
82001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3923082001
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.761285219
Short name T95
Test name
Test status
Simulation time 195978134830 ps
CPU time 3236 seconds
Started Jun 09 12:39:04 PM PDT 24
Finished Jun 09 01:33:01 PM PDT 24
Peak memory 297936 kb
Host smart-1958dbbc-f364-4836-aa30-4b75c6499fca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761285219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.761285219
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.541581552
Short name T471
Test name
Test status
Simulation time 48799805627 ps
CPU time 2959.65 seconds
Started Jun 09 12:39:08 PM PDT 24
Finished Jun 09 01:28:29 PM PDT 24
Peak memory 288992 kb
Host smart-864e9302-bb96-4ca4-a8b1-d26e5d6ed52d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541581552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.541581552
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.752218315
Short name T608
Test name
Test status
Simulation time 8988433711 ps
CPU time 249.06 seconds
Started Jun 09 12:39:04 PM PDT 24
Finished Jun 09 12:43:14 PM PDT 24
Peak memory 256792 kb
Host smart-07a8b7ef-4081-4df7-86ea-9f9675bba872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75221
8315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.752218315
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3075991134
Short name T75
Test name
Test status
Simulation time 127685160 ps
CPU time 12.27 seconds
Started Jun 09 12:39:06 PM PDT 24
Finished Jun 09 12:39:19 PM PDT 24
Peak memory 254960 kb
Host smart-83f1ddfb-bfa9-44ae-bb50-c64d09e9808f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30759
91134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3075991134
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3671045592
Short name T593
Test name
Test status
Simulation time 111732742226 ps
CPU time 872 seconds
Started Jun 09 12:39:09 PM PDT 24
Finished Jun 09 12:53:41 PM PDT 24
Peak memory 273252 kb
Host smart-3a88a8f9-991f-456b-a99b-5ffd05383321
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671045592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3671045592
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3970121444
Short name T628
Test name
Test status
Simulation time 35255258921 ps
CPU time 2156.48 seconds
Started Jun 09 12:39:08 PM PDT 24
Finished Jun 09 01:15:05 PM PDT 24
Peak memory 281172 kb
Host smart-b9802a99-002c-4d24-a870-13c69aae03d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970121444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3970121444
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3013157293
Short name T293
Test name
Test status
Simulation time 77583018818 ps
CPU time 594.67 seconds
Started Jun 09 12:39:09 PM PDT 24
Finished Jun 09 12:49:04 PM PDT 24
Peak memory 256440 kb
Host smart-626ea0c6-e4b9-46e2-9bcf-3c5491ca5b18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013157293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3013157293
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1772705802
Short name T402
Test name
Test status
Simulation time 152956939 ps
CPU time 9.78 seconds
Started Jun 09 12:39:07 PM PDT 24
Finished Jun 09 12:39:17 PM PDT 24
Peak memory 251892 kb
Host smart-2d2b050c-cbce-4fb7-844a-2882627a462e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17727
05802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1772705802
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3196951496
Short name T645
Test name
Test status
Simulation time 978013151 ps
CPU time 58.25 seconds
Started Jun 09 12:39:05 PM PDT 24
Finished Jun 09 12:40:04 PM PDT 24
Peak memory 254852 kb
Host smart-4c1d3bb7-75d9-4de1-90e5-0f339357ac9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31969
51496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3196951496
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.434731858
Short name T233
Test name
Test status
Simulation time 534548888 ps
CPU time 31.5 seconds
Started Jun 09 12:39:09 PM PDT 24
Finished Jun 09 12:39:40 PM PDT 24
Peak memory 247444 kb
Host smart-f85e63ad-18ca-4ef0-b266-859d1ab8762c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43473
1858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.434731858
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3985000307
Short name T436
Test name
Test status
Simulation time 326492166 ps
CPU time 9.29 seconds
Started Jun 09 12:39:08 PM PDT 24
Finished Jun 09 12:39:17 PM PDT 24
Peak memory 248628 kb
Host smart-9ae49e80-84f2-4b05-84a3-3d63c9fd8ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39850
00307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3985000307
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.339258580
Short name T53
Test name
Test status
Simulation time 16616146790 ps
CPU time 1699.13 seconds
Started Jun 09 12:39:10 PM PDT 24
Finished Jun 09 01:07:29 PM PDT 24
Peak memory 303116 kb
Host smart-f453c52f-7572-4dff-8bf1-a1779f56cac5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339258580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.339258580
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.3465899453
Short name T551
Test name
Test status
Simulation time 153287615094 ps
CPU time 4458.86 seconds
Started Jun 09 12:39:08 PM PDT 24
Finished Jun 09 01:53:28 PM PDT 24
Peak memory 338316 kb
Host smart-5470c7a8-33b3-4431-8ffb-0c8bdf5c55b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465899453 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.3465899453
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1518097909
Short name T67
Test name
Test status
Simulation time 15142497 ps
CPU time 2.47 seconds
Started Jun 09 12:37:46 PM PDT 24
Finished Jun 09 12:37:49 PM PDT 24
Peak memory 248876 kb
Host smart-9da1785a-2d2d-46dd-ba5b-8d42bf15b52a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1518097909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1518097909
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3681188364
Short name T91
Test name
Test status
Simulation time 56947312424 ps
CPU time 1727.41 seconds
Started Jun 09 12:37:40 PM PDT 24
Finished Jun 09 01:06:29 PM PDT 24
Peak memory 273096 kb
Host smart-259356c9-0f69-491c-8403-c4d83c8a0b87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681188364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3681188364
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2020321420
Short name T621
Test name
Test status
Simulation time 2991452621 ps
CPU time 35.81 seconds
Started Jun 09 12:37:37 PM PDT 24
Finished Jun 09 12:38:19 PM PDT 24
Peak memory 248780 kb
Host smart-47dff7a0-15ff-4eff-a8e9-6dba258d1422
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2020321420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2020321420
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1109517516
Short name T129
Test name
Test status
Simulation time 6306001196 ps
CPU time 172.39 seconds
Started Jun 09 12:37:40 PM PDT 24
Finished Jun 09 12:40:34 PM PDT 24
Peak memory 256900 kb
Host smart-d95503e1-1831-415d-a86f-84cf1cc87fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11095
17516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1109517516
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.4132118650
Short name T70
Test name
Test status
Simulation time 554726581 ps
CPU time 10.94 seconds
Started Jun 09 12:37:35 PM PDT 24
Finished Jun 09 12:37:46 PM PDT 24
Peak memory 249004 kb
Host smart-50ddee89-1608-4d3d-b8c7-3f3d41d957cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41321
18650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.4132118650
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3556380654
Short name T304
Test name
Test status
Simulation time 76433297001 ps
CPU time 1287.01 seconds
Started Jun 09 12:37:50 PM PDT 24
Finished Jun 09 12:59:18 PM PDT 24
Peak memory 286756 kb
Host smart-83332513-c493-44d7-a1d2-a325495f2a17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556380654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3556380654
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.136897750
Short name T519
Test name
Test status
Simulation time 9832183661 ps
CPU time 755.38 seconds
Started Jun 09 12:37:37 PM PDT 24
Finished Jun 09 12:50:13 PM PDT 24
Peak memory 273288 kb
Host smart-af106e8f-546e-40db-a8db-f5da8b5b3371
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136897750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.136897750
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.28377874
Short name T615
Test name
Test status
Simulation time 4834920684 ps
CPU time 165.43 seconds
Started Jun 09 12:37:38 PM PDT 24
Finished Jun 09 12:40:25 PM PDT 24
Peak memory 247084 kb
Host smart-c0cc0f04-e3d1-41c5-bd4b-8ef9d5a15be3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28377874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.28377874
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.244028813
Short name T441
Test name
Test status
Simulation time 1765972780 ps
CPU time 27.91 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 12:38:11 PM PDT 24
Peak memory 248704 kb
Host smart-e5d2c850-aabe-4a88-b937-06b01b56731f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24402
8813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.244028813
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.428845703
Short name T568
Test name
Test status
Simulation time 110758042 ps
CPU time 7.13 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 12:37:50 PM PDT 24
Peak memory 250068 kb
Host smart-bc56cb81-532e-4247-a8cc-ee67a5457eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42884
5703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.428845703
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1146344511
Short name T113
Test name
Test status
Simulation time 2398230919 ps
CPU time 36.04 seconds
Started Jun 09 12:37:34 PM PDT 24
Finished Jun 09 12:38:11 PM PDT 24
Peak memory 255384 kb
Host smart-ad8cbac8-e633-4916-be1e-d934dd3f7a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11463
44511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1146344511
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2361944695
Short name T522
Test name
Test status
Simulation time 2753309985 ps
CPU time 38.27 seconds
Started Jun 09 12:37:37 PM PDT 24
Finished Jun 09 12:38:16 PM PDT 24
Peak memory 256908 kb
Host smart-c2b55658-1f84-407e-a202-f7ee0b07a94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23619
44695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2361944695
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1048546198
Short name T107
Test name
Test status
Simulation time 39653457136 ps
CPU time 926.03 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 12:53:11 PM PDT 24
Peak memory 273356 kb
Host smart-cf8c4a47-1fce-4485-89a1-2795233e88c6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048546198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1048546198
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.4267233408
Short name T90
Test name
Test status
Simulation time 110158020 ps
CPU time 3.7 seconds
Started Jun 09 12:37:38 PM PDT 24
Finished Jun 09 12:37:43 PM PDT 24
Peak memory 248864 kb
Host smart-aa2698f4-f05d-4a54-ace6-533bda932d15
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4267233408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.4267233408
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.89253686
Short name T111
Test name
Test status
Simulation time 65169246838 ps
CPU time 860.37 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 12:52:04 PM PDT 24
Peak memory 269300 kb
Host smart-db2d60b3-94b4-4d00-b5f3-1d8d4ddb93cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89253686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.89253686
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1153145601
Short name T668
Test name
Test status
Simulation time 535763261 ps
CPU time 7.48 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 12:37:51 PM PDT 24
Peak memory 240512 kb
Host smart-9490acfb-3b44-4947-95e2-53d5598fc5fc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1153145601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1153145601
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2142527887
Short name T43
Test name
Test status
Simulation time 1055834864 ps
CPU time 84.14 seconds
Started Jun 09 12:37:58 PM PDT 24
Finished Jun 09 12:39:22 PM PDT 24
Peak memory 256808 kb
Host smart-f226725f-6435-40e6-a98e-23150bcdcd13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21425
27887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2142527887
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3126666539
Short name T462
Test name
Test status
Simulation time 541592613 ps
CPU time 12.63 seconds
Started Jun 09 12:37:39 PM PDT 24
Finished Jun 09 12:37:53 PM PDT 24
Peak memory 254716 kb
Host smart-692fda54-6d26-4b94-b008-9d8396c6e384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31266
66539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3126666539
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3578938552
Short name T258
Test name
Test status
Simulation time 153101796066 ps
CPU time 1262.61 seconds
Started Jun 09 12:37:38 PM PDT 24
Finished Jun 09 12:58:41 PM PDT 24
Peak memory 283196 kb
Host smart-98e2846f-186f-4289-8e97-889a7cb0281b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578938552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3578938552
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.4206689620
Short name T400
Test name
Test status
Simulation time 33790712812 ps
CPU time 1148.75 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 12:56:53 PM PDT 24
Peak memory 283640 kb
Host smart-62293cfc-5567-4e47-a7f7-ec19d095867d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206689620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.4206689620
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3390806578
Short name T262
Test name
Test status
Simulation time 37679582403 ps
CPU time 321.48 seconds
Started Jun 09 12:37:39 PM PDT 24
Finished Jun 09 12:43:01 PM PDT 24
Peak memory 247896 kb
Host smart-73180b86-afe4-4b6b-92f6-71c2018306bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390806578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3390806578
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2113002553
Short name T464
Test name
Test status
Simulation time 3666587632 ps
CPU time 55.39 seconds
Started Jun 09 12:37:40 PM PDT 24
Finished Jun 09 12:38:37 PM PDT 24
Peak memory 256292 kb
Host smart-b578cd85-2aee-4405-9c82-684a26f643a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21130
02553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2113002553
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3419458111
Short name T666
Test name
Test status
Simulation time 623105060 ps
CPU time 19.36 seconds
Started Jun 09 12:37:33 PM PDT 24
Finished Jun 09 12:37:53 PM PDT 24
Peak memory 256780 kb
Host smart-0b56fe9c-f482-456f-80a6-741563bb0721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34194
58111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3419458111
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1403769493
Short name T469
Test name
Test status
Simulation time 60342624 ps
CPU time 2.89 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 12:37:47 PM PDT 24
Peak memory 239340 kb
Host smart-6a6cd4d6-be08-476c-9e09-4dc2a926cb04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14037
69493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1403769493
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3352437191
Short name T673
Test name
Test status
Simulation time 3214414895 ps
CPU time 27.38 seconds
Started Jun 09 12:37:38 PM PDT 24
Finished Jun 09 12:38:06 PM PDT 24
Peak memory 256216 kb
Host smart-2be956c0-0211-4912-9451-b17787f32a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33524
37191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3352437191
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1368738960
Short name T24
Test name
Test status
Simulation time 4821726042 ps
CPU time 111.94 seconds
Started Jun 09 12:38:08 PM PDT 24
Finished Jun 09 12:40:00 PM PDT 24
Peak memory 256888 kb
Host smart-641cc922-7817-479c-b1d4-ff79c82cd802
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368738960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1368738960
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3419655775
Short name T213
Test name
Test status
Simulation time 31879211 ps
CPU time 2.96 seconds
Started Jun 09 12:37:40 PM PDT 24
Finished Jun 09 12:37:44 PM PDT 24
Peak memory 248864 kb
Host smart-6d28a5ca-3c83-4c6d-a009-8935e2d183fe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3419655775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3419655775
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2107472515
Short name T51
Test name
Test status
Simulation time 33738736025 ps
CPU time 1698.86 seconds
Started Jun 09 12:37:41 PM PDT 24
Finished Jun 09 01:06:01 PM PDT 24
Peak memory 272836 kb
Host smart-61051f42-81d0-4b86-a18f-10598568dbb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107472515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2107472515
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3012596611
Short name T652
Test name
Test status
Simulation time 14776999312 ps
CPU time 72.73 seconds
Started Jun 09 12:37:56 PM PDT 24
Finished Jun 09 12:39:09 PM PDT 24
Peak memory 251816 kb
Host smart-713078d3-fd5f-4945-ac14-3a4de4f4173b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3012596611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3012596611
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.618021113
Short name T383
Test name
Test status
Simulation time 528579695 ps
CPU time 13.17 seconds
Started Jun 09 12:37:48 PM PDT 24
Finished Jun 09 12:38:02 PM PDT 24
Peak memory 255212 kb
Host smart-135ad604-eeee-421f-a67b-08266777a2ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61802
1113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.618021113
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.411529277
Short name T98
Test name
Test status
Simulation time 2953907619 ps
CPU time 43.29 seconds
Started Jun 09 12:37:39 PM PDT 24
Finished Jun 09 12:38:23 PM PDT 24
Peak memory 255880 kb
Host smart-0f217b4e-a612-48ab-a040-c507c471d7b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41152
9277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.411529277
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.38047419
Short name T386
Test name
Test status
Simulation time 19163672303 ps
CPU time 965.17 seconds
Started Jun 09 12:37:41 PM PDT 24
Finished Jun 09 12:53:48 PM PDT 24
Peak memory 273324 kb
Host smart-24383c47-ca49-43ab-9d44-0d83f3d274d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38047419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.38047419
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.436689411
Short name T603
Test name
Test status
Simulation time 2888087461 ps
CPU time 117.45 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 12:39:41 PM PDT 24
Peak memory 247876 kb
Host smart-2297c1dd-d28d-4da9-8090-aaea5a910efe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436689411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.436689411
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.264610393
Short name T600
Test name
Test status
Simulation time 1809575670 ps
CPU time 25.7 seconds
Started Jun 09 12:37:35 PM PDT 24
Finished Jun 09 12:38:01 PM PDT 24
Peak memory 248708 kb
Host smart-bb71088a-a9b6-4829-8d0e-9b1d7c9de553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26461
0393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.264610393
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1237050600
Short name T683
Test name
Test status
Simulation time 1072448997 ps
CPU time 28.64 seconds
Started Jun 09 12:37:44 PM PDT 24
Finished Jun 09 12:38:13 PM PDT 24
Peak memory 256796 kb
Host smart-a3e71470-cfe6-43cd-8ff3-7c33ea0b9a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12370
50600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1237050600
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.574776641
Short name T629
Test name
Test status
Simulation time 139916352 ps
CPU time 10.14 seconds
Started Jun 09 12:37:38 PM PDT 24
Finished Jun 09 12:37:49 PM PDT 24
Peak memory 253756 kb
Host smart-4e1f91ce-addd-4dd4-8921-1a646e68e208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57477
6641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.574776641
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.173032772
Short name T104
Test name
Test status
Simulation time 300410585 ps
CPU time 21.94 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 12:38:06 PM PDT 24
Peak memory 248716 kb
Host smart-7cb5e60c-34f4-499e-a5c5-0345397cdf22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17303
2772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.173032772
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1309050631
Short name T591
Test name
Test status
Simulation time 274417552406 ps
CPU time 3758.34 seconds
Started Jun 09 12:38:08 PM PDT 24
Finished Jun 09 01:40:47 PM PDT 24
Peak memory 305656 kb
Host smart-c15f5aac-af78-4651-8f82-533308dbb02e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309050631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1309050631
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.436741325
Short name T211
Test name
Test status
Simulation time 16537276 ps
CPU time 2.63 seconds
Started Jun 09 12:38:01 PM PDT 24
Finished Jun 09 12:38:04 PM PDT 24
Peak memory 248784 kb
Host smart-f34453eb-11d7-4707-82e5-5aaa9f6815b1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=436741325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.436741325
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3672224419
Short name T60
Test name
Test status
Simulation time 55324506556 ps
CPU time 3103.32 seconds
Started Jun 09 12:37:32 PM PDT 24
Finished Jun 09 01:29:16 PM PDT 24
Peak memory 289024 kb
Host smart-694e2523-2c28-4ea6-8975-a0c08a4b7aef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672224419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3672224419
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2564998174
Short name T453
Test name
Test status
Simulation time 105283372 ps
CPU time 6.59 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 12:37:50 PM PDT 24
Peak memory 248728 kb
Host smart-7d781fc0-f00b-4af4-ae60-b8192ff9b2dc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2564998174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2564998174
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1862796306
Short name T528
Test name
Test status
Simulation time 362928239 ps
CPU time 17.93 seconds
Started Jun 09 12:37:38 PM PDT 24
Finished Jun 09 12:37:56 PM PDT 24
Peak memory 256000 kb
Host smart-5636b337-6294-456a-9465-798fec022a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18627
96306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1862796306
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3980646052
Short name T686
Test name
Test status
Simulation time 2462477118 ps
CPU time 36.01 seconds
Started Jun 09 12:37:38 PM PDT 24
Finished Jun 09 12:38:15 PM PDT 24
Peak memory 255768 kb
Host smart-a55ae63d-7983-408f-8ee2-15f2adc4fc46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39806
46052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3980646052
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1822259988
Short name T314
Test name
Test status
Simulation time 39099001534 ps
CPU time 2142.34 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 01:13:27 PM PDT 24
Peak memory 281460 kb
Host smart-894fd97f-79bb-46e3-91ad-cbbb25bcd6b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822259988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1822259988
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3622032191
Short name T559
Test name
Test status
Simulation time 64573543687 ps
CPU time 1630.03 seconds
Started Jun 09 12:37:45 PM PDT 24
Finished Jun 09 01:04:56 PM PDT 24
Peak memory 288732 kb
Host smart-08317ee4-9653-403a-bb3b-b72f405165f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622032191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3622032191
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.698578613
Short name T283
Test name
Test status
Simulation time 12265681872 ps
CPU time 481.02 seconds
Started Jun 09 12:37:44 PM PDT 24
Finished Jun 09 12:45:46 PM PDT 24
Peak memory 247164 kb
Host smart-94b0815b-9351-4804-a008-98964b9957bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698578613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.698578613
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1299005761
Short name T510
Test name
Test status
Simulation time 1053111162 ps
CPU time 31.63 seconds
Started Jun 09 12:37:35 PM PDT 24
Finished Jun 09 12:38:07 PM PDT 24
Peak memory 255516 kb
Host smart-86e88b96-b6bd-4d6e-be89-7951d58c280f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12990
05761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1299005761
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2608435823
Short name T470
Test name
Test status
Simulation time 29471435 ps
CPU time 3.51 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 12:37:47 PM PDT 24
Peak memory 239404 kb
Host smart-73edbf6e-3fad-4e56-a99d-a10f210b9bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26084
35823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2608435823
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.200567351
Short name T648
Test name
Test status
Simulation time 118263285 ps
CPU time 4.57 seconds
Started Jun 09 12:37:40 PM PDT 24
Finished Jun 09 12:37:46 PM PDT 24
Peak memory 240416 kb
Host smart-c96c5de3-e79f-44d1-8923-469d4980896e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20056
7351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.200567351
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2349143368
Short name T646
Test name
Test status
Simulation time 125487708 ps
CPU time 7.29 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 12:37:51 PM PDT 24
Peak memory 248700 kb
Host smart-670a25a9-f732-416f-a8d4-0e8245ed48af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23491
43368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2349143368
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3682619512
Short name T202
Test name
Test status
Simulation time 83299166 ps
CPU time 3.64 seconds
Started Jun 09 12:37:42 PM PDT 24
Finished Jun 09 12:37:47 PM PDT 24
Peak memory 248800 kb
Host smart-0dbc7b12-454f-403f-96d2-99b4a60da02b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3682619512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3682619512
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2607916097
Short name T115
Test name
Test status
Simulation time 229645204144 ps
CPU time 3234.93 seconds
Started Jun 09 12:37:39 PM PDT 24
Finished Jun 09 01:31:35 PM PDT 24
Peak memory 289432 kb
Host smart-6ab7d60f-4cb9-494b-82f3-eeffa2c8ef37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607916097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2607916097
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2822510867
Short name T589
Test name
Test status
Simulation time 3027871044 ps
CPU time 31.63 seconds
Started Jun 09 12:37:38 PM PDT 24
Finished Jun 09 12:38:11 PM PDT 24
Peak memory 248764 kb
Host smart-9080bd5d-70c0-46b5-a20e-24548413b547
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2822510867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2822510867
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1081075773
Short name T511
Test name
Test status
Simulation time 673368983 ps
CPU time 58.73 seconds
Started Jun 09 12:37:37 PM PDT 24
Finished Jun 09 12:38:37 PM PDT 24
Peak memory 248872 kb
Host smart-b3401add-91ed-457b-80ab-e81d974a83b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10810
75773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1081075773
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.370188029
Short name T423
Test name
Test status
Simulation time 1703148562 ps
CPU time 24.27 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 12:38:09 PM PDT 24
Peak memory 255164 kb
Host smart-16d05a61-8025-4056-853a-cf7239ab2b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37018
8029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.370188029
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.906487927
Short name T323
Test name
Test status
Simulation time 52864470000 ps
CPU time 1350.13 seconds
Started Jun 09 12:37:49 PM PDT 24
Finished Jun 09 01:00:20 PM PDT 24
Peak memory 288908 kb
Host smart-6c5dac5b-ddad-480e-a0eb-c9a52dece27f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906487927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.906487927
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3657036804
Short name T253
Test name
Test status
Simulation time 24343093393 ps
CPU time 561.72 seconds
Started Jun 09 12:37:40 PM PDT 24
Finished Jun 09 12:47:02 PM PDT 24
Peak memory 265004 kb
Host smart-cc47aa05-f08f-4881-b250-daab943ede59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657036804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3657036804
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.588477567
Short name T640
Test name
Test status
Simulation time 15435826495 ps
CPU time 245.44 seconds
Started Jun 09 12:37:41 PM PDT 24
Finished Jun 09 12:41:48 PM PDT 24
Peak memory 254800 kb
Host smart-ba0b2c7f-33fe-433b-9764-4a92bffe2450
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588477567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.588477567
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.691350652
Short name T346
Test name
Test status
Simulation time 3814182102 ps
CPU time 57.79 seconds
Started Jun 09 12:37:34 PM PDT 24
Finished Jun 09 12:38:32 PM PDT 24
Peak memory 257108 kb
Host smart-4ffb4920-0eef-4f2e-8804-da960274249e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69135
0652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.691350652
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.548697605
Short name T536
Test name
Test status
Simulation time 312200224 ps
CPU time 18.77 seconds
Started Jun 09 12:37:37 PM PDT 24
Finished Jun 09 12:37:57 PM PDT 24
Peak memory 248704 kb
Host smart-6d3f20f9-2621-4a40-826a-397bfaf41b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54869
7605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.548697605
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3090098223
Short name T520
Test name
Test status
Simulation time 325488294 ps
CPU time 11.29 seconds
Started Jun 09 12:37:43 PM PDT 24
Finished Jun 09 12:37:56 PM PDT 24
Peak memory 247220 kb
Host smart-dd271026-e872-4b17-9ad5-f4943c6e99bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30900
98223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3090098223
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2142866974
Short name T365
Test name
Test status
Simulation time 1017380825 ps
CPU time 58.09 seconds
Started Jun 09 12:37:41 PM PDT 24
Finished Jun 09 12:38:46 PM PDT 24
Peak memory 248628 kb
Host smart-fb339dc5-0ae0-4a5d-8149-024f74c60079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21428
66974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2142866974
Directory /workspace/9.alert_handler_smoke/latest
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