Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	63121362	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

30459105

1

T1

184536

T2

120131

T3

1023

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	13966795	1			T1	71320		T2	46495		T3	536
values[0x0]	38958401	1			T1	256142		T2	165840		T3	1283
values[0x1]	40655271	1			T1	255580		T2	166432		T3	1295

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54106623	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39473844

1

T1

233059

T2

151861

T3

1278

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	299247	1			T2	1474		T19	26		T5	1583
valid_sources[0x01]	311436	1			T2	1517		T19	23		T5	1492
valid_sources[0x02]	284278	1			T2	1481		T19	25		T5	1556
valid_sources[0x03]	292500	1			T2	1468		T19	32		T5	1555
valid_sources[0x04]	683727	1			T2	1402		T19	53		T5	1540
valid_sources[0x05]	295324	1			T2	1444		T19	31		T5	1581
valid_sources[0x06]	967944	1			T2	1387		T19	33		T5	1582
valid_sources[0x07]	295722	1			T2	1406		T19	30		T5	1554
valid_sources[0x08]	291025	1			T2	1487		T19	23		T5	1598
valid_sources[0x09]	710970	1			T2	1466		T19	54		T5	1562
valid_sources[0x0a]	318196	1			T2	1464		T19	35		T5	1593
valid_sources[0x0b]	558630	1			T2	1468		T19	36		T5	1499
valid_sources[0x0c]	287674	1			T2	1430		T19	31		T5	1592
valid_sources[0x0d]	296127	1			T2	1506		T19	30		T5	1553
valid_sources[0x0e]	764802	1			T2	1552		T19	36		T5	1619
valid_sources[0x0f]	280829	1			T2	1487		T19	45		T5	1560
valid_sources[0x10]	299768	1			T2	1486		T19	29		T5	1550
valid_sources[0x11]	290981	1			T2	1418		T19	41		T5	1583
valid_sources[0x12]	304137	1			T2	1531		T19	43		T5	1611
valid_sources[0x13]	289075	1			T2	1466		T19	39		T5	1605
valid_sources[0x14]	287696	1			T2	1493		T19	39		T5	1584
valid_sources[0x15]	296567	1			T2	1526		T19	39		T5	1594
valid_sources[0x16]	287442	1			T2	1518		T19	44		T5	1599
valid_sources[0x17]	281694	1			T2	1448		T19	45		T5	1566
valid_sources[0x18]	288057	1			T2	1554		T19	34		T5	1546
valid_sources[0x19]	299659	1			T2	1512		T19	32		T5	1544
valid_sources[0x1a]	279749	1			T2	1468		T19	30		T5	1592
valid_sources[0x1b]	309402	1			T2	1420		T19	30		T5	1593
valid_sources[0x1c]	284267	1			T2	1447		T19	32		T5	1596
valid_sources[0x1d]	294120	1			T2	1406		T19	21		T5	1633
valid_sources[0x1e]	290235	1			T2	1416		T19	29		T5	1626
valid_sources[0x1f]	770906	1			T2	1533		T19	31		T5	1587
valid_sources[0x20]	274007	1			T2	1508		T19	33		T5	1528
valid_sources[0x21]	286343	1			T2	1470		T19	28		T5	1571
valid_sources[0x22]	303332	1			T2	1452		T19	26		T5	1590
valid_sources[0x23]	293500	1			T2	1518		T19	32		T5	1495
valid_sources[0x24]	691913	1			T2	1487		T19	30		T5	1615
valid_sources[0x25]	334279	1			T2	1453		T19	32		T5	1588
valid_sources[0x26]	476652	1			T2	1423		T19	37		T5	1568
valid_sources[0x27]	738942	1			T2	1430		T19	37		T5	1527
valid_sources[0x28]	285028	1			T2	1515		T19	36		T5	1577
valid_sources[0x29]	309879	1			T2	1503		T19	31		T5	1597
valid_sources[0x2a]	296170	1			T2	1449		T19	30		T5	1513
valid_sources[0x2b]	285591	1			T2	1477		T19	31		T5	1576
valid_sources[0x2c]	294797	1			T2	1524		T19	34		T5	1557
valid_sources[0x2d]	489478	1			T2	1506		T19	38		T5	1598
valid_sources[0x2e]	295393	1			T2	1408		T19	30		T5	1577
valid_sources[0x2f]	285480	1			T2	1486		T19	34		T5	1591
valid_sources[0x30]	289521	1			T2	1478		T19	29		T5	1615
valid_sources[0x31]	659012	1			T2	1440		T19	19		T5	1613
valid_sources[0x32]	313996	1			T2	1392		T19	27		T5	1524
valid_sources[0x33]	315093	1			T2	1587		T19	41		T5	1607
valid_sources[0x34]	785073	1			T2	1489		T19	33		T5	1553
valid_sources[0x35]	298323	1			T2	1466		T19	40		T5	1567
valid_sources[0x36]	286448	1			T2	1519		T19	35		T5	1503
valid_sources[0x37]	294584	1			T2	1488		T19	31		T5	1585
valid_sources[0x38]	1128345	1			T2	1512		T19	17		T5	1586
valid_sources[0x39]	295584	1			T2	1482		T19	36		T5	1545
valid_sources[0x3a]	293889	1			T2	1484		T19	37		T5	1575
valid_sources[0x3b]	288311	1			T2	1464		T19	34		T5	1653
valid_sources[0x3c]	290237	1			T2	1522		T19	23		T5	1642
valid_sources[0x3d]	288536	1			T2	1483		T19	28		T5	1584
valid_sources[0x3e]	322333	1			T2	1473		T19	31		T5	1527
valid_sources[0x3f]	290964	1			T2	1473		T19	47		T5	1555
valid_sources[0x40]	286901	1			T2	1461		T19	35		T5	1558
valid_sources[0x41]	574775	1			T2	1511		T4	289420		T19	22
valid_sources[0x42]	285993	1			T2	1519		T19	40		T5	1567
valid_sources[0x43]	292663	1			T2	1441		T19	32		T5	1514
valid_sources[0x44]	291420	1			T2	1478		T19	27		T5	1562
valid_sources[0x45]	290642	1			T2	1552		T19	25		T5	1578
valid_sources[0x46]	286773	1			T2	1496		T19	40		T5	1540
valid_sources[0x47]	304245	1			T2	1544		T19	28		T5	1606
valid_sources[0x48]	296274	1			T2	1503		T19	37		T5	1619
valid_sources[0x49]	292255	1			T2	1397		T19	31		T5	1675
valid_sources[0x4a]	288770	1			T2	1598		T19	35		T5	1520
valid_sources[0x4b]	292620	1			T2	1494		T19	37		T5	1604
valid_sources[0x4c]	304199	1			T2	1424		T19	28		T5	1527
valid_sources[0x4d]	283899	1			T2	1539		T19	41		T5	1608
valid_sources[0x4e]	298625	1			T2	1507		T19	22		T5	1582
valid_sources[0x4f]	291382	1			T2	1410		T19	31		T5	1596
valid_sources[0x50]	719380	1			T2	1438		T19	25		T5	1530
valid_sources[0x51]	285951	1			T2	1599		T19	38		T5	1538
valid_sources[0x52]	602996	1			T2	1493		T19	26		T5	1612
valid_sources[0x53]	291629	1			T2	1447		T19	38		T5	1582
valid_sources[0x54]	289396	1			T2	1549		T19	41		T5	1523
valid_sources[0x55]	376635	1			T2	1416		T19	45		T5	1528
valid_sources[0x56]	296918	1			T2	1432		T19	46		T5	1530
valid_sources[0x57]	281374	1			T2	1517		T19	41		T5	1595
valid_sources[0x58]	290955	1			T2	1462		T19	33		T5	1571
valid_sources[0x59]	702490	1			T2	1541		T19	39		T5	1565
valid_sources[0x5a]	295429	1			T2	1456		T19	42		T5	1544
valid_sources[0x5b]	296016	1			T2	1539		T19	33		T5	1547
valid_sources[0x5c]	296160	1			T2	1476		T19	37		T5	1588
valid_sources[0x5d]	298235	1			T2	1425		T19	31		T5	1563
valid_sources[0x5e]	293829	1			T2	1450		T19	37		T5	1591
valid_sources[0x5f]	516599	1			T2	1468		T19	31		T5	1605
valid_sources[0x60]	292266	1			T2	1600		T19	37		T5	1665
valid_sources[0x61]	302970	1			T2	1485		T19	45		T5	1647
valid_sources[0x62]	296259	1			T2	1472		T19	29		T5	1617
valid_sources[0x63]	296503	1			T2	1534		T19	31		T5	1577
valid_sources[0x64]	288216	1			T2	1449		T19	35		T5	1549
valid_sources[0x65]	642708	1			T2	1443		T19	25		T5	1603
valid_sources[0x66]	280266	1			T2	1499		T19	34		T5	1605
valid_sources[0x67]	954775	1			T2	1521		T19	32		T5	1650
valid_sources[0x68]	293489	1			T2	1439		T19	36		T5	1562
valid_sources[0x69]	283289	1			T2	1514		T19	38		T5	1647
valid_sources[0x6a]	280734	1			T2	1513		T19	41		T5	1487
valid_sources[0x6b]	289467	1			T2	1522		T19	30		T5	1630
valid_sources[0x6c]	465882	1			T2	1441		T19	45		T5	1553
valid_sources[0x6d]	285356	1			T2	1435		T19	27		T5	1553
valid_sources[0x6e]	286507	1			T2	1461		T19	33		T5	1621
valid_sources[0x6f]	296577	1			T2	1448		T19	38		T5	1599
valid_sources[0x70]	591084	1			T2	1501		T19	32		T5	1607
valid_sources[0x71]	285049	1			T2	1570		T19	37		T5	1594
valid_sources[0x72]	279162	1			T2	1419		T19	28		T5	1596
valid_sources[0x73]	290642	1			T2	1479		T19	38		T5	1603
valid_sources[0x74]	692593	1			T2	1455		T19	40		T5	1517
valid_sources[0x75]	338491	1			T2	1492		T19	32		T5	1537
valid_sources[0x76]	291534	1			T2	1474		T19	31		T5	1533
valid_sources[0x77]	689747	1			T2	1514		T19	29		T5	1598
valid_sources[0x78]	280874	1			T2	1476		T19	29		T5	1591
valid_sources[0x79]	297741	1			T2	1370		T19	45		T5	1611
valid_sources[0x7a]	288516	1			T2	1431		T19	42		T5	1531
valid_sources[0x7b]	288214	1			T2	1499		T19	35		T5	1545
valid_sources[0x7c]	279108	1			T2	1500		T19	32		T5	1461
valid_sources[0x7d]	294217	1			T2	1476		T19	32		T5	1616
valid_sources[0x7e]	290890	1			T2	1437		T3	3114		T19	27
valid_sources[0x7f]	297751	1			T2	1610		T19	36		T5	1639
valid_sources[0x80]	294138	1			T2	1523		T19	34		T5	1599

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6964304

1

T1

35538

T2

23288

T3

275

values[0x0]

all_enables

biggest_size

14860328

1

T1

95059

T2

61912

T3

479

values[0x1]

all_enables

biggest_size

8634473

1

T1

53939

T2

34931

T3

269