Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T197,T198
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12952	0	0
DisabledNoTrigBkwd_A	2147483647	827722	0	0
DisabledNoTrigFwd_A	2147483647	1343174506	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12952	0	0
T6	399728	0	0	0
T7	272342	0	0	0
T15	258684	0	0	0
T16	221199	0	0	0
T17	576431	0	0	0
T18	113306	0	0	0
T20	3730	343	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T48	18369	0	0	0
T197	808	129	0	0
T198	0	351	0	0
T199	0	274	0	0
T200	0	772	0	0
T201	0	741	0	0
T202	0	515	0	0
T203	0	703	0	0
T204	0	303	0	0
T205	0	712	0	0
T206	0	1211	0	0
T207	821	137	0	0
T208	0	562	0	0
T209	0	381	0	0
T210	0	1384	0	0
T211	0	546	0	0
T212	0	1794	0	0
T213	0	672	0	0
T214	0	650	0	0
T215	0	772	0	0
T216	249854	0	0	0
T217	133344	0	0	0
T218	71562	0	0	0
T219	19333	0	0	0
T220	18582	0	0	0
T221	281660	0	0	0
T222	364294	0	0	0
T223	41217	0	0	0
T224	149345	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	827722	0	0
T1	2151759	2868	0	0
T2	1720012	42	0	0
T3	96628	13	0	0
T4	413668	4	0	0
T5	1406964	10411	0	0
T6	1598912	375	0	0
T7	0	818	0	0
T15	258684	3708	0	0
T16	0	1428	0	0
T17	0	9659	0	0
T18	0	6	0	0
T19	271456	21	0	0
T20	14920	2	0	0
T21	918216	227	0	0
T22	301000	4	0	0
T32	0	1985	0	0
T48	0	19	0	0
T49	0	1351	0	0
T50	0	12	0	0
T51	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1343174506	0	0
T1	2869012	2090496	0	0
T2	1720012	1705336	0	0
T3	96628	64228	0	0
T4	413668	413120	0	0
T5	1406964	408080	0	0
T6	1598912	1202320	0	0
T19	271456	198225	0	0
T20	14920	13091	0	0
T21	918216	245097	0	0
T22	301000	232891	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T19

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T207,T208,T209
1	1	Covered	T1,T3,T19

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T21,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	630176741	4258	0	0
DisabledNoTrigBkwd_A	630176741	231985	0	0
DisabledNoTrigFwd_A	630176741	325406093	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	4258	0	0
T207	821	137	0	0
T208	0	562	0	0
T209	0	381	0	0
T210	0	1384	0	0
T212	0	1794	0	0
T216	249854	0	0	0
T217	133344	0	0	0
T218	71562	0	0	0
T219	19333	0	0	0
T220	18582	0	0	0
T221	281660	0	0	0
T222	364294	0	0	0
T223	41217	0	0	0
T224	149345	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	231985	0	0
T1	717253	234	0	0
T2	430003	0	0	0
T3	24157	2	0	0
T4	103417	0	0	0
T5	351741	2333	0	0
T6	399728	0	0	0
T15	0	2257	0	0
T16	0	1428	0	0
T17	0	6191	0	0
T19	67864	3	0	0
T20	3730	0	0	0
T21	229554	61	0	0
T22	75250	4	0	0
T48	0	10	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	325406093	0	0
T1	717253	622386	0	0
T2	430003	429993	0	0
T3	24157	19032	0	0
T4	103417	103409	0	0
T5	351741	14963	0	0
T6	399728	399722	0	0
T19	67864	64285	0	0
T20	3730	3251	0	0
T21	229554	2031	0	0
T22	75250	7429	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T201,T202
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	630176741	4332	0	0
DisabledNoTrigBkwd_A	630176741	197871	0	0
DisabledNoTrigFwd_A	630176741	334140677	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	4332	0	0
T6	399728	0	0	0
T7	272342	0	0	0
T15	258684	0	0	0
T16	221199	0	0	0
T17	576431	0	0	0
T18	113306	0	0	0
T20	3730	343	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T48	18369	0	0	0
T201	0	741	0	0
T202	0	515	0	0
T203	0	703	0	0
T205	0	712	0	0
T211	0	546	0	0
T215	0	772	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	197871	0	0
T2	430003	6	0	0
T3	24157	0	0	0
T4	103417	2	0	0
T5	351741	3	0	0
T6	399728	0	0	0
T15	258684	0	0	0
T17	0	2516	0	0
T18	0	6	0	0
T19	67864	0	0	0
T20	3730	2	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T32	0	702	0	0
T48	0	4	0	0
T50	0	3	0	0
T51	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	334140677	0	0
T1	717253	647149	0	0
T2	430003	427264	0	0
T3	24157	24077	0	0
T4	103417	103151	0	0
T5	351741	349723	0	0
T6	399728	399722	0	0
T19	67864	64033	0	0
T20	3730	3268	0	0
T21	229554	229469	0	0
T22	75250	75154	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T197,T206,T213
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	630176741	2662	0	0
DisabledNoTrigBkwd_A	630176741	183985	0	0
DisabledNoTrigFwd_A	630176741	349520396	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	2662	0	0
T10	116690	0	0	0
T34	221286	0	0	0
T52	34459	0	0	0
T107	21613	0	0	0
T197	808	129	0	0
T206	0	1211	0	0
T213	0	672	0	0
T214	0	650	0	0
T225	1289	0	0	0
T226	12283	0	0	0
T227	5627	0	0	0
T228	65013	0	0	0
T229	2439	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	183985	0	0
T1	717253	2	0	0
T2	430003	36	0	0
T3	24157	3	0	0
T4	103417	0	0	0
T5	351741	1554	0	0
T6	399728	0	0	0
T17	0	569	0	0
T19	67864	18	0	0
T20	3730	0	0	0
T21	229554	90	0	0
T22	75250	0	0	0
T32	0	1283	0	0
T49	0	1351	0	0
T50	0	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	349520396	0	0
T1	717253	644105	0	0
T2	430003	418086	0	0
T3	24157	9644	0	0
T4	103417	103409	0	0
T5	351741	23837	0	0
T6	399728	399722	0	0
T19	67864	2116	0	0
T20	3730	3276	0	0
T21	229554	11525	0	0
T22	75250	75154	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T198,T199,T200
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	630176741	1700	0	0
DisabledNoTrigBkwd_A	630176741	213881	0	0
DisabledNoTrigFwd_A	630176741	334107340	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	1700	0	0
T86	59622	0	0	0
T87	19729	0	0	0
T198	1100	351	0	0
T199	0	274	0	0
T200	0	772	0	0
T204	0	303	0	0
T230	178715	0	0	0
T231	193626	0	0	0
T232	24867	0	0	0
T233	115434	0	0	0
T234	240809	0	0	0
T235	616109	0	0	0
T236	330353	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	213881	0	0
T1	717253	2632	0	0
T2	430003	0	0	0
T3	24157	8	0	0
T4	103417	2	0	0
T5	351741	6521	0	0
T6	399728	375	0	0
T7	0	818	0	0
T15	0	1451	0	0
T17	0	383	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	76	0	0
T22	75250	0	0	0
T48	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	334107340	0	0
T1	717253	176856	0	0
T2	430003	429993	0	0
T3	24157	11475	0	0
T4	103417	103151	0	0
T5	351741	19557	0	0
T6	399728	3154	0	0
T19	67864	67791	0	0
T20	3730	3296	0	0
T21	229554	2072	0	0
T22	75250	75154	0	0