Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T23,T24
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T5,T20
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T3,T19

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T19
0	1	Covered	T1,T3,T19
1	0	Covered	T25,T26,T27

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T19
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T25,T26,T27

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T19
1	0	Covered	T28
1	1	Covered	T1,T3,T19

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T19

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T19

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T3,T19

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T3,T19
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T29,T30,T31
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T1,T5,T32
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T33,T34,T31
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T35,T33,T36
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T4
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T22,T17
TimeoutSt->Phase0St	172	Covered	T1,T19,T17

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T17
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T17
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T30,T31
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T5,T32
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T33,T34,T31
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T35,T33,T36
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1269	0	0
CheckAccumTrig0_A	2147483647	2355	0	0
CheckAccumTrig1_A	2147483647	97	0	0
CheckClr_A	2147483647	1037	0	0
CheckEn_A	2147483647	1073248620	0	0
CheckPhase0_A	2147483647	2628	0	0
CheckPhase1_A	2147483647	2573	0	0
CheckPhase2_A	2147483647	2524	0	0
CheckPhase3_A	2147483647	2473	0	0
CheckTimeout0_A	2147483647	4344	0	0
CheckTimeoutSt1_A	2147483647	423910	0	0
CheckTimeoutSt2_A	2147483647	4024	0	0
CheckTimeoutStTrig_A	2147483647	221	0	0
ErrorStAllEscAsserted_A	2147483647	6425	0	0
ErrorStIsTerminal_A	2147483647	5345	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1269	0	0
T12	223980	318	0	0
T13	0	130	0	0
T14	0	279	0	0
T37	0	261	0	0
T38	0	281	0	0
T39	2090304	0	0	0
T40	843600	0	0	0
T41	160320	0	0	0
T42	1365412	0	0	0
T43	215528	0	0	0
T44	1010228	0	0	0
T45	61788	0	0	0
T46	2916632	0	0	0
T47	49720	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2355	0	0
T1	2151759	9	0	0
T2	1720012	4	0	0
T3	96628	2	0	0
T4	413668	2	0	0
T5	1406964	10	0	0
T6	1598912	1	0	0
T7	0	1	0	0
T15	258684	2	0	0
T16	0	1	0	0
T17	0	21	0	0
T18	0	2	0	0
T19	271456	1	0	0
T20	14920	1	0	0
T21	918216	3	0	0
T22	301000	1	0	0
T32	0	7	0	0
T35	0	1	0	0
T48	0	3	0	0
T49	0	1	0	0
T50	0	4	0	0
T51	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	97	0	0
T5	351741	0	0	0
T6	399728	0	0	0
T20	3730	0	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T25	477874	3	0	0
T26	497913	1	0	0
T27	328005	1	0	0
T29	43937	0	0	0
T33	388360	1	0	0
T40	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	20520	0	0	0
T69	351876	0	0	0
T70	237048	0	0	0
T71	74130	0	0	0
T72	123720	0	0	0
T73	264486	0	0	0
T74	2340894	0	0	0
T75	729351	0	0	0
T76	35133	0	0	0
T77	24742	0	0	0
T78	186298	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1037	0	0
T1	1434506	5	0	0
T2	860006	2	0	0
T3	48314	0	0	0
T4	413668	2	0	0
T5	1406964	7	0	0
T6	1598912	0	0	0
T8	0	1	0	0
T15	517368	0	0	0
T16	442398	0	0	0
T17	1152862	8	0	0
T19	271456	0	0	0
T20	14920	0	0	0
T21	918216	0	0	0
T22	301000	0	0	0
T25	0	5	0	0
T26	0	8	0	0
T27	0	4	0	0
T29	0	1	0	0
T32	0	15	0	0
T33	0	5	0	0
T35	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T70	0	1	0	0
T73	0	1	0	0
T75	0	1	0	0
T79	0	5	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1073248620	0	0
T1	2869012	2309839	0	0
T2	1720012	881785	0	0
T3	96628	30279	0	0
T4	413668	412652	0	0
T5	1406964	75115	0	0
T6	1598912	1202320	0	0
T19	271456	143710	0	0
T20	14920	13091	0	0
T21	918216	245096	0	0
T22	301000	232888	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2628	0	0
T1	2151759	10	0	0
T2	1720012	4	0	0
T3	96628	3	0	0
T4	413668	2	0	0
T5	1406964	11	0	0
T6	1598912	1	0	0
T7	0	1	0	0
T15	258684	2	0	0
T16	0	1	0	0
T17	0	23	0	0
T18	0	1	0	0
T19	271456	2	0	0
T20	14920	1	0	0
T21	918216	3	0	0
T22	301000	1	0	0
T32	0	7	0	0
T48	0	4	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2573	0	0
T1	2151759	9	0	0
T2	1720012	4	0	0
T3	96628	3	0	0
T4	413668	2	0	0
T5	1406964	10	0	0
T6	1598912	1	0	0
T7	0	1	0	0
T15	258684	2	0	0
T16	0	1	0	0
T17	0	23	0	0
T18	0	1	0	0
T19	271456	2	0	0
T20	14920	1	0	0
T21	918216	3	0	0
T22	301000	1	0	0
T32	0	6	0	0
T48	0	4	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2524	0	0
T1	2151759	9	0	0
T2	1720012	4	0	0
T3	96628	3	0	0
T4	413668	2	0	0
T5	1406964	10	0	0
T6	1598912	1	0	0
T7	0	1	0	0
T15	258684	2	0	0
T16	0	1	0	0
T17	0	23	0	0
T18	0	1	0	0
T19	271456	2	0	0
T20	14920	1	0	0
T21	918216	3	0	0
T22	301000	1	0	0
T32	0	6	0	0
T48	0	4	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2473	0	0
T1	2151759	9	0	0
T2	1720012	4	0	0
T3	96628	3	0	0
T4	413668	2	0	0
T5	1406964	10	0	0
T6	1598912	1	0	0
T7	0	1	0	0
T15	258684	2	0	0
T16	0	1	0	0
T17	0	23	0	0
T18	0	1	0	0
T19	271456	2	0	0
T20	14920	1	0	0
T21	918216	3	0	0
T22	301000	1	0	0
T32	0	6	0	0
T48	0	4	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4344	0	0
T1	2151759	145	0	0
T2	1290009	0	0	0
T3	96628	1	0	0
T4	413668	0	0	0
T5	1406964	1	0	0
T6	1598912	0	0	0
T15	258684	0	0	0
T16	221199	0	0	0
T17	0	30	0	0
T19	271456	1	0	0
T20	14920	0	0	0
T21	918216	0	0	0
T22	301000	1	0	0
T25	0	498	0	0
T26	0	20	0	0
T27	0	17	0	0
T30	0	1	0	0
T32	0	9	0	0
T33	0	1	0	0
T35	0	2	0	0
T48	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T68	0	1	0	0
T69	0	3	0	0
T72	0	1	0	0
T79	0	51	0	0
T80	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	423910	0	0
T1	2151759	28533	0	0
T2	1290009	0	0	0
T3	96628	414	0	0
T4	413668	0	0	0
T5	1406964	6	0	0
T6	1598912	0	0	0
T15	258684	0	0	0
T16	221199	0	0	0
T17	0	3139	0	0
T19	271456	682	0	0
T20	14920	0	0	0
T21	918216	0	0	0
T22	301000	22	0	0
T25	0	48862	0	0
T26	0	1818	0	0
T27	0	3431	0	0
T30	0	48	0	0
T32	0	489	0	0
T33	0	232	0	0
T35	0	66	0	0
T48	0	264	0	0
T50	0	117	0	0
T51	0	219	0	0
T68	0	115	0	0
T69	0	196	0	0
T72	0	107	0	0
T79	0	2997	0	0
T80	0	240	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4024	0	0
T1	2151759	144	0	0
T2	1290009	0	0	0
T3	72471	0	0	0
T4	310251	0	0	0
T5	1055223	0	0	0
T6	1199184	0	0	0
T7	272342	0	0	0
T17	576431	28	0	0
T18	113306	0	0	0
T19	203592	0	0	0
T20	11190	0	0	0
T21	688662	0	0	0
T22	225750	1	0	0
T25	0	493	0	0
T26	0	18	0	0
T27	0	24	0	0
T29	0	1	0	0
T30	0	1	0	0
T32	634133	6	0	0
T33	0	3	0	0
T35	0	1	0	0
T48	18369	1	0	0
T49	123404	0	0	0
T50	29340	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T68	0	1	0	0
T69	0	3	0	0
T72	0	1	0	0
T79	0	51	0	0
T80	87198	1	0	0
T81	0	10	0	0
T82	17621	0	0	0
T83	37934	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	221	0	0
T1	717253	1	0	0
T2	430003	0	0	0
T3	24157	1	0	0
T4	103417	0	0	0
T5	703482	0	0	0
T6	799456	0	0	0
T8	537171	0	0	0
T15	258684	0	0	0
T17	0	2	0	0
T19	135728	1	0	0
T20	7460	0	0	0
T21	459108	0	0	0
T22	150500	0	0	0
T25	238937	2	0	0
T26	0	2	0	0
T27	0	4	0	0
T28	0	2	0	0
T30	0	2	0	0
T31	0	9	0	0
T35	946070	1	0	0
T46	0	2	0	0
T47	0	3	0	0
T51	226360	1	0	0
T54	0	5	0	0
T58	0	5	0	0
T68	10260	0	0	0
T69	175938	0	0	0
T70	118524	0	0	0
T71	37065	0	0	0
T79	176853	0	0	0
T84	0	2	0	0
T85	0	5	0	0
T86	0	1	0	0
T87	0	3	0	0
T88	0	1	0	0
T89	183850	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6425	0	0
T12	223980	1495	0	0
T13	0	689	0	0
T14	0	1459	0	0
T37	0	1419	0	0
T38	0	1363	0	0
T39	2090304	0	0	0
T40	843600	0	0	0
T41	160320	0	0	0
T42	1365412	0	0	0
T43	215528	0	0	0
T44	1010228	0	0	0
T45	61788	0	0	0
T46	2916632	0	0	0
T47	49720	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5345	0	0
T12	223980	1255	0	0
T13	0	569	0	0
T14	0	1219	0	0
T37	0	1179	0	0
T38	0	1123	0	0
T39	2090304	0	0	0
T40	843600	0	0	0
T41	160320	0	0	0
T42	1365412	0	0	0
T43	215528	0	0	0
T44	1010228	0	0	0
T45	61788	0	0	0
T46	2916632	0	0	0
T47	49720	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2869012	2868712	0	0
T2	1720012	1719972	0	0
T3	96628	96308	0	0
T4	413668	413636	0	0
T5	1406964	1406932	0	0
T6	1598912	1598888	0	0
T19	271456	271164	0	0
T20	14920	14596	0	0
T21	918216	917876	0	0
T22	301000	300616	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2869012	2868712	0	0
T2	1720012	1719972	0	0
T3	96628	96308	0	0
T4	413668	413636	0	0
T5	1406964	1406932	0	0
T6	1598912	1598888	0	0
T19	271456	271164	0	0
T20	14920	14596	0	0
T21	918216	917876	0	0
T22	301000	300616	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Covered	T1,T20,T17
1	1	0	Covered	T1,T3,T19
1	1	1	Covered	T1,T17,T50

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T50
0	1	Covered	T51,T35,T25
1	0	Covered	T25,T54,T56

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T17,T50
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T25,T54,T56

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T50
1	0	Not Covered
1	1	Covered	T51,T35,T25

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T17
1	Covered	T4,T5,T20

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T32,T35,T25

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T20
1	Covered	T5,T32,T51

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T20
1	Covered	T2,T17,T48

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T5,T20,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T4,T5,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T5,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T4,T5
Phase1St	198	Covered	T2,T4,T5
Phase2St	215	Covered	T2,T4,T5
Phase3St	233	Covered	T2,T4,T5
TerminalSt	249	Covered	T2,T4,T5
TimeoutSt	159	Covered	T1,T17,T50

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T2,T4,T5
IdleSt->TimeoutSt	159	Covered	T1,T17,T50
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T31,T28,T60
Phase0St->Phase1St	198	Covered	T2,T4,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T5,T32,T53
Phase1St->Phase2St	215	Covered	T2,T4,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T34,T90,T91
Phase2St->Phase3St	233	Covered	T2,T4,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T35,T92,T93
Phase3St->TerminalSt	249	Covered	T2,T4,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T5,T17
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T17,T50
TimeoutSt->Phase0St	172	Covered	T51,T35,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T50
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T51,T35,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T50
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T50
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T31,T60,T93
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T32,T53
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T34,T90,T91
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T35,T92,T93
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	630176741	314	0	0
CheckAccumTrig0_A	630176741	526	0	0
CheckAccumTrig1_A	630176741	17	0	0
CheckClr_A	630176741	240	0	0
CheckEn_A	629883362	269014921	0	0
CheckPhase0_A	630176741	600	0	0
CheckPhase1_A	630176741	586	0	0
CheckPhase2_A	630176741	578	0	0
CheckPhase3_A	630176741	567	0	0
CheckTimeout0_A	630176741	1326	0	0
CheckTimeoutSt1_A	630176741	129111	0	0
CheckTimeoutSt2_A	630176741	1241	0	0
CheckTimeoutStTrig_A	630176741	68	0	0
ErrorStAllEscAsserted_A	630176741	1582	0	0
ErrorStIsTerminal_A	630176741	1312	0	0
EscStateOut_A	629882143	629808744	0	0
u_state_regs_A	630176741	629987731	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	314	0	0
T12	55995	70	0	0
T13	0	29	0	0
T14	0	84	0	0
T37	0	62	0	0
T38	0	69	0	0
T39	522576	0	0	0
T40	210900	0	0	0
T41	40080	0	0	0
T42	341353	0	0	0
T43	53882	0	0	0
T44	252557	0	0	0
T45	15447	0	0	0
T46	729158	0	0	0
T47	12430	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	526	0	0
T2	430003	1	0	0
T3	24157	0	0	0
T4	103417	1	0	0
T5	351741	3	0	0
T6	399728	0	0	0
T15	258684	0	0	0
T17	0	5	0	0
T18	0	1	0	0
T19	67864	0	0	0
T20	3730	1	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T32	0	5	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	17	0	0
T25	238937	1	0	0
T26	165971	0	0	0
T27	109335	0	0	0
T40	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	10260	0	0	0
T69	175938	0	0	0
T70	118524	0	0	0
T71	37065	0	0	0
T72	61860	0	0	0
T73	88162	0	0	0
T74	780298	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	240	0	0
T4	103417	1	0	0
T5	351741	2	0	0
T6	399728	0	0	0
T8	0	1	0	0
T15	258684	0	0	0
T16	221199	0	0	0
T17	576431	1	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T25	0	1	0	0
T32	0	4	0	0
T35	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T70	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629883362	269014921	0	0
T1	717253	647149	0	0
T2	430003	3025	0	0
T3	24157	24076	0	0
T4	103417	102917	0	0
T5	351741	20568	0	0
T6	399728	399722	0	0
T19	67864	64032	0	0
T20	3730	3268	0	0
T21	229554	229468	0	0
T22	75250	75153	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	600	0	0
T2	430003	1	0	0
T3	24157	0	0	0
T4	103417	1	0	0
T5	351741	3	0	0
T6	399728	0	0	0
T15	258684	0	0	0
T17	0	5	0	0
T18	0	1	0	0
T19	67864	0	0	0
T20	3730	1	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T32	0	5	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	586	0	0
T2	430003	1	0	0
T3	24157	0	0	0
T4	103417	1	0	0
T5	351741	2	0	0
T6	399728	0	0	0
T15	258684	0	0	0
T17	0	5	0	0
T18	0	1	0	0
T19	67864	0	0	0
T20	3730	1	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T32	0	4	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	578	0	0
T2	430003	1	0	0
T3	24157	0	0	0
T4	103417	1	0	0
T5	351741	2	0	0
T6	399728	0	0	0
T15	258684	0	0	0
T17	0	5	0	0
T18	0	1	0	0
T19	67864	0	0	0
T20	3730	1	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T32	0	4	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	567	0	0
T2	430003	1	0	0
T3	24157	0	0	0
T4	103417	1	0	0
T5	351741	2	0	0
T6	399728	0	0	0
T15	258684	0	0	0
T17	0	5	0	0
T18	0	1	0	0
T19	67864	0	0	0
T20	3730	1	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T32	0	4	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	1326	0	0
T1	717253	49	0	0
T2	430003	0	0	0
T3	24157	0	0	0
T4	103417	0	0	0
T5	351741	0	0	0
T6	399728	0	0	0
T17	0	11	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T25	0	251	0	0
T26	0	7	0	0
T32	0	3	0	0
T35	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T69	0	3	0	0
T79	0	38	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	129111	0	0
T1	717253	9309	0	0
T2	430003	0	0	0
T3	24157	0	0	0
T4	103417	0	0	0
T5	351741	0	0	0
T6	399728	0	0	0
T17	0	1402	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T25	0	23663	0	0
T26	0	772	0	0
T32	0	186	0	0
T35	0	21	0	0
T50	0	117	0	0
T51	0	18	0	0
T69	0	196	0	0
T79	0	2230	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	1241	0	0
T1	717253	49	0	0
T2	430003	0	0	0
T3	24157	0	0	0
T4	103417	0	0	0
T5	351741	0	0	0
T6	399728	0	0	0
T17	0	11	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T25	0	249	0	0
T26	0	5	0	0
T27	0	9	0	0
T32	0	3	0	0
T50	0	1	0	0
T52	0	1	0	0
T69	0	3	0	0
T79	0	38	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	68	0	0
T8	537171	0	0	0
T25	238937	1	0	0
T26	0	2	0	0
T27	0	2	0	0
T31	0	5	0	0
T35	946070	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T51	226360	1	0	0
T54	0	2	0	0
T58	0	2	0	0
T68	10260	0	0	0
T69	175938	0	0	0
T70	118524	0	0	0
T71	37065	0	0	0
T79	176853	0	0	0
T89	183850	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	1582	0	0
T12	55995	388	0	0
T13	0	153	0	0
T14	0	388	0	0
T37	0	338	0	0
T38	0	315	0	0
T39	522576	0	0	0
T40	210900	0	0	0
T41	40080	0	0	0
T42	341353	0	0	0
T43	53882	0	0	0
T44	252557	0	0	0
T45	15447	0	0	0
T46	729158	0	0	0
T47	12430	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	1312	0	0
T12	55995	328	0	0
T13	0	123	0	0
T14	0	328	0	0
T37	0	278	0	0
T38	0	255	0	0
T39	522576	0	0	0
T40	210900	0	0	0
T41	40080	0	0	0
T42	341353	0	0	0
T43	53882	0	0	0
T44	252557	0	0	0
T45	15447	0	0	0
T46	729158	0	0	0
T47	12430	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629882143	629808744	0	0
T1	717253	717178	0	0
T2	430003	429993	0	0
T3	24157	24077	0	0
T4	103417	103409	0	0
T5	351741	351733	0	0
T6	399728	399722	0	0
T19	67864	67791	0	0
T20	3730	3649	0	0
T21	229554	229469	0	0
T22	75250	75154	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	629987731	0	0
T1	717253	717178	0	0
T2	430003	429993	0	0
T3	24157	24077	0	0
T4	103417	103409	0	0
T5	351741	351733	0	0
T6	399728	399722	0	0
T19	67864	67791	0	0
T20	3730	3649	0	0
T21	229554	229469	0	0
T22	75250	75154	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T3,T19
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T19

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T24
1	1	1	Covered	T1,T3,T19

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T19
1	0	1	Covered	T1,T21,T22
1	1	0	Covered	T1,T19,T5
1	1	1	Covered	T1,T22,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T17
0	1	Covered	T1,T25,T27
1	0	Covered	T26,T33,T53

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T22,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T33,T53

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T17
1	0	Not Covered
1	1	Covered	T1,T25,T27

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T19,T5
1	Covered	T1,T3,T21

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T19
1	Covered	T1,T5,T80

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T19,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T19
1	Covered	T1,T17,T48

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T3,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T3,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T3,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T19,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T19
Phase1St	198	Covered	T1,T3,T19
Phase2St	215	Covered	T1,T3,T19
Phase3St	233	Covered	T1,T3,T19
TerminalSt	249	Covered	T1,T3,T19
TimeoutSt	159	Covered	T1,T22,T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T3,T19
IdleSt->TimeoutSt	159	Covered	T1,T22,T17
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T30,T54,T46
Phase0St->Phase1St	198	Covered	T1,T3,T19
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T1,T32,T26
Phase1St->Phase2St	215	Covered	T1,T3,T19
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T33,T31,T59
Phase2St->Phase3St	233	Covered	T1,T3,T19
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T33,T36,T55
Phase3St->TerminalSt	249	Covered	T1,T3,T19
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T5,T17
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T22,T17
TimeoutSt->Phase0St	172	Covered	T1,T25,T26

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T17
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T54,T94
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T19
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T19
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T32,T26
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T19
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T19,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T33,T31,T59
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T19
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T33,T36,T55
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T5,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T19
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	630176741	285	0	0
CheckAccumTrig0_A	630176741	810	0	0
CheckAccumTrig1_A	630176741	40	0	0
CheckClr_A	630176741	349	0	0
CheckEn_A	629883362	252396580	0	0
CheckPhase0_A	630176741	885	0	0
CheckPhase1_A	630176741	860	0	0
CheckPhase2_A	630176741	845	0	0
CheckPhase3_A	630176741	818	0	0
CheckTimeout0_A	630176741	1220	0	0
CheckTimeoutSt1_A	630176741	102133	0	0
CheckTimeoutSt2_A	630176741	1128	0	0
CheckTimeoutStTrig_A	630176741	50	0	0
ErrorStAllEscAsserted_A	630176741	1596	0	0
ErrorStIsTerminal_A	630176741	1326	0	0
EscStateOut_A	629882143	629808744	0	0
u_state_regs_A	630176741	629987731	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	285	0	0
T12	55995	78	0	0
T13	0	29	0	0
T14	0	58	0	0
T37	0	56	0	0
T38	0	64	0	0
T39	522576	0	0	0
T40	210900	0	0	0
T41	40080	0	0	0
T42	341353	0	0	0
T43	53882	0	0	0
T44	252557	0	0	0
T45	15447	0	0	0
T46	729158	0	0	0
T47	12430	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	810	0	0
T1	717253	7	0	0
T2	430003	0	0	0
T3	24157	1	0	0
T4	103417	0	0	0
T5	351741	6	0	0
T6	399728	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	3	0	0
T19	67864	1	0	0
T20	3730	0	0	0
T21	229554	1	0	0
T22	75250	1	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	40	0	0
T26	165971	1	0	0
T27	109335	0	0	0
T29	43937	0	0	0
T33	388360	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T73	88162	0	0	0
T74	780298	0	0	0
T75	729351	0	0	0
T76	35133	0	0	0
T77	24742	0	0	0
T78	186298	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	349	0	0
T1	717253	4	0	0
T2	430003	0	0	0
T3	24157	0	0	0
T4	103417	0	0	0
T5	351741	5	0	0
T6	399728	0	0	0
T17	0	1	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T25	0	1	0	0
T26	0	6	0	0
T27	0	2	0	0
T32	0	3	0	0
T49	0	1	0	0
T73	0	1	0	0
T79	0	5	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629883362	252396580	0	0
T1	717253	842423	0	0
T2	430003	429993	0	0
T3	24157	2051	0	0
T4	103417	103409	0	0
T5	351741	14963	0	0
T6	399728	399722	0	0
T19	67864	9772	0	0
T20	3730	3251	0	0
T21	229554	2031	0	0
T22	75250	7429	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	885	0	0
T1	717253	8	0	0
T2	430003	0	0	0
T3	24157	1	0	0
T4	103417	0	0	0
T5	351741	6	0	0
T6	399728	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	3	0	0
T19	67864	1	0	0
T20	3730	0	0	0
T21	229554	1	0	0
T22	75250	1	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	860	0	0
T1	717253	7	0	0
T2	430003	0	0	0
T3	24157	1	0	0
T4	103417	0	0	0
T5	351741	6	0	0
T6	399728	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	3	0	0
T19	67864	1	0	0
T20	3730	0	0	0
T21	229554	1	0	0
T22	75250	1	0	0
T48	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	845	0	0
T1	717253	7	0	0
T2	430003	0	0	0
T3	24157	1	0	0
T4	103417	0	0	0
T5	351741	6	0	0
T6	399728	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	3	0	0
T19	67864	1	0	0
T20	3730	0	0	0
T21	229554	1	0	0
T22	75250	1	0	0
T48	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	818	0	0
T1	717253	7	0	0
T2	430003	0	0	0
T3	24157	1	0	0
T4	103417	0	0	0
T5	351741	6	0	0
T6	399728	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	3	0	0
T19	67864	1	0	0
T20	3730	0	0	0
T21	229554	1	0	0
T22	75250	1	0	0
T48	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	1220	0	0
T1	717253	47	0	0
T2	430003	0	0	0
T3	24157	0	0	0
T4	103417	0	0	0
T5	351741	0	0	0
T6	399728	0	0	0
T17	0	1	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	0	0	0
T22	75250	1	0	0
T25	0	3	0	0
T32	0	1	0	0
T51	0	1	0	0
T68	0	1	0	0
T72	0	1	0	0
T79	0	2	0	0
T80	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	102133	0	0
T1	717253	9572	0	0
T2	430003	0	0	0
T3	24157	0	0	0
T4	103417	0	0	0
T5	351741	0	0	0
T6	399728	0	0	0
T17	0	53	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	0	0	0
T22	75250	22	0	0
T25	0	443	0	0
T32	0	127	0	0
T51	0	201	0	0
T68	0	115	0	0
T72	0	107	0	0
T79	0	51	0	0
T80	0	240	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	1128	0	0
T1	717253	46	0	0
T2	430003	0	0	0
T3	24157	0	0	0
T4	103417	0	0	0
T5	351741	0	0	0
T6	399728	0	0	0
T17	0	1	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	0	0	0
T22	75250	1	0	0
T25	0	2	0	0
T32	0	1	0	0
T51	0	1	0	0
T68	0	1	0	0
T72	0	1	0	0
T79	0	2	0	0
T80	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	50	0	0
T1	717253	1	0	0
T2	430003	0	0	0
T3	24157	0	0	0
T4	103417	0	0	0
T5	351741	0	0	0
T6	399728	0	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T28	0	1	0	0
T30	0	2	0	0
T31	0	1	0	0
T54	0	2	0	0
T85	0	4	0	0
T87	0	1	0	0
T88	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	1596	0	0
T12	55995	348	0	0
T13	0	168	0	0
T14	0	373	0	0
T37	0	377	0	0
T38	0	330	0	0
T39	522576	0	0	0
T40	210900	0	0	0
T41	40080	0	0	0
T42	341353	0	0	0
T43	53882	0	0	0
T44	252557	0	0	0
T45	15447	0	0	0
T46	729158	0	0	0
T47	12430	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	1326	0	0
T12	55995	288	0	0
T13	0	138	0	0
T14	0	313	0	0
T37	0	317	0	0
T38	0	270	0	0
T39	522576	0	0	0
T40	210900	0	0	0
T41	40080	0	0	0
T42	341353	0	0	0
T43	53882	0	0	0
T44	252557	0	0	0
T45	15447	0	0	0
T46	729158	0	0	0
T47	12430	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629882143	629808744	0	0
T1	717253	717178	0	0
T2	430003	429993	0	0
T3	24157	24077	0	0
T4	103417	103409	0	0
T5	351741	351733	0	0
T6	399728	399722	0	0
T19	67864	67791	0	0
T20	3730	3649	0	0
T21	229554	229469	0	0
T22	75250	75154	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	629987731	0	0
T1	717253	717178	0	0
T2	430003	429993	0	0
T3	24157	24077	0	0
T4	103417	103409	0	0
T5	351741	351733	0	0
T6	399728	399722	0	0
T19	67864	67791	0	0
T20	3730	3649	0	0
T21	229554	229469	0	0
T22	75250	75154	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T23
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T5,T21
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T19,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T17
0	1	Covered	T19,T17,T27
1	0	Covered	T25,T27,T52

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T19,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T25,T27,T52

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T17
1	0	Not Covered
1	1	Covered	T19,T17,T27

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T19
1	Covered	T3,T17,T25

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T19,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T50

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T1,T2,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T19,T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T19,T17
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T29,T63,T95
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T30,T91,T96
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T97,T98,T99
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T92,T97,T100
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T17
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T17,T32
TimeoutSt->Phase0St	172	Covered	T19,T17,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T19,T17,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T32
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T95,T101
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T30,T91,T96
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T19
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T97,T98,T99
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T92,T97,T100
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	630176741	336	0	0
CheckAccumTrig0_A	630176741	512	0	0
CheckAccumTrig1_A	630176741	19	0	0
CheckClr_A	630176741	219	0	0
CheckEn_A	629883362	263613846	0	0
CheckPhase0_A	630176741	577	0	0
CheckPhase1_A	630176741	570	0	0
CheckPhase2_A	630176741	560	0	0
CheckPhase3_A	630176741	556	0	0
CheckTimeout0_A	630176741	993	0	0
CheckTimeoutSt1_A	630176741	98195	0	0
CheckTimeoutSt2_A	630176741	919	0	0
CheckTimeoutStTrig_A	630176741	55	0	0
ErrorStAllEscAsserted_A	630176741	1634	0	0
ErrorStIsTerminal_A	630176741	1364	0	0
EscStateOut_A	629882143	629808744	0	0
u_state_regs_A	630176741	629987731	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	336	0	0
T12	55995	104	0	0
T13	0	39	0	0
T14	0	71	0	0
T37	0	66	0	0
T38	0	56	0	0
T39	522576	0	0	0
T40	210900	0	0	0
T41	40080	0	0	0
T42	341353	0	0	0
T43	53882	0	0	0
T44	252557	0	0	0
T45	15447	0	0	0
T46	729158	0	0	0
T47	12430	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	512	0	0
T1	717253	1	0	0
T2	430003	3	0	0
T3	24157	1	0	0
T4	103417	0	0	0
T5	351741	1	0	0
T6	399728	0	0	0
T17	0	10	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	1	0	0
T22	75250	0	0	0
T32	0	2	0	0
T35	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	19	0	0
T25	238937	2	0	0
T26	165971	0	0	0
T27	109335	1	0	0
T46	0	1	0	0
T52	0	1	0	0
T58	0	1	0	0
T68	10260	0	0	0
T69	175938	0	0	0
T70	118524	0	0	0
T71	37065	0	0	0
T72	61860	0	0	0
T73	88162	0	0	0
T74	780298	0	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	219	0	0
T1	717253	1	0	0
T2	430003	2	0	0
T3	24157	0	0	0
T4	103417	0	0	0
T5	351741	0	0	0
T6	399728	0	0	0
T17	0	6	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T25	0	2	0	0
T26	0	2	0	0
T27	0	2	0	0
T29	0	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T50	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629883362	263613846	0	0
T1	717253	644104	0	0
T2	430003	18774	0	0
T3	24157	2070	0	0
T4	103417	103409	0	0
T5	351741	23837	0	0
T6	399728	399722	0	0
T19	67864	2116	0	0
T20	3730	3276	0	0
T21	229554	11525	0	0
T22	75250	75153	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	577	0	0
T1	717253	1	0	0
T2	430003	3	0	0
T3	24157	1	0	0
T4	103417	0	0	0
T5	351741	1	0	0
T6	399728	0	0	0
T17	0	12	0	0
T19	67864	1	0	0
T20	3730	0	0	0
T21	229554	1	0	0
T22	75250	0	0	0
T32	0	2	0	0
T49	0	1	0	0
T50	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	570	0	0
T1	717253	1	0	0
T2	430003	3	0	0
T3	24157	1	0	0
T4	103417	0	0	0
T5	351741	1	0	0
T6	399728	0	0	0
T17	0	12	0	0
T19	67864	1	0	0
T20	3730	0	0	0
T21	229554	1	0	0
T22	75250	0	0	0
T32	0	2	0	0
T49	0	1	0	0
T50	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	560	0	0
T1	717253	1	0	0
T2	430003	3	0	0
T3	24157	1	0	0
T4	103417	0	0	0
T5	351741	1	0	0
T6	399728	0	0	0
T17	0	12	0	0
T19	67864	1	0	0
T20	3730	0	0	0
T21	229554	1	0	0
T22	75250	0	0	0
T32	0	2	0	0
T49	0	1	0	0
T50	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	556	0	0
T1	717253	1	0	0
T2	430003	3	0	0
T3	24157	1	0	0
T4	103417	0	0	0
T5	351741	1	0	0
T6	399728	0	0	0
T17	0	12	0	0
T19	67864	1	0	0
T20	3730	0	0	0
T21	229554	1	0	0
T22	75250	0	0	0
T32	0	2	0	0
T49	0	1	0	0
T50	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	993	0	0
T1	717253	49	0	0
T2	430003	0	0	0
T3	24157	0	0	0
T4	103417	0	0	0
T5	351741	0	0	0
T6	399728	0	0	0
T17	0	6	0	0
T19	67864	1	0	0
T20	3730	0	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T25	0	18	0	0
T26	0	12	0	0
T27	0	16	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T79	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	98195	0	0
T1	717253	9652	0	0
T2	430003	0	0	0
T3	24157	0	0	0
T4	103417	0	0	0
T5	351741	0	0	0
T6	399728	0	0	0
T17	0	192	0	0
T19	67864	682	0	0
T20	3730	0	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T25	0	2119	0	0
T26	0	991	0	0
T27	0	3337	0	0
T30	0	48	0	0
T32	0	169	0	0
T33	0	232	0	0
T79	0	59	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	919	0	0
T1	717253	49	0	0
T2	430003	0	0	0
T3	24157	0	0	0
T4	103417	0	0	0
T5	351741	0	0	0
T6	399728	0	0	0
T17	0	4	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T25	0	16	0	0
T26	0	12	0	0
T27	0	14	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T79	0	1	0	0
T81	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	55	0	0
T5	351741	0	0	0
T6	399728	0	0	0
T7	272342	0	0	0
T15	258684	0	0	0
T16	221199	0	0	0
T17	576431	2	0	0
T19	67864	1	0	0
T20	3730	0	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T31	0	1	0	0
T54	0	1	0	0
T58	0	2	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	1634	0	0
T12	55995	385	0	0
T13	0	201	0	0
T14	0	368	0	0
T37	0	353	0	0
T38	0	327	0	0
T39	522576	0	0	0
T40	210900	0	0	0
T41	40080	0	0	0
T42	341353	0	0	0
T43	53882	0	0	0
T44	252557	0	0	0
T45	15447	0	0	0
T46	729158	0	0	0
T47	12430	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	1364	0	0
T12	55995	325	0	0
T13	0	171	0	0
T14	0	308	0	0
T37	0	293	0	0
T38	0	267	0	0
T39	522576	0	0	0
T40	210900	0	0	0
T41	40080	0	0	0
T42	341353	0	0	0
T43	53882	0	0	0
T44	252557	0	0	0
T45	15447	0	0	0
T46	729158	0	0	0
T47	12430	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629882143	629808744	0	0
T1	717253	717178	0	0
T2	430003	429993	0	0
T3	24157	24077	0	0
T4	103417	103409	0	0
T5	351741	351733	0	0
T6	399728	399722	0	0
T19	67864	67791	0	0
T20	3730	3649	0	0
T21	229554	229469	0	0
T22	75250	75154	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	629987731	0	0
T1	717253	717178	0	0
T2	430003	429993	0	0
T3	24157	24077	0	0
T4	103417	103409	0	0
T5	351741	351733	0	0
T6	399728	399722	0	0
T19	67864	67791	0	0
T20	3730	3649	0	0
T21	229554	229469	0	0
T22	75250	75154	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T21

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T5
1	0	1	Covered	T21,T6,T17
1	1	0	Covered	T1,T19,T5
1	1	1	Covered	T3,T5,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T17
0	1	Covered	T3,T48,T107
1	0	Covered	T5,T32,T33

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T5,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T32,T33

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T17
1	0	Covered	T28
1	1	Covered	T3,T48,T107

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T48,T32

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T21,T15

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T5,T6,T48

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T4,T17,T51

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T3,T6,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T21,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T4
Phase1St	198	Covered	T1,T3,T4
Phase2St	215	Covered	T1,T3,T4
Phase3St	233	Covered	T1,T3,T4
TerminalSt	249	Covered	T1,T3,T4
TimeoutSt	159	Covered	T3,T5,T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T4,T21
IdleSt->TimeoutSt	159	Covered	T3,T5,T17
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T33,T108,T53
Phase0St->Phase1St	198	Covered	T1,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T32,T40,T109
Phase1St->Phase2St	215	Covered	T1,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T75,T108,T110
Phase2St->Phase3St	233	Covered	T1,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T32,T111,T112
Phase3St->TerminalSt	249	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T17
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T17,T48,T35
TimeoutSt->Phase0St	172	Covered	T3,T5,T48

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T21
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T48
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T48,T35
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T33,T108,T53
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T32,T40,T109
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T75,T108,T110
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T32,T111,T112
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T48,T32
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	630176741	334	0	0
CheckAccumTrig0_A	630176741	507	0	0
CheckAccumTrig1_A	630176741	21	0	0
CheckClr_A	630176741	229	0	0
CheckEn_A	629883362	288223273	0	0
CheckPhase0_A	630176741	566	0	0
CheckPhase1_A	630176741	557	0	0
CheckPhase2_A	630176741	541	0	0
CheckPhase3_A	630176741	532	0	0
CheckTimeout0_A	630176741	805	0	0
CheckTimeoutSt1_A	630176741	94471	0	0
CheckTimeoutSt2_A	630176741	736	0	0
CheckTimeoutStTrig_A	630176741	48	0	0
ErrorStAllEscAsserted_A	630176741	1613	0	0
ErrorStIsTerminal_A	630176741	1343	0	0
EscStateOut_A	629882143	629808744	0	0
u_state_regs_A	630176741	629987731	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	334	0	0
T12	55995	66	0	0
T13	0	33	0	0
T14	0	66	0	0
T37	0	77	0	0
T38	0	92	0	0
T39	522576	0	0	0
T40	210900	0	0	0
T41	40080	0	0	0
T42	341353	0	0	0
T43	53882	0	0	0
T44	252557	0	0	0
T45	15447	0	0	0
T46	729158	0	0	0
T47	12430	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	507	0	0
T1	717253	1	0	0
T2	430003	0	0	0
T3	24157	0	0	0
T4	103417	1	0	0
T5	351741	0	0	0
T6	399728	1	0	0
T7	0	1	0	0
T15	0	1	0	0
T17	0	3	0	0
T18	0	1	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	1	0	0
T22	75250	0	0	0
T48	0	1	0	0
T50	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	21	0	0
T5	351741	1	0	0
T6	399728	0	0	0
T7	272342	0	0	0
T15	258684	0	0	0
T16	221199	0	0	0
T17	576431	0	0	0
T20	3730	0	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T32	0	3	0	0
T33	0	1	0	0
T48	18369	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T104	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	1	0	0
T116	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	229	0	0
T4	103417	1	0	0
T5	351741	0	0	0
T6	399728	0	0	0
T15	258684	0	0	0
T16	221199	0	0	0
T17	576431	0	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T25	0	1	0	0
T30	0	1	0	0
T32	0	7	0	0
T33	0	2	0	0
T48	0	1	0	0
T51	0	1	0	0
T75	0	1	0	0
T108	0	3	0	0
T111	0	4	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629883362	288223273	0	0
T1	717253	176163	0	0
T2	430003	429993	0	0
T3	24157	2082	0	0
T4	103417	102917	0	0
T5	351741	15747	0	0
T6	399728	3154	0	0
T19	67864	67790	0	0
T20	3730	3296	0	0
T21	229554	2072	0	0
T22	75250	75153	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	566	0	0
T1	717253	1	0	0
T2	430003	0	0	0
T3	24157	1	0	0
T4	103417	1	0	0
T5	351741	1	0	0
T6	399728	1	0	0
T7	0	1	0	0
T15	0	1	0	0
T17	0	3	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	1	0	0
T22	75250	0	0	0
T48	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	557	0	0
T1	717253	1	0	0
T2	430003	0	0	0
T3	24157	1	0	0
T4	103417	1	0	0
T5	351741	1	0	0
T6	399728	1	0	0
T7	0	1	0	0
T15	0	1	0	0
T17	0	3	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	1	0	0
T22	75250	0	0	0
T48	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	541	0	0
T1	717253	1	0	0
T2	430003	0	0	0
T3	24157	1	0	0
T4	103417	1	0	0
T5	351741	1	0	0
T6	399728	1	0	0
T7	0	1	0	0
T15	0	1	0	0
T17	0	3	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	1	0	0
T22	75250	0	0	0
T48	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	532	0	0
T1	717253	1	0	0
T2	430003	0	0	0
T3	24157	1	0	0
T4	103417	1	0	0
T5	351741	1	0	0
T6	399728	1	0	0
T7	0	1	0	0
T15	0	1	0	0
T17	0	3	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	1	0	0
T22	75250	0	0	0
T48	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	805	0	0
T3	24157	1	0	0
T4	103417	0	0	0
T5	351741	1	0	0
T6	399728	0	0	0
T15	258684	0	0	0
T16	221199	0	0	0
T17	0	12	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T25	0	226	0	0
T26	0	1	0	0
T27	0	1	0	0
T32	0	3	0	0
T35	0	1	0	0
T48	0	2	0	0
T79	0	10	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	94471	0	0
T3	24157	414	0	0
T4	103417	0	0	0
T5	351741	6	0	0
T6	399728	0	0	0
T15	258684	0	0	0
T16	221199	0	0	0
T17	0	1492	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T25	0	22637	0	0
T26	0	55	0	0
T27	0	94	0	0
T32	0	7	0	0
T35	0	45	0	0
T48	0	264	0	0
T79	0	657	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	736	0	0
T7	272342	0	0	0
T17	576431	12	0	0
T18	113306	0	0	0
T25	0	226	0	0
T26	0	1	0	0
T27	0	1	0	0
T29	0	1	0	0
T32	634133	0	0	0
T33	0	2	0	0
T35	0	1	0	0
T48	18369	1	0	0
T49	123404	0	0	0
T50	29340	0	0	0
T79	0	10	0	0
T80	87198	0	0	0
T81	0	3	0	0
T82	17621	0	0	0
T83	37934	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	48	0	0
T3	24157	1	0	0
T4	103417	0	0	0
T5	351741	0	0	0
T6	399728	0	0	0
T15	258684	0	0	0
T16	221199	0	0	0
T19	67864	0	0	0
T20	3730	0	0	0
T21	229554	0	0	0
T22	75250	0	0	0
T31	0	2	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T84	0	1	0	0
T87	0	2	0	0
T107	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	1613	0	0
T12	55995	374	0	0
T13	0	167	0	0
T14	0	330	0	0
T37	0	351	0	0
T38	0	391	0	0
T39	522576	0	0	0
T40	210900	0	0	0
T41	40080	0	0	0
T42	341353	0	0	0
T43	53882	0	0	0
T44	252557	0	0	0
T45	15447	0	0	0
T46	729158	0	0	0
T47	12430	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	1343	0	0
T12	55995	314	0	0
T13	0	137	0	0
T14	0	270	0	0
T37	0	291	0	0
T38	0	331	0	0
T39	522576	0	0	0
T40	210900	0	0	0
T41	40080	0	0	0
T42	341353	0	0	0
T43	53882	0	0	0
T44	252557	0	0	0
T45	15447	0	0	0
T46	729158	0	0	0
T47	12430	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629882143	629808744	0	0
T1	717253	717178	0	0
T2	430003	429993	0	0
T3	24157	24077	0	0
T4	103417	103409	0	0
T5	351741	351733	0	0
T6	399728	399722	0	0
T19	67864	67791	0	0
T20	3730	3649	0	0
T21	229554	229469	0	0
T22	75250	75154	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630176741	629987731	0	0
T1	717253	717178	0	0
T2	430003	429993	0	0
T3	24157	24077	0	0
T4	103417	103409	0	0
T5	351741	351733	0	0
T6	399728	399722	0	0
T19	67864	67791	0	0
T20	3730	3649	0	0
T21	229554	229469	0	0
T22	75250	75154	0	0