Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64794669	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31344493

1

T1

17851

T2

136261

T3

4451

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14635965	1			T1	6970		T2	53199		T3	1737
values[0x0]	39826198	1			T1	24778		T2	189666		T3	6031
values[0x1]	41676999	1			T1	24809		T2	188690		T3	5997

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55430864	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40708298

1

T1

22525

T2

172143

T3

5609

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	581935	1			T2	1653		T3	36		T5	40
valid_sources[0x01]	321905	1			T2	1714		T3	43		T5	46
valid_sources[0x02]	324800	1			T2	1717		T3	62		T5	46
valid_sources[0x03]	542357	1			T2	1640		T3	39		T5	42
valid_sources[0x04]	322871	1			T2	1723		T3	74		T5	33
valid_sources[0x05]	320677	1			T2	1658		T3	51		T5	35
valid_sources[0x06]	325309	1			T2	1645		T3	62		T5	37
valid_sources[0x07]	318337	1			T2	1628		T3	56		T5	40
valid_sources[0x08]	327021	1			T2	1722		T3	56		T5	30
valid_sources[0x09]	317420	1			T2	1703		T3	72		T5	39
valid_sources[0x0a]	711265	1			T2	1568		T3	51		T4	391853
valid_sources[0x0b]	662880	1			T2	1631		T3	57		T5	42
valid_sources[0x0c]	328738	1			T2	1783		T3	49		T5	41
valid_sources[0x0d]	323685	1			T2	1637		T3	41		T5	28
valid_sources[0x0e]	323280	1			T2	1702		T3	49		T5	39
valid_sources[0x0f]	317189	1			T2	1589		T3	46		T5	35
valid_sources[0x10]	341112	1			T2	1655		T3	55		T5	30
valid_sources[0x11]	333129	1			T2	1673		T3	40		T5	34
valid_sources[0x12]	332842	1			T2	1614		T3	46		T5	44
valid_sources[0x13]	741798	1			T2	1601		T3	70		T5	43
valid_sources[0x14]	326164	1			T2	1667		T3	59		T5	30
valid_sources[0x15]	336909	1			T2	1771		T3	58		T5	28
valid_sources[0x16]	336733	1			T2	1613		T3	51		T5	42
valid_sources[0x17]	319544	1			T2	1521		T3	72		T5	38
valid_sources[0x18]	1111351	1			T2	1726		T3	48		T5	30
valid_sources[0x19]	321930	1			T2	1697		T3	62		T5	25
valid_sources[0x1a]	323315	1			T2	1669		T3	34		T5	32
valid_sources[0x1b]	776928	1			T2	1731		T3	35		T5	34
valid_sources[0x1c]	317585	1			T2	1805		T3	60		T5	32
valid_sources[0x1d]	323871	1			T2	1619		T3	54		T5	34
valid_sources[0x1e]	320756	1			T2	1697		T3	57		T5	38
valid_sources[0x1f]	323210	1			T2	1737		T3	57		T5	40
valid_sources[0x20]	320489	1			T2	1719		T3	31		T5	43
valid_sources[0x21]	328434	1			T2	1705		T3	44		T5	34
valid_sources[0x22]	336229	1			T2	1728		T3	90		T5	38
valid_sources[0x23]	324348	1			T2	1671		T3	61		T5	45
valid_sources[0x24]	326866	1			T2	1632		T3	44		T5	24
valid_sources[0x25]	321151	1			T2	1813		T3	41		T5	31
valid_sources[0x26]	332619	1			T2	1736		T3	33		T5	31
valid_sources[0x27]	322310	1			T2	1592		T3	50		T5	32
valid_sources[0x28]	328718	1			T2	1674		T3	68		T5	43
valid_sources[0x29]	321793	1			T2	1730		T3	56		T5	40
valid_sources[0x2a]	336316	1			T2	1635		T3	28		T5	32
valid_sources[0x2b]	322711	1			T2	1702		T3	51		T5	28
valid_sources[0x2c]	620513	1			T2	1603		T3	61		T5	33
valid_sources[0x2d]	321596	1			T2	1622		T3	43		T5	25
valid_sources[0x2e]	320957	1			T2	1661		T3	79		T5	46
valid_sources[0x2f]	331145	1			T2	1784		T3	79		T5	36
valid_sources[0x30]	321814	1			T2	1705		T3	61		T5	48
valid_sources[0x31]	520282	1			T2	1808		T3	93		T5	28
valid_sources[0x32]	316338	1			T2	1706		T3	77		T5	37
valid_sources[0x33]	317790	1			T2	1661		T3	27		T5	39
valid_sources[0x34]	321634	1			T2	1679		T3	54		T5	34
valid_sources[0x35]	647902	1			T2	1692		T3	49		T5	35
valid_sources[0x36]	323994	1			T2	1671		T3	94		T5	24
valid_sources[0x37]	325337	1			T2	1668		T3	34		T5	35
valid_sources[0x38]	324320	1			T2	1728		T3	64		T5	50
valid_sources[0x39]	331726	1			T2	1749		T3	56		T5	35
valid_sources[0x3a]	329801	1			T2	1641		T3	36		T5	31
valid_sources[0x3b]	351449	1			T2	1740		T3	52		T5	54
valid_sources[0x3c]	327181	1			T2	1633		T3	59		T5	40
valid_sources[0x3d]	337332	1			T2	1617		T3	66		T5	39
valid_sources[0x3e]	717804	1			T2	1551		T3	46		T5	50
valid_sources[0x3f]	317012	1			T2	1767		T3	49		T5	49
valid_sources[0x40]	328238	1			T2	1742		T3	45		T5	33
valid_sources[0x41]	340361	1			T2	1720		T3	64		T5	34
valid_sources[0x42]	328734	1			T2	1654		T3	48		T5	31
valid_sources[0x43]	324572	1			T2	1692		T3	56		T5	30
valid_sources[0x44]	338744	1			T2	1662		T3	34		T5	48
valid_sources[0x45]	313878	1			T2	1742		T3	48		T5	41
valid_sources[0x46]	323290	1			T2	1706		T3	81		T5	33
valid_sources[0x47]	350262	1			T2	1746		T3	34		T5	18
valid_sources[0x48]	314532	1			T2	1653		T3	51		T5	28
valid_sources[0x49]	329296	1			T2	1674		T3	39		T5	39
valid_sources[0x4a]	327669	1			T2	1630		T3	72		T5	49
valid_sources[0x4b]	322731	1			T2	1748		T3	47		T5	63
valid_sources[0x4c]	316642	1			T2	1747		T3	59		T5	41
valid_sources[0x4d]	320181	1			T2	1647		T3	41		T5	29
valid_sources[0x4e]	658869	1			T2	1685		T3	44		T5	33
valid_sources[0x4f]	315892	1			T2	1657		T3	53		T5	26
valid_sources[0x50]	316554	1			T2	1686		T3	74		T5	32
valid_sources[0x51]	321348	1			T2	1663		T3	65		T5	47
valid_sources[0x52]	695559	1			T2	1494		T3	44		T5	31
valid_sources[0x53]	318007	1			T2	1728		T3	56		T5	26
valid_sources[0x54]	319284	1			T2	1640		T3	63		T5	36
valid_sources[0x55]	317161	1			T2	1828		T3	83		T5	34
valid_sources[0x56]	621774	1			T2	1607		T3	67		T5	39
valid_sources[0x57]	707077	1			T2	1548		T3	49		T5	39
valid_sources[0x58]	329519	1			T2	1592		T3	65		T5	34
valid_sources[0x59]	337698	1			T2	1656		T3	56		T5	48
valid_sources[0x5a]	363800	1			T2	1627		T3	31		T5	33
valid_sources[0x5b]	327717	1			T2	1661		T3	67		T5	47
valid_sources[0x5c]	329566	1			T2	1694		T3	50		T5	33
valid_sources[0x5d]	331886	1			T2	1646		T3	73		T5	42
valid_sources[0x5e]	324794	1			T2	1714		T3	58		T5	34
valid_sources[0x5f]	611176	1			T2	1599		T3	46		T5	29
valid_sources[0x60]	315829	1			T2	1609		T3	52		T5	39
valid_sources[0x61]	392980	1			T2	1520		T3	77		T5	29
valid_sources[0x62]	324096	1			T2	1717		T3	35		T5	36
valid_sources[0x63]	327836	1			T2	1658		T3	74		T5	31
valid_sources[0x64]	366641	1			T2	1835		T3	52		T5	36
valid_sources[0x65]	323318	1			T2	1690		T3	56		T5	30
valid_sources[0x66]	665841	1			T2	1658		T3	71		T5	42
valid_sources[0x67]	324271	1			T2	1759		T3	50		T5	35
valid_sources[0x68]	679677	1			T2	1596		T3	38		T5	37
valid_sources[0x69]	319811	1			T2	1649		T3	55		T5	21
valid_sources[0x6a]	332447	1			T2	1701		T3	69		T5	46
valid_sources[0x6b]	803196	1			T2	1736		T3	67		T5	39
valid_sources[0x6c]	347045	1			T2	1618		T3	48		T5	27
valid_sources[0x6d]	323711	1			T2	1701		T3	55		T5	39
valid_sources[0x6e]	325340	1			T2	1723		T3	50		T5	28
valid_sources[0x6f]	321871	1			T2	1663		T3	75		T5	37
valid_sources[0x70]	330295	1			T2	1695		T3	56		T5	45
valid_sources[0x71]	807275	1			T2	1632		T3	58		T5	22
valid_sources[0x72]	321137	1			T2	1710		T3	54		T5	34
valid_sources[0x73]	320007	1			T2	1631		T3	39		T5	28
valid_sources[0x74]	324670	1			T2	1678		T3	57		T5	41
valid_sources[0x75]	327431	1			T2	1739		T3	68		T5	41
valid_sources[0x76]	317502	1			T2	1657		T3	59		T5	47
valid_sources[0x77]	335927	1			T2	1747		T3	49		T5	34
valid_sources[0x78]	333454	1			T2	1822		T3	75		T5	43
valid_sources[0x79]	317157	1			T2	1662		T3	33		T5	32
valid_sources[0x7a]	1027897	1			T2	1677		T3	55		T5	37
valid_sources[0x7b]	321989	1			T2	1700		T3	45		T5	29
valid_sources[0x7c]	321842	1			T2	1705		T3	57		T5	33
valid_sources[0x7d]	318503	1			T2	1632		T3	45		T5	53
valid_sources[0x7e]	331521	1			T2	1698		T3	49		T5	29
valid_sources[0x7f]	321696	1			T2	1612		T3	72		T5	40
valid_sources[0x80]	314927	1			T2	1761		T3	51		T5	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7257353

1

T1

3514

T2

26471

T3

848

values[0x0]

all_enables

biggest_size

15217364

1

T1

9112

T2

70261

T3

2305

values[0x1]

all_enables

biggest_size

8869776

1

T1

5225

T2

39529

T3

1298