Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T205,T38
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12938	0	0
DisabledNoTrigBkwd_A	2147483647	790459	0	0
DisabledNoTrigFwd_A	2147483647	1607905215	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12938	0	0
T11	38050	0	0	0
T32	360740	0	0	0
T33	274413	0	0	0
T34	6601	0	0	0
T35	14037	0	0	0
T36	555083	0	0	0
T37	68451	0	0	0
T38	0	1315	0	0
T57	34990	0	0	0
T71	0	1477	0	0
T82	264183	0	0	0
T122	569717	0	0	0
T191	0	637	0	0
T205	1468	720	0	0
T206	0	1316	0	0
T207	1404	618	0	0
T208	2949	606	0	0
T209	0	192	0	0
T210	0	412	0	0
T211	0	302	0	0
T212	0	388	0	0
T213	0	251	0	0
T214	0	164	0	0
T215	0	639	0	0
T216	0	631	0	0
T217	0	632	0	0
T218	0	659	0	0
T219	0	379	0	0
T220	0	424	0	0
T221	0	1176	0	0
T222	34202	0	0	0
T223	141779	0	0	0
T224	26658	0	0	0
T225	95268	0	0	0
T226	804149	0	0	0
T227	582472	0	0	0
T228	562252	0	0	0
T229	467042	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	790459	0	0
T1	2792248	258	0	0
T2	1250980	8471	0	0
T3	448544	2	0	0
T4	1737160	720	0	0
T5	3346308	0	0	0
T6	1236052	632	0	0
T7	1570588	13887	0	0
T8	11808	0	0	0
T9	60304	0	0	0
T10	10452	0	0	0
T15	0	1058	0	0
T16	0	8683	0	0
T17	0	681	0	0
T24	0	1692	0	0
T25	0	2760	0	0
T41	0	4	0	0
T42	0	3694	0	0
T43	0	1	0	0
T44	0	438	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1607905215	0	0
T1	2792248	2137034	0	0
T2	1250980	63642	0	0
T3	448544	1219675	0	0
T4	1737160	895237	0	0
T5	3346308	2235923	0	0
T6	1236052	980331	0	0
T7	1570588	788965	0	0
T8	11808	7956	0	0
T9	60304	31951	0	0
T10	10452	6294	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T207,T215
1	1	Covered	T1,T2,T6

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	693562445	1257	0	0
DisabledNoTrigBkwd_A	693562445	277129	0	0
DisabledNoTrigFwd_A	693562445	360449773	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	1257	0	0
T57	34990	0	0	0
T207	1404	618	0	0
T215	0	639	0	0
T222	34202	0	0	0
T223	141779	0	0	0
T224	26658	0	0	0
T225	95268	0	0	0
T226	804149	0	0	0
T227	582472	0	0	0
T228	562252	0	0	0
T229	467042	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	277129	0	0
T1	698062	128	0	0
T2	312745	2009	0	0
T3	112136	0	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	363	0	0
T7	392647	42	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	149	0	0
T16	0	8437	0	0
T17	0	341	0	0
T24	0	13	0	0
T41	0	4	0	0
T42	0	1174	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	360449773	0	0
T1	698062	423599	0	0
T2	312745	2325	0	0
T3	112136	112127	0	0
T4	434290	434284	0	0
T5	836577	836499	0	0
T6	309013	167456	0	0
T7	392647	392117	0	0
T8	2952	2866	0	0
T9	15076	6235	0	0
T10	2613	596	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T205,T191,T206
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	693562445	4073	0	0
DisabledNoTrigBkwd_A	693562445	182175	0	0
DisabledNoTrigFwd_A	693562445	411934570	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	4073	0	0
T11	38050	0	0	0
T32	360740	0	0	0
T33	274413	0	0	0
T34	6601	0	0	0
T35	14037	0	0	0
T36	555083	0	0	0
T37	68451	0	0	0
T82	264183	0	0	0
T122	569717	0	0	0
T191	0	637	0	0
T205	1468	720	0	0
T206	0	1316	0	0
T209	0	192	0	0
T210	0	412	0	0
T214	0	164	0	0
T217	0	632	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	182175	0	0
T1	698062	5	0	0
T2	312745	2691	0	0
T3	112136	0	0	0
T4	434290	720	0	0
T5	836577	0	0	0
T6	309013	12	0	0
T7	392647	11251	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	0	4	0	0
T24	0	1664	0	0
T42	0	837	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	411934570	0	0
T1	698062	671506	0	0
T2	312745	16786	0	0
T3	112136	994818	0	0
T4	434290	2752	0	0
T5	836577	560185	0	0
T6	309013	275354	0	0
T7	392647	2091	0	0
T8	2952	2866	0	0
T9	15076	7990	0	0
T10	2613	600	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T208,T211,T216
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	693562445	2715	0	0
DisabledNoTrigBkwd_A	693562445	180652	0	0
DisabledNoTrigFwd_A	693562445	424236285	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	2715	0	0
T107	13385	0	0	0
T208	2949	606	0	0
T211	0	302	0	0
T216	0	631	0	0
T221	0	1176	0	0
T230	43573	0	0	0
T231	12481	0	0	0
T232	133328	0	0	0
T233	22075	0	0	0
T234	14451	0	0	0
T235	74141	0	0	0
T236	775097	0	0	0
T237	112636	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	180652	0	0
T1	698062	110	0	0
T2	312745	1639	0	0
T3	112136	0	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	158	0	0
T7	392647	0	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	241	0	0
T16	0	132	0	0
T17	0	97	0	0
T25	0	2760	0	0
T42	0	1256	0	0
T43	0	1	0	0
T44	0	438	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	424236285	0	0
T1	698062	405497	0	0
T2	312745	20594	0	0
T3	112136	112127	0	0
T4	434290	23917	0	0
T5	836577	836499	0	0
T6	309013	262368	0	0
T7	392647	392637	0	0
T8	2952	598	0	0
T9	15076	6270	0	0
T10	2613	2549	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T38,T212
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	693562445	4893	0	0
DisabledNoTrigBkwd_A	693562445	150503	0	0
DisabledNoTrigFwd_A	693562445	411284587	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	4893	0	0
T20	460894	0	0	0
T26	241003	0	0	0
T27	283553	0	0	0
T38	0	1315	0	0
T47	36560	0	0	0
T71	4969	1477	0	0
T77	24615	0	0	0
T115	131844	0	0	0
T116	101694	0	0	0
T212	0	388	0	0
T213	0	251	0	0
T218	0	659	0	0
T219	0	379	0	0
T220	0	424	0	0
T238	439299	0	0	0
T239	12888	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	150503	0	0
T1	698062	15	0	0
T2	312745	2132	0	0
T3	112136	2	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	99	0	0
T7	392647	2594	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	667	0	0
T16	0	112	0	0
T17	0	239	0	0
T24	0	15	0	0
T42	0	427	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	411284587	0	0
T1	698062	636432	0	0
T2	312745	23937	0	0
T3	112136	603	0	0
T4	434290	434284	0	0
T5	836577	2740	0	0
T6	309013	275153	0	0
T7	392647	2120	0	0
T8	2952	1626	0	0
T9	15076	11456	0	0
T10	2613	2549	0	0