Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_alert_receiver
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_alerts[0].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[1].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[2].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[3].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[4].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[5].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[6].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[7].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[8].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[9].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[10].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[11].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[12].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[13].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[14].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[15].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[16].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[17].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[18].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[19].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[20].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[21].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[22].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[23].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[24].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[25].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[26].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[27].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[28].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[29].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[30].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[31].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[32].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[33].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[34].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[35].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[36].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[37].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[38].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[39].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[40].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[41].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[42].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[43].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[44].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[45].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[46].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[47].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[48].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[49].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[50].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[51].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[52].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[53].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[54].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[55].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[56].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[57].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[58].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[59].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[60].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[61].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[62].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[63].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[64].u_alert_receiver 100.00 100.00



Module Instance : tb.dut.gen_alerts[0].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[1].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[2].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[3].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[4].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[5].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[6].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[7].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[8].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[9].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[10].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[11].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[12].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[13].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[14].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[15].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[16].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[17].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[18].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[19].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[20].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[21].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[22].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[23].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[24].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[25].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[26].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[27].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[28].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[29].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[30].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[31].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[32].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[33].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[34].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[35].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[36].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[37].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[38].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[39].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[40].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[41].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[42].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[43].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[44].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[45].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[46].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[47].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[48].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[49].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[50].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[51].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[52].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[53].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[54].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[55].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[56].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[57].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[58].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[59].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[60].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[61].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[62].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[63].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[64].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
ping_ok_o Yes Yes T2,T4,T7 Yes T2,T4,T7 OUTPUT
integ_fail_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T5 Yes T15,T24,T16 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T24,T16 Yes T2,T3,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[0].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T5,T15 Yes T2,T5,T15 INPUT
ping_ok_o Yes Yes T2,T15,T45 Yes T2,T15,T45 OUTPUT
integ_fail_o Yes Yes T6,T46,T65 Yes T6,T46,T65 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T5,T15 Yes T15,T26,T27 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T26,T27 Yes T2,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[1].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ping_ok_o Yes Yes T2,T7,T15 Yes T2,T7,T15 OUTPUT
integ_fail_o Yes Yes T2,T17,T25 Yes T2,T17,T25 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T7 Yes T15,T24,T16 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T24,T16 Yes T2,T3,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[2].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T5,T7 Yes T2,T5,T7 INPUT
ping_ok_o Yes Yes T2,T7,T16 Yes T2,T7,T16 OUTPUT
integ_fail_o Yes Yes T2,T7,T17 Yes T2,T7,T17 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T5,T7 Yes T16,T65,T27 OUTPUT
alert_rx_o.ping_p Yes Yes T16,T65,T27 Yes T2,T5,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[3].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
ping_ok_o Yes Yes T2,T4,T7 Yes T2,T4,T7 OUTPUT
integ_fail_o Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T7 Yes T2,T15,T16 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T15,T16 Yes T2,T3,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[4].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T7,T15,T24 Yes T7,T15,T24 INPUT
ping_ok_o Yes Yes T7,T15,T24 Yes T7,T15,T24 OUTPUT
integ_fail_o Yes Yes T15,T17,T46 Yes T15,T17,T46 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T15,T24 Yes T15,T16,T27 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T27 Yes T7,T15,T24 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[5].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T15,T24 Yes T2,T15,T24 INPUT
ping_ok_o Yes Yes T2,T15,T24 Yes T2,T15,T24 OUTPUT
integ_fail_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T15,T24 Yes T2,T15,T16 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T15,T16 Yes T2,T15,T24 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[6].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T3,T4,T7 Yes T3,T4,T7 INPUT
ping_ok_o Yes Yes T4,T7,T15 Yes T4,T7,T15 OUTPUT
integ_fail_o Yes Yes T15,T17,T25 Yes T15,T17,T25 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T7,T15 Yes T15,T27,T241 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T27,T241 Yes T3,T7,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[7].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T3,T4,T16 Yes T3,T4,T16 INPUT
ping_ok_o Yes Yes T4,T16,T26 Yes T4,T16,T26 OUTPUT
integ_fail_o Yes Yes T2,T15,T17 Yes T2,T15,T17 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T16,T61 Yes T16,T27,T241 OUTPUT
alert_rx_o.ping_p Yes Yes T16,T27,T241 Yes T3,T16,T61 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[8].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T4,T15,T44 Yes T4,T15,T44 INPUT
ping_ok_o Yes Yes T4,T15,T44 Yes T4,T15,T44 OUTPUT
integ_fail_o Yes Yes T6,T7,T16 Yes T6,T7,T16 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T15,T44,T45 Yes T15,T44,T65 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T44,T65 Yes T15,T44,T45 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[9].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T3,T4,T15 Yes T3,T4,T15 INPUT
ping_ok_o Yes Yes T4,T15,T42 Yes T4,T15,T42 OUTPUT
integ_fail_o Yes Yes T1,T7,T15 Yes T1,T7,T15 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T15,T42 Yes T15,T42,T16 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T42,T16 Yes T3,T15,T42 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[10].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T15,T61 Yes T2,T15,T61 INPUT
ping_ok_o Yes Yes T2,T15,T66 Yes T2,T15,T66 OUTPUT
integ_fail_o Yes Yes T6,T15,T16 Yes T6,T15,T16 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T15,T61 Yes T15,T73,T241 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T73,T241 Yes T2,T15,T61 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[11].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T15,T45 Yes T2,T15,T45 INPUT
ping_ok_o Yes Yes T2,T15,T45 Yes T2,T15,T45 OUTPUT
integ_fail_o Yes Yes T6,T15,T17 Yes T6,T15,T17 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T15,T45 Yes T2,T15,T27 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T15,T27 Yes T2,T15,T45 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[12].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T7,T16,T44 Yes T7,T16,T44 INPUT
ping_ok_o Yes Yes T7,T16,T44 Yes T7,T16,T44 OUTPUT
integ_fail_o Yes Yes T1,T6,T15 Yes T1,T6,T15 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T16,T65 Yes T7,T16,T27 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T16,T27 Yes T7,T16,T65 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[13].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T5,T7,T15 Yes T5,T7,T15 INPUT
ping_ok_o Yes Yes T7,T15,T24 Yes T7,T15,T24 OUTPUT
integ_fail_o Yes Yes T25,T48,T242 Yes T25,T48,T242 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T7,T15 Yes T15,T16,T73 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T73 Yes T5,T7,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[14].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T7,T15 Yes T2,T7,T15 INPUT
ping_ok_o Yes Yes T2,T7,T15 Yes T2,T7,T15 OUTPUT
integ_fail_o Yes Yes T7,T17,T16 Yes T7,T17,T16 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T7,T15 Yes T7,T15,T61 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T15,T61 Yes T2,T7,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[15].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T7,T15 Yes T2,T7,T15 INPUT
ping_ok_o Yes Yes T2,T7,T15 Yes T2,T7,T15 OUTPUT
integ_fail_o Yes Yes T1,T6,T7 Yes T1,T6,T7 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T7,T15 Yes T2,T7,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T7,T15 Yes T2,T7,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[16].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T15,T69,T20 Yes T15,T69,T20 INPUT
ping_ok_o Yes Yes T15,T69,T20 Yes T15,T69,T20 OUTPUT
integ_fail_o Yes Yes T1,T6,T7 Yes T1,T6,T7 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T15,T69,T20 Yes T15,T73,T74 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T73,T74 Yes T15,T69,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[17].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T5,T7 Yes T2,T5,T7 INPUT
ping_ok_o Yes Yes T2,T7,T15 Yes T2,T7,T15 OUTPUT
integ_fail_o Yes Yes T1,T15,T45 Yes T1,T15,T45 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T5,T7 Yes T15,T16,T65 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T65 Yes T2,T5,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[18].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T7,T15,T24 Yes T7,T15,T24 INPUT
ping_ok_o Yes Yes T7,T15,T24 Yes T7,T15,T24 OUTPUT
integ_fail_o Yes Yes T2,T6,T16 Yes T2,T6,T16 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T15,T24 Yes T15,T16,T27 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T27 Yes T7,T15,T24 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[19].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T3,T15 Yes T2,T3,T15 INPUT
ping_ok_o Yes Yes T2,T15,T16 Yes T2,T15,T16 OUTPUT
integ_fail_o Yes Yes T1,T2,T16 Yes T1,T2,T16 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T15 Yes T15,T16,T20 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T20 Yes T2,T3,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[20].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T7,T16 Yes T2,T7,T16 INPUT
ping_ok_o Yes Yes T2,T7,T16 Yes T2,T7,T16 OUTPUT
integ_fail_o Yes Yes T2,T7,T17 Yes T2,T7,T17 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T7,T16 Yes T16,T241,T243 OUTPUT
alert_rx_o.ping_p Yes Yes T16,T241,T243 Yes T2,T7,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[21].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T4,T6,T7 Yes T4,T6,T7 INPUT
ping_ok_o Yes Yes T4,T6,T7 Yes T4,T6,T7 OUTPUT
integ_fail_o Yes Yes T2,T7,T15 Yes T2,T7,T15 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T6,T7,T16 Yes T6,T16,T44 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T16,T44 Yes T6,T7,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[22].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T7,T15,T42 Yes T7,T15,T42 INPUT
ping_ok_o Yes Yes T7,T15,T42 Yes T7,T15,T42 OUTPUT
integ_fail_o Yes Yes T2,T6,T17 Yes T2,T6,T17 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T15,T42 Yes T15,T16,T238 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T238 Yes T7,T15,T42 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[23].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T4,T42 Yes T2,T4,T42 INPUT
ping_ok_o Yes Yes T2,T4,T42 Yes T2,T4,T42 OUTPUT
integ_fail_o Yes Yes T7,T15,T25 Yes T7,T15,T25 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T42,T16 Yes T16,T65,T27 OUTPUT
alert_rx_o.ping_p Yes Yes T16,T65,T27 Yes T2,T42,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[24].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T7,T15 Yes T2,T7,T15 INPUT
ping_ok_o Yes Yes T2,T7,T15 Yes T2,T7,T15 OUTPUT
integ_fail_o Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T7,T15 Yes T15,T20,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T20,T26 Yes T2,T7,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[25].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T7,T15 Yes T2,T7,T15 INPUT
ping_ok_o Yes Yes T2,T7,T15 Yes T2,T7,T15 OUTPUT
integ_fail_o Yes Yes T2,T6,T7 Yes T2,T6,T7 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T7,T15 Yes T7,T15,T24 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T15,T24 Yes T2,T7,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[26].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T7,T15 Yes T2,T7,T15 INPUT
ping_ok_o Yes Yes T2,T7,T15 Yes T2,T7,T15 OUTPUT
integ_fail_o Yes Yes T2,T6,T17 Yes T2,T6,T17 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T7,T15 Yes T15,T16,T241 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T241 Yes T2,T7,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[27].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T7,T15 Yes T2,T7,T15 INPUT
ping_ok_o Yes Yes T2,T7,T15 Yes T2,T7,T15 OUTPUT
integ_fail_o Yes Yes T1,T17,T16 Yes T1,T17,T16 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T7,T15 Yes T7,T15,T65 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T15,T65 Yes T2,T7,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[28].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T7,T15 Yes T2,T7,T15 INPUT
ping_ok_o Yes Yes T2,T7,T15 Yes T2,T7,T15 OUTPUT
integ_fail_o Yes Yes T7,T17,T16 Yes T7,T17,T16 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T7,T15 Yes T7,T15,T73 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T15,T73 Yes T2,T7,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[29].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T4,T7 Yes T2,T4,T7 INPUT
ping_ok_o Yes Yes T2,T4,T7 Yes T2,T4,T7 OUTPUT
integ_fail_o Yes Yes T7,T16,T25 Yes T7,T16,T25 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T4,T7 Yes T15,T25,T20 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T25,T20 Yes T2,T4,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[30].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T7,T15,T16 Yes T7,T15,T16 INPUT
ping_ok_o Yes Yes T7,T15,T16 Yes T7,T15,T16 OUTPUT
integ_fail_o Yes Yes T2,T6,T15 Yes T2,T6,T15 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T15,T16 Yes T15,T16,T20 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T20 Yes T7,T15,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[31].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T4,T5 Yes T2,T4,T5 INPUT
ping_ok_o Yes Yes T2,T4,T6 Yes T2,T4,T6 OUTPUT
integ_fail_o Yes Yes T2,T15,T25 Yes T2,T15,T25 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T4,T5 Yes T6,T7,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T7,T15 Yes T2,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[32].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T3,T7,T15 Yes T3,T7,T15 INPUT
ping_ok_o Yes Yes T7,T15,T42 Yes T7,T15,T42 OUTPUT
integ_fail_o Yes Yes T1,T6,T15 Yes T1,T6,T15 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T7,T15 Yes T15,T16,T27 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T27 Yes T3,T7,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[33].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T4,T5,T7 Yes T4,T5,T7 INPUT
ping_ok_o Yes Yes T4,T7,T15 Yes T4,T7,T15 OUTPUT
integ_fail_o Yes Yes T2,T15,T16 Yes T2,T15,T16 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T7,T15 Yes T15,T16,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T25 Yes T5,T7,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[34].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T3,T4,T15 Yes T3,T4,T15 INPUT
ping_ok_o Yes Yes T4,T15,T42 Yes T4,T15,T42 OUTPUT
integ_fail_o Yes Yes T2,T6,T7 Yes T2,T6,T7 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T15 Yes T4,T15,T73 OUTPUT
alert_rx_o.ping_p Yes Yes T4,T15,T73 Yes T3,T4,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[35].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T5,T15,T16 Yes T5,T15,T16 INPUT
ping_ok_o Yes Yes T15,T16,T44 Yes T15,T16,T44 OUTPUT
integ_fail_o Yes Yes T1,T15,T17 Yes T1,T15,T17 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T16 Yes T15,T16,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T25 Yes T5,T15,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[36].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T5,T15 Yes T2,T5,T15 INPUT
ping_ok_o Yes Yes T2,T15,T24 Yes T2,T15,T24 OUTPUT
integ_fail_o Yes Yes T6,T7,T15 Yes T6,T7,T15 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T5,T15 Yes T15,T16,T73 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T73 Yes T2,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[37].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T3,T15,T16 Yes T3,T15,T16 INPUT
ping_ok_o Yes Yes T15,T16,T65 Yes T15,T16,T65 OUTPUT
integ_fail_o Yes Yes T2,T15,T45 Yes T2,T15,T45 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T15,T16 Yes T15,T16,T20 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T20 Yes T3,T15,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[38].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T3,T7,T62 Yes T3,T7,T62 INPUT
ping_ok_o Yes Yes T7,T45,T65 Yes T7,T45,T65 OUTPUT
integ_fail_o Yes Yes T16,T25,T65 Yes T16,T25,T65 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T7,T62 Yes T7,T45,T69 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T45,T69 Yes T3,T7,T62 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[39].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T7,T44,T27 Yes T7,T44,T27 INPUT
ping_ok_o Yes Yes T7,T44,T27 Yes T7,T44,T27 OUTPUT
integ_fail_o Yes Yes T2,T7,T17 Yes T2,T7,T17 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T27,T73 Yes T7,T27,T73 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T27,T73 Yes T7,T27,T73 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[40].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T15,T44 Yes T2,T15,T44 INPUT
ping_ok_o Yes Yes T2,T15,T44 Yes T2,T15,T44 OUTPUT
integ_fail_o Yes Yes T1,T7,T16 Yes T1,T7,T16 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T15,T64 Yes T15,T65,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T65,T26 Yes T2,T15,T64 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[41].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
ping_ok_o Yes Yes T2,T4,T7 Yes T2,T4,T7 OUTPUT
integ_fail_o Yes Yes T2,T25,T46 Yes T2,T25,T46 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T7 Yes T15,T16,T66 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T66 Yes T2,T3,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[42].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ping_ok_o Yes Yes T2,T7,T16 Yes T2,T7,T16 OUTPUT
integ_fail_o Yes Yes T1,T6,T7 Yes T1,T6,T7 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T7 Yes T2,T16,T74 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T16,T74 Yes T2,T3,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[43].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T3,T7,T16 Yes T3,T7,T16 INPUT
ping_ok_o Yes Yes T7,T16,T44 Yes T7,T16,T44 OUTPUT
integ_fail_o Yes Yes T2,T15,T17 Yes T2,T15,T17 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T7,T16 Yes T7,T16,T27 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T16,T27 Yes T3,T7,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[44].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ping_ok_o Yes Yes T2,T7,T15 Yes T2,T7,T15 OUTPUT
integ_fail_o Yes Yes T2,T6,T7 Yes T2,T6,T7 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T7 Yes T7,T15,T241 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T15,T241 Yes T2,T3,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[45].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T4,T7 Yes T2,T4,T7 INPUT
ping_ok_o Yes Yes T2,T4,T7 Yes T2,T4,T7 OUTPUT
integ_fail_o Yes Yes T2,T6,T7 Yes T2,T6,T7 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T4,T7 Yes T2,T15,T24 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T15,T24 Yes T2,T4,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[46].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
ping_ok_o Yes Yes T2,T15,T45 Yes T2,T15,T45 OUTPUT
integ_fail_o Yes Yes T15,T17,T25 Yes T15,T17,T25 OUTPUT
alert_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T4 Yes T15,T62,T45 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T62,T45 Yes T2,T3,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[47].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T4,T15 Yes T2,T4,T15 INPUT
ping_ok_o Yes Yes T2,T4,T15 Yes T2,T4,T15 OUTPUT
integ_fail_o Yes Yes T2,T6,T17 Yes T2,T6,T17 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T15,T42 Yes T15,T16,T69 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T69 Yes T2,T15,T42 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[48].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T3,T7,T44 Yes T3,T7,T44 INPUT
ping_ok_o Yes Yes T7,T44,T20 Yes T7,T44,T20 OUTPUT
integ_fail_o Yes Yes T2,T6,T16 Yes T2,T6,T16 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T7,T20 Yes T7,T73,T241 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T73,T241 Yes T3,T7,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[49].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T5,T7,T15 Yes T5,T7,T15 INPUT
ping_ok_o Yes Yes T7,T15,T16 Yes T7,T15,T16 OUTPUT
integ_fail_o Yes Yes T2,T7,T15 Yes T2,T7,T15 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T7,T15 Yes T15,T16,T27 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T27 Yes T5,T7,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[50].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T4,T5,T7 Yes T4,T5,T7 INPUT
ping_ok_o Yes Yes T4,T7,T15 Yes T4,T7,T15 OUTPUT
integ_fail_o Yes Yes T7,T15,T16 Yes T7,T15,T16 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T7,T15 Yes T7,T15,T27 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T15,T27 Yes T5,T7,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[51].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T4,T15,T44 Yes T4,T15,T44 INPUT
ping_ok_o Yes Yes T4,T15,T44 Yes T4,T15,T44 OUTPUT
integ_fail_o Yes Yes T1,T45,T46 Yes T1,T45,T46 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T15,T73,T241 Yes T15,T73,T241 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T73,T241 Yes T15,T73,T241 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[52].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T7,T15,T16 Yes T7,T15,T16 INPUT
ping_ok_o Yes Yes T7,T15,T16 Yes T7,T15,T16 OUTPUT
integ_fail_o Yes Yes T6,T15,T17 Yes T6,T15,T17 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T15,T16 Yes T15,T16,T66 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T66 Yes T7,T15,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[53].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T7,T45 Yes T2,T7,T45 INPUT
ping_ok_o Yes Yes T2,T7,T45 Yes T2,T7,T45 OUTPUT
integ_fail_o Yes Yes T1,T6,T15 Yes T1,T6,T15 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T7,T45 Yes T45,T241,T48 OUTPUT
alert_rx_o.ping_p Yes Yes T45,T241,T48 Yes T2,T7,T45 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[54].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T7,T15,T24 Yes T7,T15,T24 INPUT
ping_ok_o Yes Yes T7,T15,T24 Yes T7,T15,T24 OUTPUT
integ_fail_o Yes Yes T7,T15,T16 Yes T7,T15,T16 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T15,T24 Yes T15,T24,T16 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T24,T16 Yes T7,T15,T24 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[55].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T7,T16 Yes T2,T7,T16 INPUT
ping_ok_o Yes Yes T2,T7,T16 Yes T2,T7,T16 OUTPUT
integ_fail_o Yes Yes T2,T15,T46 Yes T2,T15,T46 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T7,T16 Yes T2,T16,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T16,T25 Yes T2,T7,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[56].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T7,T15,T16 Yes T7,T15,T16 INPUT
ping_ok_o Yes Yes T7,T15,T16 Yes T7,T15,T16 OUTPUT
integ_fail_o Yes Yes T2,T15,T16 Yes T2,T15,T16 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T15,T16 Yes T15,T16,T62 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T62 Yes T7,T15,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[57].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T7,T15 Yes T2,T7,T15 INPUT
ping_ok_o Yes Yes T2,T7,T15 Yes T2,T7,T15 OUTPUT
integ_fail_o Yes Yes T1,T7,T15 Yes T1,T7,T15 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T7,T15 Yes T15,T16,T20 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T20 Yes T2,T7,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[58].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T5,T7 Yes T2,T5,T7 INPUT
ping_ok_o Yes Yes T2,T7,T15 Yes T2,T7,T15 OUTPUT
integ_fail_o Yes Yes T16,T25,T45 Yes T16,T25,T45 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T5,T7 Yes T15,T69,T27 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T69,T27 Yes T2,T5,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[59].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T15,T16 Yes T2,T15,T16 INPUT
ping_ok_o Yes Yes T2,T15,T16 Yes T2,T15,T16 OUTPUT
integ_fail_o Yes Yes T2,T6,T15 Yes T2,T6,T15 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T15,T16 Yes T15,T16,T65 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T65 Yes T2,T15,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[60].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ping_ok_o Yes Yes T2,T7,T15 Yes T2,T7,T15 OUTPUT
integ_fail_o Yes Yes T2,T15,T25 Yes T2,T15,T25 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T7 Yes T15,T25,T66 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T25,T66 Yes T2,T3,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[61].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T5,T7,T15 Yes T5,T7,T15 INPUT
ping_ok_o Yes Yes T7,T15,T24 Yes T7,T15,T24 OUTPUT
integ_fail_o Yes Yes T6,T16,T65 Yes T6,T16,T65 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T7,T15 Yes T15,T45,T73 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T45,T73 Yes T5,T7,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[62].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T2,T7,T15 Yes T2,T7,T15 INPUT
ping_ok_o Yes Yes T2,T7,T15 Yes T2,T7,T15 OUTPUT
integ_fail_o Yes Yes T2,T15,T16 Yes T2,T15,T16 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T7,T15 Yes T15,T16,T61 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T16,T61 Yes T2,T7,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[63].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T15,T44,T20 Yes T15,T44,T20 INPUT
ping_ok_o Yes Yes T15,T44,T20 Yes T15,T44,T20 OUTPUT
integ_fail_o Yes Yes T2,T6,T7 Yes T2,T6,T7 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T15,T20,T241 Yes T15,T241,T23 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T241,T23 Yes T15,T20,T241 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[64].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T15 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T15 Yes T1,T2,T5 INPUT
ping_req_i Yes Yes T15,T65,T26 Yes T15,T65,T26 INPUT
ping_ok_o Yes Yes T15,T65,T26 Yes T15,T65,T26 OUTPUT
integ_fail_o Yes Yes T15,T17,T16 Yes T15,T17,T16 OUTPUT
alert_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T15,T65,T26 Yes T15,T27,T241 OUTPUT
alert_rx_o.ping_p Yes Yes T15,T27,T241 Yes T15,T65,T26 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T4 INPUT

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%