Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.63	100.00	97.78	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T14
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T6
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T1,T2,T6
1	1	1	Covered	T1,T2,T6

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T6,T15,T16
1	0	Covered	T1,T2,T17

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T6
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T17

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T18,T19
1	1	Covered	T6,T15,T16

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T6,T7

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T6

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T2,T6
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T17,T20,T21
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T17,T22,T23
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T15,T24,T25
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T24,T26,T27
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T6,T7
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T6,T7,T8
TimeoutSt->Phase0St	172	Covered	T1,T2,T6

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T20,T21,T28
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T22,T23,T29
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T15,T24,T25
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T26,T27
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T6,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1287	0	0
CheckAccumTrig0_A	2147483647	2422	0	0
CheckAccumTrig1_A	2147483647	119	0	0
CheckClr_A	2147483647	1094	0	0
CheckEn_A	2147483647	1236577546	0	0
CheckPhase0_A	2147483647	2731	0	0
CheckPhase1_A	2147483647	2683	0	0
CheckPhase2_A	2147483647	2626	0	0
CheckPhase3_A	2147483647	2563	0	0
CheckTimeout0_A	2147483647	3435	0	0
CheckTimeoutSt1_A	2147483647	378140	0	0
CheckTimeoutSt2_A	2147483647	3078	0	0
CheckTimeoutStTrig_A	2147483647	234	0	0
ErrorStAllEscAsserted_A	2147483647	6358	0	0
ErrorStIsTerminal_A	2147483647	5278	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1287	0	0
T11	152200	287	0	0
T12	0	259	0	0
T13	0	314	0	0
T30	0	267	0	0
T31	0	160	0	0
T32	1442960	0	0	0
T33	1097652	0	0	0
T34	26404	0	0	0
T35	56148	0	0	0
T36	2220332	0	0	0
T37	273804	0	0	0
T38	15100	0	0	0
T39	416964	0	0	0
T40	1308596	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2422	0	0
T1	2792248	5	0	0
T2	1250980	3	0	0
T3	448544	1	0	0
T4	1737160	1	0	0
T5	3346308	0	0	0
T6	1236052	13	0	0
T7	1570588	4	0	0
T8	11808	0	0	0
T9	60304	0	0	0
T10	10452	0	0	0
T15	0	10	0	0
T16	0	12	0	0
T17	0	9	0	0
T24	0	9	0	0
T25	0	16	0	0
T41	0	1	0	0
T42	0	5	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	119	0	0
T1	698062	1	0	0
T2	0	1	0	0
T16	480096	2	0	0
T17	133097	1	0	0
T20	460894	0	0	0
T25	168623	1	0	0
T26	0	1	0	0
T27	0	2	0	0
T29	0	1	0	0
T44	412168	0	0	0
T45	224446	0	0	0
T46	119848	2	0	0
T47	0	1	0	0
T48	0	3	0	0
T49	0	4	0	0
T50	0	4	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	3	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	293679	0	0	0
T60	6220	0	0	0
T61	109299	0	0	0
T62	856473	0	0	0
T63	104906	0	0	0
T64	598215	0	0	0
T65	288834	0	0	0
T66	371510	0	0	0
T67	27345	0	0	0
T68	312543	0	0	0
T69	313899	0	0	0
T70	75898	0	0	0
T71	4969	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1094	0	0
T1	698062	1	0	0
T2	312745	0	0	0
T3	112136	0	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	618026	2	0	0
T7	785294	1	0	0
T8	5904	0	0	0
T9	30152	0	0	0
T10	5226	0	0	0
T15	1331862	2	0	0
T16	480096	7	0	0
T17	133097	0	0	0
T24	789246	5	0	0
T25	168623	14	0	0
T26	0	1	0	0
T28	0	1	0	0
T41	2225	1	0	0
T42	328000	1	0	0
T43	62806	0	0	0
T44	412168	0	0	0
T46	0	1	0	0
T48	0	6	0	0
T50	0	1	0	0
T59	293679	0	0	0
T60	6220	0	0	0
T67	0	1	0	0
T69	0	5	0	0
T72	0	1	0	0
T73	0	5	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1236577546	0	0
T1	2792248	1205490	0	0
T2	1250980	16737	0	0
T3	448544	1219674	0	0
T4	1737160	895237	0	0
T5	3346308	2235920	0	0
T6	1236052	874955	0	0
T7	1570588	788965	0	0
T8	11808	7953	0	0
T9	60304	31949	0	0
T10	10452	6292	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2731	0	0
T1	2792248	6	0	0
T2	1250980	4	0	0
T3	448544	1	0	0
T4	1737160	1	0	0
T5	3346308	0	0	0
T6	1236052	19	0	0
T7	1570588	4	0	0
T8	11808	0	0	0
T9	60304	0	0	0
T10	10452	0	0	0
T15	0	11	0	0
T16	0	16	0	0
T17	0	10	0	0
T24	0	9	0	0
T25	0	16	0	0
T41	0	1	0	0
T42	0	5	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2683	0	0
T1	2792248	6	0	0
T2	1250980	4	0	0
T3	448544	1	0	0
T4	1737160	1	0	0
T5	3346308	0	0	0
T6	1236052	18	0	0
T7	1570588	4	0	0
T8	11808	0	0	0
T9	60304	0	0	0
T10	10452	0	0	0
T15	0	11	0	0
T16	0	16	0	0
T17	0	9	0	0
T24	0	9	0	0
T25	0	16	0	0
T41	0	1	0	0
T42	0	5	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2626	0	0
T1	2792248	6	0	0
T2	1250980	4	0	0
T3	448544	1	0	0
T4	1737160	1	0	0
T5	3346308	0	0	0
T6	1236052	18	0	0
T7	1570588	4	0	0
T8	11808	0	0	0
T9	60304	0	0	0
T10	10452	0	0	0
T15	0	10	0	0
T16	0	16	0	0
T17	0	9	0	0
T24	0	7	0	0
T25	0	15	0	0
T41	0	1	0	0
T42	0	5	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2563	0	0
T1	2792248	6	0	0
T2	1250980	4	0	0
T3	448544	1	0	0
T4	1737160	1	0	0
T5	3346308	0	0	0
T6	1236052	18	0	0
T7	1570588	4	0	0
T8	11808	0	0	0
T9	60304	0	0	0
T10	10452	0	0	0
T15	0	9	0	0
T16	0	16	0	0
T17	0	8	0	0
T24	0	6	0	0
T25	0	15	0	0
T41	0	1	0	0
T42	0	5	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3435	0	0
T1	698062	1	0	0
T2	312745	1	0	0
T3	112136	0	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	1236052	12	0	0
T7	1570588	3	0	0
T8	11808	2	0	0
T9	60304	0	0	0
T10	10452	1	0	0
T15	1997793	3	0	0
T16	0	26	0	0
T17	0	3	0	0
T24	1183869	0	0	0
T25	0	10	0	0
T26	0	2	0	0
T27	0	9	0	0
T41	6675	0	0	0
T42	492000	0	0	0
T43	94209	0	0	0
T45	0	2	0	0
T46	0	7	0	0
T60	0	1	0	0
T63	0	14	0	0
T67	0	3	0	0
T73	0	2	0	0
T77	0	13	0	0
T78	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	378140	0	0
T1	698062	2	0	0
T2	312745	1	0	0
T3	112136	0	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	1236052	2120	0	0
T7	1570588	435	0	0
T8	11808	410	0	0
T9	60304	0	0	0
T10	10452	44	0	0
T15	1997793	786	0	0
T16	0	4033	0	0
T17	0	264	0	0
T24	1183869	0	0	0
T25	0	384	0	0
T26	0	112	0	0
T27	0	1503	0	0
T41	6675	0	0	0
T42	492000	0	0	0
T43	94209	0	0	0
T45	0	353	0	0
T46	0	811	0	0
T60	0	182	0	0
T63	0	2490	0	0
T67	0	1662	0	0
T73	0	187	0	0
T77	0	1321	0	0
T78	0	69	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3078	0	0
T6	1236052	6	0	0
T7	1570588	3	0	0
T8	11808	2	0	0
T9	60304	0	0	0
T10	10452	1	0	0
T15	2663724	2	0	0
T16	0	22	0	0
T24	1578492	0	0	0
T25	0	9	0	0
T26	0	1	0	0
T27	0	15	0	0
T41	8900	0	0	0
T42	656000	0	0	0
T43	125612	0	0	0
T45	0	2	0	0
T46	0	5	0	0
T48	0	5	0	0
T60	0	1	0	0
T63	0	7	0	0
T73	0	7	0	0
T77	0	13	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	10	0	0
T81	0	1	0	0
T82	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	234	0	0
T6	927039	2	0	0
T7	1177941	0	0	0
T8	8856	0	0	0
T9	45228	0	0	0
T10	7839	0	0	0
T15	1997793	1	0	0
T16	480096	1	0	0
T24	1183869	0	0	0
T25	168623	0	0	0
T27	0	3	0	0
T29	0	3	0	0
T37	0	2	0	0
T39	0	3	0	0
T41	6675	0	0	0
T42	492000	0	0	0
T43	94209	0	0	0
T44	412168	0	0	0
T45	224446	0	0	0
T48	0	1	0	0
T51	0	3	0	0
T54	0	1	0	0
T59	293679	0	0	0
T60	6220	0	0	0
T61	109299	0	0	0
T62	856473	0	0	0
T63	104906	0	0	0
T67	0	1	0	0
T80	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	2	0	0
T92	75739	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6358	0	0
T11	152200	1398	0	0
T12	0	1421	0	0
T13	0	1406	0	0
T30	0	1448	0	0
T31	0	685	0	0
T32	1442960	0	0	0
T33	1097652	0	0	0
T34	26404	0	0	0
T35	56148	0	0	0
T36	2220332	0	0	0
T37	273804	0	0	0
T38	15100	0	0	0
T39	416964	0	0	0
T40	1308596	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5278	0	0
T11	152200	1158	0	0
T12	0	1181	0	0
T13	0	1166	0	0
T30	0	1208	0	0
T31	0	565	0	0
T32	1442960	0	0	0
T33	1097652	0	0	0
T34	26404	0	0	0
T35	56148	0	0	0
T36	2220332	0	0	0
T37	273804	0	0	0
T38	15100	0	0	0
T39	416964	0	0	0
T40	1308596	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2792248	2791464	0	0
T2	1250980	1250952	0	0
T3	448544	448508	0	0
T4	1737160	1737136	0	0
T5	3346308	3345996	0	0
T6	1236052	1235848	0	0
T7	1570588	1570548	0	0
T8	11808	11464	0	0
T9	60304	60100	0	0
T10	10452	10196	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2792248	2791464	0	0
T2	1250980	1250952	0	0
T3	448544	448508	0	0
T4	1737160	1737136	0	0
T5	3346308	3345996	0	0
T6	1236052	1235848	0	0
T7	1570588	1570548	0	0
T8	11808	11464	0	0
T9	60304	60100	0	0
T10	10452	10196	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T6,T7
1	0	1	Covered	T3,T4,T6
1	1	0	Covered	T6,T8,T15
1	1	1	Covered	T6,T7,T10

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T10
0	1	Covered	T6,T15,T80
1	0	Covered	T46,T48,T50

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T7,T10
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T46,T48,T50

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T10
1	0	Not Covered
1	1	Covered	T6,T15,T80

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T4,T6,T15

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T2,T6,T24

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T42,T25,T65

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T7,T16

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T15,T24,T42

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T15,T17,T16

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T4
Phase1St	198	Covered	T1,T2,T4
Phase2St	215	Covered	T1,T2,T4
Phase3St	233	Covered	T1,T2,T4
TerminalSt	249	Covered	T1,T2,T4
TimeoutSt	159	Covered	T6,T7,T10

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T4
IdleSt->TimeoutSt	159	Covered	T6,T7,T10
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T93,T94,T95
Phase0St->Phase1St	198	Covered	T1,T2,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T29,T90,T53
Phase1St->Phase2St	215	Covered	T1,T2,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T24,T96,T97
Phase2St->Phase3St	233	Covered	T1,T2,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T24,T73,T98
Phase3St->TerminalSt	249	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T6,T15
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T7,T10
TimeoutSt->Phase0St	172	Covered	T6,T15,T46

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T10
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T15,T46
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T10
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T10
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T93,T95
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T90,T53
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T24,T96,T97
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T73,T98
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T15,T24,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	693562445	332	0	0
CheckAccumTrig0_A	693562445	437	0	0
CheckAccumTrig1_A	693562445	17	0	0
CheckClr_A	693562445	146	0	0
CheckEn_A	693319436	326038986	0	0
CheckPhase0_A	693562445	497	0	0
CheckPhase1_A	693562445	490	0	0
CheckPhase2_A	693562445	486	0	0
CheckPhase3_A	693562445	477	0	0
CheckTimeout0_A	693562445	1119	0	0
CheckTimeoutSt1_A	693562445	118342	0	0
CheckTimeoutSt2_A	693562445	1054	0	0
CheckTimeoutStTrig_A	693562445	47	0	0
ErrorStAllEscAsserted_A	693562445	1641	0	0
ErrorStIsTerminal_A	693562445	1371	0	0
EscStateOut_A	693318275	693243033	0	0
u_state_regs_A	693562445	693372366	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	332	0	0
T11	38050	64	0	0
T12	0	69	0	0
T13	0	75	0	0
T30	0	79	0	0
T31	0	45	0	0
T32	360740	0	0	0
T33	274413	0	0	0
T34	6601	0	0	0
T35	14037	0	0	0
T36	555083	0	0	0
T37	68451	0	0	0
T38	3775	0	0	0
T39	104241	0	0	0
T40	327149	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	437	0	0
T1	698062	1	0	0
T2	312745	1	0	0
T3	112136	0	0	0
T4	434290	1	0	0
T5	836577	0	0	0
T6	309013	1	0	0
T7	392647	1	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T24	0	5	0	0
T42	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	17	0	0
T20	460894	0	0	0
T46	119848	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	0	3	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0
T64	598215	0	0	0
T65	288834	0	0	0
T66	371510	0	0	0
T67	27345	0	0	0
T68	312543	0	0	0
T69	313899	0	0	0
T70	75898	0	0	0
T71	4969	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	146	0	0
T15	665931	1	0	0
T16	480096	2	0	0
T17	133097	0	0	0
T24	394623	4	0	0
T25	168623	0	0	0
T28	0	1	0	0
T42	164000	0	0	0
T43	31403	0	0	0
T44	412168	0	0	0
T48	0	4	0	0
T50	0	1	0	0
T59	293679	0	0	0
T60	6220	0	0	0
T73	0	3	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693319436	326038986	0	0
T1	698062	378210	0	0
T2	312745	2337	0	0
T3	112136	994817	0	0
T4	434290	2752	0	0
T5	836577	560184	0	0
T6	309013	275353	0	0
T7	392647	2091	0	0
T8	2952	2865	0	0
T9	15076	7989	0	0
T10	2613	600	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	497	0	0
T1	698062	1	0	0
T2	312745	1	0	0
T3	112136	0	0	0
T4	434290	1	0	0
T5	836577	0	0	0
T6	309013	2	0	0
T7	392647	1	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	2	0	0
T16	0	2	0	0
T17	0	1	0	0
T24	0	5	0	0
T42	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	490	0	0
T1	698062	1	0	0
T2	312745	1	0	0
T3	112136	0	0	0
T4	434290	1	0	0
T5	836577	0	0	0
T6	309013	2	0	0
T7	392647	1	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	2	0	0
T16	0	2	0	0
T17	0	1	0	0
T24	0	5	0	0
T42	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	486	0	0
T1	698062	1	0	0
T2	312745	1	0	0
T3	112136	0	0	0
T4	434290	1	0	0
T5	836577	0	0	0
T6	309013	2	0	0
T7	392647	1	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	2	0	0
T16	0	2	0	0
T17	0	1	0	0
T24	0	4	0	0
T42	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	477	0	0
T1	698062	1	0	0
T2	312745	1	0	0
T3	112136	0	0	0
T4	434290	1	0	0
T5	836577	0	0	0
T6	309013	2	0	0
T7	392647	1	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	2	0	0
T16	0	2	0	0
T17	0	1	0	0
T24	0	3	0	0
T42	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	1119	0	0
T6	309013	2	0	0
T7	392647	3	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	1	0	0
T15	665931	1	0	0
T16	0	6	0	0
T24	394623	0	0	0
T26	0	1	0	0
T27	0	6	0	0
T41	2225	0	0	0
T42	164000	0	0	0
T43	31403	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T63	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	118342	0	0
T6	309013	341	0	0
T7	392647	435	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	44	0	0
T15	665931	133	0	0
T16	0	1114	0	0
T24	394623	0	0	0
T26	0	107	0	0
T27	0	923	0	0
T41	2225	0	0	0
T42	164000	0	0	0
T43	31403	0	0	0
T45	0	225	0	0
T46	0	35	0	0
T63	0	1233	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	1054	0	0
T6	309013	1	0	0
T7	392647	3	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	1	0	0
T15	665931	0	0	0
T16	0	6	0	0
T24	394623	0	0	0
T26	0	1	0	0
T27	0	6	0	0
T41	2225	0	0	0
T42	164000	0	0	0
T43	31403	0	0	0
T45	0	1	0	0
T63	0	6	0	0
T73	0	1	0	0
T80	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	47	0	0
T6	309013	1	0	0
T7	392647	0	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	665931	1	0	0
T24	394623	0	0	0
T37	0	2	0	0
T41	2225	0	0	0
T42	164000	0	0	0
T43	31403	0	0	0
T51	0	1	0	0
T54	0	1	0	0
T80	0	1	0	0
T84	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	1641	0	0
T11	38050	335	0	0
T12	0	366	0	0
T13	0	367	0	0
T30	0	371	0	0
T31	0	202	0	0
T32	360740	0	0	0
T33	274413	0	0	0
T34	6601	0	0	0
T35	14037	0	0	0
T36	555083	0	0	0
T37	68451	0	0	0
T38	3775	0	0	0
T39	104241	0	0	0
T40	327149	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	1371	0	0
T11	38050	275	0	0
T12	0	306	0	0
T13	0	307	0	0
T30	0	311	0	0
T31	0	172	0	0
T32	360740	0	0	0
T33	274413	0	0	0
T34	6601	0	0	0
T35	14037	0	0	0
T36	555083	0	0	0
T37	68451	0	0	0
T38	3775	0	0	0
T39	104241	0	0	0
T40	327149	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693318275	693243033	0	0
T1	698062	697866	0	0
T2	312745	312738	0	0
T3	112136	112127	0	0
T4	434290	434284	0	0
T5	836577	836499	0	0
T6	309013	308962	0	0
T7	392647	392637	0	0
T8	2952	2866	0	0
T9	15076	15025	0	0
T10	2613	2549	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	693372366	0	0
T1	698062	697866	0	0
T2	312745	312738	0	0
T3	112136	112127	0	0
T4	434290	434284	0	0
T5	836577	836499	0	0
T6	309013	308962	0	0
T7	392647	392637	0	0
T8	2952	2866	0	0
T9	15076	15025	0	0
T10	2613	2549	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T6,T7
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T2,T6,T10
1	1	1	Covered	T6,T17,T16

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T17,T16
0	1	Covered	T6,T17,T16
1	0	Covered	T6,T83,T39

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T17,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T83,T39

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T17,T16
1	0	Not Covered
1	1	Covered	T6,T17,T16

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T24

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T3,T16,T25

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T15

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T6,T7,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T6,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T6,T17,T16

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T6,T17,T16
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T21,T99,T100
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T6,T78,T28
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T24,T74,T101
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T15,T17,T54
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T6,T7
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T17,T16
TimeoutSt->Phase0St	172	Covered	T6,T17,T16

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T17,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T17,T16
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T17,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T16,T45
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T21,T100,T102
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T78,T28
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T24,T74,T101
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T15,T17,T54
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T7,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	693562445	308	0	0
CheckAccumTrig0_A	693562445	509	0	0
CheckAccumTrig1_A	693562445	21	0	0
CheckClr_A	693562445	237	0	0
CheckEn_A	693319436	317549645	0	0
CheckPhase0_A	693562445	591	0	0
CheckPhase1_A	693562445	581	0	0
CheckPhase2_A	693562445	569	0	0
CheckPhase3_A	693562445	554	0	0
CheckTimeout0_A	693562445	860	0	0
CheckTimeoutSt1_A	693562445	95000	0	0
CheckTimeoutSt2_A	693562445	764	0	0
CheckTimeoutStTrig_A	693562445	73	0	0
ErrorStAllEscAsserted_A	693562445	1516	0	0
ErrorStIsTerminal_A	693562445	1246	0	0
EscStateOut_A	693318275	693243033	0	0
u_state_regs_A	693562445	693372366	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	308	0	0
T11	38050	56	0	0
T12	0	68	0	0
T13	0	85	0	0
T30	0	53	0	0
T31	0	46	0	0
T32	360740	0	0	0
T33	274413	0	0	0
T34	6601	0	0	0
T35	14037	0	0	0
T36	555083	0	0	0
T37	68451	0	0	0
T38	3775	0	0	0
T39	104241	0	0	0
T40	327149	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	509	0	0
T1	698062	2	0	0
T2	312745	1	0	0
T3	112136	1	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	3	0	0
T7	392647	2	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	4	0	0
T16	0	2	0	0
T17	0	2	0	0
T24	0	2	0	0
T42	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	21	0	0
T6	309013	2	0	0
T7	392647	0	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	665931	0	0	0
T24	394623	0	0	0
T39	0	2	0	0
T41	2225	0	0	0
T42	164000	0	0	0
T43	31403	0	0	0
T56	0	1	0	0
T58	0	1	0	0
T83	0	1	0	0
T93	0	1	0	0
T98	0	1	0	0
T103	0	2	0	0
T104	0	1	0	0
T105	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	237	0	0
T6	309013	4	0	0
T7	392647	1	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	665931	2	0	0
T16	0	1	0	0
T17	0	1	0	0
T24	394623	1	0	0
T25	0	2	0	0
T41	2225	0	0	0
T42	164000	0	0	0
T43	31403	0	0	0
T45	0	1	0	0
T63	0	6	0	0
T67	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693319436	317549645	0	0
T1	698062	18286	0	0
T2	312745	9728	0	0
T3	112136	603	0	0
T4	434290	434284	0	0
T5	836577	2740	0	0
T6	309013	258819	0	0
T7	392647	2120	0	0
T8	2952	1625	0	0
T9	15076	11455	0	0
T10	2613	2548	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	591	0	0
T1	698062	2	0	0
T2	312745	1	0	0
T3	112136	1	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	7	0	0
T7	392647	2	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	4	0	0
T16	0	3	0	0
T17	0	3	0	0
T24	0	2	0	0
T42	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	581	0	0
T1	698062	2	0	0
T2	312745	1	0	0
T3	112136	1	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	6	0	0
T7	392647	2	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	4	0	0
T16	0	3	0	0
T17	0	3	0	0
T24	0	2	0	0
T42	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	569	0	0
T1	698062	2	0	0
T2	312745	1	0	0
T3	112136	1	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	6	0	0
T7	392647	2	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	4	0	0
T16	0	3	0	0
T17	0	3	0	0
T24	0	1	0	0
T42	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	554	0	0
T1	698062	2	0	0
T2	312745	1	0	0
T3	112136	1	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	6	0	0
T7	392647	2	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	3	0	0
T16	0	3	0	0
T17	0	2	0	0
T24	0	1	0	0
T42	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	860	0	0
T6	309013	6	0	0
T7	392647	0	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	665931	0	0	0
T16	0	3	0	0
T17	0	2	0	0
T24	394623	0	0	0
T41	2225	0	0	0
T42	164000	0	0	0
T43	31403	0	0	0
T45	0	1	0	0
T46	0	4	0	0
T63	0	7	0	0
T67	0	2	0	0
T73	0	1	0	0
T77	0	6	0	0
T78	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	95000	0	0
T6	309013	1141	0	0
T7	392647	0	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	665931	0	0	0
T16	0	350	0	0
T17	0	245	0	0
T24	394623	0	0	0
T41	2225	0	0	0
T42	164000	0	0	0
T43	31403	0	0	0
T45	0	128	0	0
T46	0	712	0	0
T63	0	994	0	0
T67	0	1000	0	0
T73	0	122	0	0
T77	0	592	0	0
T78	0	69	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	764	0	0
T6	309013	2	0	0
T7	392647	0	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	665931	0	0	0
T16	0	2	0	0
T24	394623	0	0	0
T41	2225	0	0	0
T42	164000	0	0	0
T43	31403	0	0	0
T45	0	1	0	0
T46	0	4	0	0
T48	0	2	0	0
T73	0	1	0	0
T77	0	6	0	0
T78	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	73	0	0
T6	309013	2	0	0
T7	392647	0	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	665931	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T24	394623	0	0	0
T28	0	1	0	0
T37	0	1	0	0
T41	2225	0	0	0
T42	164000	0	0	0
T43	31403	0	0	0
T48	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T63	0	7	0	0
T67	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	1516	0	0
T11	38050	332	0	0
T12	0	361	0	0
T13	0	350	0	0
T30	0	302	0	0
T31	0	171	0	0
T32	360740	0	0	0
T33	274413	0	0	0
T34	6601	0	0	0
T35	14037	0	0	0
T36	555083	0	0	0
T37	68451	0	0	0
T38	3775	0	0	0
T39	104241	0	0	0
T40	327149	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	1246	0	0
T11	38050	272	0	0
T12	0	301	0	0
T13	0	290	0	0
T30	0	242	0	0
T31	0	141	0	0
T32	360740	0	0	0
T33	274413	0	0	0
T34	6601	0	0	0
T35	14037	0	0	0
T36	555083	0	0	0
T37	68451	0	0	0
T38	3775	0	0	0
T39	104241	0	0	0
T40	327149	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693318275	693243033	0	0
T1	698062	697866	0	0
T2	312745	312738	0	0
T3	112136	112127	0	0
T4	434290	434284	0	0
T5	836577	836499	0	0
T6	309013	308962	0	0
T7	392647	392637	0	0
T8	2952	2866	0	0
T9	15076	15025	0	0
T10	2613	2549	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	693372366	0	0
T1	698062	697866	0	0
T2	312745	312738	0	0
T3	112136	112127	0	0
T4	434290	434284	0	0
T5	836577	836499	0	0
T6	309013	308962	0	0
T7	392647	392637	0	0
T8	2952	2866	0	0
T9	15076	15025	0	0
T10	2613	2549	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T6,T15

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T6
1	0	1	Covered	T4,T9,T15
1	1	0	Covered	T6,T7,T10
1	1	1	Covered	T1,T2,T6

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T6,T27,T39
1	0	Covered	T1,T2,T26

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T26

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T19
1	1	Covered	T6,T27,T39

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T15
1	Covered	T1,T2,T6

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T45,T65

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T6,T15,T46

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T42,T43,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T6,T43

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T15,T44

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T6
Phase1St	198	Covered	T1,T2,T6
Phase2St	215	Covered	T1,T2,T6
Phase3St	233	Covered	T1,T2,T6
TerminalSt	249	Covered	T1,T2,T6
TimeoutSt	159	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T6,T15
IdleSt->TimeoutSt	159	Covered	T1,T2,T6
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T17,T28,T106
Phase0St->Phase1St	198	Covered	T1,T2,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T107,T108,T109
Phase1St->Phase2St	215	Covered	T1,T2,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T25,T51,T99
Phase2St->Phase3St	233	Covered	T1,T2,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T110,T111,T112
Phase3St->TerminalSt	249	Covered	T1,T2,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T6,T15
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T8,T15
TimeoutSt->Phase0St	172	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T106,T113
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T107,T108,T109
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T25,T51,T103
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T110,T111,T112
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T6,T25
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	693562445	340	0	0
CheckAccumTrig0_A	693562445	534	0	0
CheckAccumTrig1_A	693562445	23	0	0
CheckClr_A	693562445	235	0	0
CheckEn_A	693319436	331598952	0	0
CheckPhase0_A	693562445	603	0	0
CheckPhase1_A	693562445	597	0	0
CheckPhase2_A	693562445	579	0	0
CheckPhase3_A	693562445	570	0	0
CheckTimeout0_A	693562445	609	0	0
CheckTimeoutSt1_A	693562445	73352	0	0
CheckTimeoutSt2_A	693562445	532	0	0
CheckTimeoutStTrig_A	693562445	53	0	0
ErrorStAllEscAsserted_A	693562445	1628	0	0
ErrorStIsTerminal_A	693562445	1358	0	0
EscStateOut_A	693318275	693243033	0	0
u_state_regs_A	693562445	693372366	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	340	0	0
T11	38050	87	0	0
T12	0	77	0	0
T13	0	64	0	0
T30	0	84	0	0
T31	0	28	0	0
T32	360740	0	0	0
T33	274413	0	0	0
T34	6601	0	0	0
T35	14037	0	0	0
T36	555083	0	0	0
T37	68451	0	0	0
T38	3775	0	0	0
T39	104241	0	0	0
T40	327149	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	534	0	0
T1	698062	1	0	0
T2	312745	0	0	0
T3	112136	0	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	3	0	0
T7	392647	0	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	0	2	0	0
T25	0	16	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	23	0	0
T1	698062	1	0	0
T2	312745	1	0	0
T3	112136	0	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	0	0	0
T7	392647	0	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T26	0	1	0	0
T28	0	1	0	0
T48	0	1	0	0
T50	0	3	0	0
T82	0	1	0	0
T103	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	235	0	0
T1	698062	1	0	0
T2	312745	0	0	0
T3	112136	0	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	1	0	0
T7	392647	0	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T25	0	13	0	0
T26	0	1	0	0
T48	0	2	0	0
T67	0	1	0	0
T69	0	5	0	0
T73	0	2	0	0
T115	0	1	0	0
T116	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693319436	331598952	0	0
T1	698062	391279	0	0
T2	312745	2347	0	0
T3	112136	112127	0	0
T4	434290	23917	0	0
T5	836577	836498	0	0
T6	309013	235788	0	0
T7	392647	392637	0	0
T8	2952	598	0	0
T9	15076	6270	0	0
T10	2613	2548	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	603	0	0
T1	698062	2	0	0
T2	312745	1	0	0
T3	112136	0	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	4	0	0
T7	392647	0	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	0	1	0	0
T25	0	16	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	597	0	0
T1	698062	2	0	0
T2	312745	1	0	0
T3	112136	0	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	4	0	0
T7	392647	0	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	0	1	0	0
T25	0	16	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	579	0	0
T1	698062	2	0	0
T2	312745	1	0	0
T3	112136	0	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	4	0	0
T7	392647	0	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	0	1	0	0
T25	0	15	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	570	0	0
T1	698062	2	0	0
T2	312745	1	0	0
T3	112136	0	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	4	0	0
T7	392647	0	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	0	1	0	0
T25	0	15	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	609	0	0
T1	698062	1	0	0
T2	312745	1	0	0
T3	112136	0	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	2	0	0
T7	392647	0	0	0
T8	2952	2	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	1	0	0
T16	0	13	0	0
T26	0	1	0	0
T27	0	3	0	0
T73	0	1	0	0
T77	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	73352	0	0
T1	698062	2	0	0
T2	312745	1	0	0
T3	112136	0	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	121	0	0
T7	392647	0	0	0
T8	2952	410	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	330	0	0
T16	0	2240	0	0
T26	0	5	0	0
T27	0	580	0	0
T73	0	65	0	0
T77	0	112	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	532	0	0
T6	309013	1	0	0
T7	392647	0	0	0
T8	2952	2	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	665931	1	0	0
T16	0	13	0	0
T24	394623	0	0	0
T27	0	1	0	0
T41	2225	0	0	0
T42	164000	0	0	0
T43	31403	0	0	0
T48	0	3	0	0
T73	0	1	0	0
T77	0	1	0	0
T79	0	1	0	0
T80	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	53	0	0
T6	309013	1	0	0
T7	392647	0	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	665931	0	0	0
T24	394623	0	0	0
T27	0	2	0	0
T29	0	1	0	0
T39	0	1	0	0
T41	2225	0	0	0
T42	164000	0	0	0
T43	31403	0	0	0
T51	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T91	0	1	0	0
T117	0	1	0	0
T118	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	1628	0	0
T11	38050	378	0	0
T12	0	357	0	0
T13	0	345	0	0
T30	0	391	0	0
T31	0	157	0	0
T32	360740	0	0	0
T33	274413	0	0	0
T34	6601	0	0	0
T35	14037	0	0	0
T36	555083	0	0	0
T37	68451	0	0	0
T38	3775	0	0	0
T39	104241	0	0	0
T40	327149	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	1358	0	0
T11	38050	318	0	0
T12	0	297	0	0
T13	0	285	0	0
T30	0	331	0	0
T31	0	127	0	0
T32	360740	0	0	0
T33	274413	0	0	0
T34	6601	0	0	0
T35	14037	0	0	0
T36	555083	0	0	0
T37	68451	0	0	0
T38	3775	0	0	0
T39	104241	0	0	0
T40	327149	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693318275	693243033	0	0
T1	698062	697866	0	0
T2	312745	312738	0	0
T3	112136	112127	0	0
T4	434290	434284	0	0
T5	836577	836499	0	0
T6	309013	308962	0	0
T7	392647	392637	0	0
T8	2952	2866	0	0
T9	15076	15025	0	0
T10	2613	2549	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	693372366	0	0
T1	698062	697866	0	0
T2	312745	312738	0	0
T3	112136	112127	0	0
T4	434290	434284	0	0
T5	836577	836499	0	0
T6	309013	308962	0	0
T7	392647	392637	0	0
T8	2952	2866	0	0
T9	15076	15025	0	0
T10	2613	2549	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T14
1	1	1	Covered	T1,T2,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T6
1	0	1	Covered	T6,T9,T15
1	1	0	Covered	T1,T6,T7
1	1	1	Covered	T6,T15,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T15,T17
0	1	Covered	T16,T67,T27
1	0	Covered	T17,T16,T25

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T15,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T16,T25

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T15,T17
1	0	Covered	T18
1	1	Covered	T16,T67,T27

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T6,T41,T15

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T1,T6,T15

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T41
1	Covered	T2,T6,T7

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T6,T24,T16

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T6,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T6,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T6,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T6,T41,T15

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T6
Phase1St	198	Covered	T1,T2,T6
Phase2St	215	Covered	T1,T2,T6
Phase3St	233	Covered	T1,T2,T6
TerminalSt	249	Covered	T1,T2,T6
TimeoutSt	159	Covered	T6,T15,T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T6
IdleSt->TimeoutSt	159	Covered	T6,T15,T17
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T20,T119,T120
Phase0St->Phase1St	198	Covered	T1,T2,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T17,T22,T23
Phase1St->Phase2St	215	Covered	T1,T2,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T15,T121,T122
Phase2St->Phase3St	233	Covered	T1,T2,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T26,T27,T73
Phase3St->TerminalSt	249	Covered	T1,T2,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T6,T7
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T15,T16
TimeoutSt->Phase0St	172	Covered	T17,T16,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T15,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T16,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T15,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T15,T16
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T20,T119,T120
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T22,T23,T123
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T15,T121,T122
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T27,T73
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T7,T41
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	693562445	307	0	0
CheckAccumTrig0_A	693562445	942	0	0
CheckAccumTrig1_A	693562445	58	0	0
CheckClr_A	693562445	476	0	0
CheckEn_A	693319436	261389963	0	0
CheckPhase0_A	693562445	1040	0	0
CheckPhase1_A	693562445	1015	0	0
CheckPhase2_A	693562445	992	0	0
CheckPhase3_A	693562445	962	0	0
CheckTimeout0_A	693562445	847	0	0
CheckTimeoutSt1_A	693562445	91446	0	0
CheckTimeoutSt2_A	693562445	728	0	0
CheckTimeoutStTrig_A	693562445	61	0	0
ErrorStAllEscAsserted_A	693562445	1573	0	0
ErrorStIsTerminal_A	693562445	1303	0	0
EscStateOut_A	693318275	693243033	0	0
u_state_regs_A	693562445	693372366	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	307	0	0
T11	38050	80	0	0
T12	0	45	0	0
T13	0	90	0	0
T30	0	51	0	0
T31	0	41	0	0
T32	360740	0	0	0
T33	274413	0	0	0
T34	6601	0	0	0
T35	14037	0	0	0
T36	555083	0	0	0
T37	68451	0	0	0
T38	3775	0	0	0
T39	104241	0	0	0
T40	327149	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	942	0	0
T1	698062	1	0	0
T2	312745	1	0	0
T3	112136	0	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	6	0	0
T7	392647	1	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	3	0	0
T16	0	7	0	0
T17	0	4	0	0
T24	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	58	0	0
T16	480096	2	0	0
T17	133097	1	0	0
T25	168623	1	0	0
T27	0	2	0	0
T29	0	1	0	0
T44	412168	0	0	0
T45	224446	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	4	0	0
T51	0	1	0	0
T59	293679	0	0	0
T60	6220	0	0	0
T61	109299	0	0	0
T62	856473	0	0	0
T63	104906	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	476	0	0
T6	309013	1	0	0
T7	392647	1	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	665931	1	0	0
T16	0	5	0	0
T24	394623	1	0	0
T25	0	1	0	0
T41	2225	1	0	0
T42	164000	1	0	0
T43	31403	0	0	0
T46	0	1	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693319436	261389963	0	0
T1	698062	417715	0	0
T2	312745	2325	0	0
T3	112136	112127	0	0
T4	434290	434284	0	0
T5	836577	836498	0	0
T6	309013	104995	0	0
T7	392647	392117	0	0
T8	2952	2865	0	0
T9	15076	6235	0	0
T10	2613	596	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	1040	0	0
T1	698062	1	0	0
T2	312745	1	0	0
T3	112136	0	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	6	0	0
T7	392647	1	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	3	0	0
T16	0	10	0	0
T17	0	5	0	0
T24	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	1015	0	0
T1	698062	1	0	0
T2	312745	1	0	0
T3	112136	0	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	6	0	0
T7	392647	1	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	3	0	0
T16	0	10	0	0
T17	0	4	0	0
T24	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	992	0	0
T1	698062	1	0	0
T2	312745	1	0	0
T3	112136	0	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	6	0	0
T7	392647	1	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	2	0	0
T16	0	10	0	0
T17	0	4	0	0
T24	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	962	0	0
T1	698062	1	0	0
T2	312745	1	0	0
T3	112136	0	0	0
T4	434290	0	0	0
T5	836577	0	0	0
T6	309013	6	0	0
T7	392647	1	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	0	2	0	0
T16	0	10	0	0
T17	0	4	0	0
T24	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	847	0	0
T6	309013	2	0	0
T7	392647	0	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	665931	1	0	0
T16	0	4	0	0
T17	0	1	0	0
T24	394623	0	0	0
T25	0	10	0	0
T41	2225	0	0	0
T42	164000	0	0	0
T43	31403	0	0	0
T46	0	2	0	0
T60	0	1	0	0
T63	0	1	0	0
T67	0	1	0	0
T77	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	91446	0	0
T6	309013	517	0	0
T7	392647	0	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	665931	323	0	0
T16	0	329	0	0
T17	0	19	0	0
T24	394623	0	0	0
T25	0	384	0	0
T41	2225	0	0	0
T42	164000	0	0	0
T43	31403	0	0	0
T46	0	64	0	0
T60	0	182	0	0
T63	0	263	0	0
T67	0	662	0	0
T77	0	617	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	728	0	0
T6	309013	2	0	0
T7	392647	0	0	0
T8	2952	0	0	0
T9	15076	0	0	0
T10	2613	0	0	0
T15	665931	1	0	0
T16	0	1	0	0
T24	394623	0	0	0
T25	0	9	0	0
T27	0	8	0	0
T41	2225	0	0	0
T42	164000	0	0	0
T43	31403	0	0	0
T46	0	1	0	0
T60	0	1	0	0
T63	0	1	0	0
T73	0	4	0	0
T77	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	61	0	0
T16	480096	1	0	0
T25	168623	0	0	0
T27	0	1	0	0
T29	0	2	0	0
T39	0	2	0	0
T44	412168	0	0	0
T45	224446	0	0	0
T48	0	1	0	0
T51	0	1	0	0
T59	293679	0	0	0
T60	6220	0	0	0
T61	109299	0	0	0
T62	856473	0	0	0
T63	104906	0	0	0
T67	0	1	0	0
T83	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T92	75739	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	1573	0	0
T11	38050	353	0	0
T12	0	337	0	0
T13	0	344	0	0
T30	0	384	0	0
T31	0	155	0	0
T32	360740	0	0	0
T33	274413	0	0	0
T34	6601	0	0	0
T35	14037	0	0	0
T36	555083	0	0	0
T37	68451	0	0	0
T38	3775	0	0	0
T39	104241	0	0	0
T40	327149	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	1303	0	0
T11	38050	293	0	0
T12	0	277	0	0
T13	0	284	0	0
T30	0	324	0	0
T31	0	125	0	0
T32	360740	0	0	0
T33	274413	0	0	0
T34	6601	0	0	0
T35	14037	0	0	0
T36	555083	0	0	0
T37	68451	0	0	0
T38	3775	0	0	0
T39	104241	0	0	0
T40	327149	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693318275	693243033	0	0
T1	698062	697866	0	0
T2	312745	312738	0	0
T3	112136	112127	0	0
T4	434290	434284	0	0
T5	836577	836499	0	0
T6	309013	308962	0	0
T7	392647	392637	0	0
T8	2952	2866	0	0
T9	15076	15025	0	0
T10	2613	2549	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693562445	693372366	0	0
T1	698062	697866	0	0
T2	312745	312738	0	0
T3	112136	112127	0	0
T4	434290	434284	0	0
T5	836577	836499	0	0
T6	309013	308962	0	0
T7	392647	392637	0	0
T8	2952	2866	0	0
T9	15076	15025	0	0
T10	2613	2549	0	0