Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	67620	1			T2	116		T14	10		T15	846
class_i[0x1]	57782	1			T6	1		T14	7		T15	11
class_i[0x2]	59683	1			T44	579		T14	5		T15	1010
class_i[0x3]	65937	1			T4	4		T14	4443		T16	1

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	63119	1			T2	13		T4	1		T6	1
alert[0x1]	60766	1			T2	31		T4	2		T44	9
alert[0x2]	62195	1			T2	34		T44	569		T14	1141
alert[0x3]	64942	1			T2	38		T4	1		T44	1

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

250748

1

T2

116

T4

4

T44

579

esc_ping_fail

274

1

T6

1

T9

6

T10

5

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	63038	1			T2	13		T4	1		T14	1129
esc_integrity_fail	alert[0x1]	60694	1			T2	31		T4	2		T44	9
esc_integrity_fail	alert[0x2]	62126	1			T2	34		T44	569		T14	1141
esc_integrity_fail	alert[0x3]	64890	1			T2	38		T4	1		T44	1
esc_ping_fail	alert[0x0]	81	1			T6	1		T9	3		T10	1
esc_ping_fail	alert[0x1]	72	1			T9	2		T10	2		T287	2
esc_ping_fail	alert[0x2]	69	1			T9	1		T10	1		T277	1
esc_ping_fail	alert[0x3]	52	1			T10	1		T287	1		T277	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	67548	1			T2	116		T14	10		T15	846
esc_integrity_fail	class_i[0x1]	57720	1			T14	7		T15	11		T29	484
esc_integrity_fail	class_i[0x2]	59586	1			T44	579		T14	5		T15	1010
esc_integrity_fail	class_i[0x3]	65894	1			T4	4		T14	4443		T16	1
esc_ping_fail	class_i[0x0]	72	1			T9	5		T10	5		T287	3
esc_ping_fail	class_i[0x1]	62	1			T6	1		T288	1		T289	6
esc_ping_fail	class_i[0x2]	97	1			T277	4		T288	1		T38	1
esc_ping_fail	class_i[0x3]	43	1			T9	1		T287	1		T289	1