Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	673875608	0	0	624
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	673875608	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	673875608	673700503	0	0
tb.dut.CheckAccuCntDw	0	0	624	624	0	0
tb.dut.CheckEscCntDw	0	0	624	624	0	0
tb.dut.CheckNAlerts	0	0	624	624	0	0
tb.dut.CheckNClasses	0	0	624	624	0	0
tb.dut.CheckNEscSev	0	0	624	624	0	0
tb.dut.CrashdumpKnownO_A	0	0	673875608	673700503	0	0
tb.dut.EdnKnownO_A	0	0	673875608	673700503	0	0
tb.dut.EscPKnownO_A	0	0	673875608	673700503	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	673875608	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	673875608	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	673875608	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	673875608	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	673875608	80	0	0
tb.dut.IrqAKnownO_A	0	0	673875608	673700503	0	0
tb.dut.IrqBKnownO_A	0	0	673875608	673700503	0	0
tb.dut.IrqCKnownO_A	0	0	673875608	673700503	0	0
tb.dut.IrqDKnownO_A	0	0	673875608	673700503	0	0
tb.dut.TlAReadyKnownO_A	0	0	673875608	673700503	0	0
tb.dut.TlDValidKnownO_A	0	0	673875608	673700503	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	698973289	2635742	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	698973289	14908	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	698973289	14997	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	698973289	14592	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	698973289	14868	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	698973289	14711	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	698973289	15449	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	698973289	14930	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	698973289	14724	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	698973289	14816	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	698973289	14726	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	698973289	14943	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	698973289	14960	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	698973289	14685	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	698973289	14951	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	698973289	14570	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	698973289	15046	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	698973289	14878	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	698973289	14685	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	698973289	14669	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	698973289	14951	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	698973289	15144	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	698973289	14980	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	698973289	15145	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	698973289	14949	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	698973289	14735	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	698973289	15059	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	698973289	14684	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	698973289	14977	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	698973289	14766	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	698973289	14690	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	698973289	14798	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	698973289	14754	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	698973289	14960	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	698973289	14749	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	698973289	15014	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	698973289	14839	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	698973289	14839	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	698973289	14782	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	698973289	15103	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	698973289	14574	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	698973289	14965	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	698973289	14996	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	698973289	15136	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	698973289	14723	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	698973289	14732	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	698973289	15041	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	698973289	14767	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	698973289	15069	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	698973289	14781	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	698973289	14595	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	698973289	15006	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	698973289	14943	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	698973289	15144	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	698973289	14891	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	698973289	14958	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	698973289	14765	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	698973289	15169	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	698973289	14709	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	698973289	14849	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	698973289	14859	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	698973289	14652	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	698973289	15195	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	698973289	15068	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	698973289	14786	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	698973289	14983	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	698973289	15021	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	698973289	15150	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	698973289	14849	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	698973289	14981	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	698973289	28579	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	698973289	15234	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	698973289	14468	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	698973289	15004	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	698973289	14929	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	698973289	14943	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	698973289	14835	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	698973289	14722	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	698973289	14961	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	673875608	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	673875608	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	673875608	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	673875608	1436	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	673875608	236695	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	673875608	356028287	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	673875608	342	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	673875608	915	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	673875608	43	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	673875608	464	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	673714800	281224340	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	673875608	996	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	673875608	973	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	673875608	942	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	673875608	916	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	673875608	2008	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	673875608	196594	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	673875608	1905	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	673875608	56	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	673875608	1427	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	673875608	1187	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	673713549	673641466	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	673875608	673700503	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	673875608	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	673875608	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	673875608	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	673875608	3910	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	673875608	179518	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	673875608	385705823	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	673875608	249	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	673875608	519	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	673875608	20	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	673875608	231	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	673714800	317000452	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	673875608	587	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	673875608	569	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	673875608	559	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	673875608	552	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	673875608	1355	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	673875608	171401	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	673875608	1272	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	673875608	61	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	673875608	1396	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	673875608	1156	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	673713549	673641466	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	673875608	673700503	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	673875608	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	673875608	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	673875608	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	673875608	3614	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	673875608	190347	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	673875608	352533285	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	673875608	315	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	673875608	585	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	673875608	25	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	673875608	292	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	673714800	276315051	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	673875608	657	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	673875608	642	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	673875608	632	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	673875608	624	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	673875608	1830	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	673875608	206180	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	673875608	1748	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	673875608	56	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	673875608	1461	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	673875608	1221	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	673713549	673641466	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	673875608	673700503	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	673875608	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	673875608	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	673875608	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	673875608	6845	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	673875608	175010	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	673875608	396133070	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	673875608	252	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	673875608	520	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	673875608	19	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	673875608	226	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	673714800	311549821	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	673875608	586	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	673875608	572	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	673875608	554	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	673875608	545	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	673875608	2206	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	673875608	236189	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	673875608	2128	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	673875608	55	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	673875608	1408	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	673875608	1168	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	673713549	673641466	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	673875608	673700503	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	698973289	132338387	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	698973289	698307802	0	0
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