Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	1	43	97.73

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	1	43	97.73	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	207	1			T1	1		T18	1		T14	1
index[0x1]	173	1			T2	1		T21	1		T47	1
index[0x2]	202	1			T1	1		T4	1		T47	1
index[0x3]	189	1			T4	2		T44	1		T14	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	291	1			T1	2		T4	2		T47	1
lens_less_than_1000[1]	164	1			T18	1		T21	1		T14	1
lens_less_than_1000[2]	79	1			T2	1		T16	2		T17	1
lens_less_than_1000[3]	63	1			T4	1		T8	1		T17	1
lens_less_than_1000[4]	59	1			T15	2		T69	2		T32	1
lens_less_than_1000[5]	38	1			T44	1		T29	1		T74	2
lens_less_than_1000[6]	32	1			T7	1		T15	1		T65	1
lens_less_than_1000[7]	18	1			T72	1		T259	1		T57	1
lens_less_than_1000[8]	13	1			T14	1		T15	1		T32	1
lens_less_than_1000[9]	5	1			T47	1		T28	1		T260	1
len_2	9	1			T57	1		T235	1		T104	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	1	43	97.73	1

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x1]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	84	1			T1	1		T47	1		T15	1
index[0x0]	lens_less_than_1000[1]	43	1			T18	1		T48	2		T29	1
index[0x0]	lens_less_than_1000[2]	22	1			T17	1		T26	1		T31	1
index[0x0]	lens_less_than_1000[3]	16	1			T17	1		T49	1		T82	1
index[0x0]	lens_less_than_1000[4]	13	1			T95	1		T240	1		T104	1
index[0x0]	lens_less_than_1000[5]	10	1			T74	1		T50	1		T35	1
index[0x0]	lens_less_than_1000[6]	9	1			T261	1		T262	1		T263	1
index[0x0]	lens_less_than_1000[7]	5	1			T259	1		T57	1		T118	1
index[0x0]	lens_less_than_1000[8]	2	1			T14	1		T264	1		-	-
index[0x0]	lens_less_than_1000[9]	2	1			T47	1		T260	1		-	-
index[0x0]	len_2	1	1			T265	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	55	1			T29	2		T27	2		T114	1
index[0x1]	lens_less_than_1000[1]	43	1			T21	1		T47	1		T15	1
index[0x1]	lens_less_than_1000[2]	17	1			T2	1		T49	1		T95	1
index[0x1]	lens_less_than_1000[3]	12	1			T54	1		T212	1		T266	1
index[0x1]	lens_less_than_1000[4]	20	1			T15	2		T69	1		T57	2
index[0x1]	lens_less_than_1000[5]	7	1			T29	1		T267	1		T234	1
index[0x1]	lens_less_than_1000[6]	5	1			T57	2		T107	1		T268	1
index[0x1]	lens_less_than_1000[7]	6	1			T269	1		T105	1		T63	1
index[0x1]	lens_less_than_1000[8]	5	1			T15	1		T86	2		T105	1
index[0x1]	len_2	3	1			T270	1		T257	1		T271	1
index[0x2]	lens_less_than_1000[0]	92	1			T1	1		T4	1		T15	1
index[0x2]	lens_less_than_1000[1]	30	1			T47	1		T27	1		T28	1
index[0x2]	lens_less_than_1000[2]	20	1			T16	2		T29	1		T31	1
index[0x2]	lens_less_than_1000[3]	19	1			T8	1		T42	1		T102	1
index[0x2]	lens_less_than_1000[4]	17	1			T32	1		T221	1		T240	1
index[0x2]	lens_less_than_1000[5]	12	1			T74	1		T272	1		T273	1
index[0x2]	lens_less_than_1000[6]	5	1			T65	1		T87	1		T249	1
index[0x2]	lens_less_than_1000[7]	1	1			T274	1		-	-		-	-
index[0x2]	lens_less_than_1000[8]	1	1			T32	1		-	-		-	-
index[0x2]	lens_less_than_1000[9]	2	1			T28	1		T97	1		-	-
index[0x2]	len_2	3	1			T235	1		T104	1		T275	1
index[0x3]	lens_less_than_1000[0]	60	1			T4	1		T15	1		T17	1
index[0x3]	lens_less_than_1000[1]	48	1			T14	1		T47	1		T26	1
index[0x3]	lens_less_than_1000[2]	20	1			T219	1		T276	1		T277	1
index[0x3]	lens_less_than_1000[3]	16	1			T4	1		T278	1		T279	1
index[0x3]	lens_less_than_1000[4]	9	1			T69	1		T28	1		T95	1
index[0x3]	lens_less_than_1000[5]	9	1			T44	1		T28	1		T280	1
index[0x3]	lens_less_than_1000[6]	13	1			T7	1		T15	1		T17	1
index[0x3]	lens_less_than_1000[7]	6	1			T72	1		T87	1		T281	1
index[0x3]	lens_less_than_1000[8]	5	1			T90	1		T104	1		T268	1
index[0x3]	lens_less_than_1000[9]	1	1			T92	1		-	-		-	-
index[0x3]	len_2	2	1			T57	1		T281	1		-	-