Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	56	1			T15	2		T16	1		T29	2
class_index[0x1]	61	1			T4	1		T26	1		T72	1
class_index[0x2]	56	1			T20	1		T15	2		T29	1
class_index[0x3]	55	1			T4	1		T21	1		T26	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	82	1			T4	2		T20	1		T16	1
intr_timeout_cnt[1]	44	1			T21	1		T15	1		T26	1
intr_timeout_cnt[2]	25	1			T15	1		T29	1		T72	1
intr_timeout_cnt[3]	14	1			T15	1		T29	1		T79	1
intr_timeout_cnt[4]	8	1			T26	1		T90	1		T58	1
intr_timeout_cnt[5]	13	1			T53	2		T83	1		T84	1
intr_timeout_cnt[6]	17	1			T15	1		T49	1		T54	1
intr_timeout_cnt[7]	12	1			T83	1		T58	1		T234	2
intr_timeout_cnt[8]	9	1			T79	1		T51	1		T239	1
intr_timeout_cnt[9]	4	1			T49	1		T53	1		T240	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[4]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[4]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	25	1			T16	1		T29	1		T72	1
class_index[0x0]	intr_timeout_cnt[1]	11	1			T15	1		T26	1		T104	1
class_index[0x0]	intr_timeout_cnt[2]	3	1			T118	1		T241	1		T188	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T29	1		T86	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	3	1			T53	1		T242	1		T243	1
class_index[0x0]	intr_timeout_cnt[6]	4	1			T15	1		T85	1		T244	1
class_index[0x0]	intr_timeout_cnt[7]	6	1			T83	1		T234	2		T245	1
class_index[0x0]	intr_timeout_cnt[8]	1	1			T25	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T240	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	17	1			T4	1		T72	1		T57	1
class_index[0x1]	intr_timeout_cnt[1]	8	1			T28	1		T82	1		T246	1
class_index[0x1]	intr_timeout_cnt[2]	8	1			T35	2		T83	1		T118	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T58	1		T241	1		T247	1
class_index[0x1]	intr_timeout_cnt[4]	6	1			T26	1		T90	1		T242	4
class_index[0x1]	intr_timeout_cnt[5]	4	1			T53	1		T84	1		T183	1
class_index[0x1]	intr_timeout_cnt[6]	6	1			T49	1		T25	4		T248	1
class_index[0x1]	intr_timeout_cnt[7]	2	1			T249	1		T250	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	5	1			T51	1		T239	1		T251	2
class_index[0x1]	intr_timeout_cnt[9]	1	1			T86	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	16	1			T20	1		T78	1		T106	1
class_index[0x2]	intr_timeout_cnt[1]	10	1			T58	1		T252	1		T253	1
class_index[0x2]	intr_timeout_cnt[2]	11	1			T15	1		T29	1		T72	1
class_index[0x2]	intr_timeout_cnt[3]	7	1			T15	1		T53	1		T84	1
class_index[0x2]	intr_timeout_cnt[4]	2	1			T58	1		T254	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	1	1			T83	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	5	1			T83	1		T239	1		T58	1
class_index[0x2]	intr_timeout_cnt[7]	2	1			T255	2		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T79	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T49	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	24	1			T4	1		T26	1		T32	2
class_index[0x3]	intr_timeout_cnt[1]	15	1			T21	1		T80	1		T112	1
class_index[0x3]	intr_timeout_cnt[2]	3	1			T245	1		T242	1		T24	1
class_index[0x3]	intr_timeout_cnt[3]	1	1			T79	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	5	1			T256	1		T250	4		-	-
class_index[0x3]	intr_timeout_cnt[6]	2	1			T54	1		T257	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T58	1		T258	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	2	1			T242	2		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T53	1		-	-		-	-