Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	368274	1			T1	1895		T2	455		T3	15
all_values[1]	368274	1			T1	1895		T2	455		T3	15
all_values[2]	368274	1			T1	1895		T2	455		T3	15
all_values[3]	368274	1			T1	1895		T2	455		T3	15

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

733452

1

T1

3788

T2

898

T3

41

auto[1]

739644

1

T1

3792

T2

922

T3

19

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

871586

1

T1

5553

T2

918

T3

53

auto[1]

601510

1

T1

2027

T2

902

T3

7

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	104658	1			T1	740		T2	114		T3	6
all_values[0]	auto[0]	auto[1]	78438	1			T1	230		T2	115		T3	5
all_values[0]	auto[1]	auto[0]	106391	1			T1	680		T2	113		T3	2
all_values[0]	auto[1]	auto[1]	78787	1			T1	245		T2	113		T3	2
all_values[1]	auto[0]	auto[0]	108916	1			T1	956		T2	117		T3	6
all_values[1]	auto[0]	auto[1]	73915	1			T1	1		T2	104		T18	17
all_values[1]	auto[1]	auto[0]	110929	1			T1	937		T2	116		T3	9
all_values[1]	auto[1]	auto[1]	74514	1			T1	1		T2	118		T18	20
all_values[2]	auto[0]	auto[0]	109807	1			T1	526		T2	118		T3	9
all_values[2]	auto[0]	auto[1]	74172	1			T1	414		T2	117		T18	22
all_values[2]	auto[1]	auto[0]	110285	1			T1	522		T2	108		T3	6
all_values[2]	auto[1]	auto[1]	74010	1			T1	433		T2	112		T18	15
all_values[3]	auto[0]	auto[0]	109778	1			T1	563		T2	107		T3	15
all_values[3]	auto[0]	auto[1]	73768	1			T1	358		T2	106		T18	21
all_values[3]	auto[1]	auto[0]	110822	1			T1	629		T2	125		T5	16
all_values[3]	auto[1]	auto[1]	73906	1			T1	345		T2	117		T18	15