Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	368274	1			T1	1895		T2	455		T3	15
all_pins[1]	368274	1			T1	1895		T2	455		T3	15
all_pins[2]	368274	1			T1	1895		T2	455		T3	15
all_pins[3]	368274	1			T1	1895		T2	455		T3	15

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1171879	1			T1	6556		T2	1360		T3	58
values[0x1]	301217	1			T1	1024		T2	460		T3	2
transitions[0x0=>0x1]	200144	1			T1	864		T2	281		T3	1
transitions[0x1=>0x0]	200387	1			T1	864		T2	281		T3	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	289487	1			T1	1650		T2	342		T3	13
all_pins[0]	values[0x1]	78787	1			T1	245		T2	113		T3	2
all_pins[0]	transitions[0x0=>0x1]	78168	1			T1	245		T2	112		T3	1
all_pins[0]	transitions[0x1=>0x0]	73530	1			T1	345		T2	116		T18	15
all_pins[1]	values[0x0]	293760	1			T1	1894		T2	337		T3	15
all_pins[1]	values[0x1]	74514	1			T1	1		T2	118		T18	20
all_pins[1]	transitions[0x0=>0x1]	40440	1			T1	1		T2	55		T18	8
all_pins[1]	transitions[0x1=>0x0]	44713	1			T1	245		T2	50		T3	2
all_pins[2]	values[0x0]	294264	1			T1	1462		T2	343		T3	15
all_pins[2]	values[0x1]	74010	1			T1	433		T2	112		T18	15
all_pins[2]	transitions[0x0=>0x1]	40754	1			T1	433		T2	57		T18	7
all_pins[2]	transitions[0x1=>0x0]	41258	1			T1	1		T2	63		T18	12
all_pins[3]	values[0x0]	294368	1			T1	1550		T2	338		T3	15
all_pins[3]	values[0x1]	73906	1			T1	345		T2	117		T18	15
all_pins[3]	transitions[0x0=>0x1]	40782	1			T1	185		T2	57		T18	10
all_pins[3]	transitions[0x1=>0x0]	40886	1			T1	273		T2	52		T18	10