Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	96874	1			T4	557		T14	1051		T16	972
accum_cnt_1000	243578	1			T1	1113		T2	245		T4	499
accum_cnt_100	26814	1			T1	147		T2	91		T18	28
accum_cnt_50	64574	1			T1	108		T2	123		T18	31
accum_cnt_10	174814	1			T1	43		T2	357		T3	9
accum_cnt_0	439651	1			T1	4253		T2	256		T3	35

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	272125	1			T1	1416		T2	268		T3	11
class_index[0x1]	272125	1			T1	1416		T2	268		T3	11
class_index[0x2]	272125	1			T1	1416		T2	268		T3	11
class_index[0x3]	272125	1			T1	1416		T2	268		T3	11

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	25872	1			T14	451		T17	392		T29	1027
class_index[0x0]	accum_cnt_1000	68348	1			T1	1113		T2	8		T4	5
class_index[0x0]	accum_cnt_100	7563	1			T1	147		T2	14		T4	30
class_index[0x0]	accum_cnt_50	16505	1			T1	108		T2	14		T4	1154
class_index[0x0]	accum_cnt_10	43857	1			T1	39		T2	218		T3	9
class_index[0x0]	accum_cnt_0	96362	1			T1	9		T2	14		T3	2
class_index[0x1]	accum_cnt_2000	21939	1			T4	557		T16	213		T48	316
class_index[0x1]	accum_cnt_1000	59085	1			T2	132		T4	484		T15	171
class_index[0x1]	accum_cnt_100	6737	1			T2	35		T18	14		T4	58
class_index[0x1]	accum_cnt_50	15426	1			T2	76		T18	12		T4	42
class_index[0x1]	accum_cnt_10	40545	1			T1	4		T2	16		T18	9
class_index[0x1]	accum_cnt_0	119318	1			T1	1412		T2	9		T3	11
class_index[0x2]	accum_cnt_2000	27689	1			T14	600		T16	410		T17	443
class_index[0x2]	accum_cnt_1000	63364	1			T2	50		T4	10		T44	4
class_index[0x2]	accum_cnt_100	6727	1			T2	23		T18	14		T4	24
class_index[0x2]	accum_cnt_50	17241	1			T2	17		T18	19		T4	19
class_index[0x2]	accum_cnt_10	43280	1			T2	7		T18	4		T4	13
class_index[0x2]	accum_cnt_0	105183	1			T1	1416		T2	171		T3	11
class_index[0x3]	accum_cnt_2000	21374	1			T16	349		T17	237		T48	408
class_index[0x3]	accum_cnt_1000	52781	1			T2	55		T15	72		T16	473
class_index[0x3]	accum_cnt_100	5787	1			T2	19		T4	30		T15	22
class_index[0x3]	accum_cnt_50	15402	1			T2	16		T4	1129		T14	22
class_index[0x3]	accum_cnt_10	47132	1			T2	116		T4	40		T20	4
class_index[0x3]	accum_cnt_0	118788	1			T1	1416		T2	62		T3	11