Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	6077	1			T4	115		T72	15		T32	661
alert[0x1]	6314	1			T4	71		T6	1		T14	42
alert[0x2]	5623	1			T2	1		T4	103		T44	49
alert[0x3]	6010	1			T72	14		T32	1564		T110	35
alert[0x4]	5614	1			T4	24		T6	1		T15	72
alert[0x5]	2368	1			T44	4		T17	12		T110	12
alert[0x6]	2382	1			T15	15		T8	1		T72	38
alert[0x7]	2488	1			T4	39		T14	61		T17	90
alert[0x8]	4364	1			T4	76		T15	2		T8	1
alert[0x9]	4331	1			T4	12		T15	3		T17	39
alert[0xa]	10485	1			T4	82		T15	3		T16	3
alert[0xb]	5137	1			T17	59		T285	1		T286	584
alert[0xc]	6142	1			T4	67		T16	2		T29	290
alert[0xd]	10129	1			T2	2		T17	14		T29	2455
alert[0xe]	7117	1			T4	64		T72	81		T9	1
alert[0xf]	4758	1			T17	49		T29	30		T110	29
alert[0x10]	4578	1			T2	6		T4	94		T6	1
alert[0x11]	10414	1			T4	26		T15	3		T16	3
alert[0x12]	6273	1			T14	14		T17	555		T72	878
alert[0x13]	7529	1			T4	81		T14	76		T15	3
alert[0x14]	8514	1			T4	40		T44	1		T6	1
alert[0x15]	3706	1			T14	1		T15	2		T29	211
alert[0x16]	4839	1			T2	2		T4	6		T44	8
alert[0x17]	7577	1			T15	8		T72	31		T27	129
alert[0x18]	5684	1			T14	208		T27	2		T32	71
alert[0x19]	3925	1			T14	689		T17	148		T72	104
alert[0x1a]	5958	1			T15	146		T29	754		T26	11
alert[0x1b]	13446	1			T2	23		T17	165		T29	23
alert[0x1c]	7768	1			T4	248		T15	5		T29	8
alert[0x1d]	8417	1			T14	88		T15	8		T17	17
alert[0x1e]	3218	1			T14	22		T15	1		T72	21
alert[0x1f]	6042	1			T4	209		T14	19		T15	27
alert[0x20]	8128	1			T4	37		T44	10		T15	222
alert[0x21]	5024	1			T2	21		T14	547		T17	23
alert[0x22]	7808	1			T2	2		T14	19		T8	1
alert[0x23]	8197	1			T4	95		T15	5		T17	44
alert[0x24]	6767	1			T2	12		T14	77		T15	19
alert[0x25]	5666	1			T2	11		T4	5		T14	367
alert[0x26]	7754	1			T4	10		T15	4		T17	28
alert[0x27]	5929	1			T29	844		T50	923		T51	2
alert[0x28]	10653	1			T14	93		T17	149		T72	322
alert[0x29]	4495	1			T4	49		T14	49		T17	34
alert[0x2a]	25366	1			T2	3		T4	262		T14	337
alert[0x2b]	5587	1			T15	34		T32	90		T110	256
alert[0x2c]	8645	1			T4	15		T14	100		T15	10
alert[0x2d]	8563	1			T2	42		T4	14		T44	4
alert[0x2e]	5977	1			T4	141		T14	15		T17	840
alert[0x2f]	19373	1			T14	4193		T17	297		T75	22
alert[0x30]	7710	1			T6	1		T46	3		T15	7
alert[0x31]	12245	1			T14	316		T17	66		T29	129
alert[0x32]	13304	1			T4	51		T29	65		T72	58
alert[0x33]	5403	1			T4	11		T14	22		T29	201
alert[0x34]	3910	1			T4	30		T15	1		T29	46
alert[0x35]	3227	1			T29	101		T49	3		T50	28
alert[0x36]	4155	1			T4	19		T14	121		T16	2
alert[0x37]	6995	1			T4	76		T14	189		T15	4
alert[0x38]	7604	1			T4	39		T15	26		T29	71
alert[0x39]	8899	1			T14	103		T15	6		T75	2
alert[0x3a]	2681	1			T4	29		T14	31		T29	263
alert[0x3b]	4947	1			T2	1		T4	3		T14	271
alert[0x3c]	2753	1			T4	353		T14	10		T15	86
alert[0x3d]	6454	1			T14	182		T15	8		T29	11
alert[0x3e]	3451	1			T15	1		T29	219		T72	72
alert[0x3f]	6343	1			T14	4		T15	104		T27	174
alert[0x40]	4219	1			T14	19		T15	11		T17	7

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	103056	1			T6	1		T15	379		T29	1555
class_i[0x1]	149804	1			T44	76		T14	8659		T15	165
class_i[0x2]	97064	1			T2	126		T4	2596		T14	42
class_i[0x3]	95535	1			T6	5		T15	249		T8	3

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

444826

1

T2

126

T4

2596

T44

76

alert_ping_fail

633

1

T6

6

T8

3

T9

11

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	6062	1			T4	115		T72	15		T32	661
alert_integrity_fail	alert[0x1]	6301	1			T4	71		T14	42		T15	4
alert_integrity_fail	alert[0x2]	5612	1			T2	1		T4	103		T44	49
alert_integrity_fail	alert[0x3]	5997	1			T72	14		T32	1564		T110	35
alert_integrity_fail	alert[0x4]	5605	1			T4	24		T15	72		T29	15
alert_integrity_fail	alert[0x5]	2353	1			T44	4		T17	12		T110	12
alert_integrity_fail	alert[0x6]	2371	1			T15	15		T72	38		T27	25
alert_integrity_fail	alert[0x7]	2477	1			T4	39		T14	61		T17	90
alert_integrity_fail	alert[0x8]	4344	1			T4	76		T15	2		T29	33
alert_integrity_fail	alert[0x9]	4318	1			T4	12		T15	3		T17	39
alert_integrity_fail	alert[0xa]	10477	1			T4	82		T15	3		T16	3
alert_integrity_fail	alert[0xb]	5125	1			T17	59		T285	1		T286	584
alert_integrity_fail	alert[0xc]	6136	1			T4	67		T16	2		T29	290
alert_integrity_fail	alert[0xd]	10119	1			T2	2		T17	14		T29	2455
alert_integrity_fail	alert[0xe]	7111	1			T4	64		T72	81		T110	41
alert_integrity_fail	alert[0xf]	4745	1			T17	49		T29	30		T110	29
alert_integrity_fail	alert[0x10]	4567	1			T2	6		T4	94		T14	124
alert_integrity_fail	alert[0x11]	10408	1			T4	26		T15	3		T16	3
alert_integrity_fail	alert[0x12]	6262	1			T14	14		T17	555		T72	878
alert_integrity_fail	alert[0x13]	7522	1			T4	81		T14	76		T15	3
alert_integrity_fail	alert[0x14]	8501	1			T4	40		T44	1		T29	348
alert_integrity_fail	alert[0x15]	3698	1			T14	1		T15	2		T29	211
alert_integrity_fail	alert[0x16]	4832	1			T2	2		T4	6		T44	8
alert_integrity_fail	alert[0x17]	7574	1			T15	8		T72	31		T27	129
alert_integrity_fail	alert[0x18]	5674	1			T14	208		T27	2		T32	71
alert_integrity_fail	alert[0x19]	3913	1			T14	689		T17	148		T72	104
alert_integrity_fail	alert[0x1a]	5951	1			T15	146		T29	754		T26	11
alert_integrity_fail	alert[0x1b]	13435	1			T2	23		T17	165		T29	23
alert_integrity_fail	alert[0x1c]	7761	1			T4	248		T15	5		T29	8
alert_integrity_fail	alert[0x1d]	8407	1			T14	88		T15	8		T17	17
alert_integrity_fail	alert[0x1e]	3211	1			T14	22		T15	1		T72	21
alert_integrity_fail	alert[0x1f]	6029	1			T4	209		T14	19		T15	27
alert_integrity_fail	alert[0x20]	8119	1			T4	37		T44	10		T15	222
alert_integrity_fail	alert[0x21]	5011	1			T2	21		T14	547		T17	23
alert_integrity_fail	alert[0x22]	7797	1			T2	2		T14	19		T17	146
alert_integrity_fail	alert[0x23]	8183	1			T4	95		T15	5		T17	44
alert_integrity_fail	alert[0x24]	6759	1			T2	12		T14	77		T15	19
alert_integrity_fail	alert[0x25]	5660	1			T2	11		T4	5		T14	367
alert_integrity_fail	alert[0x26]	7742	1			T4	10		T15	4		T17	28
alert_integrity_fail	alert[0x27]	5917	1			T29	844		T50	923		T51	2
alert_integrity_fail	alert[0x28]	10637	1			T14	93		T17	149		T72	322
alert_integrity_fail	alert[0x29]	4482	1			T4	49		T14	49		T17	34
alert_integrity_fail	alert[0x2a]	25354	1			T2	3		T4	262		T14	337
alert_integrity_fail	alert[0x2b]	5578	1			T15	34		T32	90		T110	256
alert_integrity_fail	alert[0x2c]	8629	1			T4	15		T14	100		T15	10
alert_integrity_fail	alert[0x2d]	8554	1			T2	42		T4	14		T44	4
alert_integrity_fail	alert[0x2e]	5966	1			T4	141		T14	15		T17	840
alert_integrity_fail	alert[0x2f]	19364	1			T14	4193		T17	297		T75	22
alert_integrity_fail	alert[0x30]	7702	1			T46	3		T15	7		T17	1608
alert_integrity_fail	alert[0x31]	12238	1			T14	316		T17	66		T29	129
alert_integrity_fail	alert[0x32]	13296	1			T4	51		T29	65		T72	58
alert_integrity_fail	alert[0x33]	5397	1			T4	11		T14	22		T29	201
alert_integrity_fail	alert[0x34]	3907	1			T4	30		T15	1		T29	46
alert_integrity_fail	alert[0x35]	3216	1			T29	101		T49	3		T50	28
alert_integrity_fail	alert[0x36]	4149	1			T4	19		T14	121		T16	2
alert_integrity_fail	alert[0x37]	6984	1			T4	76		T14	189		T15	4
alert_integrity_fail	alert[0x38]	7595	1			T4	39		T15	26		T29	71
alert_integrity_fail	alert[0x39]	8896	1			T14	103		T15	6		T75	2
alert_integrity_fail	alert[0x3a]	2671	1			T4	29		T14	31		T29	263
alert_integrity_fail	alert[0x3b]	4937	1			T2	1		T4	3		T14	271
alert_integrity_fail	alert[0x3c]	2745	1			T4	353		T14	10		T15	86
alert_integrity_fail	alert[0x3d]	6448	1			T14	182		T15	8		T29	11
alert_integrity_fail	alert[0x3e]	3444	1			T15	1		T29	219		T72	72
alert_integrity_fail	alert[0x3f]	6340	1			T14	4		T15	104		T27	174
alert_integrity_fail	alert[0x40]	4211	1			T14	19		T15	11		T17	7
alert_ping_fail	alert[0x0]	15	1			T287	1		T288	1		T289	1
alert_ping_fail	alert[0x1]	13	1			T6	1		T288	1		T36	1
alert_ping_fail	alert[0x2]	11	1			T6	1		T289	1		T290	1
alert_ping_fail	alert[0x3]	13	1			T10	1		T287	1		T291	1
alert_ping_fail	alert[0x4]	9	1			T6	1		T264	2		T292	1
alert_ping_fail	alert[0x5]	15	1			T10	1		T287	1		T277	2
alert_ping_fail	alert[0x6]	11	1			T8	1		T293	1		T294	1
alert_ping_fail	alert[0x7]	11	1			T38	1		T294	1		T295	1
alert_ping_fail	alert[0x8]	20	1			T8	1		T289	1		T36	1
alert_ping_fail	alert[0x9]	13	1			T288	1		T294	1		T296	2
alert_ping_fail	alert[0xa]	8	1			T297	1		T231	2		T290	1
alert_ping_fail	alert[0xb]	12	1			T277	1		T289	1		T294	1
alert_ping_fail	alert[0xc]	6	1			T9	1		T277	1		T298	1
alert_ping_fail	alert[0xd]	10	1			T9	1		T277	1		T299	1
alert_ping_fail	alert[0xe]	6	1			T9	1		T300	1		T301	1
alert_ping_fail	alert[0xf]	13	1			T10	1		T38	1		T264	1
alert_ping_fail	alert[0x10]	11	1			T6	1		T277	1		T36	1
alert_ping_fail	alert[0x11]	6	1			T288	1		T289	1		T291	1
alert_ping_fail	alert[0x12]	11	1			T9	1		T291	1		T299	1
alert_ping_fail	alert[0x13]	7	1			T296	1		T302	1		T303	1
alert_ping_fail	alert[0x14]	13	1			T6	1		T283	1		T288	1
alert_ping_fail	alert[0x15]	8	1			T36	1		T304	1		T305	1
alert_ping_fail	alert[0x16]	7	1			T291	1		T235	1		T306	1
alert_ping_fail	alert[0x17]	3	1			T299	1		T307	1		T308	1
alert_ping_fail	alert[0x18]	10	1			T10	1		T289	1		T309	1
alert_ping_fail	alert[0x19]	12	1			T36	1		T230	1		T290	1
alert_ping_fail	alert[0x1a]	7	1			T38	1		T296	1		T264	1
alert_ping_fail	alert[0x1b]	11	1			T10	1		T277	1		T230	1
alert_ping_fail	alert[0x1c]	7	1			T282	1		T291	1		T298	1
alert_ping_fail	alert[0x1d]	10	1			T282	1		T310	1		T296	1
alert_ping_fail	alert[0x1e]	7	1			T9	1		T36	1		T230	1
alert_ping_fail	alert[0x1f]	13	1			T10	1		T309	1		T294	1
alert_ping_fail	alert[0x20]	9	1			T289	1		T41	1		T291	1
alert_ping_fail	alert[0x21]	13	1			T289	1		T38	1		T310	1
alert_ping_fail	alert[0x22]	11	1			T8	1		T283	1		T36	2
alert_ping_fail	alert[0x23]	14	1			T287	1		T291	1		T309	1
alert_ping_fail	alert[0x24]	8	1			T264	2		T302	1		T311	1
alert_ping_fail	alert[0x25]	6	1			T277	1		T291	1		T310	1
alert_ping_fail	alert[0x26]	12	1			T9	1		T291	1		T296	1
alert_ping_fail	alert[0x27]	12	1			T38	1		T309	1		T299	2
alert_ping_fail	alert[0x28]	16	1			T10	1		T38	1		T310	1
alert_ping_fail	alert[0x29]	13	1			T291	2		T310	1		T230	2
alert_ping_fail	alert[0x2a]	12	1			T36	1		T291	2		T309	1
alert_ping_fail	alert[0x2b]	9	1			T10	1		T289	1		T309	1
alert_ping_fail	alert[0x2c]	16	1			T9	1		T287	1		T288	1
alert_ping_fail	alert[0x2d]	9	1			T291	1		T294	1		T312	1
alert_ping_fail	alert[0x2e]	11	1			T111	1		T290	1		T303	1
alert_ping_fail	alert[0x2f]	9	1			T111	1		T277	1		T289	1
alert_ping_fail	alert[0x30]	8	1			T6	1		T9	1		T73	1
alert_ping_fail	alert[0x31]	7	1			T277	1		T302	1		T298	1
alert_ping_fail	alert[0x32]	8	1			T38	2		T310	1		T299	1
alert_ping_fail	alert[0x33]	6	1			T310	2		T297	1		T264	1
alert_ping_fail	alert[0x34]	3	1			T302	1		T313	1		T314	1
alert_ping_fail	alert[0x35]	11	1			T309	1		T264	1		T299	2
alert_ping_fail	alert[0x36]	6	1			T9	1		T290	1		T311	1
alert_ping_fail	alert[0x37]	11	1			T9	1		T287	1		T277	1
alert_ping_fail	alert[0x38]	9	1			T9	1		T289	1		T294	1
alert_ping_fail	alert[0x39]	3	1			T277	1		T315	1		T300	1
alert_ping_fail	alert[0x3a]	10	1			T287	1		T294	1		T302	1
alert_ping_fail	alert[0x3b]	10	1			T287	1		T294	2		T230	1
alert_ping_fail	alert[0x3c]	8	1			T310	1		T230	1		T298	2
alert_ping_fail	alert[0x3d]	6	1			T289	1		T296	1		T297	1
alert_ping_fail	alert[0x3e]	7	1			T296	1		T311	1		T299	1
alert_ping_fail	alert[0x3f]	3	1			T302	1		T316	1		T265	1
alert_ping_fail	alert[0x40]	8	1			T289	1		T310	1		T296	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	102888	1			T15	379		T29	1555		T26	11
alert_integrity_fail	class_i[0x1]	149637	1			T44	76		T14	8659		T15	165
alert_integrity_fail	class_i[0x2]	96943	1			T2	126		T4	2596		T14	42
alert_integrity_fail	class_i[0x3]	95358	1			T15	249		T16	11		T17	4995
alert_ping_fail	class_i[0x0]	168	1			T6	1		T73	1		T10	1
alert_ping_fail	class_i[0x1]	167	1			T9	2		T10	6		T287	1
alert_ping_fail	class_i[0x2]	121	1			T9	8		T111	2		T282	2
alert_ping_fail	class_i[0x3]	177	1			T6	5		T8	3		T9	1