Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.68 99.99 98.70 100.00 100.00 100.00 99.38 99.68


Total test records in report: 829
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T172 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.610733978 Jun 13 01:28:21 PM PDT 24 Jun 13 01:29:07 PM PDT 24 6272769615 ps
T770 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3842708960 Jun 13 01:28:34 PM PDT 24 Jun 13 01:28:40 PM PDT 24 66139562 ps
T771 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1654126932 Jun 13 01:28:21 PM PDT 24 Jun 13 01:28:43 PM PDT 24 490323956 ps
T772 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1783359924 Jun 13 01:28:30 PM PDT 24 Jun 13 01:28:32 PM PDT 24 8084767 ps
T773 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1219306515 Jun 13 01:28:26 PM PDT 24 Jun 13 01:28:32 PM PDT 24 485037978 ps
T774 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3383455281 Jun 13 01:28:11 PM PDT 24 Jun 13 01:28:26 PM PDT 24 200953009 ps
T171 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.11065675 Jun 13 01:28:23 PM PDT 24 Jun 13 01:28:27 PM PDT 24 477484878 ps
T775 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1609828946 Jun 13 01:28:32 PM PDT 24 Jun 13 01:28:43 PM PDT 24 246186317 ps
T776 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.702859237 Jun 13 01:28:21 PM PDT 24 Jun 13 01:28:23 PM PDT 24 8863673 ps
T138 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3576549235 Jun 13 01:28:34 PM PDT 24 Jun 13 01:34:38 PM PDT 24 14240055054 ps
T777 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.716264847 Jun 13 01:28:37 PM PDT 24 Jun 13 01:28:39 PM PDT 24 6826572 ps
T778 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2036204811 Jun 13 01:28:00 PM PDT 24 Jun 13 01:28:03 PM PDT 24 7683255 ps
T779 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.657064437 Jun 13 01:28:04 PM PDT 24 Jun 13 01:28:06 PM PDT 24 13206094 ps
T780 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2967734749 Jun 13 01:28:16 PM PDT 24 Jun 13 01:28:22 PM PDT 24 32622792 ps
T781 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2894059298 Jun 13 01:28:41 PM PDT 24 Jun 13 01:28:43 PM PDT 24 6709265 ps
T782 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.669557185 Jun 13 01:28:35 PM PDT 24 Jun 13 01:28:37 PM PDT 24 9862758 ps
T783 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2249495914 Jun 13 01:28:18 PM PDT 24 Jun 13 01:28:40 PM PDT 24 342799315 ps
T157 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.4215924283 Jun 13 01:28:35 PM PDT 24 Jun 13 01:34:06 PM PDT 24 4497125983 ps
T784 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3630013024 Jun 13 01:27:58 PM PDT 24 Jun 13 01:28:03 PM PDT 24 123173508 ps
T785 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1605128950 Jun 13 01:28:08 PM PDT 24 Jun 13 01:28:09 PM PDT 24 7776339 ps
T786 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1515549727 Jun 13 01:28:37 PM PDT 24 Jun 13 01:28:39 PM PDT 24 18531572 ps
T787 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3460673265 Jun 13 01:28:29 PM PDT 24 Jun 13 01:28:47 PM PDT 24 246263615 ps
T788 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3875116294 Jun 13 01:28:16 PM PDT 24 Jun 13 01:28:19 PM PDT 24 12876477 ps
T789 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3314571181 Jun 13 01:28:36 PM PDT 24 Jun 13 01:28:38 PM PDT 24 12592060 ps
T790 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3103645312 Jun 13 01:28:40 PM PDT 24 Jun 13 01:28:42 PM PDT 24 9135876 ps
T791 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.4139684783 Jun 13 01:28:13 PM PDT 24 Jun 13 01:28:20 PM PDT 24 90125350 ps
T792 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2732099487 Jun 13 01:28:17 PM PDT 24 Jun 13 01:28:52 PM PDT 24 537304256 ps
T793 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1439517605 Jun 13 01:27:56 PM PDT 24 Jun 13 01:30:59 PM PDT 24 2920098926 ps
T794 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3405779453 Jun 13 01:28:41 PM PDT 24 Jun 13 01:28:43 PM PDT 24 14197330 ps
T795 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3014755255 Jun 13 01:27:59 PM PDT 24 Jun 13 01:28:20 PM PDT 24 552619029 ps
T796 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2396560753 Jun 13 01:28:24 PM PDT 24 Jun 13 01:28:31 PM PDT 24 42481299 ps
T797 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3001251782 Jun 13 01:28:12 PM PDT 24 Jun 13 01:28:19 PM PDT 24 61861324 ps
T798 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.4130996586 Jun 13 01:28:42 PM PDT 24 Jun 13 01:28:45 PM PDT 24 20777138 ps
T178 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1788288044 Jun 13 01:28:27 PM PDT 24 Jun 13 01:29:48 PM PDT 24 7895042931 ps
T799 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1647189972 Jun 13 01:28:21 PM PDT 24 Jun 13 01:28:30 PM PDT 24 189385451 ps
T800 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2090388838 Jun 13 01:28:31 PM PDT 24 Jun 13 01:28:37 PM PDT 24 262690339 ps
T801 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3426049199 Jun 13 01:28:12 PM PDT 24 Jun 13 01:28:14 PM PDT 24 10463636 ps
T164 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2437988704 Jun 13 01:28:16 PM PDT 24 Jun 13 01:29:01 PM PDT 24 2155679795 ps
T802 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2656935759 Jun 13 01:28:21 PM PDT 24 Jun 13 01:28:23 PM PDT 24 12197333 ps
T803 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.124866768 Jun 13 01:28:29 PM PDT 24 Jun 13 01:28:42 PM PDT 24 186237868 ps
T153 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1988989935 Jun 13 01:28:27 PM PDT 24 Jun 13 01:30:39 PM PDT 24 1725681731 ps
T804 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3187174243 Jun 13 01:28:37 PM PDT 24 Jun 13 01:28:39 PM PDT 24 11628188 ps
T805 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.4079930078 Jun 13 01:28:06 PM PDT 24 Jun 13 01:28:16 PM PDT 24 1151683861 ps
T806 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1759299080 Jun 13 01:28:29 PM PDT 24 Jun 13 01:28:31 PM PDT 24 8911818 ps
T807 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1811821158 Jun 13 01:28:11 PM PDT 24 Jun 13 01:28:23 PM PDT 24 91463004 ps
T808 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2567529424 Jun 13 01:27:57 PM PDT 24 Jun 13 01:28:03 PM PDT 24 294298820 ps
T809 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1330577650 Jun 13 01:28:01 PM PDT 24 Jun 13 01:28:08 PM PDT 24 142106755 ps
T810 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1979419397 Jun 13 01:28:33 PM PDT 24 Jun 13 01:28:44 PM PDT 24 711510714 ps
T167 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.4551133 Jun 13 01:28:40 PM PDT 24 Jun 13 01:28:45 PM PDT 24 53771987 ps
T811 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3291599177 Jun 13 01:28:35 PM PDT 24 Jun 13 01:28:48 PM PDT 24 388293160 ps
T812 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2847454233 Jun 13 01:28:30 PM PDT 24 Jun 13 01:28:35 PM PDT 24 62630392 ps
T148 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.226084163 Jun 13 01:28:16 PM PDT 24 Jun 13 01:29:45 PM PDT 24 807455217 ps
T343 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.255962748 Jun 13 01:28:00 PM PDT 24 Jun 13 01:46:54 PM PDT 24 134704459245 ps
T182 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3733202585 Jun 13 01:28:06 PM PDT 24 Jun 13 01:28:10 PM PDT 24 104770105 ps
T813 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.672713447 Jun 13 01:28:18 PM PDT 24 Jun 13 01:28:38 PM PDT 24 1466529070 ps
T814 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.804300014 Jun 13 01:28:23 PM PDT 24 Jun 13 01:28:42 PM PDT 24 546072861 ps
T154 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.185205920 Jun 13 01:28:22 PM PDT 24 Jun 13 01:36:56 PM PDT 24 25118511108 ps
T155 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2802297548 Jun 13 01:28:22 PM PDT 24 Jun 13 01:32:10 PM PDT 24 3353638531 ps
T815 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2068903128 Jun 13 01:28:41 PM PDT 24 Jun 13 01:28:43 PM PDT 24 9921490 ps
T816 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3896024638 Jun 13 01:28:31 PM PDT 24 Jun 13 01:28:37 PM PDT 24 118142058 ps
T817 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3433112103 Jun 13 01:28:30 PM PDT 24 Jun 13 01:28:40 PM PDT 24 427082873 ps
T818 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1897261708 Jun 13 01:28:13 PM PDT 24 Jun 13 01:30:54 PM PDT 24 2226795099 ps
T819 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.118322684 Jun 13 01:27:59 PM PDT 24 Jun 13 01:28:08 PM PDT 24 65239505 ps
T820 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.157112814 Jun 13 01:28:28 PM PDT 24 Jun 13 01:28:35 PM PDT 24 41132983 ps
T821 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2509022110 Jun 13 01:28:27 PM PDT 24 Jun 13 01:28:41 PM PDT 24 1051451681 ps
T822 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3009794665 Jun 13 01:28:28 PM PDT 24 Jun 13 01:28:30 PM PDT 24 7832549 ps
T823 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2976192808 Jun 13 01:28:10 PM PDT 24 Jun 13 01:28:16 PM PDT 24 115765787 ps
T173 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3689692935 Jun 13 01:28:17 PM PDT 24 Jun 13 01:28:21 PM PDT 24 60208299 ps
T170 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2511078956 Jun 13 01:28:34 PM PDT 24 Jun 13 01:28:38 PM PDT 24 109483645 ps
T824 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1530957940 Jun 13 01:28:46 PM PDT 24 Jun 13 01:28:48 PM PDT 24 13457335 ps
T176 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.899319859 Jun 13 01:28:03 PM PDT 24 Jun 13 01:28:26 PM PDT 24 160491890 ps
T825 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2001957710 Jun 13 01:28:23 PM PDT 24 Jun 13 01:28:27 PM PDT 24 33655413 ps
T826 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2391269513 Jun 13 01:28:35 PM PDT 24 Jun 13 01:28:58 PM PDT 24 345661980 ps
T152 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.592636840 Jun 13 01:27:58 PM PDT 24 Jun 13 01:31:58 PM PDT 24 2257116230 ps
T827 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1454389728 Jun 13 01:28:43 PM PDT 24 Jun 13 01:28:45 PM PDT 24 17069420 ps
T828 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2405006907 Jun 13 01:28:30 PM PDT 24 Jun 13 01:28:53 PM PDT 24 1208555962 ps
T829 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2528702906 Jun 13 01:28:24 PM PDT 24 Jun 13 01:28:26 PM PDT 24 15026469 ps
T156 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.607271216 Jun 13 01:28:24 PM PDT 24 Jun 13 01:49:38 PM PDT 24 34826634793 ps
T175 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1602909918 Jun 13 01:28:04 PM PDT 24 Jun 13 01:28:08 PM PDT 24 45628573 ps

Test location /workspace/coverage/default/23.alert_handler_stress_all.1085225028
Short name T4
Test name
Test status
Simulation time 182577044703 ps
CPU time 3342.57 seconds
Started Jun 13 01:30:37 PM PDT 24
Finished Jun 13 02:26:21 PM PDT 24
Peak memory 289400 kb
Host smart-74d84a10-2108-4eee-b44a-7570dc54c534
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085225028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1085225028
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.179900530
Short name T15
Test name
Test status
Simulation time 60316253902 ps
CPU time 2965.27 seconds
Started Jun 13 01:37:48 PM PDT 24
Finished Jun 13 02:27:15 PM PDT 24
Peak memory 304320 kb
Host smart-253a5314-9f68-4551-a715-94a3741f58b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179900530 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.179900530
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3605385815
Short name T11
Test name
Test status
Simulation time 1627816013 ps
CPU time 23.83 seconds
Started Jun 13 01:29:04 PM PDT 24
Finished Jun 13 01:29:29 PM PDT 24
Peak memory 270320 kb
Host smart-fbdf88a6-babb-4038-8d84-c7da94790059
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3605385815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3605385815
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2473353548
Short name T159
Test name
Test status
Simulation time 2492592998 ps
CPU time 45.78 seconds
Started Jun 13 01:28:12 PM PDT 24
Finished Jun 13 01:28:58 PM PDT 24
Peak memory 249028 kb
Host smart-2bc2186a-8bfa-4557-8d8e-371dde264a59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2473353548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2473353548
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1443335228
Short name T57
Test name
Test status
Simulation time 78596292865 ps
CPU time 1617.93 seconds
Started Jun 13 01:28:56 PM PDT 24
Finished Jun 13 01:55:55 PM PDT 24
Peak memory 297980 kb
Host smart-1e39854d-e984-4954-9715-1b87dc33d584
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443335228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1443335228
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.3300984615
Short name T28
Test name
Test status
Simulation time 112811422300 ps
CPU time 5444.85 seconds
Started Jun 13 01:56:31 PM PDT 24
Finished Jun 13 03:27:21 PM PDT 24
Peak memory 371820 kb
Host smart-cc9d0f28-7a82-48bf-8a6e-f1877beafc1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300984615 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.3300984615
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1394602091
Short name T122
Test name
Test status
Simulation time 14797561744 ps
CPU time 1061.56 seconds
Started Jun 13 01:28:34 PM PDT 24
Finished Jun 13 01:46:16 PM PDT 24
Peak memory 273056 kb
Host smart-8dba4fac-2974-4e5e-ae37-e7592de9fe4b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394602091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1394602091
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2505045318
Short name T224
Test name
Test status
Simulation time 1644954680 ps
CPU time 45.44 seconds
Started Jun 13 01:29:26 PM PDT 24
Finished Jun 13 01:30:13 PM PDT 24
Peak memory 249012 kb
Host smart-92c603f2-27cb-474a-bc4a-4f7616ec8b90
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2505045318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2505045318
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1329642945
Short name T8
Test name
Test status
Simulation time 205232423955 ps
CPU time 2931.37 seconds
Started Jun 13 01:28:46 PM PDT 24
Finished Jun 13 02:17:38 PM PDT 24
Peak memory 289096 kb
Host smart-ffe70820-fad5-47ed-90d2-8f44c8fb0994
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329642945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1329642945
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2735316832
Short name T129
Test name
Test status
Simulation time 6520088637 ps
CPU time 208.02 seconds
Started Jun 13 01:28:33 PM PDT 24
Finished Jun 13 01:32:01 PM PDT 24
Peak memory 265804 kb
Host smart-7884f9b9-2f7a-4e87-8901-5dd0a428bdba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2735316832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2735316832
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2377695841
Short name T52
Test name
Test status
Simulation time 15057337815 ps
CPU time 1900.49 seconds
Started Jun 13 01:29:11 PM PDT 24
Finished Jun 13 02:00:53 PM PDT 24
Peak memory 299988 kb
Host smart-8fb237eb-15d2-4a09-aa2c-485c017a6618
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377695841 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2377695841
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1059939764
Short name T140
Test name
Test status
Simulation time 12222427658 ps
CPU time 1011.84 seconds
Started Jun 13 01:28:16 PM PDT 24
Finished Jun 13 01:45:09 PM PDT 24
Peak memory 265688 kb
Host smart-728494b2-5d8d-44ca-87ee-2663dd4e0032
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059939764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1059939764
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.282717859
Short name T89
Test name
Test status
Simulation time 299694815940 ps
CPU time 2249.29 seconds
Started Jun 13 01:29:29 PM PDT 24
Finished Jun 13 02:06:59 PM PDT 24
Peak memory 270580 kb
Host smart-41f1f7a3-0f6b-486b-9485-3bc3a8339791
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282717859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.282717859
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.3032001381
Short name T104
Test name
Test status
Simulation time 105142089751 ps
CPU time 3125.06 seconds
Started Jun 13 01:29:17 PM PDT 24
Finished Jun 13 02:21:24 PM PDT 24
Peak memory 319612 kb
Host smart-9ccd5859-9208-4212-af8e-8a1f0f300dd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032001381 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.3032001381
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.998960387
Short name T134
Test name
Test status
Simulation time 4365272668 ps
CPU time 282.52 seconds
Started Jun 13 01:28:21 PM PDT 24
Finished Jun 13 01:33:04 PM PDT 24
Peak memory 265680 kb
Host smart-1919d608-ee22-4a3f-9249-25e8f691e6a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=998960387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.998960387
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.2290325084
Short name T29
Test name
Test status
Simulation time 71542844420 ps
CPU time 7299.33 seconds
Started Jun 13 01:32:12 PM PDT 24
Finished Jun 13 03:33:53 PM PDT 24
Peak memory 371980 kb
Host smart-2bf6012f-9847-4367-9a3c-5a89dd405cb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290325084 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.2290325084
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.943605926
Short name T121
Test name
Test status
Simulation time 23842713542 ps
CPU time 995.64 seconds
Started Jun 13 01:28:05 PM PDT 24
Finished Jun 13 01:44:42 PM PDT 24
Peak memory 272780 kb
Host smart-f4906289-500b-46d8-a2ca-670800eecac4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943605926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.943605926
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1670430903
Short name T282
Test name
Test status
Simulation time 195283080064 ps
CPU time 2828.54 seconds
Started Jun 13 01:31:22 PM PDT 24
Finished Jun 13 02:18:33 PM PDT 24
Peak memory 281916 kb
Host smart-0121b778-8167-4954-950e-b5910cfbea60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670430903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1670430903
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.418962759
Short name T334
Test name
Test status
Simulation time 21821670 ps
CPU time 1.49 seconds
Started Jun 13 01:28:40 PM PDT 24
Finished Jun 13 01:28:42 PM PDT 24
Peak memory 237368 kb
Host smart-78a67b32-6e41-4b2c-8fd4-dbe0b72586ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=418962759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.418962759
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.4250478118
Short name T277
Test name
Test status
Simulation time 26813116725 ps
CPU time 239.42 seconds
Started Jun 13 01:29:22 PM PDT 24
Finished Jun 13 01:33:24 PM PDT 24
Peak memory 247576 kb
Host smart-cabe48c9-1bb5-4fbb-9527-bee9eb448ca0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250478118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.4250478118
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1011532551
Short name T135
Test name
Test status
Simulation time 65256968366 ps
CPU time 1208.71 seconds
Started Jun 13 01:28:21 PM PDT 24
Finished Jun 13 01:48:30 PM PDT 24
Peak memory 265648 kb
Host smart-475bd4d4-c79b-468d-94d8-45d2bf7f7ba7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011532551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1011532551
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.864927284
Short name T73
Test name
Test status
Simulation time 127336571195 ps
CPU time 1862.37 seconds
Started Jun 13 01:30:33 PM PDT 24
Finished Jun 13 02:01:36 PM PDT 24
Peak memory 281960 kb
Host smart-ce8c8384-6494-464c-a54b-bf74e2440325
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864927284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.864927284
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1795689534
Short name T289
Test name
Test status
Simulation time 110748863562 ps
CPU time 391.14 seconds
Started Jun 13 01:29:18 PM PDT 24
Finished Jun 13 01:35:50 PM PDT 24
Peak memory 248724 kb
Host smart-ac85fa2d-3d08-4898-a0a1-4325411aee37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795689534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1795689534
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3520322030
Short name T137
Test name
Test status
Simulation time 3853313126 ps
CPU time 278.15 seconds
Started Jun 13 01:28:27 PM PDT 24
Finished Jun 13 01:33:07 PM PDT 24
Peak memory 265676 kb
Host smart-957f89d2-794d-4311-9e7a-ec914f4b4d60
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3520322030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3520322030
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1251569026
Short name T299
Test name
Test status
Simulation time 13802027404 ps
CPU time 551.43 seconds
Started Jun 13 01:28:50 PM PDT 24
Finished Jun 13 01:38:02 PM PDT 24
Peak memory 249160 kb
Host smart-ffbd7f44-435b-4b6c-8efb-0da7f6e9dfb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251569026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1251569026
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1484491222
Short name T323
Test name
Test status
Simulation time 54085762734 ps
CPU time 2837.01 seconds
Started Jun 13 01:29:41 PM PDT 24
Finished Jun 13 02:16:59 PM PDT 24
Peak memory 281924 kb
Host smart-5677ead9-691d-4b8c-8aad-571c2f772541
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484491222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1484491222
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1641467156
Short name T53
Test name
Test status
Simulation time 46092764517 ps
CPU time 2657.91 seconds
Started Jun 13 01:35:39 PM PDT 24
Finished Jun 13 02:19:58 PM PDT 24
Peak memory 287772 kb
Host smart-c6668c1c-b3ec-4f37-b39a-a816ad0ae3ea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641467156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1641467156
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.551152425
Short name T124
Test name
Test status
Simulation time 48929772000 ps
CPU time 1021.29 seconds
Started Jun 13 01:28:12 PM PDT 24
Finished Jun 13 01:45:14 PM PDT 24
Peak memory 265548 kb
Host smart-9f57219e-6ba7-4d5e-aa32-da450c957329
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551152425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.551152425
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.110895437
Short name T127
Test name
Test status
Simulation time 19308494814 ps
CPU time 328.37 seconds
Started Jun 13 01:28:16 PM PDT 24
Finished Jun 13 01:33:45 PM PDT 24
Peak memory 266684 kb
Host smart-9798c116-9213-4032-8eed-e96adebb870e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=110895437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.110895437
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1130511448
Short name T293
Test name
Test status
Simulation time 61221020934 ps
CPU time 3368.68 seconds
Started Jun 13 01:30:20 PM PDT 24
Finished Jun 13 02:26:30 PM PDT 24
Peak memory 289392 kb
Host smart-1197263e-c327-4427-a420-0256228fa8ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130511448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1130511448
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1592494431
Short name T291
Test name
Test status
Simulation time 51295361259 ps
CPU time 532.46 seconds
Started Jun 13 01:30:33 PM PDT 24
Finished Jun 13 01:39:27 PM PDT 24
Peak memory 248352 kb
Host smart-011f7c45-a48a-4283-929e-77b9495db81f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592494431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1592494431
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1233735238
Short name T161
Test name
Test status
Simulation time 17394478 ps
CPU time 1.34 seconds
Started Jun 13 01:28:25 PM PDT 24
Finished Jun 13 01:28:27 PM PDT 24
Peak memory 237176 kb
Host smart-a74b2f5e-95fe-4416-8896-55d24c50ec16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1233735238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1233735238
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.2753432069
Short name T58
Test name
Test status
Simulation time 159196642892 ps
CPU time 2358.87 seconds
Started Jun 13 01:29:36 PM PDT 24
Finished Jun 13 02:08:56 PM PDT 24
Peak memory 288836 kb
Host smart-22ba677d-0ca1-485f-a9bb-36d642345359
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753432069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.2753432069
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.3868818669
Short name T49
Test name
Test status
Simulation time 32395277368 ps
CPU time 3168.31 seconds
Started Jun 13 01:29:16 PM PDT 24
Finished Jun 13 02:22:05 PM PDT 24
Peak memory 322724 kb
Host smart-45c02375-c5cc-405b-8a56-a8b1667041a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868818669 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.3868818669
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1423622985
Short name T290
Test name
Test status
Simulation time 34267337218 ps
CPU time 390.91 seconds
Started Jun 13 01:30:01 PM PDT 24
Finished Jun 13 01:36:33 PM PDT 24
Peak memory 256948 kb
Host smart-d5720bc9-ca4a-4872-ae40-f033b4de51a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423622985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1423622985
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2802297548
Short name T155
Test name
Test status
Simulation time 3353638531 ps
CPU time 227.28 seconds
Started Jun 13 01:28:22 PM PDT 24
Finished Jun 13 01:32:10 PM PDT 24
Peak memory 265552 kb
Host smart-01b2496c-2730-4906-acb7-e38a6c86948c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2802297548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2802297548
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.4260569353
Short name T160
Test name
Test status
Simulation time 1075242697 ps
CPU time 74.48 seconds
Started Jun 13 01:28:33 PM PDT 24
Finished Jun 13 01:29:47 PM PDT 24
Peak memory 240784 kb
Host smart-39cd7aed-48b3-4241-a575-a9c3abf0c750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4260569353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.4260569353
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.1125581745
Short name T242
Test name
Test status
Simulation time 275045824751 ps
CPU time 7752.2 seconds
Started Jun 13 01:30:08 PM PDT 24
Finished Jun 13 03:39:22 PM PDT 24
Peak memory 371276 kb
Host smart-28a8fdb6-9858-452a-a633-644441e9f81b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125581745 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.1125581745
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1370993882
Short name T250
Test name
Test status
Simulation time 34398392055 ps
CPU time 2171.33 seconds
Started Jun 13 01:31:41 PM PDT 24
Finished Jun 13 02:07:54 PM PDT 24
Peak memory 289824 kb
Host smart-c4c1c524-a849-4825-8082-3a583e28fa80
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370993882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1370993882
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.20754231
Short name T264
Test name
Test status
Simulation time 12783646655 ps
CPU time 476.81 seconds
Started Jun 13 02:33:05 PM PDT 24
Finished Jun 13 02:41:04 PM PDT 24
Peak memory 256660 kb
Host smart-0c71fe81-2733-48e6-a236-359875b10041
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20754231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.20754231
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.515820482
Short name T265
Test name
Test status
Simulation time 3088691967 ps
CPU time 121.18 seconds
Started Jun 13 01:28:54 PM PDT 24
Finished Jun 13 01:30:56 PM PDT 24
Peak memory 248396 kb
Host smart-35b5a71d-fb77-4e29-a3f3-23040337e67b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515820482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.515820482
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1079073724
Short name T303
Test name
Test status
Simulation time 110513020062 ps
CPU time 1693.76 seconds
Started Jun 13 01:32:31 PM PDT 24
Finished Jun 13 02:00:45 PM PDT 24
Peak memory 272980 kb
Host smart-3c352b0a-e4ff-46bf-a72e-f8e304bcbddd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079073724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1079073724
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.11065675
Short name T171
Test name
Test status
Simulation time 477484878 ps
CPU time 3.64 seconds
Started Jun 13 01:28:23 PM PDT 24
Finished Jun 13 01:28:27 PM PDT 24
Peak memory 237612 kb
Host smart-3e3f82e2-662e-4a4f-ab8c-e7019f10c254
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=11065675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.11065675
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.4042733638
Short name T83
Test name
Test status
Simulation time 553559991 ps
CPU time 36.1 seconds
Started Jun 13 01:32:31 PM PDT 24
Finished Jun 13 01:33:07 PM PDT 24
Peak memory 255468 kb
Host smart-14cea91c-d61d-4fdc-925b-ae9b0cc96ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40427
33638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.4042733638
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3463407711
Short name T321
Test name
Test status
Simulation time 119158185879 ps
CPU time 1794.78 seconds
Started Jun 13 01:28:57 PM PDT 24
Finished Jun 13 01:58:53 PM PDT 24
Peak memory 273440 kb
Host smart-8c38f8e4-de95-4756-a339-0d14f683c049
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463407711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3463407711
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2360547137
Short name T26
Test name
Test status
Simulation time 8897097579 ps
CPU time 195.28 seconds
Started Jun 13 01:30:11 PM PDT 24
Finished Jun 13 01:33:27 PM PDT 24
Peak memory 257336 kb
Host smart-f6175651-5075-4e08-80fd-ab22879e192b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360547137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2360547137
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.356177508
Short name T144
Test name
Test status
Simulation time 3890472383 ps
CPU time 349.58 seconds
Started Jun 13 01:28:11 PM PDT 24
Finished Jun 13 01:34:02 PM PDT 24
Peak memory 265640 kb
Host smart-8050b39d-1d9d-4f81-a89e-c1aeecf6ccdc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356177508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.356177508
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.687453740
Short name T209
Test name
Test status
Simulation time 31361112 ps
CPU time 3.32 seconds
Started Jun 13 01:28:46 PM PDT 24
Finished Jun 13 01:28:50 PM PDT 24
Peak memory 249244 kb
Host smart-232b0b90-c7b3-4e4e-8797-a5bdef195bcc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=687453740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.687453740
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2811577243
Short name T200
Test name
Test status
Simulation time 23394504 ps
CPU time 2.2 seconds
Started Jun 13 01:28:46 PM PDT 24
Finished Jun 13 01:28:49 PM PDT 24
Peak memory 249184 kb
Host smart-405f5381-b604-4b38-9215-712f5d8fa4b6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2811577243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2811577243
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2336960956
Short name T205
Test name
Test status
Simulation time 14297365 ps
CPU time 2.63 seconds
Started Jun 13 01:29:24 PM PDT 24
Finished Jun 13 01:29:29 PM PDT 24
Peak memory 249252 kb
Host smart-5d80f04d-cba5-49b4-9bb2-6389cb89e602
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2336960956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2336960956
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2999667767
Short name T68
Test name
Test status
Simulation time 36229303 ps
CPU time 3.13 seconds
Started Jun 13 01:29:40 PM PDT 24
Finished Jun 13 01:29:44 PM PDT 24
Peak memory 249224 kb
Host smart-2734f719-2003-4c96-b485-112294851d8d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2999667767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2999667767
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.106002538
Short name T750
Test name
Test status
Simulation time 9887365 ps
CPU time 1.24 seconds
Started Jun 13 01:28:38 PM PDT 24
Finished Jun 13 01:28:40 PM PDT 24
Peak memory 237388 kb
Host smart-7fa52e8c-1268-4be6-aa31-a625a1e0e08c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=106002538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.106002538
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3135983429
Short name T305
Test name
Test status
Simulation time 63399917314 ps
CPU time 1874.61 seconds
Started Jun 13 01:29:33 PM PDT 24
Finished Jun 13 02:00:49 PM PDT 24
Peak memory 283448 kb
Host smart-ba4137b6-b992-4147-84b1-05271bc74849
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135983429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3135983429
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3459935406
Short name T87
Test name
Test status
Simulation time 16711661935 ps
CPU time 807.74 seconds
Started Jun 13 01:29:42 PM PDT 24
Finished Jun 13 01:43:10 PM PDT 24
Peak memory 265564 kb
Host smart-c17643a9-0d7b-4c76-8369-08f040f13e3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459935406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3459935406
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.166144272
Short name T230
Test name
Test status
Simulation time 28433828870 ps
CPU time 315.68 seconds
Started Jun 13 01:29:47 PM PDT 24
Finished Jun 13 01:35:03 PM PDT 24
Peak memory 248796 kb
Host smart-afbf838b-a8d3-44fc-aae0-1b16f148a320
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166144272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.166144272
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.149753798
Short name T106
Test name
Test status
Simulation time 5110186724 ps
CPU time 440.74 seconds
Started Jun 13 01:29:55 PM PDT 24
Finished Jun 13 01:37:17 PM PDT 24
Peak memory 267332 kb
Host smart-039a1448-fb33-4003-87a2-c0d49ca9b101
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149753798 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.149753798
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.166311095
Short name T79
Test name
Test status
Simulation time 977904136 ps
CPU time 54.7 seconds
Started Jun 13 01:30:46 PM PDT 24
Finished Jun 13 01:31:41 PM PDT 24
Peak memory 249140 kb
Host smart-b7f97761-b5c0-44d5-b120-dba75fd0ff0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16631
1095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.166311095
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1130396036
Short name T314
Test name
Test status
Simulation time 9207980687 ps
CPU time 362.21 seconds
Started Jun 13 01:49:19 PM PDT 24
Finished Jun 13 01:55:22 PM PDT 24
Peak memory 248708 kb
Host smart-91c34f87-f5ff-4c90-81c4-525426b0e0d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130396036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1130396036
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3774086786
Short name T306
Test name
Test status
Simulation time 30449184074 ps
CPU time 1772.86 seconds
Started Jun 13 02:12:02 PM PDT 24
Finished Jun 13 02:41:36 PM PDT 24
Peak memory 282560 kb
Host smart-ddd3c395-8c93-4426-9181-8b5e161288e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774086786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3774086786
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1120143211
Short name T257
Test name
Test status
Simulation time 524478825 ps
CPU time 34.19 seconds
Started Jun 13 01:29:16 PM PDT 24
Finished Jun 13 01:29:52 PM PDT 24
Peak memory 255348 kb
Host smart-5b8e6c6b-5b05-4944-8660-a6318b6936cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11201
43211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1120143211
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3502837713
Short name T118
Test name
Test status
Simulation time 48902912622 ps
CPU time 2940.3 seconds
Started Jun 13 01:30:52 PM PDT 24
Finished Jun 13 02:19:53 PM PDT 24
Peak memory 289568 kb
Host smart-5194ae44-2a73-4fc6-b11c-dc885d2dec48
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502837713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3502837713
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1668023142
Short name T126
Test name
Test status
Simulation time 7225487581 ps
CPU time 223.66 seconds
Started Jun 13 01:28:28 PM PDT 24
Finished Jun 13 01:32:12 PM PDT 24
Peak memory 265676 kb
Host smart-8e84e9ac-6ace-416e-9b3e-62135263d7c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1668023142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1668023142
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.728136521
Short name T25
Test name
Test status
Simulation time 6798107886 ps
CPU time 43.67 seconds
Started Jun 13 02:01:34 PM PDT 24
Finished Jun 13 02:02:19 PM PDT 24
Peak memory 256828 kb
Host smart-bfccde69-e5ca-43ca-b79f-19cb9ee6eab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72813
6521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.728136521
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2483454652
Short name T239
Test name
Test status
Simulation time 220046319 ps
CPU time 12.28 seconds
Started Jun 13 01:29:30 PM PDT 24
Finished Jun 13 01:29:42 PM PDT 24
Peak memory 256532 kb
Host smart-e04d0d36-f463-4647-8f4c-19854be5b92c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24834
54652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2483454652
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.662039282
Short name T274
Test name
Test status
Simulation time 85593697433 ps
CPU time 1371.26 seconds
Started Jun 13 01:29:46 PM PDT 24
Finished Jun 13 01:52:38 PM PDT 24
Peak memory 265544 kb
Host smart-545465c7-c657-46fa-b071-ca00e08c8d6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662039282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.662039282
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.2119916783
Short name T86
Test name
Test status
Simulation time 35827336650 ps
CPU time 2000.67 seconds
Started Jun 13 01:30:26 PM PDT 24
Finished Jun 13 02:03:47 PM PDT 24
Peak memory 289600 kb
Host smart-45bc7904-f40d-4695-a7d1-8ad8e5919dbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119916783 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.2119916783
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1186439332
Short name T47
Test name
Test status
Simulation time 869713284 ps
CPU time 19.39 seconds
Started Jun 13 01:30:28 PM PDT 24
Finished Jun 13 01:30:48 PM PDT 24
Peak memory 256140 kb
Host smart-322c0ba9-b7ca-401a-aacd-985f211d78e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11864
39332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1186439332
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2680088687
Short name T327
Test name
Test status
Simulation time 27169406851 ps
CPU time 1388.42 seconds
Started Jun 13 01:31:15 PM PDT 24
Finished Jun 13 01:54:24 PM PDT 24
Peak memory 289772 kb
Host smart-4cada5fb-ff81-4c2f-b63b-53f896e528d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680088687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2680088687
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.4057415403
Short name T32
Test name
Test status
Simulation time 15606735799 ps
CPU time 1535.77 seconds
Started Jun 13 01:32:13 PM PDT 24
Finished Jun 13 01:57:49 PM PDT 24
Peak memory 299116 kb
Host smart-ec2041bf-ae27-498a-900a-dbb22bd43286
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057415403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.4057415403
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.4060930391
Short name T240
Test name
Test status
Simulation time 7835015190 ps
CPU time 675.2 seconds
Started Jun 13 01:43:22 PM PDT 24
Finished Jun 13 01:54:38 PM PDT 24
Peak memory 272372 kb
Host smart-c5838cb7-5966-4b9d-8fee-b289e59c5e80
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060930391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.4060930391
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.1961296972
Short name T255
Test name
Test status
Simulation time 248373496972 ps
CPU time 1258.45 seconds
Started Jun 13 01:32:33 PM PDT 24
Finished Jun 13 01:53:32 PM PDT 24
Peak memory 287700 kb
Host smart-0839a49b-e642-46a7-a4b0-b996eee382b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961296972 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.1961296972
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3596133129
Short name T92
Test name
Test status
Simulation time 1313735021 ps
CPU time 33.93 seconds
Started Jun 13 01:37:18 PM PDT 24
Finished Jun 13 01:37:52 PM PDT 24
Peak memory 255228 kb
Host smart-38ae0462-cd33-41ff-af3e-e5842172015f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35961
33129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3596133129
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2932688226
Short name T128
Test name
Test status
Simulation time 12286191926 ps
CPU time 175.79 seconds
Started Jun 13 01:28:28 PM PDT 24
Finished Jun 13 01:31:25 PM PDT 24
Peak memory 272028 kb
Host smart-8c462b95-e11b-4a9a-81c4-50553a196e7b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2932688226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2932688226
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1224617264
Short name T169
Test name
Test status
Simulation time 2833918822 ps
CPU time 82.19 seconds
Started Jun 13 01:28:30 PM PDT 24
Finished Jun 13 01:29:53 PM PDT 24
Peak memory 237496 kb
Host smart-7a0d6079-182a-48a6-b3e4-61641f08af5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1224617264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1224617264
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3344340490
Short name T142
Test name
Test status
Simulation time 2484652898 ps
CPU time 96.1 seconds
Started Jun 13 01:28:04 PM PDT 24
Finished Jun 13 01:29:40 PM PDT 24
Peak memory 257476 kb
Host smart-39c14fe1-dc28-4d64-a87e-384c62cd3da1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3344340490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3344340490
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.128813254
Short name T168
Test name
Test status
Simulation time 25344203 ps
CPU time 2.37 seconds
Started Jun 13 01:28:27 PM PDT 24
Finished Jun 13 01:28:30 PM PDT 24
Peak memory 237352 kb
Host smart-a82f2e75-5649-4df9-b591-8550a496ae1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=128813254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.128813254
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3576549235
Short name T138
Test name
Test status
Simulation time 14240055054 ps
CPU time 363.67 seconds
Started Jun 13 01:28:34 PM PDT 24
Finished Jun 13 01:34:38 PM PDT 24
Peak memory 273804 kb
Host smart-3419a9d8-9e27-4b26-85c0-0009d99b438e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3576549235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3576549235
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1059714351
Short name T166
Test name
Test status
Simulation time 7334088877 ps
CPU time 33.55 seconds
Started Jun 13 01:28:28 PM PDT 24
Finished Jun 13 01:29:02 PM PDT 24
Peak memory 237524 kb
Host smart-c268f19e-5983-44ac-ac63-73f8285deed0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1059714351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1059714351
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1602909918
Short name T175
Test name
Test status
Simulation time 45628573 ps
CPU time 3.14 seconds
Started Jun 13 01:28:04 PM PDT 24
Finished Jun 13 01:28:08 PM PDT 24
Peak memory 237308 kb
Host smart-f9701547-afce-49ae-911c-4c02e90e921a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1602909918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1602909918
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3753470264
Short name T174
Test name
Test status
Simulation time 1930371227 ps
CPU time 46.67 seconds
Started Jun 13 01:28:10 PM PDT 24
Finished Jun 13 01:28:58 PM PDT 24
Peak memory 245688 kb
Host smart-ad58c6c8-eaf7-471d-a613-a77eb7eaf32b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3753470264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3753470264
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2437988704
Short name T164
Test name
Test status
Simulation time 2155679795 ps
CPU time 44.16 seconds
Started Jun 13 01:28:16 PM PDT 24
Finished Jun 13 01:29:01 PM PDT 24
Peak memory 240848 kb
Host smart-74fe04a5-4f2a-4c29-b164-b8f39c95ba68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2437988704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2437988704
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1788288044
Short name T178
Test name
Test status
Simulation time 7895042931 ps
CPU time 80.61 seconds
Started Jun 13 01:28:27 PM PDT 24
Finished Jun 13 01:29:48 PM PDT 24
Peak memory 240804 kb
Host smart-d7c4433e-f7d5-4e9d-9134-a23902edeeac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1788288044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1788288044
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.624854081
Short name T177
Test name
Test status
Simulation time 1426915307 ps
CPU time 41.59 seconds
Started Jun 13 01:28:00 PM PDT 24
Finished Jun 13 01:28:43 PM PDT 24
Peak memory 240736 kb
Host smart-4f0ba704-91c6-4cb0-9b74-629ff3229377
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=624854081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.624854081
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.899319859
Short name T176
Test name
Test status
Simulation time 160491890 ps
CPU time 22.47 seconds
Started Jun 13 01:28:03 PM PDT 24
Finished Jun 13 01:28:26 PM PDT 24
Peak memory 237444 kb
Host smart-1d77fc66-cc0e-4de3-99e7-240a71517bf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=899319859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.899319859
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.610733978
Short name T172
Test name
Test status
Simulation time 6272769615 ps
CPU time 45.06 seconds
Started Jun 13 01:28:21 PM PDT 24
Finished Jun 13 01:29:07 PM PDT 24
Peak memory 240844 kb
Host smart-9741daca-b2b2-4c3c-84e4-375595a40a19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=610733978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.610733978
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2511078956
Short name T170
Test name
Test status
Simulation time 109483645 ps
CPU time 3.26 seconds
Started Jun 13 01:28:34 PM PDT 24
Finished Jun 13 01:28:38 PM PDT 24
Peak memory 237452 kb
Host smart-ed793a48-581d-4da8-9e5f-763ba86c41d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2511078956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2511078956
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.4551133
Short name T167
Test name
Test status
Simulation time 53771987 ps
CPU time 4.15 seconds
Started Jun 13 01:28:40 PM PDT 24
Finished Jun 13 01:28:45 PM PDT 24
Peak memory 237360 kb
Host smart-702785ce-62c4-4372-b250-07f0e4680fd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4551133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.4551133
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3733202585
Short name T182
Test name
Test status
Simulation time 104770105 ps
CPU time 2.63 seconds
Started Jun 13 01:28:06 PM PDT 24
Finished Jun 13 01:28:10 PM PDT 24
Peak memory 237156 kb
Host smart-f030cb5f-02e4-452d-b1d3-16e9a0046b77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3733202585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3733202585
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3794820394
Short name T165
Test name
Test status
Simulation time 533217160 ps
CPU time 35.28 seconds
Started Jun 13 01:28:16 PM PDT 24
Finished Jun 13 01:28:52 PM PDT 24
Peak memory 237664 kb
Host smart-2228dbc0-8f13-46fe-a98e-7c77210a44b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3794820394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3794820394
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3689692935
Short name T173
Test name
Test status
Simulation time 60208299 ps
CPU time 2.82 seconds
Started Jun 13 01:28:17 PM PDT 24
Finished Jun 13 01:28:21 PM PDT 24
Peak memory 237444 kb
Host smart-b2a6cd7a-ed9b-440e-9c77-e8a2cb87e7e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3689692935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3689692935
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2803909563
Short name T185
Test name
Test status
Simulation time 1139781802 ps
CPU time 180.1 seconds
Started Jun 13 01:27:58 PM PDT 24
Finished Jun 13 01:31:00 PM PDT 24
Peak memory 240712 kb
Host smart-191c8b72-5a94-468a-a751-df1cb8a020f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2803909563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2803909563
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1439517605
Short name T793
Test name
Test status
Simulation time 2920098926 ps
CPU time 182.09 seconds
Started Jun 13 01:27:56 PM PDT 24
Finished Jun 13 01:30:59 PM PDT 24
Peak memory 236408 kb
Host smart-5f1c79d3-d892-4b14-98b5-ae5cce5c29fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1439517605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1439517605
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1902345991
Short name T189
Test name
Test status
Simulation time 22361135 ps
CPU time 4.03 seconds
Started Jun 13 01:28:13 PM PDT 24
Finished Jun 13 01:28:18 PM PDT 24
Peak memory 240696 kb
Host smart-e0d1bbac-0c9a-427a-b0a5-c3452cd29913
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1902345991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1902345991
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2468764483
Short name T713
Test name
Test status
Simulation time 35485264 ps
CPU time 5.36 seconds
Started Jun 13 01:28:12 PM PDT 24
Finished Jun 13 01:28:18 PM PDT 24
Peak memory 256492 kb
Host smart-4d202593-ed5f-49dc-82a0-8922b649c037
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468764483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2468764483
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3630013024
Short name T784
Test name
Test status
Simulation time 123173508 ps
CPU time 4.05 seconds
Started Jun 13 01:27:58 PM PDT 24
Finished Jun 13 01:28:03 PM PDT 24
Peak memory 240136 kb
Host smart-85b39be2-1604-436e-95ae-28fa2167e64a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3630013024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3630013024
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2036204811
Short name T778
Test name
Test status
Simulation time 7683255 ps
CPU time 1.32 seconds
Started Jun 13 01:28:00 PM PDT 24
Finished Jun 13 01:28:03 PM PDT 24
Peak memory 235392 kb
Host smart-622588f5-f246-43d5-b0e8-23efaf3392dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2036204811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2036204811
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1879867772
Short name T758
Test name
Test status
Simulation time 184405140 ps
CPU time 22.92 seconds
Started Jun 13 01:27:59 PM PDT 24
Finished Jun 13 01:28:24 PM PDT 24
Peak memory 244652 kb
Host smart-7d196c4e-203a-4f26-aafa-b711d85743c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1879867772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1879867772
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.391446286
Short name T147
Test name
Test status
Simulation time 4460783073 ps
CPU time 618.45 seconds
Started Jun 13 01:28:00 PM PDT 24
Finished Jun 13 01:38:20 PM PDT 24
Peak memory 272984 kb
Host smart-6c2741a9-1221-4fd0-a13f-05cb063e85bc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391446286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.391446286
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3014755255
Short name T795
Test name
Test status
Simulation time 552619029 ps
CPU time 19.17 seconds
Started Jun 13 01:27:59 PM PDT 24
Finished Jun 13 01:28:20 PM PDT 24
Peak memory 249032 kb
Host smart-ac379dae-9a04-435e-8ad2-9074f44adb17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3014755255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3014755255
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3064248112
Short name T180
Test name
Test status
Simulation time 7688447101 ps
CPU time 180.24 seconds
Started Jun 13 01:28:14 PM PDT 24
Finished Jun 13 01:31:15 PM PDT 24
Peak memory 240772 kb
Host smart-91e02c1b-8c6b-4855-bd08-b33eca97f14d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3064248112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3064248112
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.4237757941
Short name T736
Test name
Test status
Simulation time 6804433162 ps
CPU time 234.92 seconds
Started Jun 13 01:28:00 PM PDT 24
Finished Jun 13 01:31:57 PM PDT 24
Peak memory 240800 kb
Host smart-0426dc58-08d7-436f-862c-03d6a36e943d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4237757941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.4237757941
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1330577650
Short name T809
Test name
Test status
Simulation time 142106755 ps
CPU time 6.19 seconds
Started Jun 13 01:28:01 PM PDT 24
Finished Jun 13 01:28:08 PM PDT 24
Peak memory 240744 kb
Host smart-d787ab4e-dd0e-4d65-9f43-b0ffd9c8a939
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1330577650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1330577650
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.865065009
Short name T741
Test name
Test status
Simulation time 238678288 ps
CPU time 4.98 seconds
Started Jun 13 01:28:04 PM PDT 24
Finished Jun 13 01:28:09 PM PDT 24
Peak memory 239544 kb
Host smart-f10dead1-932d-4bd3-a4b9-9151df5e9d1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865065009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.865065009
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2567529424
Short name T808
Test name
Test status
Simulation time 294298820 ps
CPU time 5.16 seconds
Started Jun 13 01:27:57 PM PDT 24
Finished Jun 13 01:28:03 PM PDT 24
Peak memory 236340 kb
Host smart-44e0c365-d924-4628-ba4b-356b301d779f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2567529424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2567529424
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.657064437
Short name T779
Test name
Test status
Simulation time 13206094 ps
CPU time 1.72 seconds
Started Jun 13 01:28:04 PM PDT 24
Finished Jun 13 01:28:06 PM PDT 24
Peak memory 237356 kb
Host smart-e6bf9b42-c9d2-4211-b745-0efb7dc81178
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=657064437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.657064437
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3328458646
Short name T726
Test name
Test status
Simulation time 521226339 ps
CPU time 35.22 seconds
Started Jun 13 01:28:13 PM PDT 24
Finished Jun 13 01:28:49 PM PDT 24
Peak memory 245540 kb
Host smart-ffbfbf4c-ede4-4fd7-b20a-45ea8ef82b87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3328458646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3328458646
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.592636840
Short name T152
Test name
Test status
Simulation time 2257116230 ps
CPU time 239.32 seconds
Started Jun 13 01:27:58 PM PDT 24
Finished Jun 13 01:31:58 PM PDT 24
Peak memory 265780 kb
Host smart-189f193d-e4df-4679-818a-73e8859cef17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=592636840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.592636840
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.255962748
Short name T343
Test name
Test status
Simulation time 134704459245 ps
CPU time 1132.75 seconds
Started Jun 13 01:28:00 PM PDT 24
Finished Jun 13 01:46:54 PM PDT 24
Peak memory 273824 kb
Host smart-6a47538b-e137-4d26-a496-fe70ad6c063e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255962748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.255962748
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.118322684
Short name T819
Test name
Test status
Simulation time 65239505 ps
CPU time 7.75 seconds
Started Jun 13 01:27:59 PM PDT 24
Finished Jun 13 01:28:08 PM PDT 24
Peak memory 248532 kb
Host smart-cb41d8af-3970-4c4c-b7e4-a0179067da1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=118322684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.118322684
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.118044251
Short name T742
Test name
Test status
Simulation time 169153644 ps
CPU time 10.56 seconds
Started Jun 13 01:28:18 PM PDT 24
Finished Jun 13 01:28:29 PM PDT 24
Peak memory 239468 kb
Host smart-7f894228-ce77-4c23-a0e2-c751d7265b7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118044251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.118044251
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.622514920
Short name T732
Test name
Test status
Simulation time 35261469 ps
CPU time 5.72 seconds
Started Jun 13 01:28:17 PM PDT 24
Finished Jun 13 01:28:24 PM PDT 24
Peak memory 237268 kb
Host smart-46f07ab9-9204-4ec6-ba94-3d522b6b3a8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=622514920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.622514920
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.702859237
Short name T776
Test name
Test status
Simulation time 8863673 ps
CPU time 1.51 seconds
Started Jun 13 01:28:21 PM PDT 24
Finished Jun 13 01:28:23 PM PDT 24
Peak memory 236428 kb
Host smart-d3625a9e-550d-4f39-b87c-f071cb830d24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=702859237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.702859237
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2046812145
Short name T717
Test name
Test status
Simulation time 769925448 ps
CPU time 9.9 seconds
Started Jun 13 01:28:18 PM PDT 24
Finished Jun 13 01:28:29 PM PDT 24
Peak memory 244612 kb
Host smart-b15e5aca-148a-4de0-bbdc-96291adb1ee7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2046812145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2046812145
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.226084163
Short name T148
Test name
Test status
Simulation time 807455217 ps
CPU time 87.65 seconds
Started Jun 13 01:28:16 PM PDT 24
Finished Jun 13 01:29:45 PM PDT 24
Peak memory 265388 kb
Host smart-f109b1a6-ab3b-4feb-b3ed-dc8f720eee11
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=226084163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.226084163
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.672713447
Short name T813
Test name
Test status
Simulation time 1466529070 ps
CPU time 19.36 seconds
Started Jun 13 01:28:18 PM PDT 24
Finished Jun 13 01:28:38 PM PDT 24
Peak memory 248132 kb
Host smart-cca8edad-95dd-4f77-8d22-fab874bfbf07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=672713447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.672713447
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1634970845
Short name T158
Test name
Test status
Simulation time 38863473 ps
CPU time 3.11 seconds
Started Jun 13 01:28:21 PM PDT 24
Finished Jun 13 01:28:24 PM PDT 24
Peak memory 237404 kb
Host smart-1b2405fd-8379-44bb-8c30-6b21f41e59e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1634970845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1634970845
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1079381302
Short name T714
Test name
Test status
Simulation time 1973963807 ps
CPU time 7.57 seconds
Started Jun 13 01:28:27 PM PDT 24
Finished Jun 13 01:28:36 PM PDT 24
Peak memory 240052 kb
Host smart-dd83c1ec-36c6-42d1-926e-61fa3b85c595
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079381302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1079381302
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1219306515
Short name T773
Test name
Test status
Simulation time 485037978 ps
CPU time 5.22 seconds
Started Jun 13 01:28:26 PM PDT 24
Finished Jun 13 01:28:32 PM PDT 24
Peak memory 237140 kb
Host smart-9452ca78-789b-4cdc-b832-932eafff5142
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1219306515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1219306515
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2509022110
Short name T821
Test name
Test status
Simulation time 1051451681 ps
CPU time 12.39 seconds
Started Jun 13 01:28:27 PM PDT 24
Finished Jun 13 01:28:41 PM PDT 24
Peak memory 248940 kb
Host smart-609a0579-6398-4921-a6e5-c0a57874a6ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2509022110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2509022110
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1753487510
Short name T123
Test name
Test status
Simulation time 2074829887 ps
CPU time 333.23 seconds
Started Jun 13 01:28:17 PM PDT 24
Finished Jun 13 01:33:51 PM PDT 24
Peak memory 265760 kb
Host smart-54efbb9f-4769-4fa7-8924-b485c41c3618
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753487510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1753487510
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2509580641
Short name T768
Test name
Test status
Simulation time 90219643 ps
CPU time 10.79 seconds
Started Jun 13 01:28:16 PM PDT 24
Finished Jun 13 01:28:28 PM PDT 24
Peak memory 249116 kb
Host smart-d2a24b17-b17c-4207-947d-95c6c7f215f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2509580641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2509580641
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1962750267
Short name T238
Test name
Test status
Simulation time 1264635467 ps
CPU time 40.97 seconds
Started Jun 13 01:28:17 PM PDT 24
Finished Jun 13 01:28:59 PM PDT 24
Peak memory 240736 kb
Host smart-c8d644a8-a360-4bf1-9b7a-8c87d3b2635b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1962750267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1962750267
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2857303453
Short name T764
Test name
Test status
Simulation time 1339263207 ps
CPU time 11.84 seconds
Started Jun 13 01:28:23 PM PDT 24
Finished Jun 13 01:28:36 PM PDT 24
Peak memory 251220 kb
Host smart-2cd6f945-2cc3-4909-a83b-72f2fa499c15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857303453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2857303453
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2001957710
Short name T825
Test name
Test status
Simulation time 33655413 ps
CPU time 3.46 seconds
Started Jun 13 01:28:23 PM PDT 24
Finished Jun 13 01:28:27 PM PDT 24
Peak memory 240128 kb
Host smart-9732defb-9dbd-4426-9f85-6a437b31b2da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2001957710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2001957710
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.720387028
Short name T162
Test name
Test status
Simulation time 7569608 ps
CPU time 1.3 seconds
Started Jun 13 01:28:26 PM PDT 24
Finished Jun 13 01:28:28 PM PDT 24
Peak memory 235356 kb
Host smart-fb7481b0-3ec0-43db-a6b3-1044102022c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=720387028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.720387028
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.804300014
Short name T814
Test name
Test status
Simulation time 546072861 ps
CPU time 18.28 seconds
Started Jun 13 01:28:23 PM PDT 24
Finished Jun 13 01:28:42 PM PDT 24
Peak memory 245568 kb
Host smart-c7788f98-1766-48ea-a1ab-c960183daafe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=804300014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.804300014
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3360483407
Short name T130
Test name
Test status
Simulation time 3074187978 ps
CPU time 91.49 seconds
Started Jun 13 01:28:24 PM PDT 24
Finished Jun 13 01:29:56 PM PDT 24
Peak memory 265704 kb
Host smart-0c451fde-67b8-4a55-8bf6-6e8fe5d29220
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3360483407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3360483407
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1602434678
Short name T344
Test name
Test status
Simulation time 8571144052 ps
CPU time 282.44 seconds
Started Jun 13 01:28:24 PM PDT 24
Finished Jun 13 01:33:07 PM PDT 24
Peak memory 268648 kb
Host smart-856e0cf3-f524-4612-b387-065ab232a4e7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602434678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1602434678
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.157112814
Short name T820
Test name
Test status
Simulation time 41132983 ps
CPU time 5.92 seconds
Started Jun 13 01:28:28 PM PDT 24
Finished Jun 13 01:28:35 PM PDT 24
Peak memory 247860 kb
Host smart-02341491-0254-4644-b363-32bd7cf8b817
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=157112814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.157112814
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2396560753
Short name T796
Test name
Test status
Simulation time 42481299 ps
CPU time 6.67 seconds
Started Jun 13 01:28:24 PM PDT 24
Finished Jun 13 01:28:31 PM PDT 24
Peak memory 240808 kb
Host smart-3013561e-bbbb-4eba-99e0-ec8ee21c25b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396560753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2396560753
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.621026970
Short name T739
Test name
Test status
Simulation time 36015122 ps
CPU time 3.18 seconds
Started Jun 13 01:28:26 PM PDT 24
Finished Jun 13 01:28:30 PM PDT 24
Peak memory 239180 kb
Host smart-8a0f760d-1676-4d9b-ac71-aabc60a287f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=621026970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.621026970
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3009794665
Short name T822
Test name
Test status
Simulation time 7832549 ps
CPU time 1.42 seconds
Started Jun 13 01:28:28 PM PDT 24
Finished Jun 13 01:28:30 PM PDT 24
Peak memory 237300 kb
Host smart-55071436-2f2a-4a56-af42-fe81c0e01151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3009794665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3009794665
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.318084561
Short name T746
Test name
Test status
Simulation time 609098613 ps
CPU time 37.74 seconds
Started Jun 13 01:28:25 PM PDT 24
Finished Jun 13 01:29:03 PM PDT 24
Peak memory 244620 kb
Host smart-774eeb1d-afe5-4f71-8d88-57349e93ba0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=318084561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_out
standing.318084561
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.607271216
Short name T156
Test name
Test status
Simulation time 34826634793 ps
CPU time 1273.93 seconds
Started Jun 13 01:28:24 PM PDT 24
Finished Jun 13 01:49:38 PM PDT 24
Peak memory 273820 kb
Host smart-41d73675-7acb-43c9-b749-8df69e339f46
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607271216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.607271216
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2678001
Short name T722
Test name
Test status
Simulation time 1549722080 ps
CPU time 7.56 seconds
Started Jun 13 01:28:24 PM PDT 24
Finished Jun 13 01:28:32 PM PDT 24
Peak memory 249024 kb
Host smart-86afb1a4-c244-444b-bb07-852bbbcf2b5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2678001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2678001
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3227964120
Short name T757
Test name
Test status
Simulation time 135202588 ps
CPU time 6.23 seconds
Started Jun 13 01:28:27 PM PDT 24
Finished Jun 13 01:28:35 PM PDT 24
Peak memory 257156 kb
Host smart-7da2dc6b-c228-4bac-a3e9-9b2e5b95c029
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227964120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3227964120
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2847454233
Short name T812
Test name
Test status
Simulation time 62630392 ps
CPU time 5.08 seconds
Started Jun 13 01:28:30 PM PDT 24
Finished Jun 13 01:28:35 PM PDT 24
Peak memory 240204 kb
Host smart-a20c0906-af6c-4eb7-811a-31a216ea9493
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2847454233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2847454233
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2528702906
Short name T829
Test name
Test status
Simulation time 15026469 ps
CPU time 1.33 seconds
Started Jun 13 01:28:24 PM PDT 24
Finished Jun 13 01:28:26 PM PDT 24
Peak memory 236424 kb
Host smart-40425e1d-af4e-4312-b364-ef465501e0ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2528702906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2528702906
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.821360984
Short name T728
Test name
Test status
Simulation time 1068505590 ps
CPU time 21.82 seconds
Started Jun 13 01:28:32 PM PDT 24
Finished Jun 13 01:28:54 PM PDT 24
Peak memory 248968 kb
Host smart-1e794396-4383-4a54-8549-e39a91048287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=821360984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.821360984
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2545175223
Short name T145
Test name
Test status
Simulation time 3701764441 ps
CPU time 164.94 seconds
Started Jun 13 01:28:24 PM PDT 24
Finished Jun 13 01:31:09 PM PDT 24
Peak memory 266524 kb
Host smart-7cbe76f7-847c-40b5-abd8-153de9c74ae0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2545175223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2545175223
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2917223104
Short name T131
Test name
Test status
Simulation time 17393597455 ps
CPU time 1168.81 seconds
Started Jun 13 01:28:25 PM PDT 24
Finished Jun 13 01:47:54 PM PDT 24
Peak memory 273528 kb
Host smart-59f9f7cc-ac50-4338-975f-ac3ffa6cc984
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917223104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2917223104
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3494528262
Short name T711
Test name
Test status
Simulation time 119230004 ps
CPU time 8.71 seconds
Started Jun 13 01:28:22 PM PDT 24
Finished Jun 13 01:28:32 PM PDT 24
Peak memory 249000 kb
Host smart-51aeacdf-d4fd-4cc8-b33b-d6e2a245ba73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3494528262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3494528262
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.4220717139
Short name T723
Test name
Test status
Simulation time 61446800 ps
CPU time 9.48 seconds
Started Jun 13 01:28:32 PM PDT 24
Finished Jun 13 01:28:42 PM PDT 24
Peak memory 257192 kb
Host smart-f3f58bbf-f747-4cf3-9ba2-33326ea1fc3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220717139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.4220717139
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3433112103
Short name T817
Test name
Test status
Simulation time 427082873 ps
CPU time 8.92 seconds
Started Jun 13 01:28:30 PM PDT 24
Finished Jun 13 01:28:40 PM PDT 24
Peak memory 240672 kb
Host smart-e2673eb7-cb13-4bce-a7a6-99ed80c16d4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3433112103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3433112103
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1783359924
Short name T772
Test name
Test status
Simulation time 8084767 ps
CPU time 1.34 seconds
Started Jun 13 01:28:30 PM PDT 24
Finished Jun 13 01:28:32 PM PDT 24
Peak memory 237356 kb
Host smart-5768787c-a48b-4946-a36b-75e32cf0bc95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1783359924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1783359924
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.124866768
Short name T803
Test name
Test status
Simulation time 186237868 ps
CPU time 12.29 seconds
Started Jun 13 01:28:29 PM PDT 24
Finished Jun 13 01:28:42 PM PDT 24
Peak memory 245556 kb
Host smart-66fceeeb-ef73-4a23-b533-51000a9506d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=124866768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.124866768
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2668733645
Short name T132
Test name
Test status
Simulation time 8821771780 ps
CPU time 525.36 seconds
Started Jun 13 01:28:27 PM PDT 24
Finished Jun 13 01:37:14 PM PDT 24
Peak memory 269444 kb
Host smart-e9934789-e362-4817-a7e2-3213e60c926f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668733645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2668733645
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3872263045
Short name T709
Test name
Test status
Simulation time 97493988 ps
CPU time 12.2 seconds
Started Jun 13 01:28:30 PM PDT 24
Finished Jun 13 01:28:43 PM PDT 24
Peak memory 252812 kb
Host smart-547f250f-bd84-4e44-a048-7d8c7b4c67f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3872263045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3872263045
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3461836191
Short name T236
Test name
Test status
Simulation time 483443446 ps
CPU time 9.21 seconds
Started Jun 13 01:28:31 PM PDT 24
Finished Jun 13 01:28:41 PM PDT 24
Peak memory 237488 kb
Host smart-c744d502-e1ee-4550-b7f5-69f1d0d50d1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461836191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3461836191
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2389367152
Short name T712
Test name
Test status
Simulation time 64460116 ps
CPU time 4.45 seconds
Started Jun 13 01:28:33 PM PDT 24
Finished Jun 13 01:28:37 PM PDT 24
Peak memory 236392 kb
Host smart-00adcf72-63ec-40a5-89a7-636958f8bd86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2389367152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2389367152
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3927034115
Short name T163
Test name
Test status
Simulation time 9154001 ps
CPU time 1.56 seconds
Started Jun 13 01:28:28 PM PDT 24
Finished Jun 13 01:28:31 PM PDT 24
Peak memory 236424 kb
Host smart-ba9a6ef6-a90a-4cb6-b890-fc64f25df060
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3927034115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3927034115
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3460673265
Short name T787
Test name
Test status
Simulation time 246263615 ps
CPU time 17.8 seconds
Started Jun 13 01:28:29 PM PDT 24
Finished Jun 13 01:28:47 PM PDT 24
Peak memory 245548 kb
Host smart-11f65888-6c22-4084-8e6a-a848b5395872
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3460673265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3460673265
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2405006907
Short name T828
Test name
Test status
Simulation time 1208555962 ps
CPU time 21.36 seconds
Started Jun 13 01:28:30 PM PDT 24
Finished Jun 13 01:28:53 PM PDT 24
Peak memory 248880 kb
Host smart-e81dc765-c2c0-4f9a-a7b1-e030393c57d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2405006907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2405006907
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3896024638
Short name T816
Test name
Test status
Simulation time 118142058 ps
CPU time 5.67 seconds
Started Jun 13 01:28:31 PM PDT 24
Finished Jun 13 01:28:37 PM PDT 24
Peak memory 249032 kb
Host smart-b37409da-81b0-411b-a9b6-db610fbec2ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896024638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3896024638
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2090388838
Short name T800
Test name
Test status
Simulation time 262690339 ps
CPU time 5.16 seconds
Started Jun 13 01:28:31 PM PDT 24
Finished Jun 13 01:28:37 PM PDT 24
Peak memory 237240 kb
Host smart-cf23b9d7-b4c2-4dea-b390-9ec626783167
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2090388838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2090388838
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1759299080
Short name T806
Test name
Test status
Simulation time 8911818 ps
CPU time 1.53 seconds
Started Jun 13 01:28:29 PM PDT 24
Finished Jun 13 01:28:31 PM PDT 24
Peak memory 236424 kb
Host smart-2dccbb4d-d27a-4dcd-961d-091bf86e6b93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1759299080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1759299080
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.156997426
Short name T724
Test name
Test status
Simulation time 640173567 ps
CPU time 25.54 seconds
Started Jun 13 01:28:30 PM PDT 24
Finished Jun 13 01:28:56 PM PDT 24
Peak memory 245512 kb
Host smart-e38f8917-387a-4c7a-8d26-ced7b0b20dc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=156997426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.156997426
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2658556862
Short name T146
Test name
Test status
Simulation time 2537539003 ps
CPU time 377.38 seconds
Started Jun 13 01:28:32 PM PDT 24
Finished Jun 13 01:34:49 PM PDT 24
Peak memory 265600 kb
Host smart-e0f7a72e-3be2-4ffe-9e10-ff15cd5fa127
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658556862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2658556862
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2577536408
Short name T747
Test name
Test status
Simulation time 50026224 ps
CPU time 6.15 seconds
Started Jun 13 01:28:33 PM PDT 24
Finished Jun 13 01:28:40 PM PDT 24
Peak memory 249060 kb
Host smart-f0546a30-d808-4285-9292-41d2f0a58ab5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2577536408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2577536408
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1395831352
Short name T769
Test name
Test status
Simulation time 263479073 ps
CPU time 8.19 seconds
Started Jun 13 01:28:34 PM PDT 24
Finished Jun 13 01:28:43 PM PDT 24
Peak memory 237968 kb
Host smart-c4e316ee-6258-4018-a61d-3a5730a40f33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395831352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1395831352
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3842708960
Short name T770
Test name
Test status
Simulation time 66139562 ps
CPU time 5.47 seconds
Started Jun 13 01:28:34 PM PDT 24
Finished Jun 13 01:28:40 PM PDT 24
Peak memory 237276 kb
Host smart-b6f58ab6-111e-4d9e-b525-109d97960e6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3842708960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3842708960
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.4088802945
Short name T731
Test name
Test status
Simulation time 16389746 ps
CPU time 1.3 seconds
Started Jun 13 01:28:34 PM PDT 24
Finished Jun 13 01:28:35 PM PDT 24
Peak memory 235436 kb
Host smart-6658c5fe-dd25-4756-af08-9b2785a77238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4088802945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.4088802945
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3897582112
Short name T716
Test name
Test status
Simulation time 370455131 ps
CPU time 24.88 seconds
Started Jun 13 01:28:35 PM PDT 24
Finished Jun 13 01:29:01 PM PDT 24
Peak memory 245544 kb
Host smart-85393634-5842-4528-a347-7d293abd0a23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3897582112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3897582112
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.823660004
Short name T149
Test name
Test status
Simulation time 23944096376 ps
CPU time 559.3 seconds
Started Jun 13 01:28:30 PM PDT 24
Finished Jun 13 01:37:50 PM PDT 24
Peak memory 265608 kb
Host smart-293809dd-d9c6-4e42-9635-0bf7b68637c7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823660004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.823660004
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1609828946
Short name T775
Test name
Test status
Simulation time 246186317 ps
CPU time 10.45 seconds
Started Jun 13 01:28:32 PM PDT 24
Finished Jun 13 01:28:43 PM PDT 24
Peak memory 249156 kb
Host smart-3da0bb65-bfc3-436e-b62b-b60438d2f897
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1609828946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1609828946
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1979419397
Short name T810
Test name
Test status
Simulation time 711510714 ps
CPU time 10.44 seconds
Started Jun 13 01:28:33 PM PDT 24
Finished Jun 13 01:28:44 PM PDT 24
Peak memory 239432 kb
Host smart-77ee0cf7-2cab-4916-b7c2-b07c98ea1651
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979419397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1979419397
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.176388270
Short name T179
Test name
Test status
Simulation time 386262452 ps
CPU time 5.06 seconds
Started Jun 13 01:28:36 PM PDT 24
Finished Jun 13 01:28:42 PM PDT 24
Peak memory 236332 kb
Host smart-f09ea9d9-66bc-439a-9f6d-9ef388b8d0df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=176388270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.176388270
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.887064656
Short name T341
Test name
Test status
Simulation time 10353071 ps
CPU time 1.26 seconds
Started Jun 13 01:28:35 PM PDT 24
Finished Jun 13 01:28:37 PM PDT 24
Peak memory 237376 kb
Host smart-363c49c8-84d6-444b-b2a9-43e34ac7e8fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=887064656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.887064656
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3291599177
Short name T811
Test name
Test status
Simulation time 388293160 ps
CPU time 12.3 seconds
Started Jun 13 01:28:35 PM PDT 24
Finished Jun 13 01:28:48 PM PDT 24
Peak memory 245548 kb
Host smart-abd7df23-10b0-4d56-a082-b57a26eef12e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3291599177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3291599177
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2939611331
Short name T120
Test name
Test status
Simulation time 6396073354 ps
CPU time 126.31 seconds
Started Jun 13 01:28:34 PM PDT 24
Finished Jun 13 01:30:42 PM PDT 24
Peak memory 257452 kb
Host smart-285ddbe1-c654-44a6-9334-efefa66ed79a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2939611331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.2939611331
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.4215924283
Short name T157
Test name
Test status
Simulation time 4497125983 ps
CPU time 329.49 seconds
Started Jun 13 01:28:35 PM PDT 24
Finished Jun 13 01:34:06 PM PDT 24
Peak memory 265844 kb
Host smart-afa8acbc-f7d8-4ea5-bb4a-2b92cebccdc4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215924283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.4215924283
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2391269513
Short name T826
Test name
Test status
Simulation time 345661980 ps
CPU time 22.01 seconds
Started Jun 13 01:28:35 PM PDT 24
Finished Jun 13 01:28:58 PM PDT 24
Peak memory 248860 kb
Host smart-83f252f8-e43c-4182-98a5-8f715e652b4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2391269513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2391269513
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1254541073
Short name T754
Test name
Test status
Simulation time 1004167491 ps
CPU time 70.44 seconds
Started Jun 13 01:28:14 PM PDT 24
Finished Jun 13 01:29:25 PM PDT 24
Peak memory 240708 kb
Host smart-65561e95-d921-42f3-b692-bff7f4b6b3d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1254541073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1254541073
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3770314002
Short name T751
Test name
Test status
Simulation time 10825910949 ps
CPU time 551.18 seconds
Started Jun 13 01:28:04 PM PDT 24
Finished Jun 13 01:37:15 PM PDT 24
Peak memory 237356 kb
Host smart-ff04d1b4-9f9a-4acb-93dd-48e765b80fad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3770314002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3770314002
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1303629521
Short name T759
Test name
Test status
Simulation time 244868221 ps
CPU time 9.85 seconds
Started Jun 13 01:28:13 PM PDT 24
Finished Jun 13 01:28:23 PM PDT 24
Peak memory 240696 kb
Host smart-d8d6a74d-650a-4bcb-8ee0-baa6bd2f4bd8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1303629521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1303629521
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1010106662
Short name T725
Test name
Test status
Simulation time 59057531 ps
CPU time 5.31 seconds
Started Jun 13 01:28:05 PM PDT 24
Finished Jun 13 01:28:11 PM PDT 24
Peak memory 239692 kb
Host smart-d6623cea-378d-4ef3-8dc8-da093d3c9806
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010106662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1010106662
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.4079930078
Short name T805
Test name
Test status
Simulation time 1151683861 ps
CPU time 9.03 seconds
Started Jun 13 01:28:06 PM PDT 24
Finished Jun 13 01:28:16 PM PDT 24
Peak memory 236336 kb
Host smart-624daacd-d434-47b0-9ff0-6c754bd6b702
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4079930078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.4079930078
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1605128950
Short name T785
Test name
Test status
Simulation time 7776339 ps
CPU time 1.33 seconds
Started Jun 13 01:28:08 PM PDT 24
Finished Jun 13 01:28:09 PM PDT 24
Peak memory 237360 kb
Host smart-2fc8ebbb-a4f4-49de-89b1-7624e5bc18d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1605128950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1605128950
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.705896190
Short name T745
Test name
Test status
Simulation time 1446495554 ps
CPU time 48.79 seconds
Started Jun 13 01:28:06 PM PDT 24
Finished Jun 13 01:28:56 PM PDT 24
Peak memory 245508 kb
Host smart-a9485042-10ca-40ab-97a2-c76f4a98f9ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=705896190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.705896190
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2587770043
Short name T133
Test name
Test status
Simulation time 15839895012 ps
CPU time 202.03 seconds
Started Jun 13 01:28:05 PM PDT 24
Finished Jun 13 01:31:28 PM PDT 24
Peak memory 273556 kb
Host smart-fc11820a-eaec-40f5-bdee-7129c8cfe0b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2587770043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2587770043
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2037866946
Short name T708
Test name
Test status
Simulation time 270799924 ps
CPU time 11.15 seconds
Started Jun 13 01:28:04 PM PDT 24
Finished Jun 13 01:28:16 PM PDT 24
Peak memory 248996 kb
Host smart-e2329ce2-a88f-4094-823b-c6c2821d2297
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2037866946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2037866946
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3931360048
Short name T761
Test name
Test status
Simulation time 11385930 ps
CPU time 1.62 seconds
Started Jun 13 01:28:40 PM PDT 24
Finished Jun 13 01:28:43 PM PDT 24
Peak memory 237356 kb
Host smart-a38b74d8-6486-4316-ac29-987431403692
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3931360048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3931360048
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3314571181
Short name T789
Test name
Test status
Simulation time 12592060 ps
CPU time 1.6 seconds
Started Jun 13 01:28:36 PM PDT 24
Finished Jun 13 01:28:38 PM PDT 24
Peak memory 236440 kb
Host smart-940e9d91-cdac-4ab2-8b28-c64e77bf9eb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3314571181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3314571181
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3103645312
Short name T790
Test name
Test status
Simulation time 9135876 ps
CPU time 1.51 seconds
Started Jun 13 01:28:40 PM PDT 24
Finished Jun 13 01:28:42 PM PDT 24
Peak memory 236408 kb
Host smart-c15d1442-83bc-4504-8d94-751c2b4323aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3103645312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.3103645312
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.426918166
Short name T765
Test name
Test status
Simulation time 9048708 ps
CPU time 1.56 seconds
Started Jun 13 01:28:38 PM PDT 24
Finished Jun 13 01:28:40 PM PDT 24
Peak memory 236460 kb
Host smart-d29b4a76-61b4-4e29-90bd-7bdfb0c9eb86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=426918166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.426918166
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1515549727
Short name T786
Test name
Test status
Simulation time 18531572 ps
CPU time 1.39 seconds
Started Jun 13 01:28:37 PM PDT 24
Finished Jun 13 01:28:39 PM PDT 24
Peak memory 236492 kb
Host smart-a039e458-a634-45cc-b877-4c76cecc9e90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1515549727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1515549727
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.669557185
Short name T782
Test name
Test status
Simulation time 9862758 ps
CPU time 1.24 seconds
Started Jun 13 01:28:35 PM PDT 24
Finished Jun 13 01:28:37 PM PDT 24
Peak memory 237356 kb
Host smart-d9c7054d-82ed-45ec-9fda-87ab4046b669
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=669557185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.669557185
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.494531960
Short name T735
Test name
Test status
Simulation time 11112781 ps
CPU time 1.33 seconds
Started Jun 13 01:28:39 PM PDT 24
Finished Jun 13 01:28:41 PM PDT 24
Peak memory 235396 kb
Host smart-bed56230-d0ba-4311-80a7-98b11319f476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=494531960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.494531960
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.463341603
Short name T760
Test name
Test status
Simulation time 11598347 ps
CPU time 1.29 seconds
Started Jun 13 01:28:35 PM PDT 24
Finished Jun 13 01:28:37 PM PDT 24
Peak memory 237252 kb
Host smart-026c1689-45e7-402f-aca2-d660a7e66940
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=463341603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.463341603
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.813772130
Short name T335
Test name
Test status
Simulation time 8537418 ps
CPU time 1.43 seconds
Started Jun 13 01:28:35 PM PDT 24
Finished Jun 13 01:28:37 PM PDT 24
Peak memory 237356 kb
Host smart-d5327e99-14c0-4ce2-bef1-ec86a9cbbc1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=813772130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.813772130
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1897261708
Short name T818
Test name
Test status
Simulation time 2226795099 ps
CPU time 159.56 seconds
Started Jun 13 01:28:13 PM PDT 24
Finished Jun 13 01:30:54 PM PDT 24
Peak memory 240764 kb
Host smart-d34205ac-aac9-44d6-bf91-f002c9f06f4d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1897261708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1897261708
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.498004312
Short name T191
Test name
Test status
Simulation time 3270303667 ps
CPU time 106.16 seconds
Started Jun 13 01:28:10 PM PDT 24
Finished Jun 13 01:29:57 PM PDT 24
Peak memory 236404 kb
Host smart-8f19b4b2-ef50-4aa6-91e0-5d890d19e479
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=498004312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.498004312
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.4139684783
Short name T791
Test name
Test status
Simulation time 90125350 ps
CPU time 5.43 seconds
Started Jun 13 01:28:13 PM PDT 24
Finished Jun 13 01:28:20 PM PDT 24
Peak memory 240696 kb
Host smart-e15f6b90-4f40-4337-a669-be0cedec7ca3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4139684783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.4139684783
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2976192808
Short name T823
Test name
Test status
Simulation time 115765787 ps
CPU time 5.12 seconds
Started Jun 13 01:28:10 PM PDT 24
Finished Jun 13 01:28:16 PM PDT 24
Peak memory 237628 kb
Host smart-ac1584d3-078b-4f7c-8b38-b74125179575
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976192808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2976192808
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2785149995
Short name T729
Test name
Test status
Simulation time 67405837 ps
CPU time 5.38 seconds
Started Jun 13 01:28:15 PM PDT 24
Finished Jun 13 01:28:21 PM PDT 24
Peak memory 237276 kb
Host smart-d27e61ed-9885-480c-a231-18316e10198e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2785149995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2785149995
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2205925792
Short name T738
Test name
Test status
Simulation time 6828864 ps
CPU time 1.46 seconds
Started Jun 13 01:28:04 PM PDT 24
Finished Jun 13 01:28:06 PM PDT 24
Peak memory 237352 kb
Host smart-79564407-2977-4250-9a41-783fee4d8e15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2205925792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2205925792
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1811821158
Short name T807
Test name
Test status
Simulation time 91463004 ps
CPU time 11.73 seconds
Started Jun 13 01:28:11 PM PDT 24
Finished Jun 13 01:28:23 PM PDT 24
Peak memory 244608 kb
Host smart-1c8fc948-004f-4808-a4a4-594eb9c42a6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1811821158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1811821158
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2148198345
Short name T139
Test name
Test status
Simulation time 4304174764 ps
CPU time 131.86 seconds
Started Jun 13 01:28:06 PM PDT 24
Finished Jun 13 01:30:18 PM PDT 24
Peak memory 257244 kb
Host smart-77254820-dba6-40a5-b1d7-5bfa7bc2e2cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2148198345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2148198345
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2939144652
Short name T143
Test name
Test status
Simulation time 4358436944 ps
CPU time 317.25 seconds
Started Jun 13 01:28:03 PM PDT 24
Finished Jun 13 01:33:21 PM PDT 24
Peak memory 265648 kb
Host smart-20bd86cc-97bd-470a-95d0-97a1e66e4e2e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939144652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2939144652
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1947031017
Short name T720
Test name
Test status
Simulation time 348223154 ps
CPU time 21.01 seconds
Started Jun 13 01:28:04 PM PDT 24
Finished Jun 13 01:28:26 PM PDT 24
Peak memory 249064 kb
Host smart-8f7c31ec-ea3a-4b33-aac8-a75eeba0f7e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1947031017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1947031017
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.716264847
Short name T777
Test name
Test status
Simulation time 6826572 ps
CPU time 1.39 seconds
Started Jun 13 01:28:37 PM PDT 24
Finished Jun 13 01:28:39 PM PDT 24
Peak memory 236476 kb
Host smart-397b1dfa-3d04-4015-a966-610823923bad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=716264847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.716264847
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1520346016
Short name T748
Test name
Test status
Simulation time 10919301 ps
CPU time 1.68 seconds
Started Jun 13 01:28:34 PM PDT 24
Finished Jun 13 01:28:37 PM PDT 24
Peak memory 236444 kb
Host smart-56a6a9dd-ccda-4e75-b438-a4101b13e29b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1520346016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1520346016
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3187174243
Short name T804
Test name
Test status
Simulation time 11628188 ps
CPU time 1.47 seconds
Started Jun 13 01:28:37 PM PDT 24
Finished Jun 13 01:28:39 PM PDT 24
Peak memory 236388 kb
Host smart-740fb4b4-6782-4b48-ad93-24991a85e6d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3187174243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3187174243
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.102880520
Short name T734
Test name
Test status
Simulation time 11556393 ps
CPU time 1.35 seconds
Started Jun 13 01:28:42 PM PDT 24
Finished Jun 13 01:28:44 PM PDT 24
Peak memory 236440 kb
Host smart-cfe1b508-9fe9-41d5-aefa-b2275b7f798b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=102880520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.102880520
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.23735239
Short name T340
Test name
Test status
Simulation time 18856971 ps
CPU time 1.87 seconds
Started Jun 13 01:28:36 PM PDT 24
Finished Jun 13 01:28:38 PM PDT 24
Peak memory 237360 kb
Host smart-89f99af2-f74d-4325-9511-168953d800b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=23735239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.23735239
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3798392444
Short name T336
Test name
Test status
Simulation time 6142766 ps
CPU time 1.47 seconds
Started Jun 13 01:28:39 PM PDT 24
Finished Jun 13 01:28:41 PM PDT 24
Peak memory 237352 kb
Host smart-96843955-cf0e-418d-9cbc-564a26d6a403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3798392444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3798392444
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2257417760
Short name T744
Test name
Test status
Simulation time 9215240 ps
CPU time 1.5 seconds
Started Jun 13 01:28:39 PM PDT 24
Finished Jun 13 01:28:41 PM PDT 24
Peak memory 237356 kb
Host smart-2d79ac7b-92aa-43fe-bd49-6192a120244f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2257417760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2257417760
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2325007630
Short name T339
Test name
Test status
Simulation time 24651905 ps
CPU time 1.32 seconds
Started Jun 13 01:28:42 PM PDT 24
Finished Jun 13 01:28:44 PM PDT 24
Peak memory 236440 kb
Host smart-ae50dc73-32f7-4f19-9830-1332c6504e24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2325007630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2325007630
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3295704976
Short name T762
Test name
Test status
Simulation time 11035519 ps
CPU time 1.41 seconds
Started Jun 13 01:28:37 PM PDT 24
Finished Jun 13 01:28:39 PM PDT 24
Peak memory 235376 kb
Host smart-67cdc151-642f-4e7c-b42b-f5b714419224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3295704976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3295704976
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3863118844
Short name T338
Test name
Test status
Simulation time 11291170 ps
CPU time 1.56 seconds
Started Jun 13 01:28:40 PM PDT 24
Finished Jun 13 01:28:43 PM PDT 24
Peak memory 236380 kb
Host smart-6c7bb860-5555-4294-92ae-d66118d11a8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3863118844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3863118844
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2423217964
Short name T187
Test name
Test status
Simulation time 2007983514 ps
CPU time 68.55 seconds
Started Jun 13 01:28:10 PM PDT 24
Finished Jun 13 01:29:19 PM PDT 24
Peak memory 240720 kb
Host smart-7c0ec4c3-1fef-4793-8a29-227b4d59eaaa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2423217964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2423217964
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1164673212
Short name T190
Test name
Test status
Simulation time 5692613131 ps
CPU time 358.72 seconds
Started Jun 13 01:28:12 PM PDT 24
Finished Jun 13 01:34:11 PM PDT 24
Peak memory 240760 kb
Host smart-75e499b1-07ac-4343-a578-14ecdec91dd5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1164673212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1164673212
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2302852174
Short name T737
Test name
Test status
Simulation time 268359800 ps
CPU time 4.66 seconds
Started Jun 13 01:28:20 PM PDT 24
Finished Jun 13 01:28:26 PM PDT 24
Peak memory 240708 kb
Host smart-ba4f026f-c8a4-4dcb-a021-d1eca3708a9f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2302852174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2302852174
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3383455281
Short name T774
Test name
Test status
Simulation time 200953009 ps
CPU time 14.52 seconds
Started Jun 13 01:28:11 PM PDT 24
Finished Jun 13 01:28:26 PM PDT 24
Peak memory 243136 kb
Host smart-169f5638-123a-470f-b2c5-20d61caa653d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383455281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3383455281
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3463973580
Short name T753
Test name
Test status
Simulation time 1248193359 ps
CPU time 10.16 seconds
Started Jun 13 01:28:10 PM PDT 24
Finished Jun 13 01:28:20 PM PDT 24
Peak memory 240696 kb
Host smart-c385bf1e-b0d7-435b-8915-3fcbe71a5882
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3463973580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3463973580
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3426049199
Short name T801
Test name
Test status
Simulation time 10463636 ps
CPU time 1.27 seconds
Started Jun 13 01:28:12 PM PDT 24
Finished Jun 13 01:28:14 PM PDT 24
Peak memory 235396 kb
Host smart-c1cd6573-27da-4d3f-9bbb-850a4c7fe64e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3426049199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3426049199
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.403617014
Short name T733
Test name
Test status
Simulation time 609387713 ps
CPU time 26.77 seconds
Started Jun 13 01:28:10 PM PDT 24
Finished Jun 13 01:28:37 PM PDT 24
Peak memory 245588 kb
Host smart-f31aee68-1a39-471f-a20b-2d7524f17534
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=403617014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.403617014
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2927286349
Short name T136
Test name
Test status
Simulation time 3450493477 ps
CPU time 99.61 seconds
Started Jun 13 01:28:10 PM PDT 24
Finished Jun 13 01:29:50 PM PDT 24
Peak memory 265688 kb
Host smart-fd25391a-65a6-4a30-9fcb-0b79e34cd654
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2927286349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2927286349
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2943836027
Short name T721
Test name
Test status
Simulation time 190767664 ps
CPU time 11.64 seconds
Started Jun 13 01:28:11 PM PDT 24
Finished Jun 13 01:28:24 PM PDT 24
Peak memory 248812 kb
Host smart-1bc1e316-9a4e-48f4-bff0-7b95c5f5bd16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2943836027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2943836027
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3327930266
Short name T749
Test name
Test status
Simulation time 48183883 ps
CPU time 1.36 seconds
Started Jun 13 01:28:40 PM PDT 24
Finished Jun 13 01:28:42 PM PDT 24
Peak memory 235368 kb
Host smart-10972322-f3de-47d1-b5fe-2815ac68169a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3327930266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3327930266
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1732100024
Short name T337
Test name
Test status
Simulation time 6643060 ps
CPU time 1.52 seconds
Started Jun 13 01:28:36 PM PDT 24
Finished Jun 13 01:28:38 PM PDT 24
Peak memory 237308 kb
Host smart-9ce08d28-858d-43c4-80ac-714932248c3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1732100024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1732100024
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2894059298
Short name T781
Test name
Test status
Simulation time 6709265 ps
CPU time 1.4 seconds
Started Jun 13 01:28:41 PM PDT 24
Finished Jun 13 01:28:43 PM PDT 24
Peak memory 237368 kb
Host smart-cb1af686-a717-4167-85ab-97f0fa5ec3f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2894059298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2894059298
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1454389728
Short name T827
Test name
Test status
Simulation time 17069420 ps
CPU time 1.34 seconds
Started Jun 13 01:28:43 PM PDT 24
Finished Jun 13 01:28:45 PM PDT 24
Peak memory 236448 kb
Host smart-03b380f7-184a-4e22-b812-e2b11474d6d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1454389728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1454389728
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3405779453
Short name T794
Test name
Test status
Simulation time 14197330 ps
CPU time 1.34 seconds
Started Jun 13 01:28:41 PM PDT 24
Finished Jun 13 01:28:43 PM PDT 24
Peak memory 237356 kb
Host smart-6dba76f5-27ab-4d3c-95aa-6df16e77971b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3405779453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3405779453
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2068903128
Short name T815
Test name
Test status
Simulation time 9921490 ps
CPU time 1.4 seconds
Started Jun 13 01:28:41 PM PDT 24
Finished Jun 13 01:28:43 PM PDT 24
Peak memory 237352 kb
Host smart-3541354e-af80-45ff-8e03-ec2013ffefd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2068903128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2068903128
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1530957940
Short name T824
Test name
Test status
Simulation time 13457335 ps
CPU time 1.69 seconds
Started Jun 13 01:28:46 PM PDT 24
Finished Jun 13 01:28:48 PM PDT 24
Peak memory 236388 kb
Host smart-3cedd31b-a6a9-4d94-9a1d-ed18ddc9011f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1530957940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1530957940
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.635081911
Short name T727
Test name
Test status
Simulation time 14009385 ps
CPU time 1.33 seconds
Started Jun 13 01:28:46 PM PDT 24
Finished Jun 13 01:28:48 PM PDT 24
Peak memory 236432 kb
Host smart-cfc2e288-c520-4905-9eee-202b6ad90394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=635081911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.635081911
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.4130996586
Short name T798
Test name
Test status
Simulation time 20777138 ps
CPU time 1.44 seconds
Started Jun 13 01:28:42 PM PDT 24
Finished Jun 13 01:28:45 PM PDT 24
Peak memory 237360 kb
Host smart-4ea5a797-dd49-4baf-a1b3-4781b836d38b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4130996586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.4130996586
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.568843830
Short name T730
Test name
Test status
Simulation time 169659880 ps
CPU time 6.4 seconds
Started Jun 13 01:28:09 PM PDT 24
Finished Jun 13 01:28:15 PM PDT 24
Peak memory 249012 kb
Host smart-0dd1d7d8-02d9-448d-a391-ef0e9318e5c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568843830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.568843830
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2030813424
Short name T767
Test name
Test status
Simulation time 121722938 ps
CPU time 4.83 seconds
Started Jun 13 01:28:11 PM PDT 24
Finished Jun 13 01:28:17 PM PDT 24
Peak memory 237304 kb
Host smart-ae571a73-69e5-45c1-b90e-8b462c408d0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2030813424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2030813424
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2656935759
Short name T802
Test name
Test status
Simulation time 12197333 ps
CPU time 1.4 seconds
Started Jun 13 01:28:21 PM PDT 24
Finished Jun 13 01:28:23 PM PDT 24
Peak memory 237356 kb
Host smart-6f1b320d-b00d-44c2-a745-33cd838e4a9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2656935759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2656935759
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1634220893
Short name T186
Test name
Test status
Simulation time 744623940 ps
CPU time 18.57 seconds
Started Jun 13 01:28:15 PM PDT 24
Finished Jun 13 01:28:35 PM PDT 24
Peak memory 245588 kb
Host smart-eb3eb7ca-51ec-4b1e-997f-21d5be3e5770
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1634220893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.1634220893
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2877426857
Short name T125
Test name
Test status
Simulation time 24550022777 ps
CPU time 135.23 seconds
Started Jun 13 01:28:16 PM PDT 24
Finished Jun 13 01:30:32 PM PDT 24
Peak memory 265288 kb
Host smart-6ffa2280-1dd4-45e9-b89d-fdf2fdf11814
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2877426857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2877426857
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3950020422
Short name T151
Test name
Test status
Simulation time 7719319912 ps
CPU time 543.57 seconds
Started Jun 13 01:28:21 PM PDT 24
Finished Jun 13 01:37:25 PM PDT 24
Peak memory 265636 kb
Host smart-b98945dc-88f6-4756-98fc-4f56bc855954
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950020422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3950020422
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3001251782
Short name T797
Test name
Test status
Simulation time 61861324 ps
CPU time 6.31 seconds
Started Jun 13 01:28:12 PM PDT 24
Finished Jun 13 01:28:19 PM PDT 24
Peak memory 249144 kb
Host smart-f9e686a4-7e83-4263-826a-7d36041a9099
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3001251782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3001251782
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1060900641
Short name T228
Test name
Test status
Simulation time 370807298 ps
CPU time 8.75 seconds
Started Jun 13 01:28:18 PM PDT 24
Finished Jun 13 01:28:28 PM PDT 24
Peak memory 240776 kb
Host smart-fa6e76db-e54d-43cc-939a-747d60044c32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060900641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1060900641
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2972672886
Short name T718
Test name
Test status
Simulation time 52122153 ps
CPU time 5.01 seconds
Started Jun 13 01:28:18 PM PDT 24
Finished Jun 13 01:28:24 PM PDT 24
Peak memory 236344 kb
Host smart-68c29f02-46a5-40c7-ae74-a68390dfc917
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2972672886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2972672886
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3875116294
Short name T788
Test name
Test status
Simulation time 12876477 ps
CPU time 1.6 seconds
Started Jun 13 01:28:16 PM PDT 24
Finished Jun 13 01:28:19 PM PDT 24
Peak memory 237352 kb
Host smart-9b0095be-7b7b-4b6b-abdc-f3b9a74c39ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3875116294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3875116294
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.4113193549
Short name T740
Test name
Test status
Simulation time 9151058053 ps
CPU time 43.75 seconds
Started Jun 13 01:28:20 PM PDT 24
Finished Jun 13 01:29:04 PM PDT 24
Peak memory 245480 kb
Host smart-2c7f0c3d-ada1-4ea0-92b1-c86aa9f942d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4113193549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.4113193549
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2703799805
Short name T743
Test name
Test status
Simulation time 1510662224 ps
CPU time 16.45 seconds
Started Jun 13 01:28:15 PM PDT 24
Finished Jun 13 01:28:33 PM PDT 24
Peak memory 253120 kb
Host smart-e770c9da-a27e-457e-a3bc-014526feebc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2703799805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2703799805
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1048646986
Short name T181
Test name
Test status
Simulation time 139447169 ps
CPU time 9.04 seconds
Started Jun 13 01:28:15 PM PDT 24
Finished Jun 13 01:28:25 PM PDT 24
Peak memory 239820 kb
Host smart-b1fad2da-527d-40e8-9513-7adf4c2a2bd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048646986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1048646986
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2305055993
Short name T342
Test name
Test status
Simulation time 393732025 ps
CPU time 9.1 seconds
Started Jun 13 01:28:28 PM PDT 24
Finished Jun 13 01:28:38 PM PDT 24
Peak memory 237276 kb
Host smart-eec8a9b2-e0fb-4398-8849-c571dfc44cad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2305055993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2305055993
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2183135119
Short name T763
Test name
Test status
Simulation time 13928656 ps
CPU time 1.62 seconds
Started Jun 13 01:28:16 PM PDT 24
Finished Jun 13 01:28:18 PM PDT 24
Peak memory 236388 kb
Host smart-2e1c6ac6-1b73-4d02-9562-7e2f4379421e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2183135119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2183135119
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1890564022
Short name T719
Test name
Test status
Simulation time 5391726239 ps
CPU time 45.95 seconds
Started Jun 13 01:28:18 PM PDT 24
Finished Jun 13 01:29:04 PM PDT 24
Peak memory 245612 kb
Host smart-3089f91f-98c5-4d24-a646-8be4f1854eb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1890564022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1890564022
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3125875976
Short name T141
Test name
Test status
Simulation time 13595223043 ps
CPU time 555.53 seconds
Started Jun 13 01:28:18 PM PDT 24
Finished Jun 13 01:37:35 PM PDT 24
Peak memory 265648 kb
Host smart-c2c9de2f-0ee1-42e6-bc3c-06557fed7444
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125875976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3125875976
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2405712183
Short name T710
Test name
Test status
Simulation time 187549380 ps
CPU time 11.92 seconds
Started Jun 13 01:28:18 PM PDT 24
Finished Jun 13 01:28:31 PM PDT 24
Peak memory 249024 kb
Host smart-af578d61-774d-41f4-bb04-11d06b6c5a5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2405712183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2405712183
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1909401479
Short name T756
Test name
Test status
Simulation time 36773308 ps
CPU time 5.66 seconds
Started Jun 13 01:28:16 PM PDT 24
Finished Jun 13 01:28:23 PM PDT 24
Peak memory 252420 kb
Host smart-77044045-7146-4895-885c-73c9c275a114
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909401479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1909401479
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1647189972
Short name T799
Test name
Test status
Simulation time 189385451 ps
CPU time 8.34 seconds
Started Jun 13 01:28:21 PM PDT 24
Finished Jun 13 01:28:30 PM PDT 24
Peak memory 236328 kb
Host smart-82b40212-ddf5-459c-8666-a1361ecc7d8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1647189972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1647189972
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.661120017
Short name T755
Test name
Test status
Simulation time 7410900 ps
CPU time 1.47 seconds
Started Jun 13 01:28:17 PM PDT 24
Finished Jun 13 01:28:20 PM PDT 24
Peak memory 236428 kb
Host smart-8e595719-3d02-41bf-a60e-0c947759d132
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=661120017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.661120017
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2732099487
Short name T792
Test name
Test status
Simulation time 537304256 ps
CPU time 33.95 seconds
Started Jun 13 01:28:17 PM PDT 24
Finished Jun 13 01:28:52 PM PDT 24
Peak memory 248956 kb
Host smart-8153728f-1a84-4bbb-a616-71e859e4ac89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2732099487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2732099487
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1988989935
Short name T153
Test name
Test status
Simulation time 1725681731 ps
CPU time 130.66 seconds
Started Jun 13 01:28:27 PM PDT 24
Finished Jun 13 01:30:39 PM PDT 24
Peak memory 257560 kb
Host smart-f39643ac-025f-4c0f-90cb-0d807f9ba5dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1988989935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1988989935
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3883740113
Short name T752
Test name
Test status
Simulation time 180809025 ps
CPU time 14.07 seconds
Started Jun 13 01:28:17 PM PDT 24
Finished Jun 13 01:28:32 PM PDT 24
Peak memory 248720 kb
Host smart-cf22dd99-ff4e-4bf5-b0a1-a531cb0c7430
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3883740113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3883740113
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2967734749
Short name T780
Test name
Test status
Simulation time 32622792 ps
CPU time 6.13 seconds
Started Jun 13 01:28:16 PM PDT 24
Finished Jun 13 01:28:22 PM PDT 24
Peak memory 240772 kb
Host smart-0ddcab5b-655a-49a6-aac6-75c1fe4dc0fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967734749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2967734749
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2444665766
Short name T715
Test name
Test status
Simulation time 96497508 ps
CPU time 8.54 seconds
Started Jun 13 01:28:17 PM PDT 24
Finished Jun 13 01:28:26 PM PDT 24
Peak memory 236216 kb
Host smart-b7b00c00-57ac-4dc3-93f5-6a2ef45f6515
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2444665766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2444665766
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.172848767
Short name T766
Test name
Test status
Simulation time 18327509 ps
CPU time 1.34 seconds
Started Jun 13 01:28:15 PM PDT 24
Finished Jun 13 01:28:17 PM PDT 24
Peak memory 235276 kb
Host smart-7a7291ef-2f2d-40e2-a8c0-080ff6b7a016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=172848767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.172848767
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1654126932
Short name T771
Test name
Test status
Simulation time 490323956 ps
CPU time 21.1 seconds
Started Jun 13 01:28:21 PM PDT 24
Finished Jun 13 01:28:43 PM PDT 24
Peak memory 248968 kb
Host smart-cffab4ff-ca4a-44e8-a067-97d532073ff0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1654126932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1654126932
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2345165811
Short name T150
Test name
Test status
Simulation time 5098976386 ps
CPU time 174.9 seconds
Started Jun 13 01:28:18 PM PDT 24
Finished Jun 13 01:31:14 PM PDT 24
Peak memory 265652 kb
Host smart-f94acd5c-79d3-4c54-b70a-7dadd097cb3f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2345165811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2345165811
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.185205920
Short name T154
Test name
Test status
Simulation time 25118511108 ps
CPU time 513.96 seconds
Started Jun 13 01:28:22 PM PDT 24
Finished Jun 13 01:36:56 PM PDT 24
Peak memory 265608 kb
Host smart-52cd048a-ea7b-4fed-a30f-170567d48763
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185205920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.185205920
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2249495914
Short name T783
Test name
Test status
Simulation time 342799315 ps
CPU time 21.34 seconds
Started Jun 13 01:28:18 PM PDT 24
Finished Jun 13 01:28:40 PM PDT 24
Peak memory 254112 kb
Host smart-1f6a8751-6769-4c9e-840a-82784265f7c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2249495914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2249495914
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2228721384
Short name T460
Test name
Test status
Simulation time 129010958890 ps
CPU time 2166.07 seconds
Started Jun 13 01:28:44 PM PDT 24
Finished Jun 13 02:04:51 PM PDT 24
Peak memory 273584 kb
Host smart-097d4a03-0126-4250-bd9c-3be3bab1e55a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228721384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2228721384
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3729429607
Short name T601
Test name
Test status
Simulation time 1005502059 ps
CPU time 34.76 seconds
Started Jun 13 01:28:41 PM PDT 24
Finished Jun 13 01:29:16 PM PDT 24
Peak memory 249100 kb
Host smart-e489e419-b837-477a-b1a2-26acc3dccd68
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3729429607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3729429607
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2758007497
Short name T675
Test name
Test status
Simulation time 15031028763 ps
CPU time 207.24 seconds
Started Jun 13 01:28:43 PM PDT 24
Finished Jun 13 01:32:12 PM PDT 24
Peak memory 257248 kb
Host smart-f2e25f78-9f22-4afc-a992-25a5c11c1626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27580
07497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2758007497
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.475956087
Short name T21
Test name
Test status
Simulation time 1428611459 ps
CPU time 22.36 seconds
Started Jun 13 01:28:43 PM PDT 24
Finished Jun 13 01:29:06 PM PDT 24
Peak memory 254968 kb
Host smart-5c228211-1103-45d4-88da-3051d3b6bb2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47595
6087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.475956087
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2279301361
Short name T276
Test name
Test status
Simulation time 289403411792 ps
CPU time 1453.19 seconds
Started Jun 13 01:28:43 PM PDT 24
Finished Jun 13 01:52:57 PM PDT 24
Peak memory 273084 kb
Host smart-b1d94609-af1c-4b67-a458-051654e7272c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279301361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2279301361
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1111838650
Short name T528
Test name
Test status
Simulation time 3817616528 ps
CPU time 161.85 seconds
Started Jun 13 01:28:44 PM PDT 24
Finished Jun 13 01:31:27 PM PDT 24
Peak memory 248556 kb
Host smart-9fec8577-31ce-4b87-a6ca-c2c0b9c7b311
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111838650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1111838650
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1413682412
Short name T520
Test name
Test status
Simulation time 349550838 ps
CPU time 22.27 seconds
Started Jun 13 01:28:46 PM PDT 24
Finished Jun 13 01:29:09 PM PDT 24
Peak memory 249136 kb
Host smart-2a26ca18-78d5-4627-9b0e-be02a2955302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14136
82412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1413682412
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.67402259
Short name T368
Test name
Test status
Simulation time 4477677370 ps
CPU time 62.23 seconds
Started Jun 13 01:28:41 PM PDT 24
Finished Jun 13 01:29:44 PM PDT 24
Peak memory 256140 kb
Host smart-2f25ca42-3cc5-4ab2-a285-4761d7f0fe06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67402
259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.67402259
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.914629039
Short name T34
Test name
Test status
Simulation time 360045246 ps
CPU time 20.78 seconds
Started Jun 13 01:28:43 PM PDT 24
Finished Jun 13 01:29:04 PM PDT 24
Peak memory 273524 kb
Host smart-112dc258-346e-4a02-8379-81fa77f8147b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=914629039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.914629039
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1379446957
Short name T369
Test name
Test status
Simulation time 1573143496 ps
CPU time 27.06 seconds
Started Jun 13 01:28:42 PM PDT 24
Finished Jun 13 01:29:10 PM PDT 24
Peak memory 255428 kb
Host smart-3b3663a3-3b8c-4405-8ea9-090879d28700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13794
46957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1379446957
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1493078622
Short name T480
Test name
Test status
Simulation time 823410993 ps
CPU time 16 seconds
Started Jun 13 01:28:41 PM PDT 24
Finished Jun 13 01:28:57 PM PDT 24
Peak memory 256260 kb
Host smart-50682144-0ec2-4599-af6e-9a4bf7b5cbc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14930
78622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1493078622
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1277599857
Short name T16
Test name
Test status
Simulation time 73160803410 ps
CPU time 2155.29 seconds
Started Jun 13 01:28:46 PM PDT 24
Finished Jun 13 02:04:42 PM PDT 24
Peak memory 282872 kb
Host smart-f5cb9909-b3e7-4919-b9f5-6470ba1bd0d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277599857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1277599857
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2223058297
Short name T502
Test name
Test status
Simulation time 29776606435 ps
CPU time 1268.87 seconds
Started Jun 13 01:28:45 PM PDT 24
Finished Jun 13 01:49:54 PM PDT 24
Peak memory 289932 kb
Host smart-57d37c23-23ba-4a85-9a72-e98ea527fb8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223058297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2223058297
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1579928842
Short name T658
Test name
Test status
Simulation time 1624701987 ps
CPU time 20.35 seconds
Started Jun 13 01:28:44 PM PDT 24
Finished Jun 13 01:29:05 PM PDT 24
Peak memory 249068 kb
Host smart-e0d33760-48f2-470e-8668-3f3aba459cab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1579928842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1579928842
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.552840083
Short name T432
Test name
Test status
Simulation time 8484544953 ps
CPU time 169.48 seconds
Started Jun 13 01:28:44 PM PDT 24
Finished Jun 13 01:31:34 PM PDT 24
Peak memory 256128 kb
Host smart-65b176e5-d9b9-46d4-91b4-5f6b82e130ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55284
0083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.552840083
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.114098084
Short name T474
Test name
Test status
Simulation time 537910256 ps
CPU time 12.7 seconds
Started Jun 13 01:28:44 PM PDT 24
Finished Jun 13 01:28:57 PM PDT 24
Peak memory 248960 kb
Host smart-aab1ed86-4518-4c49-910f-e078773e48e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11409
8084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.114098084
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2101144431
Short name T543
Test name
Test status
Simulation time 35751508885 ps
CPU time 877.22 seconds
Started Jun 13 01:28:45 PM PDT 24
Finished Jun 13 01:43:23 PM PDT 24
Peak memory 273796 kb
Host smart-129629ea-d5bd-4ca9-80d0-21f5c23a0f3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101144431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2101144431
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.4285387547
Short name T511
Test name
Test status
Simulation time 52519878433 ps
CPU time 839.7 seconds
Started Jun 13 01:28:46 PM PDT 24
Finished Jun 13 01:42:46 PM PDT 24
Peak memory 273336 kb
Host smart-ace077af-2093-48e5-a081-679f06afe602
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285387547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.4285387547
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3916140341
Short name T300
Test name
Test status
Simulation time 8412018586 ps
CPU time 309.27 seconds
Started Jun 13 01:28:46 PM PDT 24
Finished Jun 13 01:33:56 PM PDT 24
Peak memory 248664 kb
Host smart-38b62ebb-6a6f-4cbe-a4f8-f32475ff53ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916140341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3916140341
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2165026556
Short name T30
Test name
Test status
Simulation time 925243945 ps
CPU time 58.67 seconds
Started Jun 13 01:28:44 PM PDT 24
Finished Jun 13 01:29:44 PM PDT 24
Peak memory 255752 kb
Host smart-e16bced4-e027-4c67-8d21-e3da2d5d3993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21650
26556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2165026556
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2600494255
Short name T697
Test name
Test status
Simulation time 2693908356 ps
CPU time 49.22 seconds
Started Jun 13 01:28:46 PM PDT 24
Finished Jun 13 01:29:36 PM PDT 24
Peak memory 255612 kb
Host smart-6fb41bb8-cd48-4142-93ee-b97eb07c7e33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26004
94255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2600494255
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1032468642
Short name T33
Test name
Test status
Simulation time 1133883385 ps
CPU time 11.79 seconds
Started Jun 13 01:28:44 PM PDT 24
Finished Jun 13 01:28:56 PM PDT 24
Peak memory 271604 kb
Host smart-d24b55c6-8e5e-4861-9041-74ab594ef56b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1032468642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1032468642
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2217530759
Short name T435
Test name
Test status
Simulation time 230470208 ps
CPU time 17.25 seconds
Started Jun 13 01:28:47 PM PDT 24
Finished Jun 13 01:29:05 PM PDT 24
Peak memory 249108 kb
Host smart-3b83a1e8-390f-4f6d-87d0-6eead64a2822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22175
30759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2217530759
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2364087719
Short name T370
Test name
Test status
Simulation time 1415077236 ps
CPU time 45.26 seconds
Started Jun 13 01:28:44 PM PDT 24
Finished Jun 13 01:29:30 PM PDT 24
Peak memory 249048 kb
Host smart-7771e4ab-2708-49b1-8cd8-7e1c661c5414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23640
87719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2364087719
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.590329953
Short name T494
Test name
Test status
Simulation time 1000439112005 ps
CPU time 3497.87 seconds
Started Jun 13 01:28:43 PM PDT 24
Finished Jun 13 02:27:02 PM PDT 24
Peak memory 289936 kb
Host smart-5cc418dc-77ac-44a9-bfb6-3f496ac70a8f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590329953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.590329953
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.334441177
Short name T208
Test name
Test status
Simulation time 13214099 ps
CPU time 2.4 seconds
Started Jun 13 01:29:20 PM PDT 24
Finished Jun 13 01:29:23 PM PDT 24
Peak memory 249176 kb
Host smart-202c2117-1276-40ff-9f70-fd2407659bd0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=334441177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.334441177
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2141270153
Short name T707
Test name
Test status
Simulation time 44951166269 ps
CPU time 1534.15 seconds
Started Jun 13 01:29:20 PM PDT 24
Finished Jun 13 01:54:55 PM PDT 24
Peak memory 289520 kb
Host smart-04c5abae-a731-4350-9bf4-cb45fbd5e689
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141270153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2141270153
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1677905420
Short name T40
Test name
Test status
Simulation time 406930384 ps
CPU time 17.04 seconds
Started Jun 13 01:29:15 PM PDT 24
Finished Jun 13 01:29:33 PM PDT 24
Peak memory 248956 kb
Host smart-5eda3323-c662-431c-b67d-3eccbfa71aff
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1677905420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1677905420
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.974060459
Short name T413
Test name
Test status
Simulation time 1951770134 ps
CPU time 72.45 seconds
Started Jun 13 01:29:17 PM PDT 24
Finished Jun 13 01:30:30 PM PDT 24
Peak memory 250188 kb
Host smart-50aab312-4a6a-4a8c-a8cd-783886ebcdc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97406
0459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.974060459
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3145617873
Short name T20
Test name
Test status
Simulation time 1744915244 ps
CPU time 29.12 seconds
Started Jun 13 01:29:15 PM PDT 24
Finished Jun 13 01:29:45 PM PDT 24
Peak memory 255380 kb
Host smart-18cf04d6-c454-44f2-9cef-a1573cfe1388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31456
17873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3145617873
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.3251416363
Short name T473
Test name
Test status
Simulation time 118532566234 ps
CPU time 1049.71 seconds
Started Jun 13 01:29:16 PM PDT 24
Finished Jun 13 01:46:47 PM PDT 24
Peak memory 265556 kb
Host smart-27bf3fa8-26de-4014-83e8-6eb6b2550410
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251416363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3251416363
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1639555108
Short name T599
Test name
Test status
Simulation time 10522072494 ps
CPU time 1020.78 seconds
Started Jun 13 01:29:17 PM PDT 24
Finished Jun 13 01:46:19 PM PDT 24
Peak memory 289268 kb
Host smart-3e3ecae5-65a1-440e-bcd0-7e9962dd4be9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639555108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1639555108
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3237896751
Short name T495
Test name
Test status
Simulation time 272026614 ps
CPU time 10.5 seconds
Started Jun 13 01:29:17 PM PDT 24
Finished Jun 13 01:29:29 PM PDT 24
Peak memory 257304 kb
Host smart-5007297c-14eb-4506-8ac1-caf8a463485e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32378
96751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3237896751
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.4269028835
Short name T406
Test name
Test status
Simulation time 1206663001 ps
CPU time 26.17 seconds
Started Jun 13 01:29:19 PM PDT 24
Finished Jun 13 01:29:46 PM PDT 24
Peak memory 247980 kb
Host smart-58291c05-ee0f-4250-947d-f40276aeb7a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42690
28835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.4269028835
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2266318680
Short name T576
Test name
Test status
Simulation time 180549313 ps
CPU time 10.77 seconds
Started Jun 13 01:29:17 PM PDT 24
Finished Jun 13 01:29:29 PM PDT 24
Peak memory 256188 kb
Host smart-16d8252c-a09d-4090-ac0b-762303623c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22663
18680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2266318680
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1926915003
Short name T279
Test name
Test status
Simulation time 4590789666 ps
CPU time 62.57 seconds
Started Jun 13 01:29:17 PM PDT 24
Finished Jun 13 01:30:21 PM PDT 24
Peak memory 256472 kb
Host smart-990325e3-cb18-49ae-b7dd-809ada78fd12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19269
15003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1926915003
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.2586745563
Short name T517
Test name
Test status
Simulation time 130067766130 ps
CPU time 3574.52 seconds
Started Jun 13 01:29:20 PM PDT 24
Finished Jun 13 02:28:56 PM PDT 24
Peak memory 298356 kb
Host smart-1c96695e-0003-4fdd-9de2-0fe49775e332
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586745563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.2586745563
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.4230068249
Short name T24
Test name
Test status
Simulation time 222516578554 ps
CPU time 7294.19 seconds
Started Jun 13 01:29:14 PM PDT 24
Finished Jun 13 03:30:50 PM PDT 24
Peak memory 338676 kb
Host smart-46425c9f-b7b3-4066-b855-2015c667b07c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230068249 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.4230068249
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3104278904
Short name T197
Test name
Test status
Simulation time 39526501 ps
CPU time 2.42 seconds
Started Jun 13 01:29:24 PM PDT 24
Finished Jun 13 01:29:29 PM PDT 24
Peak memory 249208 kb
Host smart-6778f25f-7a72-4102-8aa1-5b65079df170
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3104278904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3104278904
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.4195610685
Short name T107
Test name
Test status
Simulation time 38740294153 ps
CPU time 2132.21 seconds
Started Jun 13 01:29:24 PM PDT 24
Finished Jun 13 02:04:58 PM PDT 24
Peak memory 289720 kb
Host smart-0e46d47c-e7e2-4e17-a54b-3b89f86e40b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195610685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.4195610685
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2130587453
Short name T635
Test name
Test status
Simulation time 282965979 ps
CPU time 14.15 seconds
Started Jun 13 01:29:24 PM PDT 24
Finished Jun 13 01:29:41 PM PDT 24
Peak memory 249128 kb
Host smart-448c979e-b199-4bf5-b3e8-cb1ef7267fe6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2130587453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2130587453
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2550063616
Short name T450
Test name
Test status
Simulation time 6611847263 ps
CPU time 127.06 seconds
Started Jun 13 01:29:23 PM PDT 24
Finished Jun 13 01:31:32 PM PDT 24
Peak memory 257176 kb
Host smart-ee02b80e-1c1d-492a-b6e1-29f31db13c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25500
63616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2550063616
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2421982568
Short name T78
Test name
Test status
Simulation time 88208382 ps
CPU time 8.07 seconds
Started Jun 13 01:29:23 PM PDT 24
Finished Jun 13 01:29:34 PM PDT 24
Peak memory 254536 kb
Host smart-ee351698-0d72-4161-9786-6edb3c179df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24219
82568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2421982568
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3155379523
Short name T325
Test name
Test status
Simulation time 42241501250 ps
CPU time 1389.21 seconds
Started Jun 13 01:29:23 PM PDT 24
Finished Jun 13 01:52:35 PM PDT 24
Peak memory 269632 kb
Host smart-dac257e3-41f5-4e39-8410-c163b8aca2ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155379523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3155379523
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.406497187
Short name T101
Test name
Test status
Simulation time 230547417126 ps
CPU time 1965.63 seconds
Started Jun 13 01:29:28 PM PDT 24
Finished Jun 13 02:02:15 PM PDT 24
Peak memory 273308 kb
Host smart-2e2d3b69-1734-48bb-8634-6b73d280b68c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406497187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.406497187
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.977738149
Short name T563
Test name
Test status
Simulation time 7198819284 ps
CPU time 289.25 seconds
Started Jun 13 01:29:22 PM PDT 24
Finished Jun 13 01:34:13 PM PDT 24
Peak memory 255712 kb
Host smart-76269cf9-7edd-45fe-bc83-bea1bc2ab984
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977738149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.977738149
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2384707717
Short name T433
Test name
Test status
Simulation time 749406053 ps
CPU time 47.58 seconds
Started Jun 13 01:29:24 PM PDT 24
Finished Jun 13 01:30:14 PM PDT 24
Peak memory 256540 kb
Host smart-ab098682-a554-48d5-aa59-808b0259152b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23847
07717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2384707717
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2928844348
Short name T602
Test name
Test status
Simulation time 2910109043 ps
CPU time 69.38 seconds
Started Jun 13 01:29:23 PM PDT 24
Finished Jun 13 01:30:35 PM PDT 24
Peak memory 248364 kb
Host smart-98054d41-6ac1-4a2c-b98a-d96bd7064e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29288
44348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2928844348
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1868066658
Short name T648
Test name
Test status
Simulation time 581994433 ps
CPU time 34.92 seconds
Started Jun 13 01:29:29 PM PDT 24
Finished Jun 13 01:30:04 PM PDT 24
Peak memory 257208 kb
Host smart-f509e0e6-6d37-4da9-9a4f-baf8da989271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18680
66658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1868066658
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.625462407
Short name T445
Test name
Test status
Simulation time 300937389 ps
CPU time 14.65 seconds
Started Jun 13 01:29:23 PM PDT 24
Finished Jun 13 01:29:40 PM PDT 24
Peak memory 255856 kb
Host smart-141481e6-f332-4620-ab8b-bb5f2d249f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62546
2407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.625462407
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2249175725
Short name T637
Test name
Test status
Simulation time 28506907785 ps
CPU time 1694.84 seconds
Started Jun 13 01:29:22 PM PDT 24
Finished Jun 13 01:57:39 PM PDT 24
Peak memory 282968 kb
Host smart-671e6bb7-71a3-4549-ba21-614f978c323b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249175725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2249175725
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3809249260
Short name T27
Test name
Test status
Simulation time 26948123251 ps
CPU time 1121.23 seconds
Started Jun 13 01:29:26 PM PDT 24
Finished Jun 13 01:48:09 PM PDT 24
Peak memory 289796 kb
Host smart-3024b5c9-1354-4b3b-a5f3-393c28eb46fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809249260 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3809249260
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2329910480
Short name T544
Test name
Test status
Simulation time 27346560861 ps
CPU time 1245.96 seconds
Started Jun 13 01:29:25 PM PDT 24
Finished Jun 13 01:50:13 PM PDT 24
Peak memory 286212 kb
Host smart-b882346a-200a-4542-b589-2c3ab0b40c5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329910480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2329910480
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.4123017871
Short name T401
Test name
Test status
Simulation time 56780286287 ps
CPU time 349.9 seconds
Started Jun 13 01:29:25 PM PDT 24
Finished Jun 13 01:35:17 PM PDT 24
Peak memory 257296 kb
Host smart-18b8b0e7-f617-4e04-a11a-e22e6d4ca2ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41230
17871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.4123017871
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3939910005
Short name T687
Test name
Test status
Simulation time 1465771134 ps
CPU time 32.81 seconds
Started Jun 13 01:29:29 PM PDT 24
Finished Jun 13 01:30:02 PM PDT 24
Peak memory 256396 kb
Host smart-15cef7dc-36d0-45e6-b0b3-365195acc975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39399
10005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3939910005
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.693569980
Short name T312
Test name
Test status
Simulation time 409712486008 ps
CPU time 1235.03 seconds
Started Jun 13 01:29:26 PM PDT 24
Finished Jun 13 01:50:02 PM PDT 24
Peak memory 273436 kb
Host smart-b1f34393-25c5-45eb-b6a0-72c6d86e682f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693569980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.693569980
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2930295444
Short name T37
Test name
Test status
Simulation time 150985394566 ps
CPU time 2643.9 seconds
Started Jun 13 01:29:27 PM PDT 24
Finished Jun 13 02:13:32 PM PDT 24
Peak memory 289592 kb
Host smart-10cbc839-b8d8-4b49-b485-00a5b31f4c87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930295444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2930295444
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1425433742
Short name T309
Test name
Test status
Simulation time 39571639319 ps
CPU time 398.4 seconds
Started Jun 13 01:29:25 PM PDT 24
Finished Jun 13 01:36:05 PM PDT 24
Peak memory 256908 kb
Host smart-69661a53-0b68-4da2-9adc-5350c62d1b5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425433742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1425433742
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3854100007
Short name T447
Test name
Test status
Simulation time 3102396900 ps
CPU time 47.61 seconds
Started Jun 13 01:29:24 PM PDT 24
Finished Jun 13 01:30:14 PM PDT 24
Peak memory 256492 kb
Host smart-eef985c0-be06-428d-8527-fb901a786a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38541
00007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3854100007
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1848310257
Short name T493
Test name
Test status
Simulation time 266591367 ps
CPU time 21.19 seconds
Started Jun 13 01:29:24 PM PDT 24
Finished Jun 13 01:29:47 PM PDT 24
Peak memory 249188 kb
Host smart-cb05b311-5c42-4cb7-931f-17a4d89d6116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18483
10257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1848310257
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.845360825
Short name T84
Test name
Test status
Simulation time 444962651 ps
CPU time 29.83 seconds
Started Jun 13 01:29:25 PM PDT 24
Finished Jun 13 01:29:57 PM PDT 24
Peak memory 249020 kb
Host smart-4fb81a64-8939-4615-b703-300eb2727276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84536
0825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.845360825
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.532960933
Short name T346
Test name
Test status
Simulation time 2656436908 ps
CPU time 40.63 seconds
Started Jun 13 01:29:23 PM PDT 24
Finished Jun 13 01:30:06 PM PDT 24
Peak memory 257332 kb
Host smart-8957af8d-349c-4849-a754-3e94a01418ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53296
0933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.532960933
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2330394897
Short name T243
Test name
Test status
Simulation time 67382223736 ps
CPU time 1348.64 seconds
Started Jun 13 01:29:25 PM PDT 24
Finished Jun 13 01:51:56 PM PDT 24
Peak memory 298228 kb
Host smart-c6656a24-b44d-406b-9ab9-05e24e0ad8da
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330394897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2330394897
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2567909095
Short name T275
Test name
Test status
Simulation time 428320979877 ps
CPU time 4461.22 seconds
Started Jun 13 01:29:23 PM PDT 24
Finished Jun 13 02:43:46 PM PDT 24
Peak memory 336440 kb
Host smart-8312dfd5-ff49-4114-b354-9c1fe5273924
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567909095 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2567909095
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3480278407
Short name T198
Test name
Test status
Simulation time 17446798 ps
CPU time 2.57 seconds
Started Jun 13 01:29:29 PM PDT 24
Finished Jun 13 01:29:32 PM PDT 24
Peak memory 249184 kb
Host smart-524b8e70-bff0-40fc-bbd2-a4576af88a7a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3480278407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3480278407
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.4187018918
Short name T644
Test name
Test status
Simulation time 468604439 ps
CPU time 21.16 seconds
Started Jun 13 01:29:28 PM PDT 24
Finished Jun 13 01:29:50 PM PDT 24
Peak memory 249088 kb
Host smart-037a2352-04a0-4937-99be-d2b42d084e6b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4187018918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.4187018918
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2170672191
Short name T390
Test name
Test status
Simulation time 5794587402 ps
CPU time 87.15 seconds
Started Jun 13 01:29:32 PM PDT 24
Finished Jun 13 01:31:00 PM PDT 24
Peak memory 257320 kb
Host smart-939f6350-2435-425c-bd2f-f29e42b3afda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21706
72191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2170672191
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3107605835
Short name T586
Test name
Test status
Simulation time 589684182 ps
CPU time 32.57 seconds
Started Jun 13 01:29:28 PM PDT 24
Finished Jun 13 01:30:01 PM PDT 24
Peak memory 255960 kb
Host smart-d3042bbc-c194-4c6a-bcfa-14b533a313ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31076
05835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3107605835
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3866562015
Short name T97
Test name
Test status
Simulation time 42325839481 ps
CPU time 1030.72 seconds
Started Jun 13 01:29:27 PM PDT 24
Finished Jun 13 01:46:39 PM PDT 24
Peak memory 273416 kb
Host smart-253c48e2-2e83-4b18-907b-2b99892f10bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866562015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3866562015
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2639612886
Short name T287
Test name
Test status
Simulation time 7540037000 ps
CPU time 307.53 seconds
Started Jun 13 01:29:32 PM PDT 24
Finished Jun 13 01:34:40 PM PDT 24
Peak memory 256760 kb
Host smart-5063390d-8448-4c7b-b71d-173308540c66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639612886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2639612886
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2399008768
Short name T488
Test name
Test status
Simulation time 4737966197 ps
CPU time 77.08 seconds
Started Jun 13 01:29:24 PM PDT 24
Finished Jun 13 01:30:43 PM PDT 24
Peak memory 256348 kb
Host smart-cb7e4b3b-1570-415f-8640-2d7086b061ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23990
08768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2399008768
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1634725314
Short name T214
Test name
Test status
Simulation time 815771176 ps
CPU time 43.3 seconds
Started Jun 13 01:29:24 PM PDT 24
Finished Jun 13 01:30:09 PM PDT 24
Peak memory 249220 kb
Host smart-4fb97f9f-5434-49ac-991b-3d1bb78d5afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16347
25314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1634725314
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2346424461
Short name T419
Test name
Test status
Simulation time 390232834 ps
CPU time 22.81 seconds
Started Jun 13 01:29:24 PM PDT 24
Finished Jun 13 01:29:49 PM PDT 24
Peak memory 249088 kb
Host smart-a9b82d88-f3b5-48e5-b622-49ac6b05f007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23464
24461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2346424461
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.4112869660
Short name T639
Test name
Test status
Simulation time 1487230166 ps
CPU time 105.07 seconds
Started Jun 13 01:29:28 PM PDT 24
Finished Jun 13 01:31:13 PM PDT 24
Peak memory 257292 kb
Host smart-e5951e26-71ca-478f-a2da-4a1b21bf329a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112869660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.4112869660
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.2858234602
Short name T620
Test name
Test status
Simulation time 468778334446 ps
CPU time 3247.1 seconds
Started Jun 13 01:29:33 PM PDT 24
Finished Jun 13 02:23:41 PM PDT 24
Peak memory 283072 kb
Host smart-69459562-155a-4730-a76d-c049d825c26c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858234602 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2858234602
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2111735990
Short name T201
Test name
Test status
Simulation time 46518442 ps
CPU time 4.25 seconds
Started Jun 13 01:29:36 PM PDT 24
Finished Jun 13 01:29:41 PM PDT 24
Peak memory 249236 kb
Host smart-c3621a0b-f437-4c37-89dc-e799edf4f747
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2111735990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2111735990
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.4155540096
Short name T625
Test name
Test status
Simulation time 55581304152 ps
CPU time 1367.82 seconds
Started Jun 13 01:29:35 PM PDT 24
Finished Jun 13 01:52:24 PM PDT 24
Peak memory 289920 kb
Host smart-8c79321e-741d-4c88-9f74-bcbe94bb29fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155540096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.4155540096
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3022490013
Short name T380
Test name
Test status
Simulation time 89262987 ps
CPU time 6.74 seconds
Started Jun 13 01:29:36 PM PDT 24
Finished Jun 13 01:29:43 PM PDT 24
Peak memory 249096 kb
Host smart-7b382906-d247-4a50-ba1d-ca3852f2d011
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3022490013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3022490013
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3339953541
Short name T461
Test name
Test status
Simulation time 1770625033 ps
CPU time 149.39 seconds
Started Jun 13 01:29:27 PM PDT 24
Finished Jun 13 01:31:57 PM PDT 24
Peak memory 251348 kb
Host smart-56c6eddd-59ed-444b-9317-49c76efef983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33399
53541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3339953541
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.469811223
Short name T66
Test name
Test status
Simulation time 1608954498 ps
CPU time 62.54 seconds
Started Jun 13 01:29:30 PM PDT 24
Finished Jun 13 01:30:33 PM PDT 24
Peak memory 256560 kb
Host smart-65778c78-6329-47d3-b74a-3b4df18f92f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46981
1223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.469811223
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1425159389
Short name T699
Test name
Test status
Simulation time 112796929012 ps
CPU time 952.34 seconds
Started Jun 13 01:29:36 PM PDT 24
Finished Jun 13 01:45:29 PM PDT 24
Peak memory 267644 kb
Host smart-5be5f79a-61f4-48d9-8f1d-67cc9b70d69f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425159389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1425159389
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.691039255
Short name T74
Test name
Test status
Simulation time 165780367160 ps
CPU time 1930.61 seconds
Started Jun 13 01:29:36 PM PDT 24
Finished Jun 13 02:01:48 PM PDT 24
Peak memory 272440 kb
Host smart-0d8b27d4-ac9f-42a8-8841-20233461d8be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691039255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.691039255
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2413951318
Short name T6
Test name
Test status
Simulation time 4640275064 ps
CPU time 174.25 seconds
Started Jun 13 01:29:36 PM PDT 24
Finished Jun 13 01:32:31 PM PDT 24
Peak memory 248720 kb
Host smart-46d4eff0-348d-4aeb-b20b-4437426b0963
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413951318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2413951318
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2622183764
Short name T377
Test name
Test status
Simulation time 2485492600 ps
CPU time 35.87 seconds
Started Jun 13 01:29:29 PM PDT 24
Finished Jun 13 01:30:05 PM PDT 24
Peak memory 249156 kb
Host smart-7ce7f9ea-9db4-4809-91dc-0149536c0c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26221
83764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2622183764
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3416612589
Short name T653
Test name
Test status
Simulation time 140211853 ps
CPU time 10.83 seconds
Started Jun 13 01:29:28 PM PDT 24
Finished Jun 13 01:29:40 PM PDT 24
Peak memory 247852 kb
Host smart-7d322f7d-5dfb-49b3-a85f-a6513d0f78a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34166
12589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3416612589
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.818747952
Short name T81
Test name
Test status
Simulation time 1833045490 ps
CPU time 27.99 seconds
Started Jun 13 01:29:35 PM PDT 24
Finished Jun 13 01:30:03 PM PDT 24
Peak memory 255940 kb
Host smart-7d6dc21f-f955-4db7-9677-a5f864638804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81874
7952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.818747952
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1162882626
Short name T570
Test name
Test status
Simulation time 785643228 ps
CPU time 12.31 seconds
Started Jun 13 01:29:32 PM PDT 24
Finished Jun 13 01:29:45 PM PDT 24
Peak memory 249100 kb
Host smart-2e70d706-52e9-4b7b-8c8f-53fb2d2bd431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11628
82626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1162882626
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1850217590
Short name T212
Test name
Test status
Simulation time 99475443609 ps
CPU time 1599.88 seconds
Started Jun 13 01:29:40 PM PDT 24
Finished Jun 13 01:56:21 PM PDT 24
Peak memory 290088 kb
Host smart-d5329ac8-ff3c-4271-969e-6d48071a88e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850217590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1850217590
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3900044425
Short name T422
Test name
Test status
Simulation time 573800677 ps
CPU time 8.84 seconds
Started Jun 13 01:29:41 PM PDT 24
Finished Jun 13 01:29:50 PM PDT 24
Peak memory 249104 kb
Host smart-f9e58aae-3aac-4006-909b-76c77cc91947
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3900044425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3900044425
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1861093184
Short name T400
Test name
Test status
Simulation time 5152571647 ps
CPU time 133.56 seconds
Started Jun 13 01:29:42 PM PDT 24
Finished Jun 13 01:31:56 PM PDT 24
Peak memory 250448 kb
Host smart-9d90e6f9-f788-4ea7-9d85-adde589f4fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18610
93184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1861093184
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2791042170
Short name T354
Test name
Test status
Simulation time 308178679 ps
CPU time 10.82 seconds
Started Jun 13 01:29:43 PM PDT 24
Finished Jun 13 01:29:55 PM PDT 24
Peak memory 254700 kb
Host smart-9e19a876-c324-4c10-bf99-952988d407c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27910
42170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2791042170
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.4000607552
Short name T292
Test name
Test status
Simulation time 17512984761 ps
CPU time 191.28 seconds
Started Jun 13 01:29:41 PM PDT 24
Finished Jun 13 01:32:53 PM PDT 24
Peak memory 255908 kb
Host smart-5dedb117-9d7c-4df5-b293-f31eb740132f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000607552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.4000607552
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3377801095
Short name T410
Test name
Test status
Simulation time 367202065 ps
CPU time 25.63 seconds
Started Jun 13 01:29:35 PM PDT 24
Finished Jun 13 01:30:02 PM PDT 24
Peak memory 256596 kb
Host smart-ab400260-d9fb-49c4-9754-6a8a3cc334cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33778
01095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3377801095
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3718269663
Short name T680
Test name
Test status
Simulation time 1269679478 ps
CPU time 12.43 seconds
Started Jun 13 01:29:41 PM PDT 24
Finished Jun 13 01:29:54 PM PDT 24
Peak memory 253420 kb
Host smart-04e51c31-4e3d-483f-94d8-3ab0559ac7ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37182
69663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3718269663
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3911191049
Short name T458
Test name
Test status
Simulation time 273418910 ps
CPU time 13.64 seconds
Started Jun 13 01:29:40 PM PDT 24
Finished Jun 13 01:29:54 PM PDT 24
Peak memory 249196 kb
Host smart-f48e92f4-4fac-4725-91b5-42e4685d90ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39111
91049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3911191049
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3264078495
Short name T463
Test name
Test status
Simulation time 913110572 ps
CPU time 14.08 seconds
Started Jun 13 01:29:35 PM PDT 24
Finished Jun 13 01:29:50 PM PDT 24
Peak memory 249032 kb
Host smart-0f339cba-cddb-4e62-84c0-9c8a3c5f9c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32640
78495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3264078495
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2998601851
Short name T263
Test name
Test status
Simulation time 41410567648 ps
CPU time 2617.02 seconds
Started Jun 13 01:29:43 PM PDT 24
Finished Jun 13 02:13:20 PM PDT 24
Peak memory 289600 kb
Host smart-ddc172f3-ef3c-4518-a6e6-baac271ebf1b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998601851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2998601851
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3907217171
Short name T192
Test name
Test status
Simulation time 16593530 ps
CPU time 2.64 seconds
Started Jun 13 01:29:50 PM PDT 24
Finished Jun 13 01:29:53 PM PDT 24
Peak memory 249248 kb
Host smart-ebd82e62-c8e7-4917-a047-996b329e68fd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3907217171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3907217171
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3072154512
Short name T424
Test name
Test status
Simulation time 942998715 ps
CPU time 13.28 seconds
Started Jun 13 01:29:45 PM PDT 24
Finished Jun 13 01:29:59 PM PDT 24
Peak memory 249016 kb
Host smart-c0c5abd2-a5a1-4e34-ac75-62d6a40852d1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3072154512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3072154512
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3630667123
Short name T372
Test name
Test status
Simulation time 5225352777 ps
CPU time 102.71 seconds
Started Jun 13 01:29:49 PM PDT 24
Finished Jun 13 01:31:32 PM PDT 24
Peak memory 257312 kb
Host smart-11735f34-91fb-4348-8ab4-51cdc63179f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36306
67123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3630667123
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2155635748
Short name T652
Test name
Test status
Simulation time 594876472 ps
CPU time 26.77 seconds
Started Jun 13 01:29:50 PM PDT 24
Finished Jun 13 01:30:17 PM PDT 24
Peak memory 249024 kb
Host smart-1a200457-9125-4c6d-9940-6b924c5c8b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21556
35748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2155635748
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.4127929111
Short name T418
Test name
Test status
Simulation time 16109719562 ps
CPU time 1391.42 seconds
Started Jun 13 01:29:48 PM PDT 24
Finished Jun 13 01:53:01 PM PDT 24
Peak memory 281960 kb
Host smart-16975367-57de-46e9-b3a8-db268c4e1908
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127929111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.4127929111
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2190014606
Short name T546
Test name
Test status
Simulation time 13270677275 ps
CPU time 685.5 seconds
Started Jun 13 01:29:47 PM PDT 24
Finished Jun 13 01:41:13 PM PDT 24
Peak memory 272912 kb
Host smart-b728bd40-737b-49fb-ac80-1d5d9fd555c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190014606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2190014606
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.439176611
Short name T559
Test name
Test status
Simulation time 1579757761 ps
CPU time 24.89 seconds
Started Jun 13 01:29:41 PM PDT 24
Finished Jun 13 01:30:07 PM PDT 24
Peak memory 255616 kb
Host smart-ee1bae66-06ea-477e-b184-0f88839fe4d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43917
6611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.439176611
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2540824112
Short name T60
Test name
Test status
Simulation time 845138344 ps
CPU time 53.16 seconds
Started Jun 13 01:29:48 PM PDT 24
Finished Jun 13 01:30:42 PM PDT 24
Peak memory 256024 kb
Host smart-029ca197-8bca-4d18-a9d5-004ac0c0260f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25408
24112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2540824112
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1940456949
Short name T253
Test name
Test status
Simulation time 1007128450 ps
CPU time 27.11 seconds
Started Jun 13 01:29:48 PM PDT 24
Finished Jun 13 01:30:16 PM PDT 24
Peak memory 248156 kb
Host smart-97253db9-2fc5-47ca-8142-966c07b52d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19404
56949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1940456949
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3706907047
Short name T428
Test name
Test status
Simulation time 969249660 ps
CPU time 55.17 seconds
Started Jun 13 01:29:42 PM PDT 24
Finished Jun 13 01:30:38 PM PDT 24
Peak memory 249084 kb
Host smart-e39ef6c9-b74f-4ade-95e7-3b0f78481ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37069
07047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3706907047
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3404246743
Short name T35
Test name
Test status
Simulation time 210730411453 ps
CPU time 3096.58 seconds
Started Jun 13 01:29:48 PM PDT 24
Finished Jun 13 02:21:26 PM PDT 24
Peak memory 299120 kb
Host smart-eabf3666-389f-42d1-91bd-6815531c5678
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404246743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3404246743
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.158227905
Short name T203
Test name
Test status
Simulation time 14065193 ps
CPU time 2.71 seconds
Started Jun 13 01:29:54 PM PDT 24
Finished Jun 13 01:29:58 PM PDT 24
Peak memory 249248 kb
Host smart-07efee9d-70d8-4cd1-ae82-08115c4c5179
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=158227905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.158227905
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.4185880331
Short name T682
Test name
Test status
Simulation time 11791660425 ps
CPU time 1065.26 seconds
Started Jun 13 01:29:54 PM PDT 24
Finished Jun 13 01:47:41 PM PDT 24
Peak memory 273268 kb
Host smart-cf6b1e2d-27e2-4749-8fd6-f83d37417c43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185880331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.4185880331
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3733668625
Short name T618
Test name
Test status
Simulation time 197332866 ps
CPU time 10.98 seconds
Started Jun 13 01:29:56 PM PDT 24
Finished Jun 13 01:30:08 PM PDT 24
Peak memory 251792 kb
Host smart-d674cec1-bbb9-4007-b84b-87c7b81e9050
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3733668625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3733668625
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2638732121
Short name T603
Test name
Test status
Simulation time 920036041 ps
CPU time 67.1 seconds
Started Jun 13 01:29:59 PM PDT 24
Finished Jun 13 01:31:07 PM PDT 24
Peak memory 257240 kb
Host smart-2118ebaa-4fd4-4a97-ae16-0c64c9ee6a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26387
32121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2638732121
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3575758813
Short name T592
Test name
Test status
Simulation time 1780047158 ps
CPU time 27.67 seconds
Started Jun 13 01:29:54 PM PDT 24
Finished Jun 13 01:30:23 PM PDT 24
Peak memory 255848 kb
Host smart-dfd4be71-2e8d-49c1-ac13-db6127bd4ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35757
58813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3575758813
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3071798616
Short name T431
Test name
Test status
Simulation time 62141142621 ps
CPU time 1663.3 seconds
Started Jun 13 01:29:55 PM PDT 24
Finished Jun 13 01:57:40 PM PDT 24
Peak memory 289796 kb
Host smart-3bc0b81e-d11e-45b2-ba32-2de46933db5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071798616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3071798616
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.487225908
Short name T69
Test name
Test status
Simulation time 146667464745 ps
CPU time 2206.8 seconds
Started Jun 13 01:29:57 PM PDT 24
Finished Jun 13 02:06:45 PM PDT 24
Peak memory 289420 kb
Host smart-e78edd11-c019-4c6b-896b-051c18e9e14b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487225908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.487225908
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1563095766
Short name T310
Test name
Test status
Simulation time 47524296775 ps
CPU time 535.83 seconds
Started Jun 13 01:29:55 PM PDT 24
Finished Jun 13 01:38:52 PM PDT 24
Peak memory 247612 kb
Host smart-0185dfc9-779a-4de0-9774-40d8da8bd53f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563095766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1563095766
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3242980412
Short name T529
Test name
Test status
Simulation time 3703904135 ps
CPU time 46.32 seconds
Started Jun 13 01:29:53 PM PDT 24
Finished Jun 13 01:30:40 PM PDT 24
Peak memory 256512 kb
Host smart-9217f414-0373-47da-ae7b-6c841626ffe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32429
80412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3242980412
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3983303285
Short name T606
Test name
Test status
Simulation time 393294864 ps
CPU time 28.07 seconds
Started Jun 13 01:29:57 PM PDT 24
Finished Jun 13 01:30:26 PM PDT 24
Peak memory 256208 kb
Host smart-d1750cc5-c473-4708-8774-74f8756a9c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39833
03285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3983303285
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2420022873
Short name T492
Test name
Test status
Simulation time 564127920 ps
CPU time 17.71 seconds
Started Jun 13 01:29:55 PM PDT 24
Finished Jun 13 01:30:14 PM PDT 24
Peak memory 256468 kb
Host smart-8d589688-c3e8-4358-bb67-23218f1cd6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24200
22873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2420022873
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3814709974
Short name T560
Test name
Test status
Simulation time 257712750 ps
CPU time 9 seconds
Started Jun 13 01:29:54 PM PDT 24
Finished Jun 13 01:30:04 PM PDT 24
Peak memory 257212 kb
Host smart-0543148a-a839-4dc3-86a4-f7abc40f3d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38147
09974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3814709974
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2436483150
Short name T85
Test name
Test status
Simulation time 91075801577 ps
CPU time 1519.03 seconds
Started Jun 13 01:29:56 PM PDT 24
Finished Jun 13 01:55:16 PM PDT 24
Peak memory 273760 kb
Host smart-1e9328cd-ecf0-4d2c-a29e-bd23c957bd3c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436483150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2436483150
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2134733461
Short name T67
Test name
Test status
Simulation time 53038567 ps
CPU time 4.42 seconds
Started Jun 13 01:30:07 PM PDT 24
Finished Jun 13 01:30:12 PM PDT 24
Peak memory 249184 kb
Host smart-6a6d9594-d45c-4681-a534-0b00ca1f23f9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2134733461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2134733461
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2913423133
Short name T555
Test name
Test status
Simulation time 248091625250 ps
CPU time 1270.33 seconds
Started Jun 13 01:30:01 PM PDT 24
Finished Jun 13 01:51:11 PM PDT 24
Peak memory 273388 kb
Host smart-397f8da9-a501-4ca9-a0ac-4a5dbf02b593
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913423133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2913423133
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1958702076
Short name T358
Test name
Test status
Simulation time 1234867535 ps
CPU time 54.72 seconds
Started Jun 13 01:30:03 PM PDT 24
Finished Jun 13 01:30:58 PM PDT 24
Peak memory 249116 kb
Host smart-100daac7-84d1-45f1-a96d-cbedd4cc0579
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1958702076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1958702076
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1142984351
Short name T223
Test name
Test status
Simulation time 6097812906 ps
CPU time 18.9 seconds
Started Jun 13 01:30:01 PM PDT 24
Finished Jun 13 01:30:21 PM PDT 24
Peak memory 255372 kb
Host smart-2681d809-d320-4377-a0bd-ba268642cbd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11429
84351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1142984351
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1642261139
Short name T80
Test name
Test status
Simulation time 298380864 ps
CPU time 21.22 seconds
Started Jun 13 01:30:01 PM PDT 24
Finished Jun 13 01:30:23 PM PDT 24
Peak memory 254924 kb
Host smart-1d4b0c47-fe91-4999-8552-d53dc8a56ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16422
61139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1642261139
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3807281300
Short name T318
Test name
Test status
Simulation time 57224327843 ps
CPU time 1207.49 seconds
Started Jun 13 01:30:01 PM PDT 24
Finished Jun 13 01:50:10 PM PDT 24
Peak memory 273748 kb
Host smart-e6b71a76-d1f1-49a5-b02f-1edce7054b89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807281300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3807281300
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1227292489
Short name T507
Test name
Test status
Simulation time 8089062374 ps
CPU time 694 seconds
Started Jun 13 01:30:01 PM PDT 24
Finished Jun 13 01:41:36 PM PDT 24
Peak memory 273360 kb
Host smart-830c8175-3211-4229-b682-c66744ee4153
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227292489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1227292489
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.132384307
Short name T414
Test name
Test status
Simulation time 1177781815 ps
CPU time 64.05 seconds
Started Jun 13 01:30:03 PM PDT 24
Finished Jun 13 01:31:08 PM PDT 24
Peak memory 256744 kb
Host smart-cae6e309-84ad-49b6-9c34-e66040d5cece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13238
4307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.132384307
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1728867153
Short name T677
Test name
Test status
Simulation time 83597425 ps
CPU time 9.39 seconds
Started Jun 13 01:30:02 PM PDT 24
Finished Jun 13 01:30:12 PM PDT 24
Peak memory 249296 kb
Host smart-338791af-9f47-450d-8c21-8371a7967226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17288
67153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1728867153
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2812375747
Short name T688
Test name
Test status
Simulation time 1713081206 ps
CPU time 60.54 seconds
Started Jun 13 01:30:01 PM PDT 24
Finished Jun 13 01:31:02 PM PDT 24
Peak memory 249032 kb
Host smart-37839521-11f9-457e-92e6-d080cd011cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28123
75747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2812375747
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3465022967
Short name T357
Test name
Test status
Simulation time 3667631550 ps
CPU time 47.67 seconds
Started Jun 13 01:30:01 PM PDT 24
Finished Jun 13 01:30:49 PM PDT 24
Peak memory 256392 kb
Host smart-19a76377-b6fb-453d-86f9-4a7b1bd085df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34650
22967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3465022967
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.4046352566
Short name T583
Test name
Test status
Simulation time 112128218427 ps
CPU time 2979.52 seconds
Started Jun 13 01:30:01 PM PDT 24
Finished Jun 13 02:19:42 PM PDT 24
Peak memory 289460 kb
Host smart-eee223a3-af0d-41bf-86cd-2f474dfec6c6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046352566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.4046352566
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2895692603
Short name T194
Test name
Test status
Simulation time 27935860 ps
CPU time 2.92 seconds
Started Jun 13 01:30:09 PM PDT 24
Finished Jun 13 01:30:12 PM PDT 24
Peak memory 249248 kb
Host smart-5368be17-c17f-46a8-b9aa-30d61c0d981e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2895692603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2895692603
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1084335667
Short name T588
Test name
Test status
Simulation time 159587827009 ps
CPU time 1641.19 seconds
Started Jun 13 01:30:10 PM PDT 24
Finished Jun 13 01:57:32 PM PDT 24
Peak memory 281916 kb
Host smart-ec39cbce-481a-4470-8593-f684d6371b30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084335667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1084335667
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3947151260
Short name T642
Test name
Test status
Simulation time 415987724 ps
CPU time 18.07 seconds
Started Jun 13 01:30:09 PM PDT 24
Finished Jun 13 01:30:28 PM PDT 24
Peak memory 249064 kb
Host smart-25644407-aaf9-4368-9de7-7ff11b682684
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3947151260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3947151260
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2766629760
Short name T486
Test name
Test status
Simulation time 2718809986 ps
CPU time 41.38 seconds
Started Jun 13 01:30:07 PM PDT 24
Finished Jun 13 01:30:49 PM PDT 24
Peak memory 256552 kb
Host smart-b308f61c-d216-456e-8439-f4fb36ef1d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27666
29760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2766629760
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3620230345
Short name T568
Test name
Test status
Simulation time 667169125 ps
CPU time 39.03 seconds
Started Jun 13 01:30:10 PM PDT 24
Finished Jun 13 01:30:49 PM PDT 24
Peak memory 256164 kb
Host smart-d2ae8093-98e6-4d17-924a-872f1b85cc2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36202
30345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3620230345
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2705846452
Short name T1
Test name
Test status
Simulation time 56596981199 ps
CPU time 2765.23 seconds
Started Jun 13 01:30:09 PM PDT 24
Finished Jun 13 02:16:15 PM PDT 24
Peak memory 289596 kb
Host smart-93d1dadb-8900-449e-b043-befe8a5f818b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705846452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2705846452
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1171644522
Short name T469
Test name
Test status
Simulation time 25460183744 ps
CPU time 1359.66 seconds
Started Jun 13 01:30:09 PM PDT 24
Finished Jun 13 01:52:50 PM PDT 24
Peak memory 288280 kb
Host smart-a37c8786-6c83-4712-886b-2134c5028bdf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171644522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1171644522
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3506457337
Short name T9
Test name
Test status
Simulation time 8299655341 ps
CPU time 341.05 seconds
Started Jun 13 01:30:11 PM PDT 24
Finished Jun 13 01:35:53 PM PDT 24
Peak memory 255456 kb
Host smart-adb5d9b2-4a36-4bf8-ba05-64ea42d286d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506457337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3506457337
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1176954946
Short name T500
Test name
Test status
Simulation time 300429309 ps
CPU time 30.87 seconds
Started Jun 13 01:30:07 PM PDT 24
Finished Jun 13 01:30:39 PM PDT 24
Peak memory 249048 kb
Host smart-160037bb-fe33-4f34-bbce-9ae532c58470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11769
54946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1176954946
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2734814714
Short name T61
Test name
Test status
Simulation time 1118410000 ps
CPU time 24.64 seconds
Started Jun 13 01:30:07 PM PDT 24
Finished Jun 13 01:30:32 PM PDT 24
Peak memory 255200 kb
Host smart-a7dda807-533c-4828-bdc4-fa2d6cb46cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27348
14714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2734814714
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2764094708
Short name T551
Test name
Test status
Simulation time 210993223 ps
CPU time 15.17 seconds
Started Jun 13 01:30:08 PM PDT 24
Finished Jun 13 01:30:24 PM PDT 24
Peak memory 256076 kb
Host smart-cadd05f8-6054-4114-931a-a965991e6c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27640
94708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2764094708
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1576553690
Short name T64
Test name
Test status
Simulation time 1348709407 ps
CPU time 21 seconds
Started Jun 13 01:30:08 PM PDT 24
Finished Jun 13 01:30:29 PM PDT 24
Peak memory 257304 kb
Host smart-688f0c97-a353-4e81-b673-43abadad6ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15765
53690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1576553690
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.3314233133
Short name T63
Test name
Test status
Simulation time 22795735833 ps
CPU time 2062.56 seconds
Started Jun 13 01:30:09 PM PDT 24
Finished Jun 13 02:04:33 PM PDT 24
Peak memory 306272 kb
Host smart-2b941e07-f9c1-469a-a79e-7a519cb4b8c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314233133 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.3314233133
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1511411170
Short name T207
Test name
Test status
Simulation time 45630412 ps
CPU time 2.42 seconds
Started Jun 13 01:28:50 PM PDT 24
Finished Jun 13 01:28:52 PM PDT 24
Peak memory 249208 kb
Host smart-b582d0f0-4208-4a91-8615-2d86c5438bf7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1511411170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1511411170
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.911471371
Short name T655
Test name
Test status
Simulation time 14036210858 ps
CPU time 1309.97 seconds
Started Jun 13 01:28:53 PM PDT 24
Finished Jun 13 01:50:43 PM PDT 24
Peak memory 289596 kb
Host smart-a95749af-1d63-4469-bcf2-79df7e091c22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911471371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.911471371
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2365883821
Short name T225
Test name
Test status
Simulation time 2936163835 ps
CPU time 39.31 seconds
Started Jun 13 01:28:52 PM PDT 24
Finished Jun 13 01:29:32 PM PDT 24
Peak memory 249164 kb
Host smart-6d698d1d-d786-49c8-9e4a-87bb2f9f0257
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2365883821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2365883821
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2294503320
Short name T389
Test name
Test status
Simulation time 6854355421 ps
CPU time 92.43 seconds
Started Jun 13 01:28:48 PM PDT 24
Finished Jun 13 01:30:21 PM PDT 24
Peak memory 257336 kb
Host smart-3c55eb0c-8d65-4ac9-af7b-318649164a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22945
03320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2294503320
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1114498369
Short name T393
Test name
Test status
Simulation time 906947680 ps
CPU time 42.31 seconds
Started Jun 13 01:28:48 PM PDT 24
Finished Jun 13 01:29:31 PM PDT 24
Peak memory 255852 kb
Host smart-278cd1ad-6543-4870-9e33-21a110634b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11144
98369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1114498369
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3703319961
Short name T545
Test name
Test status
Simulation time 19924160904 ps
CPU time 993.12 seconds
Started Jun 13 01:28:53 PM PDT 24
Finished Jun 13 01:45:26 PM PDT 24
Peak memory 273740 kb
Host smart-0ed71c6b-06be-4e21-a57a-816b53688aaf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703319961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3703319961
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1976974773
Short name T631
Test name
Test status
Simulation time 69206380500 ps
CPU time 1011.65 seconds
Started Jun 13 01:28:51 PM PDT 24
Finished Jun 13 01:45:43 PM PDT 24
Peak memory 284956 kb
Host smart-33765637-7006-438d-8129-9f9253ece21d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976974773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1976974773
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1383523316
Short name T531
Test name
Test status
Simulation time 550969387 ps
CPU time 35.31 seconds
Started Jun 13 01:28:47 PM PDT 24
Finished Jun 13 01:29:23 PM PDT 24
Peak memory 249100 kb
Host smart-b1008015-7d38-4f9b-88f8-5ca225f92a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13835
23316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1383523316
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1638696825
Short name T116
Test name
Test status
Simulation time 422724935 ps
CPU time 27.98 seconds
Started Jun 13 01:28:51 PM PDT 24
Finished Jun 13 01:29:19 PM PDT 24
Peak memory 249120 kb
Host smart-d9abd99f-f6e1-4127-ba23-cdb40212e848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16386
96825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1638696825
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2651859945
Short name T12
Test name
Test status
Simulation time 538530866 ps
CPU time 26.84 seconds
Started Jun 13 01:28:52 PM PDT 24
Finished Jun 13 01:29:20 PM PDT 24
Peak memory 277732 kb
Host smart-3940a423-e9db-4b22-96e6-1699a19f116c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2651859945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2651859945
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1261175126
Short name T607
Test name
Test status
Simulation time 525730664 ps
CPU time 33.78 seconds
Started Jun 13 01:28:53 PM PDT 24
Finished Jun 13 01:29:27 PM PDT 24
Peak memory 249048 kb
Host smart-9dc0de1b-e62a-494e-83b2-c1284a95e099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12611
75126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1261175126
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2104855082
Short name T679
Test name
Test status
Simulation time 29273952 ps
CPU time 3.15 seconds
Started Jun 13 01:28:47 PM PDT 24
Finished Jun 13 01:28:50 PM PDT 24
Peak memory 240812 kb
Host smart-0b14d5e1-3cf5-484d-a4fc-f94be265673a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21048
55082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2104855082
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3417255112
Short name T2
Test name
Test status
Simulation time 19826073515 ps
CPU time 679.58 seconds
Started Jun 13 01:28:52 PM PDT 24
Finished Jun 13 01:40:13 PM PDT 24
Peak memory 265492 kb
Host smart-ff6d6e19-a489-4aad-82ca-577d95822ac0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417255112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3417255112
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2678754072
Short name T649
Test name
Test status
Simulation time 414869794258 ps
CPU time 9652.24 seconds
Started Jun 13 01:28:52 PM PDT 24
Finished Jun 13 04:09:46 PM PDT 24
Peak memory 366008 kb
Host smart-a8949abd-80c6-43ac-a230-9a994b0fb266
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678754072 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2678754072
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2890349618
Short name T497
Test name
Test status
Simulation time 39811197069 ps
CPU time 2130.47 seconds
Started Jun 13 01:30:16 PM PDT 24
Finished Jun 13 02:05:47 PM PDT 24
Peak memory 289324 kb
Host smart-7a37d338-e3fc-4f88-be7a-e066a3df4ede
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890349618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2890349618
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.803979448
Short name T392
Test name
Test status
Simulation time 5778253021 ps
CPU time 130.18 seconds
Started Jun 13 01:30:13 PM PDT 24
Finished Jun 13 01:32:24 PM PDT 24
Peak memory 256384 kb
Host smart-a7cbeeb3-71c7-4e99-8f20-04067c0ddc3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80397
9448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.803979448
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1509375582
Short name T700
Test name
Test status
Simulation time 388346031 ps
CPU time 12.16 seconds
Started Jun 13 01:30:14 PM PDT 24
Finished Jun 13 01:30:27 PM PDT 24
Peak memory 253024 kb
Host smart-03b072b4-1302-4c13-8338-d139bd9101f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15093
75582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1509375582
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1417992537
Short name T111
Test name
Test status
Simulation time 288773056296 ps
CPU time 1772.23 seconds
Started Jun 13 01:30:14 PM PDT 24
Finished Jun 13 01:59:47 PM PDT 24
Peak memory 281948 kb
Host smart-cea82775-0b07-49ff-b353-5950d846f09f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417992537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1417992537
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.521864718
Short name T597
Test name
Test status
Simulation time 29595867641 ps
CPU time 1935.3 seconds
Started Jun 13 01:30:12 PM PDT 24
Finished Jun 13 02:02:28 PM PDT 24
Peak memory 281624 kb
Host smart-e83f2774-9def-4d97-8718-23ad47cd8c1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521864718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.521864718
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.4279219898
Short name T685
Test name
Test status
Simulation time 40908232722 ps
CPU time 150.65 seconds
Started Jun 13 01:30:16 PM PDT 24
Finished Jun 13 01:32:47 PM PDT 24
Peak memory 248400 kb
Host smart-c3706c56-cdeb-4aa8-b6ff-89237366ffdb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279219898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.4279219898
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3664193834
Short name T384
Test name
Test status
Simulation time 2408932435 ps
CPU time 44.67 seconds
Started Jun 13 01:30:14 PM PDT 24
Finished Jun 13 01:30:59 PM PDT 24
Peak memory 256632 kb
Host smart-6e2bc123-9cbd-4548-bfc8-1aaca14e5e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36641
93834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3664193834
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.474627970
Short name T351
Test name
Test status
Simulation time 355903451 ps
CPU time 28.22 seconds
Started Jun 13 01:30:16 PM PDT 24
Finished Jun 13 01:30:45 PM PDT 24
Peak memory 248140 kb
Host smart-b0fd26ec-5d9f-45ed-8079-a76a7bc96c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47462
7970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.474627970
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1848781412
Short name T539
Test name
Test status
Simulation time 3181097688 ps
CPU time 47.15 seconds
Started Jun 13 01:30:12 PM PDT 24
Finished Jun 13 01:31:00 PM PDT 24
Peak memory 248556 kb
Host smart-05c0ceac-2581-4c34-83e4-ef81b548b325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18487
81412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1848781412
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3218832136
Short name T441
Test name
Test status
Simulation time 6788926333 ps
CPU time 41.53 seconds
Started Jun 13 01:30:14 PM PDT 24
Finished Jun 13 01:30:56 PM PDT 24
Peak memory 257344 kb
Host smart-36f1386d-16ec-48c7-9ea7-231493521c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32188
32136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3218832136
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.226045442
Short name T523
Test name
Test status
Simulation time 120846388650 ps
CPU time 1614.61 seconds
Started Jun 13 01:30:16 PM PDT 24
Finished Jun 13 01:57:11 PM PDT 24
Peak memory 273640 kb
Host smart-9173b4e4-451c-41b8-8859-62f9f2eca5ce
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226045442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_han
dler_stress_all.226045442
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3360128819
Short name T383
Test name
Test status
Simulation time 115128270744 ps
CPU time 544.63 seconds
Started Jun 13 01:30:16 PM PDT 24
Finished Jun 13 01:39:21 PM PDT 24
Peak memory 272820 kb
Host smart-6d242b55-e275-49fe-9bbc-2b80bbf63913
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360128819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3360128819
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.708028521
Short name T676
Test name
Test status
Simulation time 30941263258 ps
CPU time 260.06 seconds
Started Jun 13 01:30:16 PM PDT 24
Finished Jun 13 01:34:36 PM PDT 24
Peak memory 251424 kb
Host smart-6f526dbb-9c0b-4f7b-bb9a-b3296afa05a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70802
8521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.708028521
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3758169726
Short name T388
Test name
Test status
Simulation time 148821170 ps
CPU time 4.05 seconds
Started Jun 13 01:30:23 PM PDT 24
Finished Jun 13 01:30:27 PM PDT 24
Peak memory 240880 kb
Host smart-7028551c-4ae3-4525-84f3-c154f55b695d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37581
69726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3758169726
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1410166836
Short name T329
Test name
Test status
Simulation time 46796349465 ps
CPU time 2596.81 seconds
Started Jun 13 01:30:22 PM PDT 24
Finished Jun 13 02:13:39 PM PDT 24
Peak memory 288828 kb
Host smart-b7e3e5dd-0fcf-4818-88b9-f24e9d14d182
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410166836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1410166836
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1346856664
Short name T702
Test name
Test status
Simulation time 58063281553 ps
CPU time 1975.5 seconds
Started Jun 13 01:30:20 PM PDT 24
Finished Jun 13 02:03:16 PM PDT 24
Peak memory 281652 kb
Host smart-e8260334-4b83-48b0-9aa5-2df85ee87b69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346856664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1346856664
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1463214794
Short name T534
Test name
Test status
Simulation time 9181754124 ps
CPU time 158.63 seconds
Started Jun 13 01:30:20 PM PDT 24
Finished Jun 13 01:32:59 PM PDT 24
Peak memory 255176 kb
Host smart-e4a9ff92-2123-4df3-b885-a71ad73b07c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463214794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1463214794
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2233434090
Short name T614
Test name
Test status
Simulation time 2530855197 ps
CPU time 39.13 seconds
Started Jun 13 01:30:14 PM PDT 24
Finished Jun 13 01:30:53 PM PDT 24
Peak memory 256480 kb
Host smart-294c1bb7-80b1-4b8f-be87-0b9c81142c0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22334
34090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2233434090
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2561828705
Short name T587
Test name
Test status
Simulation time 955303633 ps
CPU time 56.32 seconds
Started Jun 13 01:30:15 PM PDT 24
Finished Jun 13 01:31:12 PM PDT 24
Peak memory 256452 kb
Host smart-e30d9221-9eb9-42d9-b509-704df602c47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25618
28705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2561828705
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.4147618193
Short name T580
Test name
Test status
Simulation time 255642647 ps
CPU time 9.27 seconds
Started Jun 13 01:30:17 PM PDT 24
Finished Jun 13 01:30:27 PM PDT 24
Peak memory 249092 kb
Host smart-b7e3950f-0ba1-4a34-80f9-674e03631b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41476
18193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.4147618193
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2386411580
Short name T446
Test name
Test status
Simulation time 995489811 ps
CPU time 29.69 seconds
Started Jun 13 01:30:14 PM PDT 24
Finished Jun 13 01:30:45 PM PDT 24
Peak memory 249084 kb
Host smart-66c6b908-6bed-4430-b75c-244803f5b00b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23864
11580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2386411580
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3686164950
Short name T281
Test name
Test status
Simulation time 17395475522 ps
CPU time 1692 seconds
Started Jun 13 01:30:19 PM PDT 24
Finished Jun 13 01:58:32 PM PDT 24
Peak memory 299336 kb
Host smart-b4361162-cc5b-4d18-8248-3b8cc8377e0d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686164950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3686164950
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.3087495466
Short name T184
Test name
Test status
Simulation time 133626700588 ps
CPU time 3589.88 seconds
Started Jun 13 01:30:20 PM PDT 24
Finished Jun 13 02:30:11 PM PDT 24
Peak memory 339380 kb
Host smart-9f01051a-03fb-45d2-bb47-acff367fb54c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087495466 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.3087495466
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2489108300
Short name T356
Test name
Test status
Simulation time 43349868922 ps
CPU time 1122.43 seconds
Started Jun 13 01:30:19 PM PDT 24
Finished Jun 13 01:49:02 PM PDT 24
Peak memory 288480 kb
Host smart-d21823d4-afd7-40fa-a97a-78f3f6359007
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489108300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2489108300
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1059493600
Short name T690
Test name
Test status
Simulation time 3763028607 ps
CPU time 207.62 seconds
Started Jun 13 01:30:22 PM PDT 24
Finished Jun 13 01:33:50 PM PDT 24
Peak memory 257148 kb
Host smart-e2d05a28-43af-4957-887c-3824812ad16a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10594
93600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1059493600
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.586356460
Short name T39
Test name
Test status
Simulation time 797930080 ps
CPU time 13.97 seconds
Started Jun 13 01:30:20 PM PDT 24
Finished Jun 13 01:30:35 PM PDT 24
Peak memory 249288 kb
Host smart-3a7fd530-c39d-488e-aa2e-d78a67936d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58635
6460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.586356460
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.4092418511
Short name T596
Test name
Test status
Simulation time 40914620055 ps
CPU time 1300.79 seconds
Started Jun 13 01:30:22 PM PDT 24
Finished Jun 13 01:52:04 PM PDT 24
Peak memory 265512 kb
Host smart-bcc8947f-d44b-4a32-88e0-f49b70477e18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092418511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.4092418511
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2779860944
Short name T10
Test name
Test status
Simulation time 11518914103 ps
CPU time 214.1 seconds
Started Jun 13 01:30:20 PM PDT 24
Finished Jun 13 01:33:55 PM PDT 24
Peak memory 248768 kb
Host smart-e8250f6e-894e-4059-9286-1ca1d62c61aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779860944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2779860944
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.125129460
Short name T462
Test name
Test status
Simulation time 75571187 ps
CPU time 5.08 seconds
Started Jun 13 01:30:20 PM PDT 24
Finished Jun 13 01:30:26 PM PDT 24
Peak memory 251252 kb
Host smart-0215f4bb-d425-400e-bf18-116b084fc1e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12512
9460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.125129460
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2095582271
Short name T600
Test name
Test status
Simulation time 387367037 ps
CPU time 26.78 seconds
Started Jun 13 01:30:21 PM PDT 24
Finished Jun 13 01:30:48 PM PDT 24
Peak memory 255840 kb
Host smart-a3ae816b-21a2-4340-bdfc-04f9ee3eef6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20955
82271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2095582271
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3442443568
Short name T585
Test name
Test status
Simulation time 118146279 ps
CPU time 16.09 seconds
Started Jun 13 01:30:21 PM PDT 24
Finished Jun 13 01:30:38 PM PDT 24
Peak memory 247816 kb
Host smart-4fbf6859-adc4-4cb2-9d99-fe51fee3866d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34424
43568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3442443568
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1085588371
Short name T352
Test name
Test status
Simulation time 54675775 ps
CPU time 4.68 seconds
Started Jun 13 01:30:19 PM PDT 24
Finished Jun 13 01:30:24 PM PDT 24
Peak memory 240864 kb
Host smart-307791db-a894-4a9a-b6c3-52454d66651f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10855
88371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1085588371
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.4246144715
Short name T247
Test name
Test status
Simulation time 46590594034 ps
CPU time 2524.25 seconds
Started Jun 13 01:30:26 PM PDT 24
Finished Jun 13 02:12:31 PM PDT 24
Peak memory 289400 kb
Host smart-e0288139-d0e3-4415-8e35-cc015e3caa7b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246144715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.4246144715
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.740746138
Short name T387
Test name
Test status
Simulation time 56515420974 ps
CPU time 1696.89 seconds
Started Jun 13 01:30:28 PM PDT 24
Finished Jun 13 01:58:46 PM PDT 24
Peak memory 273112 kb
Host smart-ffe2f11b-4ae5-4843-b26d-9642da04e658
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740746138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.740746138
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2295161802
Short name T417
Test name
Test status
Simulation time 16810335688 ps
CPU time 169.18 seconds
Started Jun 13 01:30:27 PM PDT 24
Finished Jun 13 01:33:16 PM PDT 24
Peak memory 257280 kb
Host smart-cdaa8cd1-3db2-4e99-af66-72a37fc446ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22951
61802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2295161802
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3797824307
Short name T478
Test name
Test status
Simulation time 11792015438 ps
CPU time 46.8 seconds
Started Jun 13 01:30:26 PM PDT 24
Finished Jun 13 01:31:14 PM PDT 24
Peak memory 256012 kb
Host smart-20ee9dda-055a-4abd-825c-074bcd7488fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37978
24307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3797824307
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3862838105
Short name T295
Test name
Test status
Simulation time 15390420581 ps
CPU time 1171.84 seconds
Started Jun 13 01:30:28 PM PDT 24
Finished Jun 13 01:50:00 PM PDT 24
Peak memory 284672 kb
Host smart-05242791-c563-4e19-b184-edbf23a8ea99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862838105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3862838105
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1416065156
Short name T402
Test name
Test status
Simulation time 110643939510 ps
CPU time 2039.22 seconds
Started Jun 13 01:30:37 PM PDT 24
Finished Jun 13 02:04:38 PM PDT 24
Peak memory 286460 kb
Host smart-1944a565-1910-4bea-9aef-a94e05103209
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416065156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1416065156
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.4198722914
Short name T482
Test name
Test status
Simulation time 12427377292 ps
CPU time 136.2 seconds
Started Jun 13 01:30:28 PM PDT 24
Finished Jun 13 01:32:45 PM PDT 24
Peak memory 254400 kb
Host smart-c4deaa15-a997-4aee-8c8d-8375a4c1f5bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198722914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.4198722914
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3435972860
Short name T519
Test name
Test status
Simulation time 992343060 ps
CPU time 23.53 seconds
Started Jun 13 01:30:27 PM PDT 24
Finished Jun 13 01:30:51 PM PDT 24
Peak memory 249052 kb
Host smart-03638d29-65db-4841-8580-72cdfe48ec67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34359
72860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3435972860
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3553184495
Short name T659
Test name
Test status
Simulation time 419724756 ps
CPU time 26.72 seconds
Started Jun 13 01:30:37 PM PDT 24
Finished Jun 13 01:31:04 PM PDT 24
Peak memory 255920 kb
Host smart-b9d286fc-4fe9-48c0-8315-95383c43cb64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35531
84495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3553184495
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.697722964
Short name T657
Test name
Test status
Simulation time 2123934566 ps
CPU time 34.43 seconds
Started Jun 13 01:30:26 PM PDT 24
Finished Jun 13 01:31:01 PM PDT 24
Peak memory 249088 kb
Host smart-33a238ee-817e-481d-a6ab-ce3c641813d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69772
2964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.697722964
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.4113936841
Short name T62
Test name
Test status
Simulation time 20821876901 ps
CPU time 1278.4 seconds
Started Jun 13 01:30:33 PM PDT 24
Finished Jun 13 01:51:53 PM PDT 24
Peak memory 269576 kb
Host smart-6dd4a6ec-84cf-4c4e-8d18-7030ce9110e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113936841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.4113936841
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.816670737
Short name T365
Test name
Test status
Simulation time 1726270164 ps
CPU time 99.69 seconds
Started Jun 13 01:30:31 PM PDT 24
Finished Jun 13 01:32:11 PM PDT 24
Peak memory 257144 kb
Host smart-57312de9-0cc1-4e37-86ae-4565081dda7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81667
0737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.816670737
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3317613196
Short name T213
Test name
Test status
Simulation time 267060652 ps
CPU time 8.21 seconds
Started Jun 13 01:30:29 PM PDT 24
Finished Jun 13 01:30:38 PM PDT 24
Peak memory 249476 kb
Host smart-c9999c37-1fd0-48d1-8192-c8f0f7e1fadf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33176
13196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3317613196
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2139674557
Short name T231
Test name
Test status
Simulation time 251425259839 ps
CPU time 3258.42 seconds
Started Jun 13 01:30:56 PM PDT 24
Finished Jun 13 02:25:15 PM PDT 24
Peak memory 289328 kb
Host smart-8db9ee47-2ea2-44e6-acf5-6a96d596cddb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139674557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2139674557
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.4148028019
Short name T399
Test name
Test status
Simulation time 16198609788 ps
CPU time 1314.36 seconds
Started Jun 13 01:30:32 PM PDT 24
Finished Jun 13 01:52:27 PM PDT 24
Peak memory 289512 kb
Host smart-d32d5cb6-8685-4ab5-85f8-5bc494ad9261
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148028019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.4148028019
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1007418368
Short name T527
Test name
Test status
Simulation time 20685891926 ps
CPU time 164.33 seconds
Started Jun 13 01:30:32 PM PDT 24
Finished Jun 13 01:33:18 PM PDT 24
Peak memory 255716 kb
Host smart-81b9bcba-def4-4b1f-8490-c8d427bb820b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007418368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1007418368
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.4096264536
Short name T349
Test name
Test status
Simulation time 1020512237 ps
CPU time 32.48 seconds
Started Jun 13 01:30:27 PM PDT 24
Finished Jun 13 01:31:00 PM PDT 24
Peak memory 249116 kb
Host smart-6cef0dcf-f4e0-4b7e-bfd4-8b54178e0fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40962
64536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.4096264536
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.1780988337
Short name T532
Test name
Test status
Simulation time 352753218 ps
CPU time 30.33 seconds
Started Jun 13 01:30:35 PM PDT 24
Finished Jun 13 01:31:05 PM PDT 24
Peak memory 249028 kb
Host smart-1fa88ea8-526b-43f0-9855-10b5e1593b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17809
88337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1780988337
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.472232244
Short name T90
Test name
Test status
Simulation time 217616028 ps
CPU time 20.08 seconds
Started Jun 13 01:30:28 PM PDT 24
Finished Jun 13 01:30:49 PM PDT 24
Peak memory 248212 kb
Host smart-528cf222-fa8f-4d6e-a4a5-f0c1cec6000e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47223
2244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.472232244
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3864347282
Short name T516
Test name
Test status
Simulation time 774756800 ps
CPU time 27.39 seconds
Started Jun 13 01:30:38 PM PDT 24
Finished Jun 13 01:31:07 PM PDT 24
Peak memory 249076 kb
Host smart-1445a72b-4719-4fb9-8f25-3f65a5165384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38643
47282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3864347282
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3798220336
Short name T72
Test name
Test status
Simulation time 55930055310 ps
CPU time 1110.51 seconds
Started Jun 13 01:30:33 PM PDT 24
Finished Jun 13 01:49:05 PM PDT 24
Peak memory 284032 kb
Host smart-5938ffb2-94e6-4460-8df0-ef148e284113
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798220336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3798220336
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.434699790
Short name T248
Test name
Test status
Simulation time 56961204054 ps
CPU time 1445.8 seconds
Started Jun 13 01:30:34 PM PDT 24
Finished Jun 13 01:54:41 PM PDT 24
Peak memory 290224 kb
Host smart-1ab9b160-8e01-4cff-922c-7e6cd557923f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434699790 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.434699790
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2533621976
Short name T578
Test name
Test status
Simulation time 40396120032 ps
CPU time 1360.63 seconds
Started Jun 13 01:30:33 PM PDT 24
Finished Jun 13 01:53:16 PM PDT 24
Peak memory 266608 kb
Host smart-d5456aa7-2301-423b-904e-4efc16486026
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533621976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2533621976
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.735593058
Short name T436
Test name
Test status
Simulation time 4078753485 ps
CPU time 253.77 seconds
Started Jun 13 01:30:34 PM PDT 24
Finished Jun 13 01:34:49 PM PDT 24
Peak memory 257280 kb
Host smart-ed16a307-4eec-4750-bfd1-6e3e17e03bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73559
3058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.735593058
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2405090736
Short name T411
Test name
Test status
Simulation time 2438872159 ps
CPU time 37.05 seconds
Started Jun 13 01:30:31 PM PDT 24
Finished Jun 13 01:31:09 PM PDT 24
Peak memory 249272 kb
Host smart-42bcbe28-3135-4d61-ae21-6a84b8282af2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24050
90736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2405090736
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.780546945
Short name T270
Test name
Test status
Simulation time 62639021265 ps
CPU time 2130.27 seconds
Started Jun 13 01:30:37 PM PDT 24
Finished Jun 13 02:06:08 PM PDT 24
Peak memory 286804 kb
Host smart-7f6958f7-4409-46bc-a618-d07089003c78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780546945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.780546945
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.905684055
Short name T347
Test name
Test status
Simulation time 862044796 ps
CPU time 31.3 seconds
Started Jun 13 01:30:33 PM PDT 24
Finished Jun 13 01:31:06 PM PDT 24
Peak memory 256236 kb
Host smart-a792ddca-7c94-4da3-9b13-a7afec7aca19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90568
4055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.905684055
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2306253167
Short name T566
Test name
Test status
Simulation time 202876640 ps
CPU time 7.28 seconds
Started Jun 13 01:30:33 PM PDT 24
Finished Jun 13 01:30:42 PM PDT 24
Peak memory 252208 kb
Host smart-20429531-3045-4940-8759-0dfe9e5760c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23062
53167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2306253167
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.807674778
Short name T459
Test name
Test status
Simulation time 300869897 ps
CPU time 34.75 seconds
Started Jun 13 01:30:35 PM PDT 24
Finished Jun 13 01:31:11 PM PDT 24
Peak memory 255616 kb
Host smart-7de72d9d-fe36-4589-a196-ec03b9a83181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80767
4778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.807674778
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2842240053
Short name T229
Test name
Test status
Simulation time 97075119 ps
CPU time 6.28 seconds
Started Jun 13 01:30:33 PM PDT 24
Finished Jun 13 01:30:41 PM PDT 24
Peak memory 249088 kb
Host smart-98540a4d-c030-4740-b701-8191398326b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28422
40053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2842240053
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.744872092
Short name T609
Test name
Test status
Simulation time 32026291019 ps
CPU time 1292 seconds
Started Jun 13 01:30:38 PM PDT 24
Finished Jun 13 01:52:11 PM PDT 24
Peak memory 289860 kb
Host smart-ad020506-4390-4181-8b6a-d94cc7c23efc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744872092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.744872092
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3328624934
Short name T93
Test name
Test status
Simulation time 22887287655 ps
CPU time 2429.74 seconds
Started Jun 13 01:30:37 PM PDT 24
Finished Jun 13 02:11:08 PM PDT 24
Peak memory 305892 kb
Host smart-ef184979-0f7d-4a16-9a3f-06939478f0c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328624934 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3328624934
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.831685878
Short name T650
Test name
Test status
Simulation time 347897839537 ps
CPU time 1965.83 seconds
Started Jun 13 01:30:38 PM PDT 24
Finished Jun 13 02:03:25 PM PDT 24
Peak memory 283104 kb
Host smart-f8d95bbe-6976-4647-bc8d-02147ebb7e39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831685878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.831685878
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.4004565568
Short name T404
Test name
Test status
Simulation time 6540911275 ps
CPU time 178.9 seconds
Started Jun 13 01:30:38 PM PDT 24
Finished Jun 13 01:33:37 PM PDT 24
Peak memory 256016 kb
Host smart-f2c19dae-ae7f-4025-8927-d2e79aeff46a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40045
65568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.4004565568
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1419676074
Short name T616
Test name
Test status
Simulation time 749707292 ps
CPU time 48.46 seconds
Started Jun 13 01:30:37 PM PDT 24
Finished Jun 13 01:31:27 PM PDT 24
Peak memory 256300 kb
Host smart-1b7d7779-4fbb-40dc-b3e4-1f6902aaad52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14196
76074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1419676074
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.2768150101
Short name T456
Test name
Test status
Simulation time 29059583297 ps
CPU time 985.66 seconds
Started Jun 13 01:30:40 PM PDT 24
Finished Jun 13 01:47:06 PM PDT 24
Peak memory 269568 kb
Host smart-3334ca86-d5db-4e6c-b8ab-2b331e78d922
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768150101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2768150101
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3061270703
Short name T280
Test name
Test status
Simulation time 137163705531 ps
CPU time 1953.29 seconds
Started Jun 13 01:30:47 PM PDT 24
Finished Jun 13 02:03:21 PM PDT 24
Peak memory 287360 kb
Host smart-41fe6102-a0bf-4ffc-88d9-5baebc70af1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061270703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3061270703
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2734134813
Short name T477
Test name
Test status
Simulation time 7653077899 ps
CPU time 306.26 seconds
Started Jun 13 01:30:39 PM PDT 24
Finished Jun 13 01:35:46 PM PDT 24
Peak memory 248524 kb
Host smart-dbff135c-362f-44b9-8159-4711278ae34a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734134813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2734134813
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1689822223
Short name T681
Test name
Test status
Simulation time 8227673229 ps
CPU time 54.26 seconds
Started Jun 13 01:30:37 PM PDT 24
Finished Jun 13 01:31:33 PM PDT 24
Peak memory 256908 kb
Host smart-bc68d275-b096-408f-88a2-79993177e25b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16898
22223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1689822223
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.1732562634
Short name T564
Test name
Test status
Simulation time 973398283 ps
CPU time 19.74 seconds
Started Jun 13 01:30:40 PM PDT 24
Finished Jun 13 01:31:00 PM PDT 24
Peak memory 255304 kb
Host smart-f6d47dda-5f86-4308-9c15-6dd82f2e789e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17325
62634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1732562634
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3728964529
Short name T611
Test name
Test status
Simulation time 2428568815 ps
CPU time 40.19 seconds
Started Jun 13 01:30:38 PM PDT 24
Finished Jun 13 01:31:19 PM PDT 24
Peak memory 249172 kb
Host smart-685fe02d-2ca2-499f-a482-fa7a5410de62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37289
64529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3728964529
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.4176302653
Short name T550
Test name
Test status
Simulation time 240448823 ps
CPU time 25.57 seconds
Started Jun 13 01:30:38 PM PDT 24
Finished Jun 13 01:31:04 PM PDT 24
Peak memory 249084 kb
Host smart-88d5c727-908b-4b6d-956a-a41689051b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41763
02653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.4176302653
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.600398690
Short name T251
Test name
Test status
Simulation time 68697977590 ps
CPU time 3874.43 seconds
Started Jun 13 01:30:45 PM PDT 24
Finished Jun 13 02:35:20 PM PDT 24
Peak memory 298380 kb
Host smart-8d3957dd-3c47-4815-ae4e-79a6ffe3d08b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600398690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.600398690
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.3375185917
Short name T183
Test name
Test status
Simulation time 51548805418 ps
CPU time 2856.04 seconds
Started Jun 13 01:30:46 PM PDT 24
Finished Jun 13 02:18:23 PM PDT 24
Peak memory 322624 kb
Host smart-cc26ce88-56d8-46e1-b1f9-db8b0e5597f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375185917 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.3375185917
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1994126972
Short name T598
Test name
Test status
Simulation time 6469507619 ps
CPU time 739.56 seconds
Started Jun 13 01:30:47 PM PDT 24
Finished Jun 13 01:43:07 PM PDT 24
Peak memory 273696 kb
Host smart-3ea1dab2-8a04-4b2b-a62a-5b76fe395684
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994126972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1994126972
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.126120224
Short name T660
Test name
Test status
Simulation time 1668072180 ps
CPU time 100.38 seconds
Started Jun 13 01:30:45 PM PDT 24
Finished Jun 13 01:32:26 PM PDT 24
Peak memory 257048 kb
Host smart-50fead50-e71d-456c-bc84-26e90a59b850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12612
0224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.126120224
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3090394560
Short name T646
Test name
Test status
Simulation time 62570381 ps
CPU time 4.81 seconds
Started Jun 13 01:30:47 PM PDT 24
Finished Jun 13 01:30:52 PM PDT 24
Peak memory 240864 kb
Host smart-f4f6e33a-14bd-4a5e-abf6-b614e31f839a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30903
94560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3090394560
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1020358360
Short name T691
Test name
Test status
Simulation time 110036223105 ps
CPU time 1238.7 seconds
Started Jun 13 01:30:51 PM PDT 24
Finished Jun 13 01:51:30 PM PDT 24
Peak memory 271492 kb
Host smart-6c195981-d4bd-43ec-9a64-3f592e966919
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020358360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1020358360
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.1019854344
Short name T102
Test name
Test status
Simulation time 12801460165 ps
CPU time 1369.53 seconds
Started Jun 13 01:30:52 PM PDT 24
Finished Jun 13 01:53:42 PM PDT 24
Peak memory 289520 kb
Host smart-00a59fb5-6651-41d6-9b44-2712e3d329d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019854344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1019854344
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.268478984
Short name T301
Test name
Test status
Simulation time 11369036980 ps
CPU time 487.3 seconds
Started Jun 13 01:30:47 PM PDT 24
Finished Jun 13 01:38:55 PM PDT 24
Peak memory 248664 kb
Host smart-b4572b08-562c-4627-9237-93cdbf68d3b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268478984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.268478984
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1726666643
Short name T647
Test name
Test status
Simulation time 1531324608 ps
CPU time 44.14 seconds
Started Jun 13 01:30:46 PM PDT 24
Finished Jun 13 01:31:31 PM PDT 24
Peak memory 257104 kb
Host smart-fb405ed9-5fc0-450c-ae56-532186c13eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17266
66643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1726666643
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2896426884
Short name T522
Test name
Test status
Simulation time 390216008 ps
CPU time 18.36 seconds
Started Jun 13 01:30:46 PM PDT 24
Finished Jun 13 01:31:05 PM PDT 24
Peak memory 247820 kb
Host smart-197c1184-ddab-484d-adb1-133e39366aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28964
26884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2896426884
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.810961405
Short name T367
Test name
Test status
Simulation time 1203636490 ps
CPU time 38.85 seconds
Started Jun 13 01:30:46 PM PDT 24
Finished Jun 13 01:31:25 PM PDT 24
Peak memory 249108 kb
Host smart-28377db8-1815-4397-baf3-59b077736863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81096
1405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.810961405
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2404914144
Short name T188
Test name
Test status
Simulation time 406595502536 ps
CPU time 2112.21 seconds
Started Jun 13 01:30:52 PM PDT 24
Finished Jun 13 02:06:05 PM PDT 24
Peak memory 290200 kb
Host smart-bae1ff0e-1fb1-47b3-b175-598380f9505d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404914144 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2404914144
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2327364396
Short name T484
Test name
Test status
Simulation time 42350829422 ps
CPU time 1088.56 seconds
Started Jun 13 01:30:52 PM PDT 24
Finished Jun 13 01:49:01 PM PDT 24
Peak memory 273696 kb
Host smart-919b5da6-1d79-441d-b23a-7d67a78f4e85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327364396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2327364396
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.4028831361
Short name T350
Test name
Test status
Simulation time 35335573 ps
CPU time 6.75 seconds
Started Jun 13 01:30:51 PM PDT 24
Finished Jun 13 01:30:58 PM PDT 24
Peak memory 254716 kb
Host smart-c96d8d11-936c-4f86-b069-6969a006daa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40288
31361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.4028831361
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3273708320
Short name T669
Test name
Test status
Simulation time 787587729 ps
CPU time 51.1 seconds
Started Jun 13 01:30:52 PM PDT 24
Finished Jun 13 01:31:43 PM PDT 24
Peak memory 249064 kb
Host smart-4b24175c-523c-43a7-a58d-356c7c0eb89f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32737
08320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3273708320
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2392598989
Short name T317
Test name
Test status
Simulation time 25569046484 ps
CPU time 1346.38 seconds
Started Jun 13 01:30:57 PM PDT 24
Finished Jun 13 01:53:24 PM PDT 24
Peak memory 289856 kb
Host smart-52fbfd4f-5dc2-49cd-bc94-fe21609d460c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392598989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2392598989
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1609442059
Short name T260
Test name
Test status
Simulation time 139298600883 ps
CPU time 1873.25 seconds
Started Jun 13 01:31:01 PM PDT 24
Finished Jun 13 02:02:15 PM PDT 24
Peak memory 285824 kb
Host smart-62961e3d-5d61-4548-bec4-dd8895aa2119
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609442059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1609442059
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3238789559
Short name T664
Test name
Test status
Simulation time 17568714158 ps
CPU time 367.1 seconds
Started Jun 13 01:30:51 PM PDT 24
Finished Jun 13 01:36:59 PM PDT 24
Peak memory 248268 kb
Host smart-28663abb-520a-4271-bf59-f53c41bdf559
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238789559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3238789559
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2657214545
Short name T481
Test name
Test status
Simulation time 737329482 ps
CPU time 44.66 seconds
Started Jun 13 01:30:58 PM PDT 24
Finished Jun 13 01:31:44 PM PDT 24
Peak memory 256348 kb
Host smart-b10f7f81-cb3b-40d8-9c6d-4afb567b4177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26572
14545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2657214545
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1564580926
Short name T443
Test name
Test status
Simulation time 1725833751 ps
CPU time 27.01 seconds
Started Jun 13 01:30:52 PM PDT 24
Finished Jun 13 01:31:20 PM PDT 24
Peak memory 256188 kb
Host smart-6e678bfc-f044-42fa-8378-3cbdd9e6867f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15645
80926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1564580926
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3302368894
Short name T673
Test name
Test status
Simulation time 990626183 ps
CPU time 61.2 seconds
Started Jun 13 01:30:52 PM PDT 24
Finished Jun 13 01:31:54 PM PDT 24
Peak memory 248268 kb
Host smart-36defd24-4780-4bc5-9d08-817a964a55cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33023
68894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3302368894
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.640628808
Short name T643
Test name
Test status
Simulation time 325636319 ps
CPU time 12.89 seconds
Started Jun 13 01:30:52 PM PDT 24
Finished Jun 13 01:31:06 PM PDT 24
Peak memory 249128 kb
Host smart-bb555f24-ff2e-423f-928f-a8a802857f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64062
8808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.640628808
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.11013491
Short name T91
Test name
Test status
Simulation time 17102028812 ps
CPU time 1245.53 seconds
Started Jun 13 01:30:59 PM PDT 24
Finished Jun 13 01:51:46 PM PDT 24
Peak memory 289556 kb
Host smart-dcd2f0fa-d8bd-4ca8-bb83-ecbc863c42a6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11013491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_hand
ler_stress_all.11013491
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3385993512
Short name T674
Test name
Test status
Simulation time 22584809684 ps
CPU time 1265.16 seconds
Started Jun 13 01:31:06 PM PDT 24
Finished Jun 13 01:52:12 PM PDT 24
Peak memory 272164 kb
Host smart-4b3c595c-bcc7-4e18-9cef-3e4b2986f684
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385993512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3385993512
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3355212297
Short name T634
Test name
Test status
Simulation time 50868084160 ps
CPU time 268.34 seconds
Started Jun 13 01:31:05 PM PDT 24
Finished Jun 13 01:35:34 PM PDT 24
Peak memory 257196 kb
Host smart-1d9f4965-fb94-47fb-bdaf-5e2e285bdd7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33552
12297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3355212297
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1785968753
Short name T706
Test name
Test status
Simulation time 560567895 ps
CPU time 33.72 seconds
Started Jun 13 01:30:59 PM PDT 24
Finished Jun 13 01:31:34 PM PDT 24
Peak memory 255956 kb
Host smart-3f2fedd2-be06-41a0-b88c-a93457a2ec2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17859
68753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1785968753
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2110279049
Short name T99
Test name
Test status
Simulation time 39261105925 ps
CPU time 1590.4 seconds
Started Jun 13 01:31:07 PM PDT 24
Finished Jun 13 01:57:38 PM PDT 24
Peak memory 281972 kb
Host smart-8fa80aa4-0304-48a7-b368-b864e50d2a9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110279049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2110279049
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1651953613
Short name T42
Test name
Test status
Simulation time 114134924500 ps
CPU time 1816.47 seconds
Started Jun 13 01:31:06 PM PDT 24
Finished Jun 13 02:01:24 PM PDT 24
Peak memory 273192 kb
Host smart-368889b8-cd6d-45e1-ab55-142948e8539a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651953613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1651953613
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3641471385
Short name T656
Test name
Test status
Simulation time 32482617920 ps
CPU time 228.33 seconds
Started Jun 13 01:31:04 PM PDT 24
Finished Jun 13 01:34:53 PM PDT 24
Peak memory 255444 kb
Host smart-89c9dcbc-1a9f-466b-8dac-13bc7caf78ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641471385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3641471385
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.4072804957
Short name T613
Test name
Test status
Simulation time 400843521 ps
CPU time 23.95 seconds
Started Jun 13 01:30:59 PM PDT 24
Finished Jun 13 01:31:23 PM PDT 24
Peak memory 249028 kb
Host smart-e7fc16ce-8ed8-45fb-bce5-a347aad0abdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40728
04957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.4072804957
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1794320398
Short name T100
Test name
Test status
Simulation time 576062201 ps
CPU time 16.7 seconds
Started Jun 13 01:30:58 PM PDT 24
Finished Jun 13 01:31:15 PM PDT 24
Peak memory 255912 kb
Host smart-a49fdb51-adf2-4b93-b96c-c844fe38c2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17943
20398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1794320398
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2080844221
Short name T46
Test name
Test status
Simulation time 72618380 ps
CPU time 6.08 seconds
Started Jun 13 01:31:05 PM PDT 24
Finished Jun 13 01:31:12 PM PDT 24
Peak memory 239792 kb
Host smart-ec7e8366-1a52-44cd-9e0c-53d8d31743f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20808
44221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2080844221
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3308319193
Short name T496
Test name
Test status
Simulation time 504089134 ps
CPU time 14.87 seconds
Started Jun 13 01:30:59 PM PDT 24
Finished Jun 13 01:31:14 PM PDT 24
Peak memory 256344 kb
Host smart-3cb83cf3-2bd6-4759-bd42-26f3a011f363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33083
19193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3308319193
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.4146952315
Short name T556
Test name
Test status
Simulation time 7723498425 ps
CPU time 398.14 seconds
Started Jun 13 01:31:06 PM PDT 24
Finished Jun 13 01:37:45 PM PDT 24
Peak memory 273660 kb
Host smart-9ea832ed-47b0-4e9e-a80c-66234f3d932e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146952315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.4146952315
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.4208422967
Short name T227
Test name
Test status
Simulation time 248717849604 ps
CPU time 3965.67 seconds
Started Jun 13 01:31:06 PM PDT 24
Finished Jun 13 02:37:13 PM PDT 24
Peak memory 306644 kb
Host smart-5beca301-9189-4ec8-bf33-41b76cb957f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208422967 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.4208422967
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.3213929467
Short name T193
Test name
Test status
Simulation time 20534266 ps
CPU time 2.34 seconds
Started Jun 13 01:28:55 PM PDT 24
Finished Jun 13 01:28:58 PM PDT 24
Peak memory 249248 kb
Host smart-c96acdad-b919-4e33-8d07-273a66e75226
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3213929467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3213929467
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1840366746
Short name T694
Test name
Test status
Simulation time 126639389921 ps
CPU time 2055.61 seconds
Started Jun 13 01:28:57 PM PDT 24
Finished Jun 13 02:03:14 PM PDT 24
Peak memory 273696 kb
Host smart-896a2542-54f7-4b4d-8f67-1a56e3da4285
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840366746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1840366746
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1695814933
Short name T375
Test name
Test status
Simulation time 448368057 ps
CPU time 20.92 seconds
Started Jun 13 01:28:57 PM PDT 24
Finished Jun 13 01:29:19 PM PDT 24
Peak memory 249072 kb
Host smart-5114f68a-d807-4826-bf7a-16a033d88404
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1695814933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1695814933
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3330751385
Short name T525
Test name
Test status
Simulation time 3792917518 ps
CPU time 114.53 seconds
Started Jun 13 01:28:57 PM PDT 24
Finished Jun 13 01:30:52 PM PDT 24
Peak memory 250372 kb
Host smart-95a66d0d-abdc-4deb-aadd-3c2ae349ea80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33307
51385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3330751385
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2611119288
Short name T371
Test name
Test status
Simulation time 3369602662 ps
CPU time 54.44 seconds
Started Jun 13 01:28:52 PM PDT 24
Finished Jun 13 01:29:47 PM PDT 24
Peak memory 249204 kb
Host smart-57f75bff-cfbc-47d9-9ecb-1c9b8c40e44e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26111
19288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2611119288
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.3790944701
Short name T671
Test name
Test status
Simulation time 13553414241 ps
CPU time 1151.94 seconds
Started Jun 13 01:28:55 PM PDT 24
Finished Jun 13 01:48:08 PM PDT 24
Peak memory 289488 kb
Host smart-d95cf208-afc7-4912-a155-8f0a4bd44995
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790944701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3790944701
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2321861771
Short name T3
Test name
Test status
Simulation time 678142431 ps
CPU time 25.4 seconds
Started Jun 13 01:28:51 PM PDT 24
Finished Jun 13 01:29:16 PM PDT 24
Peak memory 256340 kb
Host smart-39c07f63-ee3d-4a7e-b07f-458b4e532366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23218
61771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2321861771
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1740448411
Short name T103
Test name
Test status
Simulation time 134877267 ps
CPU time 10.75 seconds
Started Jun 13 01:28:50 PM PDT 24
Finished Jun 13 01:29:01 PM PDT 24
Peak memory 256056 kb
Host smart-a6d2d06a-6ab9-4948-b0df-ddfb73478a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17404
48411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1740448411
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.21982783
Short name T13
Test name
Test status
Simulation time 1040513449 ps
CPU time 14.8 seconds
Started Jun 13 01:28:56 PM PDT 24
Finished Jun 13 01:29:11 PM PDT 24
Peak memory 270952 kb
Host smart-f0bfbaa8-9e3f-4a44-91fc-66e3874a3188
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=21982783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.21982783
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1658935151
Short name T608
Test name
Test status
Simulation time 1805407223 ps
CPU time 27.85 seconds
Started Jun 13 01:28:54 PM PDT 24
Finished Jun 13 01:29:23 PM PDT 24
Peak memory 255432 kb
Host smart-85329e0d-e39f-467c-82ec-adb551765dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16589
35151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1658935151
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1895608148
Short name T259
Test name
Test status
Simulation time 3994464430 ps
CPU time 21.62 seconds
Started Jun 13 01:28:51 PM PDT 24
Finished Jun 13 01:29:13 PM PDT 24
Peak memory 249084 kb
Host smart-9af32b70-d1ac-46cc-a118-b07aa34a2990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18956
08148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1895608148
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1077025838
Short name T453
Test name
Test status
Simulation time 162347729306 ps
CPU time 2724.83 seconds
Started Jun 13 01:31:14 PM PDT 24
Finished Jun 13 02:16:39 PM PDT 24
Peak memory 286384 kb
Host smart-14e4c78f-f2d4-4d20-bbe9-97a1b07aae91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077025838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1077025838
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3771339329
Short name T541
Test name
Test status
Simulation time 2530743893 ps
CPU time 96.55 seconds
Started Jun 13 01:31:13 PM PDT 24
Finished Jun 13 01:32:51 PM PDT 24
Peak memory 250460 kb
Host smart-da44d9d4-c708-458c-8d95-2ad83ef0e169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37713
39329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3771339329
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1478626221
Short name T553
Test name
Test status
Simulation time 937012625 ps
CPU time 14.1 seconds
Started Jun 13 01:31:05 PM PDT 24
Finished Jun 13 01:31:20 PM PDT 24
Peak memory 254196 kb
Host smart-01d04d9c-e371-45f7-8000-6904f30d06eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14786
26221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1478626221
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.4234224361
Short name T696
Test name
Test status
Simulation time 133868361335 ps
CPU time 2260.4 seconds
Started Jun 13 01:31:17 PM PDT 24
Finished Jun 13 02:08:57 PM PDT 24
Peak memory 273772 kb
Host smart-54dc092b-3c3c-4267-8174-f35e7fe97140
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234224361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.4234224361
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.1948838571
Short name T307
Test name
Test status
Simulation time 5811574572 ps
CPU time 244.6 seconds
Started Jun 13 01:31:22 PM PDT 24
Finished Jun 13 01:35:29 PM PDT 24
Peak memory 254908 kb
Host smart-986c9277-8f9d-46d9-962c-5cbbf1dac1a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948838571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1948838571
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2779785985
Short name T668
Test name
Test status
Simulation time 414356394 ps
CPU time 22.4 seconds
Started Jun 13 01:31:05 PM PDT 24
Finished Jun 13 01:31:28 PM PDT 24
Peak memory 257272 kb
Host smart-8aeace65-2bf8-4379-acaf-2512f43fe4c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27797
85985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2779785985
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.730043978
Short name T670
Test name
Test status
Simulation time 1157941400 ps
CPU time 46.45 seconds
Started Jun 13 01:31:06 PM PDT 24
Finished Jun 13 01:31:53 PM PDT 24
Peak memory 257256 kb
Host smart-057a9d9b-9ea8-425c-9eac-b665c8800472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73004
3978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.730043978
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.483275721
Short name T44
Test name
Test status
Simulation time 1054166734 ps
CPU time 17.5 seconds
Started Jun 13 01:31:13 PM PDT 24
Finished Jun 13 01:31:31 PM PDT 24
Peak memory 256228 kb
Host smart-09f76f98-b4a2-45d6-a6ab-5e510b5d96cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48327
5721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.483275721
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2519343392
Short name T630
Test name
Test status
Simulation time 575409364 ps
CPU time 10.04 seconds
Started Jun 13 01:31:07 PM PDT 24
Finished Jun 13 01:31:18 PM PDT 24
Peak memory 249224 kb
Host smart-ec62cd1f-0e79-485b-8385-fdb31bf640ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25193
43392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2519343392
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1909619539
Short name T249
Test name
Test status
Simulation time 87959167467 ps
CPU time 2979.03 seconds
Started Jun 13 01:31:18 PM PDT 24
Finished Jun 13 02:20:58 PM PDT 24
Peak memory 305608 kb
Host smart-a24a4761-a23c-4841-a3b3-f52bae5d4f3c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909619539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1909619539
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.3895022175
Short name T226
Test name
Test status
Simulation time 18336061230 ps
CPU time 1350.73 seconds
Started Jun 13 01:31:13 PM PDT 24
Finished Jun 13 01:53:44 PM PDT 24
Peak memory 273640 kb
Host smart-6658b80d-1b72-4ca0-bac5-c20a6057dbe2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895022175 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.3895022175
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3860130112
Short name T569
Test name
Test status
Simulation time 66221183670 ps
CPU time 2476.45 seconds
Started Jun 13 01:31:22 PM PDT 24
Finished Jun 13 02:12:40 PM PDT 24
Peak memory 289388 kb
Host smart-a34f4c80-0c37-4840-af11-a80301a74156
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860130112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3860130112
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2257569946
Short name T617
Test name
Test status
Simulation time 307480359 ps
CPU time 40.05 seconds
Started Jun 13 01:31:19 PM PDT 24
Finished Jun 13 01:31:59 PM PDT 24
Peak memory 255436 kb
Host smart-f4c03c5c-7f51-4488-bce4-b0ed9dfbc767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22575
69946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2257569946
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.4052371854
Short name T703
Test name
Test status
Simulation time 1107263872 ps
CPU time 35.18 seconds
Started Jun 13 01:31:14 PM PDT 24
Finished Jun 13 01:31:49 PM PDT 24
Peak memory 249104 kb
Host smart-24154241-2f19-4a4f-ba7f-54fd0afe73de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40523
71854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.4052371854
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1428153682
Short name T273
Test name
Test status
Simulation time 42269941369 ps
CPU time 2483.03 seconds
Started Jun 13 01:31:24 PM PDT 24
Finished Jun 13 02:12:48 PM PDT 24
Peak memory 285340 kb
Host smart-e9630c81-c19a-4d81-9793-6a0ee7303331
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428153682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1428153682
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1460780021
Short name T612
Test name
Test status
Simulation time 33719233473 ps
CPU time 340 seconds
Started Jun 13 01:31:21 PM PDT 24
Finished Jun 13 01:37:01 PM PDT 24
Peak memory 255744 kb
Host smart-86a9864b-fe64-4098-a539-46660914be75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460780021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1460780021
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3762096544
Short name T76
Test name
Test status
Simulation time 53751878 ps
CPU time 2.73 seconds
Started Jun 13 01:31:18 PM PDT 24
Finished Jun 13 01:31:21 PM PDT 24
Peak memory 240776 kb
Host smart-a696d9ae-3208-49f9-9c34-cf28b9028bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37620
96544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3762096544
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2951407543
Short name T405
Test name
Test status
Simulation time 1293085584 ps
CPU time 30.38 seconds
Started Jun 13 01:31:14 PM PDT 24
Finished Jun 13 01:31:45 PM PDT 24
Peak memory 248996 kb
Host smart-0dc7fb41-ca12-4a22-a2a6-6ae291d341a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29514
07543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2951407543
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1488806056
Short name T258
Test name
Test status
Simulation time 899827486 ps
CPU time 16.64 seconds
Started Jun 13 01:31:21 PM PDT 24
Finished Jun 13 01:31:40 PM PDT 24
Peak memory 255020 kb
Host smart-eb9155b5-27cc-43b0-a22f-9285976e2671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14888
06056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1488806056
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.795729930
Short name T114
Test name
Test status
Simulation time 1515877158 ps
CPU time 24.53 seconds
Started Jun 13 01:31:14 PM PDT 24
Finished Jun 13 01:31:39 PM PDT 24
Peak memory 257296 kb
Host smart-823864d0-25c8-4101-80ad-79db50af63f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79572
9930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.795729930
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3540359844
Short name T552
Test name
Test status
Simulation time 13522879892 ps
CPU time 1181.9 seconds
Started Jun 13 01:31:21 PM PDT 24
Finished Jun 13 01:51:05 PM PDT 24
Peak memory 290148 kb
Host smart-b7dc7d89-4f6e-4666-b053-228ad98df17f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540359844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3540359844
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1024049865
Short name T286
Test name
Test status
Simulation time 27580316392 ps
CPU time 1601.59 seconds
Started Jun 13 01:31:22 PM PDT 24
Finished Jun 13 01:58:06 PM PDT 24
Peak memory 290076 kb
Host smart-5db1b2c3-a3c0-4971-9c5a-33c308a6e3e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024049865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1024049865
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2593405132
Short name T407
Test name
Test status
Simulation time 5274819719 ps
CPU time 173.32 seconds
Started Jun 13 01:31:21 PM PDT 24
Finished Jun 13 01:34:16 PM PDT 24
Peak memory 257332 kb
Host smart-64ba743a-d3bb-423a-abfe-61081f3a3434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25934
05132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2593405132
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.266082707
Short name T509
Test name
Test status
Simulation time 163024023 ps
CPU time 13.38 seconds
Started Jun 13 01:31:21 PM PDT 24
Finished Jun 13 01:31:35 PM PDT 24
Peak memory 255300 kb
Host smart-2fdc1f66-751c-4c96-8cef-1db7eaefcfea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26608
2707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.266082707
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2575646513
Short name T235
Test name
Test status
Simulation time 283590392059 ps
CPU time 2850.37 seconds
Started Jun 13 01:31:22 PM PDT 24
Finished Jun 13 02:18:54 PM PDT 24
Peak memory 281852 kb
Host smart-68b15f0d-024d-4895-8c4b-f7424b18df36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575646513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2575646513
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.966091160
Short name T491
Test name
Test status
Simulation time 43985249734 ps
CPU time 2380.84 seconds
Started Jun 13 01:31:21 PM PDT 24
Finished Jun 13 02:11:04 PM PDT 24
Peak memory 289768 kb
Host smart-45503a32-6b06-4a15-b9a6-65e5cc42dcdf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966091160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.966091160
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.559421079
Short name T294
Test name
Test status
Simulation time 16995915463 ps
CPU time 387.25 seconds
Started Jun 13 01:31:20 PM PDT 24
Finished Jun 13 01:37:48 PM PDT 24
Peak memory 248720 kb
Host smart-6ff96a12-c14e-41c0-a3b1-5781068b7588
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559421079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.559421079
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2516928190
Short name T423
Test name
Test status
Simulation time 487130143 ps
CPU time 35.52 seconds
Started Jun 13 01:31:20 PM PDT 24
Finished Jun 13 01:31:56 PM PDT 24
Peak memory 256444 kb
Host smart-89cda37c-f42d-4600-9b58-a09e3f33f16d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25169
28190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2516928190
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2389266144
Short name T373
Test name
Test status
Simulation time 399579111 ps
CPU time 20.67 seconds
Started Jun 13 01:31:22 PM PDT 24
Finished Jun 13 01:31:45 PM PDT 24
Peak memory 248560 kb
Host smart-adcde905-e5e9-42c8-9cdf-40b7ba6afcc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23892
66144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2389266144
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1568372339
Short name T574
Test name
Test status
Simulation time 283436788 ps
CPU time 18.18 seconds
Started Jun 13 01:31:21 PM PDT 24
Finished Jun 13 01:31:40 PM PDT 24
Peak memory 255080 kb
Host smart-de581e72-6127-4dea-af45-91ba4d952551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15683
72339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1568372339
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.619062448
Short name T633
Test name
Test status
Simulation time 703605193 ps
CPU time 41.7 seconds
Started Jun 13 01:31:22 PM PDT 24
Finished Jun 13 01:32:06 PM PDT 24
Peak memory 249256 kb
Host smart-453726d6-43d7-45dc-930e-4cca1eda2ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61906
2448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.619062448
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.389262517
Short name T454
Test name
Test status
Simulation time 128958147081 ps
CPU time 2471.04 seconds
Started Jun 13 01:31:21 PM PDT 24
Finished Jun 13 02:12:32 PM PDT 24
Peak memory 288896 kb
Host smart-1954c26f-69d6-412a-9db4-87e4565e00be
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389262517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.389262517
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.4075226717
Short name T503
Test name
Test status
Simulation time 256284239194 ps
CPU time 1581.15 seconds
Started Jun 13 01:31:34 PM PDT 24
Finished Jun 13 01:57:56 PM PDT 24
Peak memory 273644 kb
Host smart-0645b4e1-c37b-46b7-a4ba-42e194a19248
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075226717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.4075226717
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3985568353
Short name T692
Test name
Test status
Simulation time 541275136 ps
CPU time 16.85 seconds
Started Jun 13 01:31:36 PM PDT 24
Finished Jun 13 01:31:54 PM PDT 24
Peak memory 256172 kb
Host smart-0d3eebe7-2663-43e6-857b-d49eabe6b971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39855
68353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3985568353
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2340955582
Short name T220
Test name
Test status
Simulation time 104768630 ps
CPU time 4.25 seconds
Started Jun 13 01:31:37 PM PDT 24
Finished Jun 13 01:31:42 PM PDT 24
Peak memory 239852 kb
Host smart-bc0809b0-6211-4170-b1e7-7e4c1ccac03c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23409
55582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2340955582
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2629647247
Short name T331
Test name
Test status
Simulation time 13099922581 ps
CPU time 1083.48 seconds
Started Jun 13 01:31:34 PM PDT 24
Finished Jun 13 01:49:39 PM PDT 24
Peak memory 273156 kb
Host smart-c287b027-8574-4fca-8568-4add910c1e05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629647247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2629647247
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3535820942
Short name T332
Test name
Test status
Simulation time 205060611414 ps
CPU time 2948.92 seconds
Started Jun 13 01:31:36 PM PDT 24
Finished Jun 13 02:20:46 PM PDT 24
Peak memory 289332 kb
Host smart-638ed99c-56e1-4e81-a665-fa92f74ce383
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535820942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3535820942
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3638842372
Short name T452
Test name
Test status
Simulation time 12426651868 ps
CPU time 495.28 seconds
Started Jun 13 01:31:35 PM PDT 24
Finished Jun 13 01:39:51 PM PDT 24
Peak memory 248648 kb
Host smart-0ccffb76-c2ca-4862-9f21-b255e1cdc9bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638842372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3638842372
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.634791177
Short name T641
Test name
Test status
Simulation time 253369324 ps
CPU time 7.56 seconds
Started Jun 13 01:31:29 PM PDT 24
Finished Jun 13 01:31:37 PM PDT 24
Peak memory 253280 kb
Host smart-7c9e27cb-501e-4922-b1c9-7f1484be2d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63479
1177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.634791177
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3255406025
Short name T361
Test name
Test status
Simulation time 1144178005 ps
CPU time 21.84 seconds
Started Jun 13 01:31:39 PM PDT 24
Finished Jun 13 01:32:02 PM PDT 24
Peak memory 255916 kb
Host smart-bd6290a9-1a0f-406d-bf21-98554029005f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32554
06025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3255406025
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1529430572
Short name T662
Test name
Test status
Simulation time 102019245 ps
CPU time 14.63 seconds
Started Jun 13 01:31:32 PM PDT 24
Finished Jun 13 01:31:47 PM PDT 24
Peak memory 249004 kb
Host smart-9971da6e-45d4-4ec2-9c30-9363d3278189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15294
30572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1529430572
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.940604868
Short name T71
Test name
Test status
Simulation time 301037613 ps
CPU time 25.05 seconds
Started Jun 13 01:31:28 PM PDT 24
Finished Jun 13 01:31:54 PM PDT 24
Peak memory 256568 kb
Host smart-0ebba7a9-1a1b-45b8-a3ec-bf34225bdea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94060
4868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.940604868
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1636574474
Short name T50
Test name
Test status
Simulation time 23345449449 ps
CPU time 945.54 seconds
Started Jun 13 01:31:36 PM PDT 24
Finished Jun 13 01:47:23 PM PDT 24
Peak memory 283740 kb
Host smart-a22a1a13-d701-41b0-9139-b7cc04dbe51c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636574474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1636574474
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3660788759
Short name T524
Test name
Test status
Simulation time 64336623208 ps
CPU time 2343.32 seconds
Started Jun 13 01:31:40 PM PDT 24
Finished Jun 13 02:10:45 PM PDT 24
Peak memory 288776 kb
Host smart-a4ef6fa8-3648-4953-b9ff-925676245d80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660788759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3660788759
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.796364834
Short name T686
Test name
Test status
Simulation time 1650068140 ps
CPU time 30.81 seconds
Started Jun 13 01:31:41 PM PDT 24
Finished Jun 13 01:32:13 PM PDT 24
Peak memory 249380 kb
Host smart-83097dc5-4c6a-4d0a-9c32-bf16bce1409d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79636
4834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.796364834
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.70741763
Short name T408
Test name
Test status
Simulation time 599846976 ps
CPU time 33.26 seconds
Started Jun 13 01:31:41 PM PDT 24
Finished Jun 13 01:32:16 PM PDT 24
Peak memory 257268 kb
Host smart-23293d9d-bb4d-42cf-8513-47aaec3c96a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70741
763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.70741763
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.36703208
Short name T333
Test name
Test status
Simulation time 144702043333 ps
CPU time 1851.74 seconds
Started Jun 13 01:31:39 PM PDT 24
Finished Jun 13 02:02:32 PM PDT 24
Peak memory 273736 kb
Host smart-9b129ae4-d89b-469b-9036-2ab7d5b2c7d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36703208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.36703208
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1411262088
Short name T623
Test name
Test status
Simulation time 20709879025 ps
CPU time 817.99 seconds
Started Jun 13 01:31:44 PM PDT 24
Finished Jun 13 01:45:22 PM PDT 24
Peak memory 273288 kb
Host smart-dec9aeaa-3e96-4dbc-99f3-eca97db785c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411262088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1411262088
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.496572526
Short name T36
Test name
Test status
Simulation time 5907550246 ps
CPU time 220.54 seconds
Started Jun 13 01:31:41 PM PDT 24
Finished Jun 13 01:35:23 PM PDT 24
Peak memory 248808 kb
Host smart-1bc6ca64-6774-4a8f-8516-bb919a2f7882
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496572526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.496572526
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1360627395
Short name T629
Test name
Test status
Simulation time 368712322 ps
CPU time 10.56 seconds
Started Jun 13 01:31:40 PM PDT 24
Finished Jun 13 01:31:52 PM PDT 24
Peak memory 249092 kb
Host smart-73624dff-6382-4521-8ab5-cbb6d1b5867d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13606
27395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1360627395
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3988323665
Short name T487
Test name
Test status
Simulation time 547706110 ps
CPU time 16.74 seconds
Started Jun 13 01:31:41 PM PDT 24
Finished Jun 13 01:32:00 PM PDT 24
Peak memory 249160 kb
Host smart-86c29b47-6991-477c-95e7-f04900f290ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39883
23665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3988323665
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2370698512
Short name T645
Test name
Test status
Simulation time 350575669 ps
CPU time 9.81 seconds
Started Jun 13 01:31:41 PM PDT 24
Finished Jun 13 01:31:53 PM PDT 24
Peak memory 247868 kb
Host smart-745ee41b-352c-4db3-9ba3-7bd6c194b031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23706
98512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2370698512
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1163262210
Short name T684
Test name
Test status
Simulation time 394193224 ps
CPU time 19.05 seconds
Started Jun 13 01:31:36 PM PDT 24
Finished Jun 13 01:31:56 PM PDT 24
Peak memory 257264 kb
Host smart-a65eaf36-3c06-4ec3-99f6-fb42a7ba4c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11632
62210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1163262210
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.904694110
Short name T108
Test name
Test status
Simulation time 31814840098 ps
CPU time 3954.05 seconds
Started Jun 13 01:31:41 PM PDT 24
Finished Jun 13 02:37:37 PM PDT 24
Peak memory 335792 kb
Host smart-0dd5e3ce-bac8-4279-983d-245892f36fc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904694110 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.904694110
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1486966175
Short name T94
Test name
Test status
Simulation time 42349594747 ps
CPU time 2442.18 seconds
Started Jun 13 01:31:48 PM PDT 24
Finished Jun 13 02:12:32 PM PDT 24
Peak memory 289428 kb
Host smart-f19f5175-b621-4b83-a81a-f69229c6875a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486966175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1486966175
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1500868990
Short name T705
Test name
Test status
Simulation time 20330477322 ps
CPU time 209.27 seconds
Started Jun 13 01:31:42 PM PDT 24
Finished Jun 13 01:35:12 PM PDT 24
Peak memory 257284 kb
Host smart-e2060230-6fa7-4a7f-b196-da3d366e0e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15008
68990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1500868990
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.16070660
Short name T396
Test name
Test status
Simulation time 1288544690 ps
CPU time 81.72 seconds
Started Jun 13 01:31:40 PM PDT 24
Finished Jun 13 01:33:03 PM PDT 24
Peak memory 256352 kb
Host smart-13d346df-3af6-49f5-be07-c4efa9919175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16070
660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.16070660
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2369908189
Short name T319
Test name
Test status
Simulation time 9147110202 ps
CPU time 821.86 seconds
Started Jun 13 01:31:46 PM PDT 24
Finished Jun 13 01:45:28 PM PDT 24
Peak memory 273492 kb
Host smart-285c3ce4-8cdd-42b9-a79c-8780572c4fca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369908189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2369908189
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2214289638
Short name T364
Test name
Test status
Simulation time 87928227749 ps
CPU time 3123.16 seconds
Started Jun 13 01:31:47 PM PDT 24
Finished Jun 13 02:23:51 PM PDT 24
Peak memory 289996 kb
Host smart-0f78b33a-9dd9-4096-9e5d-2577c89a031e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214289638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2214289638
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1934428863
Short name T468
Test name
Test status
Simulation time 14975794182 ps
CPU time 155.53 seconds
Started Jun 13 01:31:47 PM PDT 24
Finished Jun 13 01:34:23 PM PDT 24
Peak memory 248696 kb
Host smart-468541f4-61cf-4b70-83e8-866d310818d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934428863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1934428863
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1003022397
Short name T233
Test name
Test status
Simulation time 65348226 ps
CPU time 4.2 seconds
Started Jun 13 01:31:38 PM PDT 24
Finished Jun 13 01:31:43 PM PDT 24
Peak memory 251460 kb
Host smart-3ec531f4-8215-4f42-9045-796e6f39b264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10030
22397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1003022397
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.810572746
Short name T604
Test name
Test status
Simulation time 271733809 ps
CPU time 29.48 seconds
Started Jun 13 01:31:41 PM PDT 24
Finished Jun 13 01:32:12 PM PDT 24
Peak memory 248064 kb
Host smart-65fa8102-f3ac-41dc-b188-2aa8ab626a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81057
2746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.810572746
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2491856102
Short name T75
Test name
Test status
Simulation time 172705529 ps
CPU time 18.38 seconds
Started Jun 13 01:31:40 PM PDT 24
Finished Jun 13 01:32:00 PM PDT 24
Peak memory 248104 kb
Host smart-4a5a58fe-f201-4585-864b-4b3b315eb3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24918
56102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2491856102
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.13062293
Short name T19
Test name
Test status
Simulation time 679331729 ps
CPU time 7.93 seconds
Started Jun 13 01:31:40 PM PDT 24
Finished Jun 13 01:31:49 PM PDT 24
Peak memory 249092 kb
Host smart-180258a8-a6f6-40cb-ade0-6dcfefcd4cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13062
293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.13062293
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.359971684
Short name T379
Test name
Test status
Simulation time 110573093505 ps
CPU time 3384.85 seconds
Started Jun 13 01:31:48 PM PDT 24
Finished Jun 13 02:28:14 PM PDT 24
Peak memory 289448 kb
Host smart-337e0b55-2247-4652-b863-f62d1d26ee37
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359971684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.359971684
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2679951332
Short name T638
Test name
Test status
Simulation time 103507695272 ps
CPU time 2689.72 seconds
Started Jun 13 01:31:49 PM PDT 24
Finished Jun 13 02:16:40 PM PDT 24
Peak memory 322412 kb
Host smart-5cbe1075-a967-4660-8042-a21038d2c966
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679951332 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2679951332
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2812784709
Short name T573
Test name
Test status
Simulation time 104693286736 ps
CPU time 1886.87 seconds
Started Jun 13 01:31:46 PM PDT 24
Finished Jun 13 02:03:13 PM PDT 24
Peak memory 285548 kb
Host smart-80a6f11b-1e3f-456e-a795-7959fcd88eee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812784709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2812784709
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3853913737
Short name T448
Test name
Test status
Simulation time 32770591934 ps
CPU time 233.47 seconds
Started Jun 13 01:31:48 PM PDT 24
Finished Jun 13 01:35:43 PM PDT 24
Peak memory 250380 kb
Host smart-cbedb789-c6d6-4ac8-b512-16465ac62478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38539
13737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3853913737
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1765148609
Short name T262
Test name
Test status
Simulation time 2673641158 ps
CPU time 55.53 seconds
Started Jun 13 01:31:47 PM PDT 24
Finished Jun 13 01:32:43 PM PDT 24
Peak memory 256020 kb
Host smart-1f93acaa-d65d-41ed-abd8-5e111aa81781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17651
48609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1765148609
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3794481281
Short name T284
Test name
Test status
Simulation time 18711743411 ps
CPU time 1193.96 seconds
Started Jun 13 01:31:57 PM PDT 24
Finished Jun 13 01:51:52 PM PDT 24
Peak memory 273640 kb
Host smart-80299b7b-ef7c-442d-a789-b99a9ec16f85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794481281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3794481281
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1383225212
Short name T330
Test name
Test status
Simulation time 43471822564 ps
CPU time 2626.48 seconds
Started Jun 13 01:31:57 PM PDT 24
Finished Jun 13 02:15:44 PM PDT 24
Peak memory 285208 kb
Host smart-3f2b7f00-f8d1-4be9-9b87-613e29ed1f16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383225212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1383225212
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2638165471
Short name T38
Test name
Test status
Simulation time 93195205764 ps
CPU time 300.96 seconds
Started Jun 13 01:31:53 PM PDT 24
Finished Jun 13 01:36:55 PM PDT 24
Peak memory 248624 kb
Host smart-619ca88a-a106-47db-b215-b97683a3c2bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638165471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2638165471
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2863768880
Short name T665
Test name
Test status
Simulation time 579796025 ps
CPU time 12.62 seconds
Started Jun 13 01:31:47 PM PDT 24
Finished Jun 13 01:32:00 PM PDT 24
Peak memory 256152 kb
Host smart-915ba2bd-0375-41a9-89f2-396cad7d829e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28637
68880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2863768880
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1168211086
Short name T88
Test name
Test status
Simulation time 723087779 ps
CPU time 46.81 seconds
Started Jun 13 01:31:48 PM PDT 24
Finished Jun 13 01:32:36 PM PDT 24
Peak memory 249180 kb
Host smart-1b465f01-66e4-478e-a9fd-4257da9ec1c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11682
11086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1168211086
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.124733598
Short name T51
Test name
Test status
Simulation time 2360898821 ps
CPU time 39.32 seconds
Started Jun 13 01:31:48 PM PDT 24
Finished Jun 13 01:32:28 PM PDT 24
Peak memory 248436 kb
Host smart-ba192f1e-0cfe-4e97-954a-d52f6dc4c297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12473
3598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.124733598
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3270437170
Short name T577
Test name
Test status
Simulation time 214302967 ps
CPU time 18.86 seconds
Started Jun 13 01:31:47 PM PDT 24
Finished Jun 13 01:32:07 PM PDT 24
Peak memory 249028 kb
Host smart-289e7e48-bff0-4c04-9e86-535c576bff66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32704
37170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3270437170
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.715579970
Short name T14
Test name
Test status
Simulation time 48793564694 ps
CPU time 1615.53 seconds
Started Jun 13 01:31:53 PM PDT 24
Finished Jun 13 01:58:49 PM PDT 24
Peak memory 289368 kb
Host smart-fe9a899c-1365-40f9-ba56-bc1d18ebb38d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715579970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.715579970
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2347074103
Short name T17
Test name
Test status
Simulation time 62253114790 ps
CPU time 2368.09 seconds
Started Jun 13 01:31:52 PM PDT 24
Finished Jun 13 02:11:21 PM PDT 24
Peak memory 289268 kb
Host smart-2eb8557d-4c21-4001-807d-15c82b573d4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347074103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2347074103
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3141825527
Short name T394
Test name
Test status
Simulation time 7704924515 ps
CPU time 123.18 seconds
Started Jun 13 01:31:57 PM PDT 24
Finished Jun 13 01:34:00 PM PDT 24
Peak memory 257292 kb
Host smart-98ede69a-dbfd-42d7-8584-5c25f15c8f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31418
25527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3141825527
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.919975603
Short name T466
Test name
Test status
Simulation time 2153688806 ps
CPU time 60.76 seconds
Started Jun 13 01:31:53 PM PDT 24
Finished Jun 13 01:32:54 PM PDT 24
Peak memory 249368 kb
Host smart-880df71f-ec11-45ee-ab68-799d975c89c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91997
5603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.919975603
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2894112048
Short name T666
Test name
Test status
Simulation time 33584395988 ps
CPU time 1284.23 seconds
Started Jun 13 01:31:54 PM PDT 24
Finished Jun 13 01:53:19 PM PDT 24
Peak memory 287052 kb
Host smart-669fcd4b-1651-4cec-85d5-031fb6715a8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894112048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2894112048
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.402519347
Short name T381
Test name
Test status
Simulation time 116763610871 ps
CPU time 934.52 seconds
Started Jun 13 01:31:53 PM PDT 24
Finished Jun 13 01:47:28 PM PDT 24
Peak memory 284488 kb
Host smart-24e59c35-eea4-4640-a716-46c119b22e81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402519347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.402519347
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3399218321
Short name T298
Test name
Test status
Simulation time 12277084716 ps
CPU time 465.64 seconds
Started Jun 13 01:31:56 PM PDT 24
Finished Jun 13 01:39:42 PM PDT 24
Peak memory 248420 kb
Host smart-2869efee-00d9-4d72-959f-3c0bd937c066
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399218321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3399218321
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.4016842657
Short name T605
Test name
Test status
Simulation time 763214823 ps
CPU time 40.35 seconds
Started Jun 13 01:31:54 PM PDT 24
Finished Jun 13 01:32:35 PM PDT 24
Peak memory 249116 kb
Host smart-fe5be3fc-eba0-4029-be28-cc4025adb0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40168
42657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.4016842657
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1777718775
Short name T98
Test name
Test status
Simulation time 71996881 ps
CPU time 8.09 seconds
Started Jun 13 01:31:54 PM PDT 24
Finished Jun 13 01:32:03 PM PDT 24
Peak memory 248008 kb
Host smart-c456a328-21c8-4462-9514-1b764bf45a58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17777
18775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1777718775
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2508728477
Short name T252
Test name
Test status
Simulation time 297760919 ps
CPU time 28.02 seconds
Started Jun 13 01:31:53 PM PDT 24
Finished Jun 13 01:32:21 PM PDT 24
Peak memory 248264 kb
Host smart-c3d95480-34bc-4326-9c30-1dada1931514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25087
28477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2508728477
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.396028162
Short name T359
Test name
Test status
Simulation time 234164201 ps
CPU time 7.42 seconds
Started Jun 13 01:32:22 PM PDT 24
Finished Jun 13 01:32:30 PM PDT 24
Peak memory 249016 kb
Host smart-777bf666-898f-4c06-a284-8d46b3716709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39602
8162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.396028162
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3215889685
Short name T427
Test name
Test status
Simulation time 39595803441 ps
CPU time 611.85 seconds
Started Jun 13 01:32:04 PM PDT 24
Finished Jun 13 01:42:17 PM PDT 24
Peak memory 257340 kb
Host smart-b3cfd87c-ff5f-4323-9d4b-152b73bbd167
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215889685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3215889685
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.4241187031
Short name T420
Test name
Test status
Simulation time 39745602597 ps
CPU time 832.79 seconds
Started Jun 13 01:32:05 PM PDT 24
Finished Jun 13 01:45:59 PM PDT 24
Peak memory 272740 kb
Host smart-d794e2ba-a253-4491-8f04-95f77f7d64e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241187031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.4241187031
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2846181617
Short name T640
Test name
Test status
Simulation time 13918486419 ps
CPU time 230.43 seconds
Started Jun 13 01:32:05 PM PDT 24
Finished Jun 13 01:35:55 PM PDT 24
Peak memory 257224 kb
Host smart-5b157f9a-5ebc-4f64-ac4a-51ba28fcf788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28461
81617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2846181617
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2084259214
Short name T345
Test name
Test status
Simulation time 859136471 ps
CPU time 9.2 seconds
Started Jun 13 01:32:06 PM PDT 24
Finished Jun 13 01:32:16 PM PDT 24
Peak memory 249092 kb
Host smart-1895fa89-e31d-45ed-bbaa-7dc5d3896976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20842
59214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2084259214
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.4034091166
Short name T283
Test name
Test status
Simulation time 112577383773 ps
CPU time 1052.44 seconds
Started Jun 13 01:47:20 PM PDT 24
Finished Jun 13 02:04:53 PM PDT 24
Peak memory 273676 kb
Host smart-cc19d2ea-88f4-418d-aecd-893de86ad9f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034091166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.4034091166
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3093856064
Short name T698
Test name
Test status
Simulation time 53031499023 ps
CPU time 3094.59 seconds
Started Jun 13 02:01:55 PM PDT 24
Finished Jun 13 02:53:30 PM PDT 24
Peak memory 289316 kb
Host smart-07f9cd67-0ec0-4972-88d9-fb84c6dbcf1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093856064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3093856064
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.186636788
Short name T313
Test name
Test status
Simulation time 30479292553 ps
CPU time 212.58 seconds
Started Jun 13 02:08:52 PM PDT 24
Finished Jun 13 02:12:25 PM PDT 24
Peak memory 248652 kb
Host smart-fe5057fa-ddc0-49e2-99c4-92198f247cbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186636788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.186636788
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1934068371
Short name T457
Test name
Test status
Simulation time 1058983854 ps
CPU time 12.09 seconds
Started Jun 13 01:32:04 PM PDT 24
Finished Jun 13 01:32:17 PM PDT 24
Peak memory 254208 kb
Host smart-9245316e-54b1-4f60-b029-b1ff009c4b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19340
68371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1934068371
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.39254872
Short name T561
Test name
Test status
Simulation time 2683001299 ps
CPU time 24.68 seconds
Started Jun 13 01:32:05 PM PDT 24
Finished Jun 13 01:32:31 PM PDT 24
Peak memory 249112 kb
Host smart-6c10146a-d49e-452e-b9b4-2d279c4e6da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39254
872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.39254872
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2977133667
Short name T234
Test name
Test status
Simulation time 3665732830 ps
CPU time 38.18 seconds
Started Jun 13 01:52:55 PM PDT 24
Finished Jun 13 01:53:35 PM PDT 24
Peak memory 248600 kb
Host smart-7c36977d-5313-46b9-a81c-e5015def1853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29771
33667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2977133667
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3536679641
Short name T348
Test name
Test status
Simulation time 1650558000 ps
CPU time 32.21 seconds
Started Jun 13 01:32:06 PM PDT 24
Finished Jun 13 01:32:39 PM PDT 24
Peak memory 249104 kb
Host smart-6c562413-d8f4-4187-97b8-9e257768f8b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35366
79641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3536679641
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3411008644
Short name T449
Test name
Test status
Simulation time 12267867541 ps
CPU time 1416.69 seconds
Started Jun 13 01:57:31 PM PDT 24
Finished Jun 13 02:21:09 PM PDT 24
Peak memory 290008 kb
Host smart-55ebf013-eff7-4d92-98a0-a603ae1c3ee9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411008644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3411008644
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3557150147
Short name T512
Test name
Test status
Simulation time 9786138945 ps
CPU time 74.45 seconds
Started Jun 13 01:32:06 PM PDT 24
Finished Jun 13 01:33:21 PM PDT 24
Peak memory 257352 kb
Host smart-03c6046f-0e35-450d-853d-ae6986b79a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35571
50147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3557150147
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3512194478
Short name T622
Test name
Test status
Simulation time 270623055 ps
CPU time 7.61 seconds
Started Jun 13 01:53:54 PM PDT 24
Finished Jun 13 01:54:03 PM PDT 24
Peak memory 249112 kb
Host smart-c79a79d3-6a26-4d95-958a-dd3a1ade40f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35121
94478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3512194478
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.576005694
Short name T269
Test name
Test status
Simulation time 19210191278 ps
CPU time 1613.52 seconds
Started Jun 13 01:32:12 PM PDT 24
Finished Jun 13 01:59:06 PM PDT 24
Peak memory 288252 kb
Host smart-11882511-6640-4d39-bd63-1adb7f788b34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576005694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.576005694
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1943185969
Short name T455
Test name
Test status
Simulation time 8624641806 ps
CPU time 720.37 seconds
Started Jun 13 01:51:18 PM PDT 24
Finished Jun 13 02:03:20 PM PDT 24
Peak memory 272920 kb
Host smart-39a25fc1-b929-4544-b940-9c98dc0f9d13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943185969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1943185969
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1035467431
Short name T575
Test name
Test status
Simulation time 5049122241 ps
CPU time 102.64 seconds
Started Jun 13 01:32:12 PM PDT 24
Finished Jun 13 01:33:56 PM PDT 24
Peak memory 248712 kb
Host smart-c8f8d536-5a67-4672-8631-0e88a278e74b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035467431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1035467431
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3078675939
Short name T610
Test name
Test status
Simulation time 1045859486 ps
CPU time 17.98 seconds
Started Jun 13 02:30:49 PM PDT 24
Finished Jun 13 02:31:08 PM PDT 24
Peak memory 253780 kb
Host smart-1cccaf2b-b01e-4820-aee7-f7aaa28404f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30786
75939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3078675939
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1201633367
Short name T579
Test name
Test status
Simulation time 308615018 ps
CPU time 10.21 seconds
Started Jun 13 02:31:40 PM PDT 24
Finished Jun 13 02:31:55 PM PDT 24
Peak memory 247900 kb
Host smart-6013d374-5073-4889-83ff-3a4296350bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12016
33367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1201633367
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3053931502
Short name T475
Test name
Test status
Simulation time 1507111636 ps
CPU time 28.4 seconds
Started Jun 13 01:36:36 PM PDT 24
Finished Jun 13 01:37:05 PM PDT 24
Peak memory 247916 kb
Host smart-f1e11b41-96b6-47e0-9902-52f7ef4cc8f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30539
31502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3053931502
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.1289490946
Short name T451
Test name
Test status
Simulation time 110595013 ps
CPU time 12.94 seconds
Started Jun 13 01:32:06 PM PDT 24
Finished Jun 13 01:32:20 PM PDT 24
Peak memory 257236 kb
Host smart-e46f542c-909a-4ea6-bc52-9bf46ebb0ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12894
90946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1289490946
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3326791250
Short name T196
Test name
Test status
Simulation time 22884100 ps
CPU time 3.22 seconds
Started Jun 13 01:29:04 PM PDT 24
Finished Jun 13 01:29:09 PM PDT 24
Peak memory 249248 kb
Host smart-c45f0816-08a8-40d3-8290-41149c88a3dd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3326791250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3326791250
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2021363242
Short name T483
Test name
Test status
Simulation time 31880771877 ps
CPU time 1998.62 seconds
Started Jun 13 01:28:55 PM PDT 24
Finished Jun 13 02:02:15 PM PDT 24
Peak memory 289084 kb
Host smart-a28ded07-63da-4ec2-bc77-1d49c4bf512b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021363242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2021363242
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3740821358
Short name T661
Test name
Test status
Simulation time 1275857642 ps
CPU time 48.45 seconds
Started Jun 13 01:29:02 PM PDT 24
Finished Jun 13 01:29:51 PM PDT 24
Peak memory 249096 kb
Host smart-de0bbfb9-b097-4f0f-b933-6081536f45a2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3740821358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3740821358
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3918267586
Short name T362
Test name
Test status
Simulation time 3274202169 ps
CPU time 191.32 seconds
Started Jun 13 01:28:57 PM PDT 24
Finished Jun 13 01:32:08 PM PDT 24
Peak memory 257308 kb
Host smart-3d5bf0c4-e1c6-445e-b95f-0fe60420c9d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39182
67586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3918267586
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1792857280
Short name T584
Test name
Test status
Simulation time 906422058 ps
CPU time 16.91 seconds
Started Jun 13 01:28:54 PM PDT 24
Finished Jun 13 01:29:11 PM PDT 24
Peak memory 249044 kb
Host smart-9c2dbc2c-1ce5-4feb-97c3-150eb6aa500a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17928
57280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1792857280
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2546952025
Short name T7
Test name
Test status
Simulation time 17235917823 ps
CPU time 1482.3 seconds
Started Jun 13 01:29:02 PM PDT 24
Finished Jun 13 01:53:45 PM PDT 24
Peak memory 289220 kb
Host smart-223b06c5-f0cf-4c4a-82fd-db30f73e8ed4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546952025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2546952025
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3472858050
Short name T113
Test name
Test status
Simulation time 28007445274 ps
CPU time 1259.31 seconds
Started Jun 13 01:29:03 PM PDT 24
Finished Jun 13 01:50:03 PM PDT 24
Peak memory 289488 kb
Host smart-386d1ac7-ea23-4d56-8d87-62030727d11a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472858050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3472858050
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.476017439
Short name T416
Test name
Test status
Simulation time 8163199168 ps
CPU time 319.27 seconds
Started Jun 13 01:29:05 PM PDT 24
Finished Jun 13 01:34:25 PM PDT 24
Peak memory 248668 kb
Host smart-57f86ca2-8305-4344-bc3b-5b1b80171651
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476017439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.476017439
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1652325087
Short name T701
Test name
Test status
Simulation time 363665473 ps
CPU time 19.61 seconds
Started Jun 13 01:28:57 PM PDT 24
Finished Jun 13 01:29:17 PM PDT 24
Peak memory 249136 kb
Host smart-2074dcf3-1225-4f04-b7ea-48a5a225004b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16523
25087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1652325087
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.3032367738
Short name T267
Test name
Test status
Simulation time 908165946 ps
CPU time 38.32 seconds
Started Jun 13 01:28:57 PM PDT 24
Finished Jun 13 01:29:36 PM PDT 24
Peak memory 250040 kb
Host smart-a2d4ba3f-f576-48b5-aef0-8d258e35b7b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30323
67738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3032367738
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3993907686
Short name T244
Test name
Test status
Simulation time 2002647890 ps
CPU time 71.52 seconds
Started Jun 13 01:28:53 PM PDT 24
Finished Jun 13 01:30:05 PM PDT 24
Peak memory 249060 kb
Host smart-d1c00d19-9598-41fa-bdeb-d170d85f15c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39939
07686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3993907686
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.337234010
Short name T382
Test name
Test status
Simulation time 1337372693 ps
CPU time 21.44 seconds
Started Jun 13 01:28:55 PM PDT 24
Finished Jun 13 01:29:17 PM PDT 24
Peak memory 249064 kb
Host smart-422c1301-075f-49b6-8c14-b73bfe7da789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33723
4010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.337234010
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.650630921
Short name T77
Test name
Test status
Simulation time 2314054173 ps
CPU time 65.01 seconds
Started Jun 13 01:29:04 PM PDT 24
Finished Jun 13 01:30:10 PM PDT 24
Peak memory 249124 kb
Host smart-f02ca20b-bde9-4d0d-98c0-8603c599c982
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650630921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.650630921
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.706095128
Short name T117
Test name
Test status
Simulation time 81804543414 ps
CPU time 2560.64 seconds
Started Jun 13 01:29:01 PM PDT 24
Finished Jun 13 02:11:42 PM PDT 24
Peak memory 298364 kb
Host smart-122e1833-ed89-40e4-b30b-ec05257a2f5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706095128 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.706095128
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1239653060
Short name T438
Test name
Test status
Simulation time 232488431797 ps
CPU time 1353.25 seconds
Started Jun 13 02:13:18 PM PDT 24
Finished Jun 13 02:35:52 PM PDT 24
Peak memory 289820 kb
Host smart-f52bde3d-cf8e-445e-b945-fdfe11e061e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239653060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1239653060
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3148249665
Short name T499
Test name
Test status
Simulation time 7135749156 ps
CPU time 166.37 seconds
Started Jun 13 01:40:55 PM PDT 24
Finished Jun 13 01:43:43 PM PDT 24
Peak memory 257328 kb
Host smart-62d079b7-dfe7-4590-b4fe-028ba27b9ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31482
49665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3148249665
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1644424213
Short name T222
Test name
Test status
Simulation time 4052873997 ps
CPU time 52.56 seconds
Started Jun 13 01:32:13 PM PDT 24
Finished Jun 13 01:33:06 PM PDT 24
Peak memory 256268 kb
Host smart-6d5d2340-6ac0-404f-a718-e0fda20e5bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16444
24213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1644424213
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3841526146
Short name T663
Test name
Test status
Simulation time 43009203441 ps
CPU time 993.1 seconds
Started Jun 13 01:32:17 PM PDT 24
Finished Jun 13 01:48:51 PM PDT 24
Peak memory 273036 kb
Host smart-c60bff22-097c-46a4-a8fa-a4936fe62df8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841526146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3841526146
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3204331879
Short name T526
Test name
Test status
Simulation time 246438693023 ps
CPU time 3504.89 seconds
Started Jun 13 02:00:27 PM PDT 24
Finished Jun 13 02:58:53 PM PDT 24
Peak memory 289616 kb
Host smart-fa64fd37-5406-48dc-8d9e-3815f0057943
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204331879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3204331879
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.179022783
Short name T504
Test name
Test status
Simulation time 17427534927 ps
CPU time 187.66 seconds
Started Jun 13 01:45:19 PM PDT 24
Finished Jun 13 01:48:28 PM PDT 24
Peak memory 248716 kb
Host smart-d8effe25-9aad-4b21-bd0c-a404dcd3efa0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179022783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.179022783
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.553765614
Short name T485
Test name
Test status
Simulation time 1436114850 ps
CPU time 59.92 seconds
Started Jun 13 01:32:12 PM PDT 24
Finished Jun 13 01:33:12 PM PDT 24
Peak memory 256684 kb
Host smart-d469f21f-afeb-4501-ba9b-9bdc95e56bcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55376
5614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.553765614
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1729663377
Short name T216
Test name
Test status
Simulation time 876655822 ps
CPU time 31.99 seconds
Started Jun 13 01:55:46 PM PDT 24
Finished Jun 13 01:56:19 PM PDT 24
Peak memory 256016 kb
Host smart-4d44841c-fd1f-4571-8448-1b680274c456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17296
63377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1729663377
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.607603935
Short name T626
Test name
Test status
Simulation time 676698650 ps
CPU time 27.05 seconds
Started Jun 13 01:57:18 PM PDT 24
Finished Jun 13 01:57:47 PM PDT 24
Peak memory 248988 kb
Host smart-73e6feb9-bf6c-428e-9837-c409482c807c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60760
3935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.607603935
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3442074737
Short name T5
Test name
Test status
Simulation time 2430899078 ps
CPU time 69.34 seconds
Started Jun 13 01:55:06 PM PDT 24
Finished Jun 13 01:56:16 PM PDT 24
Peak memory 256172 kb
Host smart-ccde4c55-9604-4473-9998-2a4f9716f839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34420
74737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3442074737
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1405307839
Short name T65
Test name
Test status
Simulation time 5021455598 ps
CPU time 109.96 seconds
Started Jun 13 02:08:25 PM PDT 24
Finished Jun 13 02:10:16 PM PDT 24
Peak memory 255964 kb
Host smart-54d2e612-f00c-4b61-b383-aca68fd56907
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405307839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1405307839
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2455642814
Short name T627
Test name
Test status
Simulation time 421171561267 ps
CPU time 2001.48 seconds
Started Jun 13 02:23:20 PM PDT 24
Finished Jun 13 02:56:43 PM PDT 24
Peak memory 272988 kb
Host smart-c4139d90-61f4-41a9-b6c9-43b0daddfb1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455642814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2455642814
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.301310590
Short name T363
Test name
Test status
Simulation time 3853687890 ps
CPU time 87.42 seconds
Started Jun 13 01:32:17 PM PDT 24
Finished Jun 13 01:33:45 PM PDT 24
Peak memory 257144 kb
Host smart-578dc5fd-48ac-4504-8e92-1f9eff3d8d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30131
0590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.301310590
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1816113875
Short name T467
Test name
Test status
Simulation time 1266636848 ps
CPU time 71.51 seconds
Started Jun 13 02:09:30 PM PDT 24
Finished Jun 13 02:10:42 PM PDT 24
Peak memory 249108 kb
Host smart-ed2fccef-511f-4d56-993d-8de833051775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18161
13875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1816113875
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3709720249
Short name T324
Test name
Test status
Simulation time 11874206162 ps
CPU time 1176.51 seconds
Started Jun 13 01:53:46 PM PDT 24
Finished Jun 13 02:13:25 PM PDT 24
Peak memory 281924 kb
Host smart-736c1627-4015-40d3-9f62-1323616d3a1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709720249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3709720249
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.733071492
Short name T353
Test name
Test status
Simulation time 23181548142 ps
CPU time 630.82 seconds
Started Jun 13 01:56:17 PM PDT 24
Finished Jun 13 02:06:49 PM PDT 24
Peak memory 273060 kb
Host smart-a384c05e-c582-41b8-b3a3-36a574e69c2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733071492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.733071492
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3133213802
Short name T316
Test name
Test status
Simulation time 17569990775 ps
CPU time 576.05 seconds
Started Jun 13 01:32:17 PM PDT 24
Finished Jun 13 01:41:53 PM PDT 24
Peak memory 248596 kb
Host smart-553d4486-fc9a-4f67-a7af-dd7bf39869fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133213802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3133213802
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.457851213
Short name T547
Test name
Test status
Simulation time 450120349 ps
CPU time 23.89 seconds
Started Jun 13 01:32:19 PM PDT 24
Finished Jun 13 01:32:44 PM PDT 24
Peak memory 254808 kb
Host smart-5d413a1d-9e59-4235-a669-840145c7be0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45785
1213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.457851213
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2407599754
Short name T521
Test name
Test status
Simulation time 894784757 ps
CPU time 52.75 seconds
Started Jun 13 01:57:35 PM PDT 24
Finished Jun 13 01:58:29 PM PDT 24
Peak memory 249032 kb
Host smart-503fb0ae-fa2f-4fd4-af12-48b56e0a3d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24075
99754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2407599754
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3032800960
Short name T506
Test name
Test status
Simulation time 353943488 ps
CPU time 27.84 seconds
Started Jun 13 01:32:46 PM PDT 24
Finished Jun 13 01:33:14 PM PDT 24
Peak memory 249044 kb
Host smart-6b65f07d-a7cd-476f-b382-5588a4d07aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30328
00960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3032800960
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.205636983
Short name T45
Test name
Test status
Simulation time 349509488 ps
CPU time 15.43 seconds
Started Jun 13 02:17:20 PM PDT 24
Finished Jun 13 02:17:40 PM PDT 24
Peak memory 249096 kb
Host smart-8edcebd5-b21d-43e1-8eb2-5da8636ae105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20563
6983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.205636983
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3212488862
Short name T268
Test name
Test status
Simulation time 48210710905 ps
CPU time 2579.05 seconds
Started Jun 13 01:41:16 PM PDT 24
Finished Jun 13 02:24:18 PM PDT 24
Peak memory 289752 kb
Host smart-9b470e37-d273-4295-9fb5-212381b8e826
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212488862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3212488862
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1016402522
Short name T505
Test name
Test status
Simulation time 52191568197 ps
CPU time 1019.42 seconds
Started Jun 13 02:25:46 PM PDT 24
Finished Jun 13 02:42:47 PM PDT 24
Peak memory 282996 kb
Host smart-28186e5b-56f8-49b5-9286-676f46353ecb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016402522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1016402522
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2148722957
Short name T442
Test name
Test status
Simulation time 4373705728 ps
CPU time 259.11 seconds
Started Jun 13 01:46:22 PM PDT 24
Finished Jun 13 01:50:42 PM PDT 24
Peak memory 251292 kb
Host smart-81dba953-60f5-494b-a5d5-f55747010b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21487
22957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2148722957
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2887086338
Short name T489
Test name
Test status
Simulation time 518556508 ps
CPU time 10.95 seconds
Started Jun 13 01:32:18 PM PDT 24
Finished Jun 13 01:32:30 PM PDT 24
Peak memory 254120 kb
Host smart-10cbd0d9-b6d0-4dd7-9ee4-e5798d0a24b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28870
86338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2887086338
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2193322750
Short name T621
Test name
Test status
Simulation time 79042418424 ps
CPU time 721.55 seconds
Started Jun 13 01:32:31 PM PDT 24
Finished Jun 13 01:44:33 PM PDT 24
Peak memory 272156 kb
Host smart-3dfd9ef7-991d-4f81-9f44-f5e8764f1639
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193322750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2193322750
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3083387561
Short name T261
Test name
Test status
Simulation time 48332126907 ps
CPU time 2684.84 seconds
Started Jun 13 02:09:36 PM PDT 24
Finished Jun 13 02:54:22 PM PDT 24
Peak memory 287804 kb
Host smart-fde94416-6b4e-4325-9e31-c620e25f6fcd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083387561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3083387561
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1014241402
Short name T302
Test name
Test status
Simulation time 13059096835 ps
CPU time 539.05 seconds
Started Jun 13 01:32:19 PM PDT 24
Finished Jun 13 01:41:19 PM PDT 24
Peak memory 248672 kb
Host smart-b87c127f-5701-4c64-b8b2-4d0f5b54cc69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014241402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1014241402
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.962551493
Short name T43
Test name
Test status
Simulation time 436525733 ps
CPU time 32.04 seconds
Started Jun 13 02:12:46 PM PDT 24
Finished Jun 13 02:13:18 PM PDT 24
Peak memory 257044 kb
Host smart-a09785c3-d3aa-4c42-9705-dd88930f5336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96255
1493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.962551493
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1956965747
Short name T615
Test name
Test status
Simulation time 898428369 ps
CPU time 50.63 seconds
Started Jun 13 02:17:04 PM PDT 24
Finished Jun 13 02:18:01 PM PDT 24
Peak memory 248400 kb
Host smart-cdac3899-d242-49f4-bacd-42e3f5bc6b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19569
65747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1956965747
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2641233880
Short name T498
Test name
Test status
Simulation time 215079503 ps
CPU time 22.91 seconds
Started Jun 13 01:54:44 PM PDT 24
Finished Jun 13 01:55:13 PM PDT 24
Peak memory 249040 kb
Host smart-57bcca16-41e4-40a1-a729-a75bac989e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26412
33880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2641233880
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3085820902
Short name T415
Test name
Test status
Simulation time 1142166333 ps
CPU time 66.96 seconds
Started Jun 13 01:32:19 PM PDT 24
Finished Jun 13 01:33:27 PM PDT 24
Peak memory 256740 kb
Host smart-cea90e7b-c25f-4697-9955-df5bc22ac418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30858
20902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3085820902
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3472296192
Short name T472
Test name
Test status
Simulation time 100644426560 ps
CPU time 2836.79 seconds
Started Jun 13 01:32:24 PM PDT 24
Finished Jun 13 02:19:41 PM PDT 24
Peak memory 300972 kb
Host smart-18c96947-14e1-4b7d-a422-15af44cef9d3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472296192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3472296192
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2386390828
Short name T651
Test name
Test status
Simulation time 51166249388 ps
CPU time 2814.78 seconds
Started Jun 13 02:20:43 PM PDT 24
Finished Jun 13 03:07:42 PM PDT 24
Peak memory 288228 kb
Host smart-c57686ca-c038-4f7c-86c5-a6f6ef1813d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386390828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2386390828
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1819755098
Short name T536
Test name
Test status
Simulation time 3509072408 ps
CPU time 76.52 seconds
Started Jun 13 01:40:37 PM PDT 24
Finished Jun 13 01:41:54 PM PDT 24
Peak memory 257276 kb
Host smart-c37885a6-f3fc-4da9-9b7e-00d2a24077c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18197
55098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1819755098
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1847262993
Short name T439
Test name
Test status
Simulation time 639308025 ps
CPU time 36.22 seconds
Started Jun 13 02:15:35 PM PDT 24
Finished Jun 13 02:16:13 PM PDT 24
Peak memory 249108 kb
Host smart-f6049c2e-0ede-414f-a6aa-5769c0271e6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18472
62993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1847262993
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2077758268
Short name T115
Test name
Test status
Simulation time 121191384147 ps
CPU time 1259.89 seconds
Started Jun 13 01:32:24 PM PDT 24
Finished Jun 13 01:53:25 PM PDT 24
Peak memory 286516 kb
Host smart-2abae582-67fa-4309-905f-26d22ef87c6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077758268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2077758268
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.381522795
Short name T421
Test name
Test status
Simulation time 7302320062 ps
CPU time 152.69 seconds
Started Jun 13 01:32:24 PM PDT 24
Finished Jun 13 01:34:57 PM PDT 24
Peak memory 248676 kb
Host smart-43a09590-8548-48c0-8d58-65191fb01a27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381522795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.381522795
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3140619605
Short name T378
Test name
Test status
Simulation time 514423205 ps
CPU time 31.17 seconds
Started Jun 13 01:56:55 PM PDT 24
Finished Jun 13 01:57:28 PM PDT 24
Peak memory 256560 kb
Host smart-ae0b0c01-57a5-4a3e-8833-5b3cca5e7fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31406
19605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3140619605
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.622073479
Short name T582
Test name
Test status
Simulation time 1651435753 ps
CPU time 17.01 seconds
Started Jun 13 01:32:27 PM PDT 24
Finished Jun 13 01:32:44 PM PDT 24
Peak memory 253696 kb
Host smart-677dd4bb-00fe-4201-a650-91cbde6d3c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62207
3479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.622073479
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.380093112
Short name T241
Test name
Test status
Simulation time 826916913 ps
CPU time 24.47 seconds
Started Jun 13 02:10:00 PM PDT 24
Finished Jun 13 02:10:25 PM PDT 24
Peak memory 253672 kb
Host smart-dc4beb48-549a-48b7-9878-d24d48f6cf8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38009
3112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.380093112
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3505452306
Short name T530
Test name
Test status
Simulation time 526822490 ps
CPU time 38.17 seconds
Started Jun 13 01:37:01 PM PDT 24
Finished Jun 13 01:37:40 PM PDT 24
Peak memory 249104 kb
Host smart-f79d3fba-f12e-47a6-a88a-b5856da7c3c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35054
52306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3505452306
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3806042609
Short name T386
Test name
Test status
Simulation time 121883542463 ps
CPU time 3524.64 seconds
Started Jun 13 01:38:09 PM PDT 24
Finished Jun 13 02:36:55 PM PDT 24
Peak memory 289460 kb
Host smart-3203fc09-11d0-4b8d-9870-afae6d1801df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806042609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3806042609
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.625924574
Short name T219
Test name
Test status
Simulation time 8565365506 ps
CPU time 135.83 seconds
Started Jun 13 01:40:41 PM PDT 24
Finished Jun 13 01:42:58 PM PDT 24
Peak memory 257212 kb
Host smart-b4487fa9-73f6-4799-aafd-d31b4fe72d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62592
4574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.625924574
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3626977067
Short name T594
Test name
Test status
Simulation time 1746120531 ps
CPU time 48.29 seconds
Started Jun 13 02:12:34 PM PDT 24
Finished Jun 13 02:13:23 PM PDT 24
Peak memory 249120 kb
Host smart-949c7263-b082-4b7c-a3fb-69d1bf650ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36269
77067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3626977067
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2126748834
Short name T41
Test name
Test status
Simulation time 14156346591 ps
CPU time 1243.51 seconds
Started Jun 13 02:01:41 PM PDT 24
Finished Jun 13 02:22:26 PM PDT 24
Peak memory 281812 kb
Host smart-cbf2d4b6-88be-4121-aee8-a3277aa15be9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126748834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2126748834
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3616878631
Short name T518
Test name
Test status
Simulation time 22793182295 ps
CPU time 913.15 seconds
Started Jun 13 01:59:47 PM PDT 24
Finished Jun 13 02:15:01 PM PDT 24
Peak memory 282984 kb
Host smart-2f2d5799-bf78-4fe4-b8c9-3c3bb5a2fcbf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616878631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3616878631
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3822729438
Short name T311
Test name
Test status
Simulation time 8911918158 ps
CPU time 193.39 seconds
Started Jun 13 02:14:33 PM PDT 24
Finished Jun 13 02:17:46 PM PDT 24
Peak memory 249092 kb
Host smart-83a1f94b-1852-4f6b-9345-d8debc4b6640
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822729438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3822729438
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3921580781
Short name T510
Test name
Test status
Simulation time 677118473 ps
CPU time 10.83 seconds
Started Jun 13 01:43:45 PM PDT 24
Finished Jun 13 01:43:58 PM PDT 24
Peak memory 252796 kb
Host smart-a99c4b0d-2b2e-41b3-be37-0413444f46f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39215
80781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3921580781
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.140101755
Short name T360
Test name
Test status
Simulation time 293238260 ps
CPU time 29.09 seconds
Started Jun 13 01:43:27 PM PDT 24
Finished Jun 13 01:43:57 PM PDT 24
Peak memory 249172 kb
Host smart-040dae5d-71ab-4bc8-968c-ec7929c6dfcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14010
1755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.140101755
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3879336780
Short name T654
Test name
Test status
Simulation time 309705211 ps
CPU time 23.96 seconds
Started Jun 13 01:35:32 PM PDT 24
Finished Jun 13 01:35:56 PM PDT 24
Peak memory 249084 kb
Host smart-1a00264d-11ce-49a0-8fa8-22a35288a027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38793
36780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3879336780
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1917319245
Short name T672
Test name
Test status
Simulation time 124709268180 ps
CPU time 3393.93 seconds
Started Jun 13 01:32:32 PM PDT 24
Finished Jun 13 02:29:07 PM PDT 24
Peak memory 289932 kb
Host smart-08e78f0b-b8dd-4e44-9ffd-12c176b43123
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917319245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1917319245
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.845581290
Short name T110
Test name
Test status
Simulation time 138559431983 ps
CPU time 4291.79 seconds
Started Jun 13 01:32:39 PM PDT 24
Finished Jun 13 02:44:12 PM PDT 24
Peak memory 338760 kb
Host smart-cdea2e2f-e876-4a38-ae4b-5c2e61271522
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845581290 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.845581290
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.474303199
Short name T590
Test name
Test status
Simulation time 146387502528 ps
CPU time 2163.1 seconds
Started Jun 13 02:13:37 PM PDT 24
Finished Jun 13 02:49:41 PM PDT 24
Peak memory 281908 kb
Host smart-2e70f44a-764c-4de7-9d75-12e6bc8f9ab6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474303199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.474303199
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2255753261
Short name T589
Test name
Test status
Simulation time 3236240675 ps
CPU time 192.01 seconds
Started Jun 13 01:32:39 PM PDT 24
Finished Jun 13 01:35:52 PM PDT 24
Peak memory 257300 kb
Host smart-6c9e5bbf-533c-417c-a5b8-7126ec23d7b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22557
53261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2255753261
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1657253204
Short name T82
Test name
Test status
Simulation time 2663294727 ps
CPU time 43.64 seconds
Started Jun 13 02:39:37 PM PDT 24
Finished Jun 13 02:40:26 PM PDT 24
Peak memory 249176 kb
Host smart-2788d6a8-2e67-4fe7-bde2-75a89a7b4561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16572
53204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1657253204
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.1981155467
Short name T425
Test name
Test status
Simulation time 10657065142 ps
CPU time 980.32 seconds
Started Jun 13 01:32:30 PM PDT 24
Finished Jun 13 01:48:51 PM PDT 24
Peak memory 272720 kb
Host smart-01eb0762-0b32-4287-9ae7-015b9f8d0a6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981155467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.1981155467
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2727216035
Short name T426
Test name
Test status
Simulation time 8776264197 ps
CPU time 881.59 seconds
Started Jun 13 01:32:31 PM PDT 24
Finished Jun 13 01:47:13 PM PDT 24
Peak memory 273692 kb
Host smart-0a3bc7ea-cef9-41b8-bf9c-77fac5c10793
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727216035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2727216035
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.550556289
Short name T434
Test name
Test status
Simulation time 588578812 ps
CPU time 28.02 seconds
Started Jun 13 01:56:59 PM PDT 24
Finished Jun 13 01:57:28 PM PDT 24
Peak memory 256688 kb
Host smart-0f237a06-549e-4cf4-9159-843eac39c1a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55055
6289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.550556289
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1476846906
Short name T471
Test name
Test status
Simulation time 3169518601 ps
CPU time 46.63 seconds
Started Jun 13 01:32:39 PM PDT 24
Finished Jun 13 01:33:26 PM PDT 24
Peak memory 248896 kb
Host smart-ea8e9086-e006-45a4-baef-927c9129aa8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14768
46906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1476846906
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3047488756
Short name T266
Test name
Test status
Simulation time 369921787 ps
CPU time 28.25 seconds
Started Jun 13 01:55:57 PM PDT 24
Finished Jun 13 01:56:27 PM PDT 24
Peak memory 255880 kb
Host smart-97745512-d996-4701-b995-ee4d05b7ecfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30474
88756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3047488756
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.426962448
Short name T395
Test name
Test status
Simulation time 30010742 ps
CPU time 2.71 seconds
Started Jun 13 01:32:32 PM PDT 24
Finished Jun 13 01:32:35 PM PDT 24
Peak memory 240888 kb
Host smart-5c911c96-c9fb-4fdd-a552-acd0f23702fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42696
2448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.426962448
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2108146484
Short name T54
Test name
Test status
Simulation time 14118170108 ps
CPU time 724.98 seconds
Started Jun 13 01:32:37 PM PDT 24
Finished Jun 13 01:44:43 PM PDT 24
Peak memory 265544 kb
Host smart-05c62b63-f20e-45ec-92e7-0b3747a85cf7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108146484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2108146484
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1229843088
Short name T105
Test name
Test status
Simulation time 173617463941 ps
CPU time 1855.68 seconds
Started Jun 13 01:39:40 PM PDT 24
Finished Jun 13 02:10:37 PM PDT 24
Peak memory 289832 kb
Host smart-463fe23b-cf2c-42a6-977b-93605926cf34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229843088 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1229843088
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3468444157
Short name T581
Test name
Test status
Simulation time 190670151597 ps
CPU time 2822.37 seconds
Started Jun 13 01:32:36 PM PDT 24
Finished Jun 13 02:19:40 PM PDT 24
Peak memory 289488 kb
Host smart-d429c0fd-66fc-44cc-ac90-b991750619b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468444157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3468444157
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3212708492
Short name T366
Test name
Test status
Simulation time 9598100630 ps
CPU time 125.96 seconds
Started Jun 13 01:32:37 PM PDT 24
Finished Jun 13 01:34:43 PM PDT 24
Peak memory 257040 kb
Host smart-433dd377-dc2b-4ca5-a07e-2b3a013ef1cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32127
08492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3212708492
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3775113575
Short name T403
Test name
Test status
Simulation time 1069763275 ps
CPU time 55.03 seconds
Started Jun 13 02:01:28 PM PDT 24
Finished Jun 13 02:02:24 PM PDT 24
Peak memory 249084 kb
Host smart-f217ecf0-bbce-4c23-b35b-cfe427e46fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37751
13575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3775113575
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2246207511
Short name T322
Test name
Test status
Simulation time 51251640394 ps
CPU time 2860.39 seconds
Started Jun 13 01:32:36 PM PDT 24
Finished Jun 13 02:20:18 PM PDT 24
Peak memory 289992 kb
Host smart-0744f9ac-8349-47c5-9c93-026ced662849
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246207511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2246207511
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3231644804
Short name T695
Test name
Test status
Simulation time 127355047452 ps
CPU time 2016.53 seconds
Started Jun 13 01:57:13 PM PDT 24
Finished Jun 13 02:30:51 PM PDT 24
Peak memory 287656 kb
Host smart-b4851a92-ec99-42ad-a616-72ba37f1f96c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231644804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3231644804
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1363713689
Short name T308
Test name
Test status
Simulation time 8315999046 ps
CPU time 346.14 seconds
Started Jun 13 01:32:36 PM PDT 24
Finished Jun 13 01:38:23 PM PDT 24
Peak memory 256448 kb
Host smart-ac072f5a-5c71-4968-88fe-6eddad25a9ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363713689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1363713689
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.509025618
Short name T55
Test name
Test status
Simulation time 1574150268 ps
CPU time 34.74 seconds
Started Jun 13 01:42:14 PM PDT 24
Finished Jun 13 01:42:49 PM PDT 24
Peak memory 255964 kb
Host smart-14eca804-ad00-427f-a912-4b4edc835e02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50902
5618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.509025618
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.529787501
Short name T215
Test name
Test status
Simulation time 4064141345 ps
CPU time 61.35 seconds
Started Jun 13 01:32:38 PM PDT 24
Finished Jun 13 01:33:39 PM PDT 24
Peak memory 249196 kb
Host smart-c360c379-b6b8-4ff7-862b-e429a7f2ece8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52978
7501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.529787501
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.4196566403
Short name T374
Test name
Test status
Simulation time 328301527 ps
CPU time 29.58 seconds
Started Jun 13 01:50:26 PM PDT 24
Finished Jun 13 01:50:57 PM PDT 24
Peak memory 257176 kb
Host smart-95e7f1b8-6805-4028-8a8a-55f1e63f8a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41965
66403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.4196566403
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.4247501847
Short name T513
Test name
Test status
Simulation time 540832732963 ps
CPU time 2055.84 seconds
Started Jun 13 01:32:36 PM PDT 24
Finished Jun 13 02:06:53 PM PDT 24
Peak memory 273156 kb
Host smart-a0d78452-0c19-49d5-b0f4-8c1d0cad9789
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247501847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.4247501847
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1607667139
Short name T501
Test name
Test status
Simulation time 24667410581 ps
CPU time 645.01 seconds
Started Jun 13 01:32:46 PM PDT 24
Finished Jun 13 01:43:32 PM PDT 24
Peak memory 267636 kb
Host smart-b240db40-7b20-49cc-b73b-35cd91681309
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607667139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1607667139
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2492387179
Short name T22
Test name
Test status
Simulation time 2778595475 ps
CPU time 162.9 seconds
Started Jun 13 01:32:36 PM PDT 24
Finished Jun 13 01:35:19 PM PDT 24
Peak memory 257356 kb
Host smart-82db357c-b1ab-4fd2-90ae-02c446297199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24923
87179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2492387179
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1872505010
Short name T112
Test name
Test status
Simulation time 1736239256 ps
CPU time 58.77 seconds
Started Jun 13 01:32:37 PM PDT 24
Finished Jun 13 01:33:36 PM PDT 24
Peak memory 256004 kb
Host smart-65be1603-176a-46ce-b75b-291f7626b00b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18725
05010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1872505010
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2792741212
Short name T591
Test name
Test status
Simulation time 29117818662 ps
CPU time 840.63 seconds
Started Jun 13 01:32:43 PM PDT 24
Finished Jun 13 01:46:45 PM PDT 24
Peak memory 266616 kb
Host smart-082a24be-4e0f-4446-9f09-1b9be466ee76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792741212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2792741212
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3181980445
Short name T470
Test name
Test status
Simulation time 10766759005 ps
CPU time 1320.58 seconds
Started Jun 13 01:32:44 PM PDT 24
Finished Jun 13 01:54:45 PM PDT 24
Peak memory 289096 kb
Host smart-4654c877-42df-452c-8cd0-a122f663800f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181980445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3181980445
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.27677515
Short name T636
Test name
Test status
Simulation time 12823693314 ps
CPU time 515.6 seconds
Started Jun 13 01:34:13 PM PDT 24
Finished Jun 13 01:42:50 PM PDT 24
Peak memory 254524 kb
Host smart-27aa0246-2540-47a8-a188-df6ad38e3380
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27677515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.27677515
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.690376121
Short name T704
Test name
Test status
Simulation time 487297198 ps
CPU time 17.07 seconds
Started Jun 13 01:48:11 PM PDT 24
Finished Jun 13 01:48:28 PM PDT 24
Peak memory 253852 kb
Host smart-b91f0d7e-266d-438a-b6d8-09fbea4a21b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69037
6121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.690376121
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.83197066
Short name T278
Test name
Test status
Simulation time 738421981 ps
CPU time 42.98 seconds
Started Jun 13 01:54:26 PM PDT 24
Finished Jun 13 01:55:14 PM PDT 24
Peak memory 255248 kb
Host smart-308e39e1-9ddd-4288-9b90-08ae70c2463b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83197
066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.83197066
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2326825484
Short name T549
Test name
Test status
Simulation time 235702982 ps
CPU time 4.7 seconds
Started Jun 13 01:52:44 PM PDT 24
Finished Jun 13 01:52:49 PM PDT 24
Peak memory 239792 kb
Host smart-15fdb6a1-630e-4037-84a1-0d63fc60bbcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23268
25484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2326825484
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2436938486
Short name T558
Test name
Test status
Simulation time 291758836 ps
CPU time 27.66 seconds
Started Jun 13 01:32:36 PM PDT 24
Finished Jun 13 01:33:05 PM PDT 24
Peak memory 249160 kb
Host smart-60d40388-36ed-40e8-a869-9d08af37e7e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24369
38486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2436938486
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1492281211
Short name T109
Test name
Test status
Simulation time 7716593681 ps
CPU time 121.43 seconds
Started Jun 13 01:32:43 PM PDT 24
Finished Jun 13 01:34:45 PM PDT 24
Peak memory 257356 kb
Host smart-5bd3caac-d078-4da6-b15b-aadc10b9209d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492281211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1492281211
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1199253611
Short name T557
Test name
Test status
Simulation time 322701268612 ps
CPU time 1269.93 seconds
Started Jun 13 01:36:41 PM PDT 24
Finished Jun 13 01:57:51 PM PDT 24
Peak memory 273420 kb
Host smart-62d2e237-2b21-425c-a9d4-048b74ad4905
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199253611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1199253611
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1235406698
Short name T18
Test name
Test status
Simulation time 1567738141 ps
CPU time 77.86 seconds
Started Jun 13 01:32:45 PM PDT 24
Finished Jun 13 01:34:03 PM PDT 24
Peak memory 257224 kb
Host smart-569f2d2f-5c67-49d8-9ae3-68837bb28e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12354
06698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1235406698
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.855453149
Short name T619
Test name
Test status
Simulation time 3557456984 ps
CPU time 49.7 seconds
Started Jun 13 02:09:56 PM PDT 24
Finished Jun 13 02:10:47 PM PDT 24
Peak memory 255776 kb
Host smart-df1e17e2-e8a9-406d-bc48-ff291c5e1d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85545
3149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.855453149
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.311358455
Short name T119
Test name
Test status
Simulation time 155913744347 ps
CPU time 2453.89 seconds
Started Jun 13 01:32:50 PM PDT 24
Finished Jun 13 02:13:45 PM PDT 24
Peak memory 289508 kb
Host smart-c8af1e3a-9098-4026-ae63-3847727e0dba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311358455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.311358455
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2101996685
Short name T48
Test name
Test status
Simulation time 95705261289 ps
CPU time 1858.31 seconds
Started Jun 13 01:40:30 PM PDT 24
Finished Jun 13 02:11:29 PM PDT 24
Peak memory 270700 kb
Host smart-60eb59e4-9853-46e3-ab2d-aa54b186aed5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101996685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2101996685
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3086448789
Short name T562
Test name
Test status
Simulation time 216480065 ps
CPU time 6.72 seconds
Started Jun 13 01:32:44 PM PDT 24
Finished Jun 13 01:32:51 PM PDT 24
Peak memory 254568 kb
Host smart-007dcae9-74de-44b5-a9bc-d0b6928daaca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30864
48789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3086448789
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.874931418
Short name T245
Test name
Test status
Simulation time 353222361 ps
CPU time 14.83 seconds
Started Jun 13 01:32:52 PM PDT 24
Finished Jun 13 01:33:08 PM PDT 24
Peak memory 249040 kb
Host smart-f647acb9-c7b5-4da0-b72f-52ebb8eb13af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87493
1418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.874931418
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.104777790
Short name T490
Test name
Test status
Simulation time 841168010 ps
CPU time 14.49 seconds
Started Jun 13 01:35:26 PM PDT 24
Finished Jun 13 01:35:41 PM PDT 24
Peak memory 249108 kb
Host smart-0a8ac28f-dabc-4fce-81e2-95b74ed53aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10477
7790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.104777790
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2724451193
Short name T628
Test name
Test status
Simulation time 77510508336 ps
CPU time 2027.47 seconds
Started Jun 13 01:58:31 PM PDT 24
Finished Jun 13 02:32:20 PM PDT 24
Peak memory 305592 kb
Host smart-1beca506-e395-4ab9-9dc1-ce7ec048165e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724451193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2724451193
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1150514859
Short name T430
Test name
Test status
Simulation time 38014471027 ps
CPU time 2252.45 seconds
Started Jun 13 01:32:50 PM PDT 24
Finished Jun 13 02:10:23 PM PDT 24
Peak memory 287120 kb
Host smart-dc48f3e2-7a8f-4c93-9a9e-070b49163d8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150514859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1150514859
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2301143096
Short name T221
Test name
Test status
Simulation time 4110105789 ps
CPU time 223.68 seconds
Started Jun 13 02:07:33 PM PDT 24
Finished Jun 13 02:11:19 PM PDT 24
Peak memory 257308 kb
Host smart-6443d56a-6e98-42d6-ac50-bd3d0db1b70f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23011
43096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2301143096
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.518256781
Short name T246
Test name
Test status
Simulation time 598454623 ps
CPU time 42.68 seconds
Started Jun 13 01:32:51 PM PDT 24
Finished Jun 13 01:33:34 PM PDT 24
Peak memory 256160 kb
Host smart-91fbf59f-fe28-427e-989c-e8cf900528f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51825
6781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.518256781
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1267597862
Short name T479
Test name
Test status
Simulation time 14440577515 ps
CPU time 1512.77 seconds
Started Jun 13 01:32:52 PM PDT 24
Finished Jun 13 01:58:05 PM PDT 24
Peak memory 289044 kb
Host smart-c1221bd9-665a-4876-be67-fe69138a6d0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267597862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1267597862
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2973042254
Short name T296
Test name
Test status
Simulation time 47582852967 ps
CPU time 453.66 seconds
Started Jun 13 02:30:06 PM PDT 24
Finished Jun 13 02:37:41 PM PDT 24
Peak memory 248840 kb
Host smart-d1ff5eba-6bde-43d5-bf27-d3719350bce1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973042254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2973042254
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1116124825
Short name T210
Test name
Test status
Simulation time 84343100 ps
CPU time 7.5 seconds
Started Jun 13 02:22:15 PM PDT 24
Finished Jun 13 02:22:23 PM PDT 24
Peak memory 252716 kb
Host smart-7be52bbb-88fa-42c1-a146-8d9dc6b148ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11161
24825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1116124825
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1654214712
Short name T538
Test name
Test status
Simulation time 928202973 ps
CPU time 53.34 seconds
Started Jun 13 01:32:51 PM PDT 24
Finished Jun 13 01:33:46 PM PDT 24
Peak memory 255632 kb
Host smart-e43ece7d-f4d8-4d8f-9e14-9d764b6a69c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16542
14712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1654214712
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.4135630396
Short name T440
Test name
Test status
Simulation time 360512983 ps
CPU time 15.9 seconds
Started Jun 13 02:08:31 PM PDT 24
Finished Jun 13 02:08:47 PM PDT 24
Peak memory 256392 kb
Host smart-738f46ff-5637-48c8-98d5-115be1190789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41356
30396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.4135630396
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3677714003
Short name T624
Test name
Test status
Simulation time 4787125846 ps
CPU time 69.33 seconds
Started Jun 13 01:32:51 PM PDT 24
Finished Jun 13 01:34:01 PM PDT 24
Peak memory 249140 kb
Host smart-4ef15079-7354-47ed-90ce-302a577a4064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36777
14003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3677714003
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.4156075835
Short name T31
Test name
Test status
Simulation time 19785915591 ps
CPU time 1308.5 seconds
Started Jun 13 01:33:42 PM PDT 24
Finished Jun 13 01:55:32 PM PDT 24
Peak memory 273556 kb
Host smart-b44149ae-b32d-4baf-8186-3c2263b58bb8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156075835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.4156075835
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2776826884
Short name T195
Test name
Test status
Simulation time 144414889 ps
CPU time 3.14 seconds
Started Jun 13 01:29:04 PM PDT 24
Finished Jun 13 01:29:08 PM PDT 24
Peak memory 249256 kb
Host smart-f027217b-07d5-490b-9c64-c42c6890f91b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2776826884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2776826884
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2755640113
Short name T437
Test name
Test status
Simulation time 130726544594 ps
CPU time 2227.19 seconds
Started Jun 13 01:29:08 PM PDT 24
Finished Jun 13 02:06:16 PM PDT 24
Peak memory 281992 kb
Host smart-809ba6d2-d2df-485e-99b3-95c7e77adab6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755640113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2755640113
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3106545919
Short name T537
Test name
Test status
Simulation time 153460459 ps
CPU time 9.5 seconds
Started Jun 13 01:29:08 PM PDT 24
Finished Jun 13 01:29:18 PM PDT 24
Peak memory 249120 kb
Host smart-f348e7e2-cdf9-4efe-b233-8da32ce0fc2a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3106545919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3106545919
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.2042808551
Short name T689
Test name
Test status
Simulation time 20254618369 ps
CPU time 225.89 seconds
Started Jun 13 01:29:04 PM PDT 24
Finished Jun 13 01:32:51 PM PDT 24
Peak memory 257260 kb
Host smart-a6e54fb4-50ec-4610-b493-8755335c12c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20428
08551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2042808551
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3405807354
Short name T412
Test name
Test status
Simulation time 245985661 ps
CPU time 8.57 seconds
Started Jun 13 01:29:04 PM PDT 24
Finished Jun 13 01:29:14 PM PDT 24
Peak memory 249100 kb
Host smart-646d8393-a063-44f8-adbf-0a3fd5c02139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34058
07354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3405807354
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.4090015924
Short name T328
Test name
Test status
Simulation time 25035663105 ps
CPU time 1255.78 seconds
Started Jun 13 01:29:05 PM PDT 24
Finished Jun 13 01:50:01 PM PDT 24
Peak memory 287088 kb
Host smart-234ab7f5-1109-4650-a43b-32b5dc87045c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090015924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.4090015924
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3372805336
Short name T542
Test name
Test status
Simulation time 435370585481 ps
CPU time 2835.3 seconds
Started Jun 13 01:29:04 PM PDT 24
Finished Jun 13 02:16:21 PM PDT 24
Peak memory 281696 kb
Host smart-a7f246b9-645e-4403-89ca-91dd1680ab7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372805336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3372805336
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.251489646
Short name T315
Test name
Test status
Simulation time 18312536460 ps
CPU time 357.21 seconds
Started Jun 13 01:29:02 PM PDT 24
Finished Jun 13 01:35:00 PM PDT 24
Peak memory 248796 kb
Host smart-aefa5d4f-e4c7-42be-a138-14ff502ce978
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251489646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.251489646
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3701257053
Short name T409
Test name
Test status
Simulation time 324291785 ps
CPU time 32.77 seconds
Started Jun 13 01:29:06 PM PDT 24
Finished Jun 13 01:29:39 PM PDT 24
Peak memory 256452 kb
Host smart-7507fb1d-8702-47c6-b7e8-639b1bc76e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37012
57053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3701257053
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3905650765
Short name T23
Test name
Test status
Simulation time 479272944 ps
CPU time 30.77 seconds
Started Jun 13 01:29:03 PM PDT 24
Finished Jun 13 01:29:34 PM PDT 24
Peak memory 248980 kb
Host smart-1b23e2e5-500d-4c29-a148-18d7c8249623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39056
50765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3905650765
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3764797994
Short name T464
Test name
Test status
Simulation time 1281809613 ps
CPU time 40.61 seconds
Started Jun 13 01:29:08 PM PDT 24
Finished Jun 13 01:29:49 PM PDT 24
Peak memory 249048 kb
Host smart-7610098a-7cfe-4032-854d-71da658b9bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37647
97994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3764797994
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.866571991
Short name T476
Test name
Test status
Simulation time 69278175 ps
CPU time 6.09 seconds
Started Jun 13 01:29:02 PM PDT 24
Finished Jun 13 01:29:09 PM PDT 24
Peak memory 240940 kb
Host smart-1f74203e-7122-471a-926b-c14029cffd23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86657
1991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.866571991
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1524531601
Short name T254
Test name
Test status
Simulation time 98553747724 ps
CPU time 2698.62 seconds
Started Jun 13 01:29:04 PM PDT 24
Finished Jun 13 02:14:04 PM PDT 24
Peak memory 290084 kb
Host smart-f2b4170e-affa-492a-8e23-704ef148caf6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524531601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1524531601
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.94385110
Short name T95
Test name
Test status
Simulation time 74953279469 ps
CPU time 7956.26 seconds
Started Jun 13 01:29:04 PM PDT 24
Finished Jun 13 03:41:42 PM PDT 24
Peak memory 371100 kb
Host smart-5a0a2112-3c1f-4fa4-a6dd-5d3d43a631cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94385110 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.94385110
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2638401784
Short name T199
Test name
Test status
Simulation time 155684556 ps
CPU time 3.58 seconds
Started Jun 13 01:29:12 PM PDT 24
Finished Jun 13 01:29:17 PM PDT 24
Peak memory 249208 kb
Host smart-e15289b2-955b-49bc-9cd9-a1416061b2b0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2638401784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2638401784
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3797511999
Short name T548
Test name
Test status
Simulation time 133070238979 ps
CPU time 1722.95 seconds
Started Jun 13 01:29:10 PM PDT 24
Finished Jun 13 01:57:54 PM PDT 24
Peak memory 284524 kb
Host smart-0e9c14a0-c031-44c6-af29-8a95c4f93b26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797511999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3797511999
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3208061213
Short name T678
Test name
Test status
Simulation time 489097448 ps
CPU time 21.58 seconds
Started Jun 13 01:29:11 PM PDT 24
Finished Jun 13 01:29:34 PM PDT 24
Peak memory 249088 kb
Host smart-07384787-a563-4110-b4e2-8e2ef4d4d4b3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3208061213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3208061213
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.968393760
Short name T515
Test name
Test status
Simulation time 8828975562 ps
CPU time 259.4 seconds
Started Jun 13 01:29:12 PM PDT 24
Finished Jun 13 01:33:33 PM PDT 24
Peak memory 257324 kb
Host smart-d9b8a89f-cc90-4938-98a9-d5d743b70ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96839
3760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.968393760
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1714005261
Short name T237
Test name
Test status
Simulation time 478127117 ps
CPU time 39.36 seconds
Started Jun 13 01:29:12 PM PDT 24
Finished Jun 13 01:29:52 PM PDT 24
Peak memory 249376 kb
Host smart-df1e77ed-405a-44c5-8aa5-4f66b4091477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17140
05261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1714005261
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2163600655
Short name T320
Test name
Test status
Simulation time 22627043451 ps
CPU time 957.18 seconds
Started Jun 13 01:29:12 PM PDT 24
Finished Jun 13 01:45:11 PM PDT 24
Peak memory 273232 kb
Host smart-c0b3fec2-ed31-493f-b2fe-f52de66020a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163600655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2163600655
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2258533479
Short name T376
Test name
Test status
Simulation time 41515102268 ps
CPU time 1647.91 seconds
Started Jun 13 01:29:12 PM PDT 24
Finished Jun 13 01:56:41 PM PDT 24
Peak memory 290132 kb
Host smart-981f7a58-27e5-4401-b93e-312873dec4fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258533479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2258533479
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2887066513
Short name T297
Test name
Test status
Simulation time 7234916474 ps
CPU time 154.24 seconds
Started Jun 13 01:29:10 PM PDT 24
Finished Jun 13 01:31:46 PM PDT 24
Peak memory 248564 kb
Host smart-363525be-327e-4e5a-b0ac-a50cb438dd0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887066513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2887066513
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3053920914
Short name T465
Test name
Test status
Simulation time 50145537 ps
CPU time 5.04 seconds
Started Jun 13 01:29:05 PM PDT 24
Finished Jun 13 01:29:11 PM PDT 24
Peak memory 257124 kb
Host smart-b6454145-3337-4236-b187-9c1220d67646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30539
20914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3053920914
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3655345045
Short name T96
Test name
Test status
Simulation time 3133676260 ps
CPU time 37.2 seconds
Started Jun 13 01:29:11 PM PDT 24
Finished Jun 13 01:29:49 PM PDT 24
Peak memory 249036 kb
Host smart-76769711-7f3f-4163-a744-405e663715b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36553
45045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3655345045
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.3269576305
Short name T595
Test name
Test status
Simulation time 19671900 ps
CPU time 3.07 seconds
Started Jun 13 01:29:11 PM PDT 24
Finished Jun 13 01:29:15 PM PDT 24
Peak memory 239700 kb
Host smart-338def81-6d9e-4b7a-88c4-18cb70be405d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32695
76305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3269576305
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3158253323
Short name T385
Test name
Test status
Simulation time 198052794 ps
CPU time 19.84 seconds
Started Jun 13 01:29:06 PM PDT 24
Finished Jun 13 01:29:26 PM PDT 24
Peak memory 256416 kb
Host smart-3f9fbc36-a9c7-4875-b205-471d05a05bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31582
53323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3158253323
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.4196722565
Short name T693
Test name
Test status
Simulation time 20094778752 ps
CPU time 1168.76 seconds
Started Jun 13 01:29:11 PM PDT 24
Finished Jun 13 01:48:41 PM PDT 24
Peak memory 285516 kb
Host smart-32e5ab26-ebee-4bac-800c-562ab4dd6bfb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196722565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.4196722565
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1831783831
Short name T206
Test name
Test status
Simulation time 76551116 ps
CPU time 4 seconds
Started Jun 13 01:29:12 PM PDT 24
Finished Jun 13 01:29:17 PM PDT 24
Peak memory 249220 kb
Host smart-bc801374-911d-4927-a22e-077db36cbd15
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1831783831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1831783831
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3066322082
Short name T533
Test name
Test status
Simulation time 8454778608 ps
CPU time 854.3 seconds
Started Jun 13 01:29:10 PM PDT 24
Finished Jun 13 01:43:25 PM PDT 24
Peak memory 272840 kb
Host smart-5b8bb8d1-285a-4a0e-bc02-0781bc0e087e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066322082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3066322082
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1470371371
Short name T667
Test name
Test status
Simulation time 2117016569 ps
CPU time 13.78 seconds
Started Jun 13 01:29:12 PM PDT 24
Finished Jun 13 01:29:27 PM PDT 24
Peak memory 249064 kb
Host smart-a6d0ff18-ded6-44ac-bc9c-2e908dc67bab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1470371371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1470371371
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.914195051
Short name T391
Test name
Test status
Simulation time 1610103389 ps
CPU time 124.77 seconds
Started Jun 13 01:29:09 PM PDT 24
Finished Jun 13 01:31:15 PM PDT 24
Peak memory 257276 kb
Host smart-eaefa691-62a4-4f4a-b954-4847a6320f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91419
5051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.914195051
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2913741914
Short name T217
Test name
Test status
Simulation time 1695134207 ps
CPU time 28.31 seconds
Started Jun 13 01:29:24 PM PDT 24
Finished Jun 13 01:29:54 PM PDT 24
Peak memory 256188 kb
Host smart-d6ee3eb4-b49b-4b2f-b73b-1d98c7521a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29137
41914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2913741914
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2240558149
Short name T304
Test name
Test status
Simulation time 134028336279 ps
CPU time 1939.74 seconds
Started Jun 13 01:29:09 PM PDT 24
Finished Jun 13 02:01:30 PM PDT 24
Peak memory 285940 kb
Host smart-1cbf0186-9e75-45d3-a86f-be0e34ed19bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240558149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2240558149
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2394155633
Short name T571
Test name
Test status
Simulation time 134733339110 ps
CPU time 1950.35 seconds
Started Jun 13 01:29:18 PM PDT 24
Finished Jun 13 02:01:50 PM PDT 24
Peak memory 270956 kb
Host smart-7cd02385-9903-4673-9ac0-db8274610d41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394155633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2394155633
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2628310236
Short name T288
Test name
Test status
Simulation time 32921886624 ps
CPU time 155.75 seconds
Started Jun 13 01:29:11 PM PDT 24
Finished Jun 13 01:31:48 PM PDT 24
Peak memory 248576 kb
Host smart-057053bb-df2b-4968-825b-a2ec76cfefac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628310236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2628310236
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3708828201
Short name T572
Test name
Test status
Simulation time 468007846 ps
CPU time 40.33 seconds
Started Jun 13 01:29:12 PM PDT 24
Finished Jun 13 01:29:53 PM PDT 24
Peak memory 249104 kb
Host smart-4261e59e-c5c7-4035-8e74-2f78555e992d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37088
28201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3708828201
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.45898582
Short name T59
Test name
Test status
Simulation time 1975178583 ps
CPU time 18.32 seconds
Started Jun 13 01:29:11 PM PDT 24
Finished Jun 13 01:29:31 PM PDT 24
Peak memory 248060 kb
Host smart-bf200fde-2332-426d-ab55-1bd076fee3e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45898
582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.45898582
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.8534237
Short name T256
Test name
Test status
Simulation time 1830800226 ps
CPU time 30.81 seconds
Started Jun 13 01:29:11 PM PDT 24
Finished Jun 13 01:29:42 PM PDT 24
Peak memory 248372 kb
Host smart-5c4b5fb4-5de0-4a02-944c-15af6fdb1325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85342
37 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.8534237
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.133361737
Short name T444
Test name
Test status
Simulation time 1094005958 ps
CPU time 64.5 seconds
Started Jun 13 01:29:09 PM PDT 24
Finished Jun 13 01:30:15 PM PDT 24
Peak memory 249056 kb
Host smart-507de9b2-d409-49a9-a0e5-9a8626328314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13336
1737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.133361737
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3059220644
Short name T271
Test name
Test status
Simulation time 41744993292 ps
CPU time 2423.45 seconds
Started Jun 13 01:29:12 PM PDT 24
Finished Jun 13 02:09:37 PM PDT 24
Peak memory 289888 kb
Host smart-15acf9b4-b02f-407b-a291-746664da2e52
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059220644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3059220644
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3889833407
Short name T202
Test name
Test status
Simulation time 48597018 ps
CPU time 3.82 seconds
Started Jun 13 01:29:17 PM PDT 24
Finished Jun 13 01:29:22 PM PDT 24
Peak memory 249276 kb
Host smart-864a3714-4689-47b7-806d-2a1aada57cd9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3889833407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3889833407
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.337506896
Short name T397
Test name
Test status
Simulation time 8799927441 ps
CPU time 844.37 seconds
Started Jun 13 01:29:12 PM PDT 24
Finished Jun 13 01:43:18 PM PDT 24
Peak memory 270024 kb
Host smart-ee368079-734a-4def-96d1-30943b766ce0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337506896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.337506896
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2554508878
Short name T398
Test name
Test status
Simulation time 5568784445 ps
CPU time 23.97 seconds
Started Jun 13 01:29:17 PM PDT 24
Finished Jun 13 01:29:42 PM PDT 24
Peak memory 249184 kb
Host smart-87d758e8-2bd5-486d-89b1-6af5b6d81b80
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2554508878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2554508878
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3969627618
Short name T514
Test name
Test status
Simulation time 3819067710 ps
CPU time 227.2 seconds
Started Jun 13 01:29:19 PM PDT 24
Finished Jun 13 01:33:07 PM PDT 24
Peak memory 251272 kb
Host smart-60b8ef7d-7317-4d93-b43e-8acf598614ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39696
27618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3969627618
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2255006776
Short name T593
Test name
Test status
Simulation time 1242290899 ps
CPU time 71.07 seconds
Started Jun 13 01:29:11 PM PDT 24
Finished Jun 13 01:30:23 PM PDT 24
Peak memory 249012 kb
Host smart-d458d51c-2b1a-42ba-bbff-258b50d8b526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22550
06776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2255006776
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.4153691728
Short name T326
Test name
Test status
Simulation time 71553864729 ps
CPU time 956.98 seconds
Started Jun 13 01:29:19 PM PDT 24
Finished Jun 13 01:45:16 PM PDT 24
Peak memory 273792 kb
Host smart-bd748a0b-d637-43c2-bb18-6dbbfd492618
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153691728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.4153691728
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3213717537
Short name T232
Test name
Test status
Simulation time 42342802223 ps
CPU time 2538.36 seconds
Started Jun 13 01:29:14 PM PDT 24
Finished Jun 13 02:11:33 PM PDT 24
Peak memory 289496 kb
Host smart-f24d1832-b3a1-4b6a-975d-f7a9c881065c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213717537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3213717537
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2235673733
Short name T70
Test name
Test status
Simulation time 770058209 ps
CPU time 13.33 seconds
Started Jun 13 01:29:19 PM PDT 24
Finished Jun 13 01:29:33 PM PDT 24
Peak memory 248948 kb
Host smart-5ebcc77c-3423-4ef6-a127-0045129efcc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22356
73733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2235673733
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3459762328
Short name T272
Test name
Test status
Simulation time 2014414562 ps
CPU time 75.41 seconds
Started Jun 13 01:29:13 PM PDT 24
Finished Jun 13 01:30:29 PM PDT 24
Peak memory 249028 kb
Host smart-31b02763-6c30-49e2-bd2a-f4aa52048674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34597
62328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3459762328
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.424805790
Short name T285
Test name
Test status
Simulation time 969483321 ps
CPU time 11.9 seconds
Started Jun 13 01:29:18 PM PDT 24
Finished Jun 13 01:29:31 PM PDT 24
Peak memory 252500 kb
Host smart-645d7eb2-863f-46be-881c-62e85d97325b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42480
5790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.424805790
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.800624778
Short name T218
Test name
Test status
Simulation time 947309156 ps
CPU time 37.58 seconds
Started Jun 13 01:29:11 PM PDT 24
Finished Jun 13 01:29:49 PM PDT 24
Peak memory 249072 kb
Host smart-4833b197-d3f4-4ba0-bbd9-5c3cb88766d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80062
4778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.800624778
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3493424895
Short name T429
Test name
Test status
Simulation time 17048790760 ps
CPU time 1768.61 seconds
Started Jun 13 01:29:20 PM PDT 24
Finished Jun 13 01:58:50 PM PDT 24
Peak memory 290092 kb
Host smart-80824f5d-d3ba-4ca4-af3d-b8f1266c1670
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493424895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3493424895
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1768973638
Short name T204
Test name
Test status
Simulation time 25819403 ps
CPU time 2.78 seconds
Started Jun 13 01:29:15 PM PDT 24
Finished Jun 13 01:29:18 PM PDT 24
Peak memory 249208 kb
Host smart-7c881b9b-4c39-4978-b9b1-ac6ea4b58ea8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1768973638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1768973638
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2406304704
Short name T508
Test name
Test status
Simulation time 90950984721 ps
CPU time 1442.61 seconds
Started Jun 13 01:29:15 PM PDT 24
Finished Jun 13 01:53:18 PM PDT 24
Peak memory 273696 kb
Host smart-0ff8172f-17d3-4a61-a594-8146ad864f20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406304704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2406304704
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.4244992526
Short name T355
Test name
Test status
Simulation time 1537180662 ps
CPU time 19.24 seconds
Started Jun 13 01:29:16 PM PDT 24
Finished Jun 13 01:29:36 PM PDT 24
Peak memory 249068 kb
Host smart-bed0dc92-a1db-4c12-a31b-76060ca1eef8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4244992526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.4244992526
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.511105330
Short name T632
Test name
Test status
Simulation time 19321119111 ps
CPU time 268.92 seconds
Started Jun 13 01:29:20 PM PDT 24
Finished Jun 13 01:33:50 PM PDT 24
Peak memory 251348 kb
Host smart-3c3f0ff2-4c4b-42a7-86da-0af43825e104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51110
5330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.511105330
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.1312933380
Short name T540
Test name
Test status
Simulation time 798378493 ps
CPU time 18.61 seconds
Started Jun 13 01:29:20 PM PDT 24
Finished Jun 13 01:29:39 PM PDT 24
Peak memory 249100 kb
Host smart-b6f7c323-0905-49e3-ab46-f227eb3a8fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13129
33380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1312933380
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.547193896
Short name T211
Test name
Test status
Simulation time 25440386184 ps
CPU time 1145.89 seconds
Started Jun 13 01:29:16 PM PDT 24
Finished Jun 13 01:48:23 PM PDT 24
Peak memory 272348 kb
Host smart-af607a40-e94a-464c-a6d8-45b0c0d4ea29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547193896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.547193896
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1422144644
Short name T567
Test name
Test status
Simulation time 285424617720 ps
CPU time 1924.03 seconds
Started Jun 13 01:29:14 PM PDT 24
Finished Jun 13 02:01:19 PM PDT 24
Peak memory 273776 kb
Host smart-fbc3ffb7-dd97-46c7-9002-cc642ef11041
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422144644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1422144644
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3614780170
Short name T683
Test name
Test status
Simulation time 12645120809 ps
CPU time 469.15 seconds
Started Jun 13 01:29:15 PM PDT 24
Finished Jun 13 01:37:05 PM PDT 24
Peak memory 247640 kb
Host smart-9b988152-d0dc-4b55-9710-3305c736f20f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614780170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3614780170
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.953163060
Short name T535
Test name
Test status
Simulation time 1691486621 ps
CPU time 32.55 seconds
Started Jun 13 01:29:18 PM PDT 24
Finished Jun 13 01:29:52 PM PDT 24
Peak memory 257276 kb
Host smart-1900a199-89dd-43ef-9d35-601468cf82de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95316
3060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.953163060
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3092665351
Short name T56
Test name
Test status
Simulation time 502206950 ps
CPU time 25.53 seconds
Started Jun 13 01:29:17 PM PDT 24
Finished Jun 13 01:29:44 PM PDT 24
Peak memory 248176 kb
Host smart-89879bde-6898-4040-a687-016515b4421c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30926
65351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3092665351
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2054032434
Short name T554
Test name
Test status
Simulation time 554055734 ps
CPU time 23.64 seconds
Started Jun 13 01:29:15 PM PDT 24
Finished Jun 13 01:29:39 PM PDT 24
Peak memory 257064 kb
Host smart-408a6473-c314-4db4-a140-60b740320914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20540
32434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2054032434
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.714279169
Short name T565
Test name
Test status
Simulation time 90711667679 ps
CPU time 1420.92 seconds
Started Jun 13 01:29:17 PM PDT 24
Finished Jun 13 01:53:00 PM PDT 24
Peak memory 289568 kb
Host smart-f52b8670-fc64-4925-9d7f-88e7bc42b721
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714279169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.714279169
Directory /workspace/9.alert_handler_stress_all/latest
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