Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	87435	1			T27	10		T8	2909		T15	6
class_i[0x1]	68955	1			T16	31		T27	6		T8	434
class_i[0x2]	85350	1			T27	5		T7	2		T28	147
class_i[0x3]	41715	1			T16	46		T27	845		T7	1

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	68160	1			T16	38		T27	9		T8	839
alert[0x1]	71780	1			T16	11		T27	375		T8	943
alert[0x2]	71506	1			T16	19		T27	479		T8	763
alert[0x3]	72009	1			T16	9		T27	3		T8	798

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

283167

1

T16

77

T27

866

T8

3343

esc_ping_fail

288

1

T7

5

T9

8

T15

7

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	68072	1			T16	38		T27	9		T8	839
esc_integrity_fail	alert[0x1]	71710	1			T16	11		T27	375		T8	943
esc_integrity_fail	alert[0x2]	71432	1			T16	19		T27	479		T8	763
esc_integrity_fail	alert[0x3]	71953	1			T16	9		T27	3		T8	798
esc_ping_fail	alert[0x0]	88	1			T9	3		T15	2		T89	4
esc_ping_fail	alert[0x1]	70	1			T7	1		T9	2		T15	1
esc_ping_fail	alert[0x2]	74	1			T7	2		T9	1		T15	2
esc_ping_fail	alert[0x3]	56	1			T7	2		T9	2		T15	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	87386	1			T27	10		T8	2909		T32	18
esc_integrity_fail	class_i[0x1]	68881	1			T16	31		T27	6		T8	434
esc_integrity_fail	class_i[0x2]	85259	1			T27	5		T7	2		T28	147
esc_integrity_fail	class_i[0x3]	41641	1			T16	46		T27	845		T28	11
esc_ping_fail	class_i[0x0]	49	1			T15	6		T89	1		T305	1
esc_ping_fail	class_i[0x1]	74	1			T7	4		T9	8		T89	1
esc_ping_fail	class_i[0x2]	91	1			T15	1		T89	1		T248	11
esc_ping_fail	class_i[0x3]	74	1			T7	1		T89	4		T320	1