Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	674783191	0	0	626
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	674783191	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	674783191	674599046	0	0
tb.dut.CheckAccuCntDw	0	0	626	626	0	0
tb.dut.CheckEscCntDw	0	0	626	626	0	0
tb.dut.CheckNAlerts	0	0	626	626	0	0
tb.dut.CheckNClasses	0	0	626	626	0	0
tb.dut.CheckNEscSev	0	0	626	626	0	0
tb.dut.CrashdumpKnownO_A	0	0	674783191	674599046	0	0
tb.dut.EdnKnownO_A	0	0	674783191	674599046	0	0
tb.dut.EscPKnownO_A	0	0	674783191	674599046	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	674783191	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	674783191	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	674783191	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	674783191	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	674783191	90	0	0
tb.dut.IrqAKnownO_A	0	0	674783191	674599046	0	0
tb.dut.IrqBKnownO_A	0	0	674783191	674599046	0	0
tb.dut.IrqCKnownO_A	0	0	674783191	674599046	0	0
tb.dut.IrqDKnownO_A	0	0	674783191	674599046	0	0
tb.dut.TlAReadyKnownO_A	0	0	674783191	674599046	0	0
tb.dut.TlDValidKnownO_A	0	0	674783191	674599046	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	702721946	2747453	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	702721946	20204	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	702721946	21686	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	702721946	19904	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	702721946	20141	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	702721946	20879	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	702721946	20245	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	702721946	21235	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	702721946	20441	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	702721946	20919	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	702721946	21043	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	702721946	20412	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	702721946	21359	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	702721946	21658	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	702721946	21312	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	702721946	19702	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	702721946	23352	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	702721946	20182	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	702721946	21532	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	702721946	20943	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	702721946	21225	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	702721946	22516	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	702721946	21074	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	702721946	22570	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	702721946	22525	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	702721946	21165	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	702721946	21213	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	702721946	21584	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	702721946	21268	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	702721946	21485	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	702721946	21207	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	702721946	20994	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	702721946	21407	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	702721946	20631	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	702721946	21290	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	702721946	20300	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	702721946	20164	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	702721946	19991	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	702721946	20954	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	702721946	20309	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	702721946	21567	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	702721946	22685	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	702721946	21035	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	702721946	20002	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	702721946	19820	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	702721946	21135	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	702721946	20089	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	702721946	21710	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	702721946	22301	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	702721946	22025	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	702721946	20029	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	702721946	21785	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	702721946	21225	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	702721946	21890	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	702721946	21104	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	702721946	20152	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	702721946	20044	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	702721946	21298	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	702721946	21544	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	702721946	22474	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	702721946	19944	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	702721946	23289	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	702721946	21683	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	702721946	21200	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	702721946	21375	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	702721946	20593	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	702721946	20954	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	702721946	21074	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	702721946	20354	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	702721946	21433	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	702721946	39803	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	702721946	21014	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	702721946	22466	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	702721946	22875	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	702721946	20753	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	702721946	21244	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	702721946	20168	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	702721946	20873	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	702721946	20037	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	674783191	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	674783191	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	674783191	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	674783191	1985	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	674783191	224390	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	674783191	355579953	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	674783191	309	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	674783191	819	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	674783191	51	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	674783191	384	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	674522911	261095660	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	674783191	902	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	674783191	884	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	674783191	869	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	674783191	843	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	674783191	1400	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	674783191	131078	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	674783191	1291	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	674783191	57	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	674783191	1597	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	674783191	1327	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	674521019	674451549	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	674783191	674599046	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	674783191	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	674783191	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	674783191	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	674783191	3063	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	674783191	201982	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	674783191	391615582	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	674783191	316	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	674783191	487	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	674783191	25	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	674783191	225	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	674522911	296699418	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	674783191	568	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	674783191	557	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	674783191	547	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	674783191	536	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	674783191	1009	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	674783191	112551	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	674783191	916	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	674783191	67	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	674783191	1629	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	674783191	1359	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	674521019	674451549	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	674783191	674599046	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	674783191	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	674783191	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	674783191	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	674783191	6211	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	674783191	241343	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	674783191	364910449	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	674783191	280	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	674783191	477	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	674783191	20	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	674783191	204	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	674522911	302746830	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	674783191	551	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	674783191	544	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	674783191	533	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	674783191	519	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	674783191	1512	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	674783191	166026	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	674783191	1425	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	674783191	64	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	674783191	1581	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	674783191	1311	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	674521019	674451549	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	674783191	674599046	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	674783191	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	674783191	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	674783191	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	674783191	4472	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	674783191	163473	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	674783191	391365629	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	674783191	320	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	674783191	499	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	674783191	21	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	674783191	234	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	674522911	324259016	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	674783191	589	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	674783191	584	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	674783191	574	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	674783191	562	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	674783191	1010	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	674783191	101702	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	674783191	906	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	674783191	82	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	674783191	1581	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	674783191	1311	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	674521019	674451549	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	674783191	674599046	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	702721946	130732809	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	702721946	702043390	0	0
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