Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	1	43	97.73

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	1	43	97.73	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	171	1			T3	1		T16	1		T4	1
index[0x1]	168	1			T16	1		T4	1		T27	1
index[0x2]	207	1			T16	1		T18	3		T21	1
index[0x3]	187	1			T3	1		T16	2		T4	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	213	1			T16	2		T18	5		T21	1
lens_less_than_1000[1]	163	1			T21	1		T27	1		T23	1
lens_less_than_1000[2]	94	1			T3	1		T16	1		T4	2
lens_less_than_1000[3]	92	1			T3	1		T20	1		T76	1
lens_less_than_1000[4]	56	1			T80	1		T38	1		T106	1
lens_less_than_1000[5]	43	1			T16	1		T37	1		T87	2
lens_less_than_1000[6]	28	1			T16	1		T4	1		T75	1
lens_less_than_1000[7]	19	1			T20	1		T54	1		T30	1
lens_less_than_1000[8]	13	1			T20	1		T75	1		T38	1
lens_less_than_1000[9]	3	1			T278	1		T96	1		T279	1
len_2	9	1			T186	2		T69	2		T280	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	1	43	97.73	1

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	47	1			T21	1		T15	1		T32	2
index[0x0]	lens_less_than_1000[1]	35	1			T23	1		T55	1		T56	1
index[0x0]	lens_less_than_1000[2]	20	1			T3	1		T4	1		T5	1
index[0x0]	lens_less_than_1000[3]	24	1			T76	1		T77	1		T281	1
index[0x0]	lens_less_than_1000[4]	16	1			T84	1		T282	1		T87	1
index[0x0]	lens_less_than_1000[5]	13	1			T16	1		T278	1		T283	5
index[0x0]	lens_less_than_1000[6]	4	1			T75	1		T30	1		T284	1
index[0x0]	lens_less_than_1000[7]	6	1			T20	1		T285	1		T26	4
index[0x0]	lens_less_than_1000[8]	2	1			T20	1		T38	1		-	-
index[0x0]	lens_less_than_1000[9]	1	1			T279	1		-	-		-	-
index[0x0]	len_2	3	1			T186	2		T280	1		-	-
index[0x1]	lens_less_than_1000[0]	52	1			T16	1		T29	1		T8	2
index[0x1]	lens_less_than_1000[1]	39	1			T27	1		T37	1		T275	1
index[0x1]	lens_less_than_1000[2]	22	1			T4	1		T14	1		T30	1
index[0x1]	lens_less_than_1000[3]	21	1			T87	1		T258	1		T88	1
index[0x1]	lens_less_than_1000[4]	8	1			T35	1		T84	1		T25	1
index[0x1]	lens_less_than_1000[5]	6	1			T87	1		T110	1		T112	1
index[0x1]	lens_less_than_1000[6]	12	1			T38	1		T87	1		T61	1
index[0x1]	lens_less_than_1000[7]	2	1			T37	1		T286	1		-	-
index[0x1]	lens_less_than_1000[8]	3	1			T75	1		T287	1		T288	1
index[0x1]	lens_less_than_1000[9]	1	1			T278	1		-	-		-	-
index[0x1]	len_2	2	1			T69	1		T289	1		-	-
index[0x2]	lens_less_than_1000[0]	62	1			T16	1		T18	3		T72	1
index[0x2]	lens_less_than_1000[1]	44	1			T21	1		T32	1		T75	1
index[0x2]	lens_less_than_1000[2]	26	1			T82	3		T37	1		T87	2
index[0x2]	lens_less_than_1000[3]	26	1			T30	1		T35	1		T61	1
index[0x2]	lens_less_than_1000[4]	16	1			T38	1		T94	1		T108	2
index[0x2]	lens_less_than_1000[5]	14	1			T37	1		T94	1		T290	1
index[0x2]	lens_less_than_1000[6]	3	1			T291	1		T292	1		T293	1
index[0x2]	lens_less_than_1000[7]	7	1			T30	1		T263	1		T253	1
index[0x2]	lens_less_than_1000[8]	6	1			T39	1		T267	1		T294	1
index[0x2]	lens_less_than_1000[9]	1	1			T96	1		-	-		-	-
index[0x2]	len_2	2	1			T100	1		T295	1		-	-
index[0x3]	lens_less_than_1000[0]	52	1			T18	2		T8	1		T32	1
index[0x3]	lens_less_than_1000[1]	45	1			T75	1		T275	1		T35	1
index[0x3]	lens_less_than_1000[2]	26	1			T16	1		T30	1		T35	1
index[0x3]	lens_less_than_1000[3]	21	1			T3	1		T20	1		T39	4
index[0x3]	lens_less_than_1000[4]	16	1			T80	1		T106	1		T61	1
index[0x3]	lens_less_than_1000[5]	10	1			T87	1		T296	1		T297	1
index[0x3]	lens_less_than_1000[6]	9	1			T16	1		T4	1		T278	1
index[0x3]	lens_less_than_1000[7]	4	1			T54	1		T96	1		T189	1
index[0x3]	lens_less_than_1000[8]	2	1			T99	1		T268	1		-	-
index[0x3]	len_2	2	1			T69	1		T289	1		-	-