Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	57	1			T32	1		T38	1		T35	1
class_index[0x1]	67	1			T27	1		T32	3		T75	2
class_index[0x2]	64	1			T8	1		T28	1		T32	2
class_index[0x3]	82	1			T54	5		T8	1		T28	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	88	1			T54	5		T74	1		T32	2
intr_timeout_cnt[1]	69	1			T32	2		T75	2		T80	1
intr_timeout_cnt[2]	35	1			T75	1		T37	1		T60	1
intr_timeout_cnt[3]	18	1			T35	2		T108	1		T261	1
intr_timeout_cnt[4]	12	1			T32	1		T80	1		T87	1
intr_timeout_cnt[5]	8	1			T8	1		T28	1		T80	1
intr_timeout_cnt[6]	16	1			T27	1		T8	1		T28	1
intr_timeout_cnt[7]	9	1			T32	3		T260	1		T262	1
intr_timeout_cnt[8]	11	1			T75	1		T35	1		T85	1
intr_timeout_cnt[9]	4	1			T39	1		T259	1		T263	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	16	1			T85	1		T60	1		T31	1
class_index[0x0]	intr_timeout_cnt[1]	19	1			T38	1		T86	1		T31	1
class_index[0x0]	intr_timeout_cnt[2]	8	1			T39	1		T88	1		T186	1
class_index[0x0]	intr_timeout_cnt[3]	1	1			T261	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[4]	3	1			T109	1		T264	2		-	-
class_index[0x0]	intr_timeout_cnt[6]	4	1			T87	1		T60	1		T67	1
class_index[0x0]	intr_timeout_cnt[7]	1	1			T32	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	4	1			T35	1		T112	1		T99	2
class_index[0x0]	intr_timeout_cnt[9]	1	1			T39	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	28	1			T32	2		T75	1		T76	1
class_index[0x1]	intr_timeout_cnt[1]	12	1			T75	1		T81	1		T85	1
class_index[0x1]	intr_timeout_cnt[2]	7	1			T263	3		T265	1		T266	1
class_index[0x1]	intr_timeout_cnt[3]	6	1			T263	1		T265	1		T264	1
class_index[0x1]	intr_timeout_cnt[4]	2	1			T32	1		T88	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	1	1			T98	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	5	1			T27	1		T267	1		T99	1
class_index[0x1]	intr_timeout_cnt[7]	3	1			T260	1		T268	1		T254	1
class_index[0x1]	intr_timeout_cnt[8]	3	1			T85	1		T253	1		T269	1
class_index[0x2]	intr_timeout_cnt[0]	20	1			T75	1		T77	1		T30	1
class_index[0x2]	intr_timeout_cnt[1]	15	1			T32	2		T82	3		T37	1
class_index[0x2]	intr_timeout_cnt[2]	7	1			T60	1		T270	1		T25	1
class_index[0x2]	intr_timeout_cnt[3]	5	1			T108	1		T271	1		T272	1
class_index[0x2]	intr_timeout_cnt[4]	4	1			T87	1		T39	1		T187	1
class_index[0x2]	intr_timeout_cnt[5]	4	1			T8	1		T80	1		T38	1
class_index[0x2]	intr_timeout_cnt[6]	2	1			T28	1		T35	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	3	1			T262	1		T273	1		T274	1
class_index[0x2]	intr_timeout_cnt[8]	2	1			T75	1		T258	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	2	1			T259	1		T263	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	24	1			T54	5		T74	1		T275	1
class_index[0x3]	intr_timeout_cnt[1]	23	1			T75	1		T80	1		T38	2
class_index[0x3]	intr_timeout_cnt[2]	13	1			T75	1		T37	1		T108	1
class_index[0x3]	intr_timeout_cnt[3]	6	1			T35	2		T272	1		T96	1
class_index[0x3]	intr_timeout_cnt[4]	3	1			T80	1		T64	1		T67	1
class_index[0x3]	intr_timeout_cnt[5]	3	1			T28	1		T112	1		T263	1
class_index[0x3]	intr_timeout_cnt[6]	5	1			T8	1		T55	1		T109	1
class_index[0x3]	intr_timeout_cnt[7]	2	1			T32	2		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	2	1			T276	2		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T277	1		-	-		-	-