Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	353158	1			T1	61		T2	889		T3	29
all_values[1]	353158	1			T1	61		T2	889		T3	29
all_values[2]	353158	1			T1	61		T2	889		T3	29
all_values[3]	353158	1			T1	61		T2	889		T3	29

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

702853

1

T1

136

T2

1743

T3

50

auto[1]

709779

1

T1

108

T2

1813

T3

66

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

840992

1

T1

124

T2

1989

T3

60

auto[1]

571640

1

T1

120

T2

1567

T3

56

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	100801	1			T1	16		T2	233		T3	5
all_values[0]	auto[0]	auto[1]	75066	1			T1	16		T2	206		T3	5
all_values[0]	auto[1]	auto[0]	102128	1			T1	15		T2	238		T3	10
all_values[0]	auto[1]	auto[1]	75163	1			T1	14		T2	212		T3	9
all_values[1]	auto[0]	auto[0]	105142	1			T1	17		T2	272		T3	8
all_values[1]	auto[0]	auto[1]	69667	1			T1	16		T2	182		T3	7
all_values[1]	auto[1]	auto[0]	107450	1			T1	14		T2	269		T3	7
all_values[1]	auto[1]	auto[1]	70899	1			T1	14		T2	166		T3	7
all_values[2]	auto[0]	auto[0]	104844	1			T1	18		T2	246		T3	6
all_values[2]	auto[0]	auto[1]	71003	1			T1	17		T2	201		T3	6
all_values[2]	auto[1]	auto[0]	106149	1			T1	13		T2	242		T3	9
all_values[2]	auto[1]	auto[1]	71162	1			T1	13		T2	200		T3	8
all_values[3]	auto[0]	auto[0]	106869	1			T1	18		T2	222		T3	7
all_values[3]	auto[0]	auto[1]	69461	1			T1	18		T2	181		T3	6
all_values[3]	auto[1]	auto[0]	107609	1			T1	13		T2	267		T3	8
all_values[3]	auto[1]	auto[1]	69219	1			T1	12		T2	219		T3	8