Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	353158	1			T1	61		T2	889		T3	29
all_pins[1]	353158	1			T1	61		T2	889		T3	29
all_pins[2]	353158	1			T1	61		T2	889		T3	29
all_pins[3]	353158	1			T1	61		T2	889		T3	29

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1126189	1			T1	191		T2	2759		T3	84
values[0x1]	286443	1			T1	53		T2	797		T3	32
transitions[0x0=>0x1]	190379	1			T1	32		T2	542		T3	21
transitions[0x1=>0x0]	190636	1			T1	33		T2	542		T3	22

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	277995	1			T1	47		T2	677		T3	20
all_pins[0]	values[0x1]	75163	1			T1	14		T2	212		T3	9
all_pins[0]	transitions[0x0=>0x1]	74501	1			T1	13		T2	212		T3	8
all_pins[0]	transitions[0x1=>0x0]	68814	1			T1	12		T2	219		T3	8
all_pins[1]	values[0x0]	282259	1			T1	47		T2	723		T3	22
all_pins[1]	values[0x1]	70899	1			T1	14		T2	166		T3	7
all_pins[1]	transitions[0x0=>0x1]	38715	1			T1	8		T2	90		T3	4
all_pins[1]	transitions[0x1=>0x0]	42979	1			T1	8		T2	136		T3	6
all_pins[2]	values[0x0]	281996	1			T1	48		T2	689		T3	21
all_pins[2]	values[0x1]	71162	1			T1	13		T2	200		T3	8
all_pins[2]	transitions[0x0=>0x1]	39338	1			T1	6		T2	128		T3	5
all_pins[2]	transitions[0x1=>0x0]	39075	1			T1	7		T2	94		T3	4
all_pins[3]	values[0x0]	283939	1			T1	49		T2	670		T3	21
all_pins[3]	values[0x1]	69219	1			T1	12		T2	219		T3	8
all_pins[3]	transitions[0x0=>0x1]	37825	1			T1	5		T2	112		T3	4
all_pins[3]	transitions[0x1=>0x0]	39768	1			T1	6		T2	93		T3	4