Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	263	1			T166	7		T167	4		T168	7
all_values[1]	263	1			T166	7		T167	4		T168	7
all_values[2]	263	1			T166	7		T167	4		T168	7
all_values[3]	263	1			T166	7		T167	4		T168	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

595

1

T166

20

T167

3

T168

12

auto[1]

457

1

T166

8

T167

13

T168

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

398

1

T166

12

T167

11

T168

4

auto[1]

654

1

T166

16

T167

5

T168

24

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

596

1

T166

15

T167

13

T168

13

auto[1]

456

1

T166

13

T167

3

T168

15

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

54

1

T166

1

T246

3

T342

1

all_values[0]

auto[0]

auto[0]

auto[1]

27

1

T167

1

T343

2

T344

1

all_values[0]

auto[0]

auto[1]

auto[0]

45

1

T166

3

T167

2

T168

1

all_values[0]

auto[0]

auto[1]

auto[1]

24

1

T168

2

T342

2

T345

1

all_values[0]

auto[1]

auto[0]

auto[1]

66

1

T166

3

T167

1

T168

2

all_values[0]

auto[1]

auto[1]

auto[1]

47

1

T168

2

T342

1

T256

1

all_values[1]

auto[0]

auto[0]

auto[0]

48

1

T166

1

T246

1

T342

1

all_values[1]

auto[0]

auto[0]

auto[1]

24

1

T166

1

T168

2

T256

1

all_values[1]

auto[0]

auto[1]

auto[0]

39

1

T167

2

T168

1

T246

1

all_values[1]

auto[0]

auto[1]

auto[1]

29

1

T167

1

T168

1

T246

2

all_values[1]

auto[1]

auto[0]

auto[1]

70

1

T166

5

T342

1

T256

1

all_values[1]

auto[1]

auto[1]

auto[1]

53

1

T167

1

T168

3

T246

3

all_values[2]

auto[0]

auto[0]

auto[0]

66

1

T166

2

T167

1

T246

2

all_values[2]

auto[0]

auto[0]

auto[1]

28

1

T168

1

T346

2

T347

1

all_values[2]

auto[0]

auto[1]

auto[0]

44

1

T166

1

T167

3

T168

1

all_values[2]

auto[0]

auto[1]

auto[1]

16

1

T166

1

T342

1

T256

1

all_values[2]

auto[1]

auto[0]

auto[1]

68

1

T166

2

T168

2

T246

3

all_values[2]

auto[1]

auto[1]

auto[1]

41

1

T166

1

T168

3

T246

1

all_values[3]

auto[0]

auto[0]

auto[0]

60

1

T166

2

T168

1

T246

1

all_values[3]

auto[0]

auto[0]

auto[1]

23

1

T166

1

T168

2

T344

1

all_values[3]

auto[0]

auto[1]

auto[0]

42

1

T166

2

T167

3

T246

3

all_values[3]

auto[0]

auto[1]

auto[1]

27

1

T168

1

T246

1

T342

3

all_values[3]

auto[1]

auto[0]

auto[1]

61

1

T166

2

T168

2

T345

1

all_values[3]

auto[1]

auto[1]

auto[1]

50

1

T167

1

T168

1

T246

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal