Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	89600	1			T2	326		T4	837		T8	935
accum_cnt_1000	221113	1			T2	284		T16	123		T4	1002
accum_cnt_100	26664	1			T1	25		T2	26		T16	120
accum_cnt_50	67575	1			T1	48		T2	14		T3	41
accum_cnt_10	190392	1			T1	43		T2	3		T3	29
accum_cnt_0	400722	1			T1	4		T2	1967		T3	14

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	260482	1			T1	30		T2	655		T3	21
class_index[0x1]	260482	1			T1	30		T2	655		T3	21
class_index[0x2]	260482	1			T1	30		T2	655		T3	21
class_index[0x3]	260482	1			T1	30		T2	655		T3	21

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	22508	1			T2	326		T14	181		T32	183
class_index[0x0]	accum_cnt_1000	57644	1			T2	284		T13	809		T14	154
class_index[0x0]	accum_cnt_100	6987	1			T2	26		T17	7		T72	4
class_index[0x0]	accum_cnt_50	16518	1			T2	14		T3	13		T16	12
class_index[0x0]	accum_cnt_10	54166	1			T1	29		T2	3		T3	5
class_index[0x0]	accum_cnt_0	91038	1			T1	1		T2	2		T3	3
class_index[0x1]	accum_cnt_2000	19553	1			T4	433		T8	162		T33	528
class_index[0x1]	accum_cnt_1000	53466	1			T16	123		T4	629		T21	5
class_index[0x1]	accum_cnt_100	7234	1			T1	9		T16	99		T4	35
class_index[0x1]	accum_cnt_50	16537	1			T1	15		T3	14		T16	96
class_index[0x1]	accum_cnt_10	57540	1			T1	5		T3	3		T16	45
class_index[0x1]	accum_cnt_0	97171	1			T1	1		T2	655		T3	4
class_index[0x2]	accum_cnt_2000	26033	1			T4	404		T8	773		T14	553
class_index[0x2]	accum_cnt_1000	49896	1			T4	373		T21	12		T5	1300
class_index[0x2]	accum_cnt_100	5714	1			T1	4		T4	20		T21	16
class_index[0x2]	accum_cnt_50	19098	1			T1	20		T3	14		T4	13
class_index[0x2]	accum_cnt_10	38093	1			T1	5		T3	4		T16	157
class_index[0x2]	accum_cnt_0	102791	1			T1	1		T2	655		T3	3
class_index[0x3]	accum_cnt_2000	21506	1			T79	258		T34	196		T87	35
class_index[0x3]	accum_cnt_1000	60107	1			T6	807		T27	16		T8	765
class_index[0x3]	accum_cnt_100	6729	1			T1	12		T16	21		T6	92
class_index[0x3]	accum_cnt_50	15422	1			T1	13		T16	17		T6	65
class_index[0x3]	accum_cnt_10	40593	1			T1	4		T3	17		T16	147
class_index[0x3]	accum_cnt_0	109722	1			T1	1		T2	655		T3	4