Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	5379	1			T90	2420		T82	96		T302	1
alert[0x1]	8640	1			T7	1		T14	22		T89	1
alert[0x2]	5486	1			T8	115		T9	1		T14	48
alert[0x3]	5505	1			T7	1		T9	1		T14	355
alert[0x4]	7747	1			T14	181		T55	1		T78	817
alert[0x5]	6172	1			T7	1		T9	1		T14	48
alert[0x6]	5696	1			T9	1		T14	420		T32	111
alert[0x7]	5449	1			T27	11		T14	73		T90	179
alert[0x8]	7417	1			T8	103		T7	1		T28	6
alert[0x9]	7452	1			T7	1		T9	1		T14	67
alert[0xa]	5739	1			T7	1		T14	99		T32	134
alert[0xb]	13578	1			T2	26		T90	96		T35	24
alert[0xc]	7212	1			T15	1		T32	49		T89	1
alert[0xd]	2947	1			T9	1		T15	1		T82	9
alert[0xe]	1827	1			T90	8		T30	9		T35	6
alert[0xf]	2513	1			T8	20		T14	20		T15	1
alert[0x10]	6854	1			T8	326		T90	742		T82	75
alert[0x11]	9123	1			T14	292		T15	1		T32	3
alert[0x12]	3450	1			T2	6		T32	31		T90	23
alert[0x13]	3549	1			T8	210		T7	1		T32	7
alert[0x14]	5612	1			T7	1		T9	1		T14	1325
alert[0x15]	2787	1			T71	1		T32	26		T82	5
alert[0x16]	9769	1			T9	1		T14	84		T89	1
alert[0x17]	13290	1			T14	486		T90	30		T78	56
alert[0x18]	2466	1			T2	38		T14	8		T90	252
alert[0x19]	1814	1			T27	3		T8	7		T14	28
alert[0x1a]	14217	1			T7	1		T14	712		T32	10
alert[0x1b]	3183	1			T2	344		T7	1		T28	1
alert[0x1c]	4344	1			T89	1		T82	99		T248	1
alert[0x1d]	2404	1			T32	249		T84	15		T87	49
alert[0x1e]	3749	1			T71	7		T32	21		T30	6
alert[0x1f]	2719	1			T5	1		T8	20		T13	1
alert[0x20]	4312	1			T2	112		T8	472		T7	1
alert[0x21]	3816	1			T9	1		T32	4		T90	560
alert[0x22]	2911	1			T32	778		T90	28		T82	89
alert[0x23]	1887	1			T2	239		T8	60		T89	1
alert[0x24]	4737	1			T8	171		T7	1		T32	5
alert[0x25]	6468	1			T2	4		T15	1		T32	40
alert[0x26]	2276	1			T55	1		T89	1		T37	1
alert[0x27]	10041	1			T27	3		T8	7		T9	1
alert[0x28]	8689	1			T8	4		T32	82		T90	419
alert[0x29]	3393	1			T15	1		T32	22		T90	17
alert[0x2a]	2891	1			T6	1		T14	20		T32	137
alert[0x2b]	10910	1			T82	76		T84	16		T303	46
alert[0x2c]	7410	1			T82	34		T30	19		T248	1
alert[0x2d]	2541	1			T71	1		T90	815		T78	55
alert[0x2e]	5057	1			T7	1		T14	58		T32	36
alert[0x2f]	5551	1			T15	1		T82	5		T38	1
alert[0x30]	11158	1			T55	2		T78	2		T302	1
alert[0x31]	5262	1			T9	1		T14	26		T32	329
alert[0x32]	4617	1			T8	113		T71	63		T14	44
alert[0x33]	11585	1			T9	1		T32	762		T76	7
alert[0x34]	7287	1			T2	99		T14	85		T90	36
alert[0x35]	6874	1			T7	1		T9	1		T55	2
alert[0x36]	12275	1			T2	114		T9	1		T14	221
alert[0x37]	4149	1			T15	1		T32	45		T30	11
alert[0x38]	4029	1			T8	1		T14	246		T82	1110
alert[0x39]	6287	1			T8	43		T71	1		T7	1
alert[0x3a]	2644	1			T27	3		T9	1		T14	100
alert[0x3b]	10471	1			T2	611		T9	1		T14	78
alert[0x3c]	4438	1			T32	21		T82	13		T30	24
alert[0x3d]	4112	1			T71	1		T7	1		T14	1205
alert[0x3e]	7132	1			T71	1		T14	55		T32	5
alert[0x3f]	7590	1			T2	3		T14	28		T82	7
alert[0x40]	8218	1			T71	2		T30	11		T78	454

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	103120	1			T2	1596		T6	1		T8	24
class_i[0x1]	123584	1			T5	1		T27	3		T7	1
class_i[0x2]	99187	1			T27	17		T8	1623		T71	77
class_i[0x3]	63216	1			T8	25		T7	3		T28	6

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

388447

1

T2

1596

T27

20

T8

1672

alert_ping_fail

660

1

T5

1

T6

1

T7

16

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	5365	1			T90	2420		T82	96		T303	239
alert_integrity_fail	alert[0x1]	8622	1			T14	22		T90	9		T82	2709
alert_integrity_fail	alert[0x2]	5478	1			T8	115		T14	48		T35	58
alert_integrity_fail	alert[0x3]	5495	1			T14	355		T32	7		T84	37
alert_integrity_fail	alert[0x4]	7741	1			T14	181		T55	1		T78	817
alert_integrity_fail	alert[0x5]	6149	1			T14	48		T90	11		T84	13
alert_integrity_fail	alert[0x6]	5678	1			T14	420		T32	111		T90	55
alert_integrity_fail	alert[0x7]	5436	1			T27	11		T14	73		T90	179
alert_integrity_fail	alert[0x8]	7412	1			T8	103		T28	6		T32	55
alert_integrity_fail	alert[0x9]	7444	1			T14	67		T32	1162		T82	163
alert_integrity_fail	alert[0xa]	5735	1			T14	99		T32	134		T90	2
alert_integrity_fail	alert[0xb]	13570	1			T2	26		T90	96		T35	24
alert_integrity_fail	alert[0xc]	7202	1			T32	49		T30	91		T78	176
alert_integrity_fail	alert[0xd]	2934	1			T82	9		T78	592		T35	250
alert_integrity_fail	alert[0xe]	1817	1			T90	8		T30	9		T35	6
alert_integrity_fail	alert[0xf]	2505	1			T8	20		T14	20		T82	43
alert_integrity_fail	alert[0x10]	6849	1			T8	326		T90	742		T82	75
alert_integrity_fail	alert[0x11]	9109	1			T14	292		T32	3		T87	79
alert_integrity_fail	alert[0x12]	3439	1			T2	6		T32	31		T90	23
alert_integrity_fail	alert[0x13]	3535	1			T8	210		T32	7		T90	74
alert_integrity_fail	alert[0x14]	5598	1			T14	1325		T32	250		T82	251
alert_integrity_fail	alert[0x15]	2772	1			T71	1		T32	26		T82	5
alert_integrity_fail	alert[0x16]	9760	1			T14	84		T75	1		T78	77
alert_integrity_fail	alert[0x17]	13280	1			T14	486		T90	30		T78	56
alert_integrity_fail	alert[0x18]	2456	1			T2	38		T14	8		T90	252
alert_integrity_fail	alert[0x19]	1806	1			T27	3		T8	7		T14	28
alert_integrity_fail	alert[0x1a]	14210	1			T14	712		T32	10		T78	44
alert_integrity_fail	alert[0x1b]	3171	1			T2	344		T28	1		T75	1
alert_integrity_fail	alert[0x1c]	4337	1			T82	99		T38	3		T35	35
alert_integrity_fail	alert[0x1d]	2394	1			T32	249		T84	15		T87	49
alert_integrity_fail	alert[0x1e]	3740	1			T71	7		T32	21		T30	6
alert_integrity_fail	alert[0x1f]	2705	1			T8	20		T32	80		T90	8
alert_integrity_fail	alert[0x20]	4303	1			T2	112		T8	472		T28	2
alert_integrity_fail	alert[0x21]	3805	1			T32	4		T90	560		T82	231
alert_integrity_fail	alert[0x22]	2892	1			T32	778		T90	28		T82	89
alert_integrity_fail	alert[0x23]	1882	1			T2	239		T8	60		T82	75
alert_integrity_fail	alert[0x24]	4728	1			T8	171		T32	5		T80	2
alert_integrity_fail	alert[0x25]	6456	1			T2	4		T32	40		T35	20
alert_integrity_fail	alert[0x26]	2265	1			T55	1		T37	1		T35	42
alert_integrity_fail	alert[0x27]	10035	1			T27	3		T8	7		T14	464
alert_integrity_fail	alert[0x28]	8676	1			T8	4		T32	82		T90	419
alert_integrity_fail	alert[0x29]	3387	1			T32	22		T90	17		T82	103
alert_integrity_fail	alert[0x2a]	2884	1			T14	20		T32	137		T82	19
alert_integrity_fail	alert[0x2b]	10904	1			T82	76		T84	16		T303	46
alert_integrity_fail	alert[0x2c]	7398	1			T82	34		T30	19		T304	2
alert_integrity_fail	alert[0x2d]	2530	1			T71	1		T90	815		T78	55
alert_integrity_fail	alert[0x2e]	5046	1			T14	58		T32	36		T75	1
alert_integrity_fail	alert[0x2f]	5540	1			T82	5		T38	1		T87	139
alert_integrity_fail	alert[0x30]	11151	1			T55	2		T78	2		T85	1
alert_integrity_fail	alert[0x31]	5254	1			T14	26		T32	329		T90	29
alert_integrity_fail	alert[0x32]	4609	1			T8	113		T71	63		T14	44
alert_integrity_fail	alert[0x33]	11576	1			T32	762		T76	7		T82	141
alert_integrity_fail	alert[0x34]	7274	1			T2	99		T14	85		T90	36
alert_integrity_fail	alert[0x35]	6862	1			T55	2		T82	37		T78	155
alert_integrity_fail	alert[0x36]	12264	1			T2	114		T14	221		T82	130
alert_integrity_fail	alert[0x37]	4142	1			T32	45		T30	11		T78	27
alert_integrity_fail	alert[0x38]	4025	1			T8	1		T14	246		T82	1110
alert_integrity_fail	alert[0x39]	6278	1			T8	43		T71	1		T14	85
alert_integrity_fail	alert[0x3a]	2630	1			T27	3		T14	100		T32	135
alert_integrity_fail	alert[0x3b]	10460	1			T2	611		T14	78		T32	88
alert_integrity_fail	alert[0x3c]	4427	1			T32	21		T82	13		T30	24
alert_integrity_fail	alert[0x3d]	4101	1			T71	1		T14	1205		T90	63
alert_integrity_fail	alert[0x3e]	7121	1			T71	1		T14	55		T32	5
alert_integrity_fail	alert[0x3f]	7585	1			T2	3		T14	28		T82	7
alert_integrity_fail	alert[0x40]	8213	1			T71	2		T30	11		T78	454
alert_ping_fail	alert[0x0]	14	1			T302	1		T305	1		T306	1
alert_ping_fail	alert[0x1]	18	1			T7	1		T89	1		T302	3
alert_ping_fail	alert[0x2]	8	1			T9	1		T306	1		T307	1
alert_ping_fail	alert[0x3]	10	1			T7	1		T9	1		T15	1
alert_ping_fail	alert[0x4]	6	1			T248	1		T40	1		T308	1
alert_ping_fail	alert[0x5]	23	1			T7	1		T9	1		T15	1
alert_ping_fail	alert[0x6]	18	1			T9	1		T89	1		T106	1
alert_ping_fail	alert[0x7]	13	1			T248	1		T307	2		T309	1
alert_ping_fail	alert[0x8]	5	1			T7	1		T106	1		T310	1
alert_ping_fail	alert[0x9]	8	1			T7	1		T9	1		T311	1
alert_ping_fail	alert[0xa]	4	1			T7	1		T312	1		T313	1
alert_ping_fail	alert[0xb]	8	1			T40	1		T305	1		T245	1
alert_ping_fail	alert[0xc]	10	1			T15	1		T89	1		T306	1
alert_ping_fail	alert[0xd]	13	1			T9	1		T15	1		T251	1
alert_ping_fail	alert[0xe]	10	1			T306	1		T230	1		T194	1
alert_ping_fail	alert[0xf]	8	1			T15	1		T307	1		T314	1
alert_ping_fail	alert[0x10]	5	1			T307	1		T231	1		T309	1
alert_ping_fail	alert[0x11]	14	1			T15	1		T245	1		T315	1
alert_ping_fail	alert[0x12]	11	1			T302	1		T310	1		T315	2
alert_ping_fail	alert[0x13]	14	1			T7	1		T40	1		T310	1
alert_ping_fail	alert[0x14]	14	1			T7	1		T9	1		T106	3
alert_ping_fail	alert[0x15]	15	1			T248	1		T40	1		T315	1
alert_ping_fail	alert[0x16]	9	1			T9	1		T89	1		T248	1
alert_ping_fail	alert[0x17]	10	1			T248	1		T302	1		T316	1
alert_ping_fail	alert[0x18]	10	1			T305	1		T245	2		T315	1
alert_ping_fail	alert[0x19]	8	1			T251	1		T40	1		T311	1
alert_ping_fail	alert[0x1a]	7	1			T7	1		T305	1		T316	1
alert_ping_fail	alert[0x1b]	12	1			T7	1		T15	1		T89	1
alert_ping_fail	alert[0x1c]	7	1			T89	1		T248	1		T40	1
alert_ping_fail	alert[0x1d]	10	1			T92	1		T306	1		T314	1
alert_ping_fail	alert[0x1e]	9	1			T251	1		T315	2		T317	1
alert_ping_fail	alert[0x1f]	14	1			T5	1		T13	1		T9	1
alert_ping_fail	alert[0x20]	9	1			T7	1		T248	1		T305	1
alert_ping_fail	alert[0x21]	11	1			T9	1		T310	1		T315	1
alert_ping_fail	alert[0x22]	19	1			T302	2		T245	1		T300	1
alert_ping_fail	alert[0x23]	5	1			T89	1		T318	1		T319	1
alert_ping_fail	alert[0x24]	9	1			T7	1		T316	1		T311	1
alert_ping_fail	alert[0x25]	12	1			T15	1		T89	1		T251	1
alert_ping_fail	alert[0x26]	11	1			T89	1		T251	1		T302	1
alert_ping_fail	alert[0x27]	6	1			T9	1		T15	1		T310	1
alert_ping_fail	alert[0x28]	13	1			T248	1		T320	1		T305	1
alert_ping_fail	alert[0x29]	6	1			T15	1		T316	1		T231	2
alert_ping_fail	alert[0x2a]	7	1			T6	1		T251	1		T302	1
alert_ping_fail	alert[0x2b]	6	1			T239	1		T301	2		T307	1
alert_ping_fail	alert[0x2c]	12	1			T248	1		T40	1		T305	1
alert_ping_fail	alert[0x2d]	11	1			T40	1		T46	2		T321	1
alert_ping_fail	alert[0x2e]	11	1			T7	1		T302	1		T315	2
alert_ping_fail	alert[0x2f]	11	1			T15	1		T40	1		T322	1
alert_ping_fail	alert[0x30]	7	1			T302	1		T320	1		T315	1
alert_ping_fail	alert[0x31]	8	1			T9	1		T89	3		T320	1
alert_ping_fail	alert[0x32]	8	1			T248	2		T40	1		T311	1
alert_ping_fail	alert[0x33]	9	1			T9	1		T305	1		T245	2
alert_ping_fail	alert[0x34]	13	1			T248	1		T302	1		T40	2
alert_ping_fail	alert[0x35]	12	1			T7	1		T9	1		T248	1
alert_ping_fail	alert[0x36]	11	1			T9	1		T89	1		T302	1
alert_ping_fail	alert[0x37]	7	1			T15	1		T306	1		T231	1
alert_ping_fail	alert[0x38]	4	1			T313	1		T323	1		T319	1
alert_ping_fail	alert[0x39]	9	1			T7	1		T40	1		T316	1
alert_ping_fail	alert[0x3a]	14	1			T9	1		T89	1		T251	1
alert_ping_fail	alert[0x3b]	11	1			T9	1		T248	1		T251	1
alert_ping_fail	alert[0x3c]	11	1			T248	1		T245	3		T92	1
alert_ping_fail	alert[0x3d]	11	1			T7	1		T302	1		T314	1
alert_ping_fail	alert[0x3e]	11	1			T89	1		T248	1		T251	1
alert_ping_fail	alert[0x3f]	5	1			T320	1		T309	1		T324	1
alert_ping_fail	alert[0x40]	5	1			T231	1		T325	1		T309	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	102941	1			T2	1596		T8	24		T28	1
alert_integrity_fail	class_i[0x1]	123360	1			T27	3		T75	17		T90	7685
alert_integrity_fail	class_i[0x2]	99016	1			T27	17		T8	1623		T71	77
alert_integrity_fail	class_i[0x3]	63130	1			T8	25		T28	6		T76	7
alert_ping_fail	class_i[0x0]	179	1			T6	1		T7	2		T320	6
alert_ping_fail	class_i[0x1]	224	1			T5	1		T7	1		T13	1
alert_ping_fail	class_i[0x2]	171	1			T7	10		T89	1		T302	1
alert_ping_fail	class_i[0x3]	86	1			T7	3		T9	17		T106	5