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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.69 99.99 98.77 100.00 100.00 100.00 99.38 99.68


Total test records in report: 831
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T771 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2850194526 Jun 21 05:14:21 PM PDT 24 Jun 21 05:14:25 PM PDT 24 9656438 ps
T179 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3956673179 Jun 21 05:14:38 PM PDT 24 Jun 21 05:15:24 PM PDT 24 1277081791 ps
T772 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2594123152 Jun 21 05:14:38 PM PDT 24 Jun 21 05:14:42 PM PDT 24 15279668 ps
T773 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3350856472 Jun 21 05:14:45 PM PDT 24 Jun 21 05:14:50 PM PDT 24 6355734 ps
T153 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2227176021 Jun 21 05:14:23 PM PDT 24 Jun 21 05:29:15 PM PDT 24 12334499008 ps
T774 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2114700118 Jun 21 05:14:40 PM PDT 24 Jun 21 05:15:03 PM PDT 24 314588964 ps
T775 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2224932631 Jun 21 05:14:41 PM PDT 24 Jun 21 05:14:55 PM PDT 24 286043511 ps
T173 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2486945922 Jun 21 05:14:50 PM PDT 24 Jun 21 05:15:35 PM PDT 24 1245248347 ps
T169 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4180006742 Jun 21 05:14:22 PM PDT 24 Jun 21 05:14:28 PM PDT 24 157150659 ps
T776 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.486419171 Jun 21 05:14:20 PM PDT 24 Jun 21 05:16:18 PM PDT 24 2001715026 ps
T777 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1376365035 Jun 21 05:14:36 PM PDT 24 Jun 21 05:14:45 PM PDT 24 110522097 ps
T778 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2199166957 Jun 21 05:14:30 PM PDT 24 Jun 21 05:14:44 PM PDT 24 179941099 ps
T779 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3352499778 Jun 21 05:14:49 PM PDT 24 Jun 21 05:14:55 PM PDT 24 7347326 ps
T146 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2990221145 Jun 21 05:14:21 PM PDT 24 Jun 21 05:30:18 PM PDT 24 12709964317 ps
T780 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2910013337 Jun 21 05:14:29 PM PDT 24 Jun 21 05:14:41 PM PDT 24 471885593 ps
T781 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3993392188 Jun 21 05:14:24 PM PDT 24 Jun 21 05:15:05 PM PDT 24 541707271 ps
T782 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1531359835 Jun 21 05:14:20 PM PDT 24 Jun 21 05:14:24 PM PDT 24 8506391 ps
T152 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3159262905 Jun 21 05:14:21 PM PDT 24 Jun 21 05:17:17 PM PDT 24 5044263809 ps
T154 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.4080617639 Jun 21 05:14:38 PM PDT 24 Jun 21 05:17:40 PM PDT 24 8710610508 ps
T783 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3391361784 Jun 21 05:14:39 PM PDT 24 Jun 21 05:14:59 PM PDT 24 321821649 ps
T184 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3957779911 Jun 21 05:14:21 PM PDT 24 Jun 21 05:15:01 PM PDT 24 2031782761 ps
T784 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1395368798 Jun 21 05:14:29 PM PDT 24 Jun 21 05:14:32 PM PDT 24 11025789 ps
T785 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2372814402 Jun 21 05:14:21 PM PDT 24 Jun 21 05:14:36 PM PDT 24 184357869 ps
T786 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2188967109 Jun 21 05:14:47 PM PDT 24 Jun 21 05:14:53 PM PDT 24 6055517 ps
T787 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2626514703 Jun 21 05:14:44 PM PDT 24 Jun 21 05:14:49 PM PDT 24 21315988 ps
T788 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2712805053 Jun 21 05:14:19 PM PDT 24 Jun 21 05:17:37 PM PDT 24 4456259988 ps
T789 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3350961071 Jun 21 05:14:24 PM PDT 24 Jun 21 05:14:36 PM PDT 24 269555527 ps
T790 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.454763989 Jun 21 05:14:37 PM PDT 24 Jun 21 05:14:44 PM PDT 24 502320557 ps
T791 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3194175424 Jun 21 05:14:36 PM PDT 24 Jun 21 05:14:46 PM PDT 24 126969612 ps
T792 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2841247597 Jun 21 05:14:51 PM PDT 24 Jun 21 05:14:58 PM PDT 24 9021066 ps
T793 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.609657868 Jun 21 05:14:47 PM PDT 24 Jun 21 05:14:52 PM PDT 24 30763303 ps
T794 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3183117807 Jun 21 05:14:46 PM PDT 24 Jun 21 05:14:51 PM PDT 24 6657263 ps
T795 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1446978626 Jun 21 05:14:30 PM PDT 24 Jun 21 05:14:33 PM PDT 24 8214483 ps
T150 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2345371966 Jun 21 05:14:43 PM PDT 24 Jun 21 05:19:49 PM PDT 24 7921893212 ps
T796 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.441874114 Jun 21 05:14:30 PM PDT 24 Jun 21 05:14:39 PM PDT 24 195341230 ps
T797 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3269666434 Jun 21 05:14:49 PM PDT 24 Jun 21 05:14:59 PM PDT 24 273581796 ps
T798 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3277539853 Jun 21 05:14:40 PM PDT 24 Jun 21 05:15:00 PM PDT 24 1054144476 ps
T799 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.571904504 Jun 21 05:14:49 PM PDT 24 Jun 21 05:14:55 PM PDT 24 6688501 ps
T800 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.856338090 Jun 21 05:14:36 PM PDT 24 Jun 21 05:14:52 PM PDT 24 740596219 ps
T801 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3570454483 Jun 21 05:14:46 PM PDT 24 Jun 21 05:14:52 PM PDT 24 9190092 ps
T143 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.4065575068 Jun 21 05:14:23 PM PDT 24 Jun 21 05:25:05 PM PDT 24 37130900963 ps
T802 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2337258795 Jun 21 05:14:25 PM PDT 24 Jun 21 05:17:57 PM PDT 24 3271300823 ps
T172 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.4269044057 Jun 21 05:14:24 PM PDT 24 Jun 21 05:14:31 PM PDT 24 130571865 ps
T803 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3156261295 Jun 21 05:14:44 PM PDT 24 Jun 21 05:14:49 PM PDT 24 8573646 ps
T804 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2749608005 Jun 21 05:14:22 PM PDT 24 Jun 21 05:15:05 PM PDT 24 672700832 ps
T805 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3793558925 Jun 21 05:14:21 PM PDT 24 Jun 21 05:14:28 PM PDT 24 85350803 ps
T148 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2831893360 Jun 21 05:14:42 PM PDT 24 Jun 21 05:18:08 PM PDT 24 1691395214 ps
T806 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2409054316 Jun 21 05:14:22 PM PDT 24 Jun 21 05:14:31 PM PDT 24 40816959 ps
T807 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3141917250 Jun 21 05:14:43 PM PDT 24 Jun 21 05:14:48 PM PDT 24 9062550 ps
T156 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1103365121 Jun 21 05:14:20 PM PDT 24 Jun 21 05:30:24 PM PDT 24 109292367444 ps
T808 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1936763244 Jun 21 05:14:35 PM PDT 24 Jun 21 05:14:38 PM PDT 24 11126031 ps
T809 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2848301711 Jun 21 05:14:24 PM PDT 24 Jun 21 05:14:35 PM PDT 24 1244769019 ps
T810 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.985422124 Jun 21 05:14:39 PM PDT 24 Jun 21 05:15:20 PM PDT 24 523973043 ps
T811 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3509854777 Jun 21 05:14:23 PM PDT 24 Jun 21 05:21:07 PM PDT 24 22837583653 ps
T812 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1410794164 Jun 21 05:14:20 PM PDT 24 Jun 21 05:14:24 PM PDT 24 8741220 ps
T813 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1108997974 Jun 21 05:14:41 PM PDT 24 Jun 21 05:14:58 PM PDT 24 734681224 ps
T151 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3645092882 Jun 21 05:14:36 PM PDT 24 Jun 21 05:17:04 PM PDT 24 4460283797 ps
T147 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.696629301 Jun 21 05:14:37 PM PDT 24 Jun 21 05:24:04 PM PDT 24 47973368857 ps
T814 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2518657439 Jun 21 05:14:23 PM PDT 24 Jun 21 05:14:30 PM PDT 24 20346712 ps
T815 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1196628691 Jun 21 05:14:29 PM PDT 24 Jun 21 05:14:35 PM PDT 24 63646045 ps
T816 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.476634966 Jun 21 05:14:50 PM PDT 24 Jun 21 05:14:56 PM PDT 24 6679267 ps
T817 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1494442737 Jun 21 05:14:25 PM PDT 24 Jun 21 05:18:44 PM PDT 24 4276724026 ps
T818 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1961588944 Jun 21 05:14:49 PM PDT 24 Jun 21 05:15:06 PM PDT 24 585632750 ps
T819 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2042507469 Jun 21 05:14:46 PM PDT 24 Jun 21 05:14:52 PM PDT 24 7488678 ps
T820 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.4223583522 Jun 21 05:14:23 PM PDT 24 Jun 21 05:14:38 PM PDT 24 150517786 ps
T821 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2673680422 Jun 21 05:14:40 PM PDT 24 Jun 21 05:14:47 PM PDT 24 30509756 ps
T159 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.431808117 Jun 21 05:14:22 PM PDT 24 Jun 21 05:17:17 PM PDT 24 4644514856 ps
T822 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.483748854 Jun 21 05:14:42 PM PDT 24 Jun 21 05:14:56 PM PDT 24 722456383 ps
T823 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.746339203 Jun 21 05:14:32 PM PDT 24 Jun 21 05:14:37 PM PDT 24 154988457 ps
T824 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1751744388 Jun 21 05:14:26 PM PDT 24 Jun 21 05:14:35 PM PDT 24 78262024 ps
T825 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2895031137 Jun 21 05:14:41 PM PDT 24 Jun 21 05:14:44 PM PDT 24 17448810 ps
T826 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1415685548 Jun 21 05:14:38 PM PDT 24 Jun 21 05:14:47 PM PDT 24 92815069 ps
T827 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3604046462 Jun 21 05:14:29 PM PDT 24 Jun 21 05:14:34 PM PDT 24 57612867 ps
T160 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3704987972 Jun 21 05:14:38 PM PDT 24 Jun 21 05:35:56 PM PDT 24 17145571182 ps
T828 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3512552291 Jun 21 05:14:20 PM PDT 24 Jun 21 05:14:43 PM PDT 24 307474090 ps
T829 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3062018986 Jun 21 05:14:26 PM PDT 24 Jun 21 05:14:34 PM PDT 24 1434451439 ps
T830 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3241855192 Jun 21 05:14:20 PM PDT 24 Jun 21 05:14:36 PM PDT 24 358105829 ps
T158 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.4154504748 Jun 21 05:14:43 PM PDT 24 Jun 21 05:19:39 PM PDT 24 16522291431 ps
T161 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.159052676 Jun 21 05:14:46 PM PDT 24 Jun 21 05:20:00 PM PDT 24 21189229142 ps
T162 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3257717547 Jun 21 05:14:39 PM PDT 24 Jun 21 05:17:18 PM PDT 24 13835054935 ps
T831 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1073750015 Jun 21 05:14:40 PM PDT 24 Jun 21 05:14:47 PM PDT 24 215277711 ps

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.1775689071
Short name T16
Test name
Test status
Simulation time 48590277598 ps
CPU time 1744.36 seconds
Started Jun 21 05:15:56 PM PDT 24
Finished Jun 21 05:45:02 PM PDT 24
Peak memory 284776 kb
Host smart-a2f49362-70cb-4769-a76a-1b6ddf8ab0f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775689071 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.1775689071
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1773827394
Short name T8
Test name
Test status
Simulation time 915192336539 ps
CPU time 7185.22 seconds
Started Jun 21 05:16:19 PM PDT 24
Finished Jun 21 07:16:07 PM PDT 24
Peak memory 322472 kb
Host smart-d4000a81-087a-419d-abf9-3e3402f536a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773827394 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1773827394
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3487554543
Short name T11
Test name
Test status
Simulation time 1354535180 ps
CPU time 55.76 seconds
Started Jun 21 05:14:51 PM PDT 24
Finished Jun 21 05:15:52 PM PDT 24
Peak memory 269744 kb
Host smart-b2e364d2-fe6f-475a-ab55-1b26ab89677b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3487554543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3487554543
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1675589966
Short name T32
Test name
Test status
Simulation time 115701468501 ps
CPU time 1926.11 seconds
Started Jun 21 05:14:53 PM PDT 24
Finished Jun 21 05:47:04 PM PDT 24
Peak memory 287296 kb
Host smart-01bf21b3-c536-4b59-a7c1-1058993ed8bf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675589966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1675589966
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.248117241
Short name T163
Test name
Test status
Simulation time 2163162257 ps
CPU time 36.92 seconds
Started Jun 21 05:14:25 PM PDT 24
Finished Jun 21 05:15:04 PM PDT 24
Peak memory 240700 kb
Host smart-d4e273bb-104e-4e68-91ec-39e0ad62ed61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=248117241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.248117241
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.3217829064
Short name T39
Test name
Test status
Simulation time 61310617866 ps
CPU time 2942.93 seconds
Started Jun 21 05:15:30 PM PDT 24
Finished Jun 21 06:04:34 PM PDT 24
Peak memory 299408 kb
Host smart-cf2df10a-ac1c-4f34-a14f-bc2f05da1a4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217829064 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.3217829064
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.671082047
Short name T38
Test name
Test status
Simulation time 259197104213 ps
CPU time 3323.93 seconds
Started Jun 21 05:15:18 PM PDT 24
Finished Jun 21 06:10:44 PM PDT 24
Peak memory 290068 kb
Host smart-3716d12d-663e-4c26-98c2-f02ddf45dabc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671082047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.671082047
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3682760573
Short name T107
Test name
Test status
Simulation time 707477991777 ps
CPU time 2685.29 seconds
Started Jun 21 05:15:18 PM PDT 24
Finished Jun 21 06:00:05 PM PDT 24
Peak memory 281832 kb
Host smart-ccad640c-ef8a-4d52-87d7-7e613f15dcc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682760573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3682760573
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2786144886
Short name T131
Test name
Test status
Simulation time 3195922762 ps
CPU time 189.44 seconds
Started Jun 21 05:14:21 PM PDT 24
Finished Jun 21 05:17:33 PM PDT 24
Peak memory 266664 kb
Host smart-814eed1b-ba12-4965-824b-0a8e9e577075
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2786144886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.2786144886
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.977608837
Short name T99
Test name
Test status
Simulation time 671966506692 ps
CPU time 2554.1 seconds
Started Jun 21 05:16:04 PM PDT 24
Finished Jun 21 05:58:40 PM PDT 24
Peak memory 288980 kb
Host smart-0b4960a1-25b5-4f61-be7f-00d55b076ab7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977608837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.977608837
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3243407209
Short name T98
Test name
Test status
Simulation time 188542563420 ps
CPU time 4331.42 seconds
Started Jun 21 05:16:16 PM PDT 24
Finished Jun 21 06:28:28 PM PDT 24
Peak memory 321636 kb
Host smart-ae48cfd5-a1d1-4029-9c06-6d231af953ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243407209 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3243407209
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3403248251
Short name T124
Test name
Test status
Simulation time 121287255332 ps
CPU time 1136.18 seconds
Started Jun 21 05:14:21 PM PDT 24
Finished Jun 21 05:33:19 PM PDT 24
Peak memory 273216 kb
Host smart-f581f7de-a578-4b19-a69d-96ae75b6a214
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403248251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3403248251
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.936843377
Short name T35
Test name
Test status
Simulation time 429476134275 ps
CPU time 5344.77 seconds
Started Jun 21 05:16:53 PM PDT 24
Finished Jun 21 06:45:59 PM PDT 24
Peak memory 348796 kb
Host smart-5c39dc2e-55e7-4950-acac-fec5e67f6e65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936843377 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.936843377
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3980321209
Short name T141
Test name
Test status
Simulation time 5682370022 ps
CPU time 177.06 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 05:17:44 PM PDT 24
Peak memory 269912 kb
Host smart-e04cfab6-2543-4cc1-a688-9902389c7ca1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3980321209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3980321209
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2869228709
Short name T103
Test name
Test status
Simulation time 135195341 ps
CPU time 15.72 seconds
Started Jun 21 05:15:24 PM PDT 24
Finished Jun 21 05:15:41 PM PDT 24
Peak memory 249056 kb
Host smart-b805f065-52b5-4556-b4a3-747a94cd1e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28692
28709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2869228709
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.3871946238
Short name T6
Test name
Test status
Simulation time 55119126155 ps
CPU time 1112.15 seconds
Started Jun 21 05:16:10 PM PDT 24
Finished Jun 21 05:34:44 PM PDT 24
Peak memory 273276 kb
Host smart-3706d316-71e1-468b-a0f7-2e273fc10eaf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871946238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3871946238
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.936089533
Short name T127
Test name
Test status
Simulation time 15208557766 ps
CPU time 1003.78 seconds
Started Jun 21 05:14:36 PM PDT 24
Finished Jun 21 05:31:21 PM PDT 24
Peak memory 273736 kb
Host smart-908e65c9-b6ed-4145-bd7e-e651ec0ce0e0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936089533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.936089533
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3925576636
Short name T40
Test name
Test status
Simulation time 12531947466 ps
CPU time 498.48 seconds
Started Jun 21 05:17:33 PM PDT 24
Finished Jun 21 05:25:52 PM PDT 24
Peak memory 248528 kb
Host smart-12b52992-49dd-4000-93b5-f35ce3581630
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925576636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3925576636
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.4137261260
Short name T168
Test name
Test status
Simulation time 28538804 ps
CPU time 1.31 seconds
Started Jun 21 05:14:26 PM PDT 24
Finished Jun 21 05:14:29 PM PDT 24
Peak memory 237312 kb
Host smart-7b02ee26-5ed8-45a7-95ff-69b13709cd5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4137261260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.4137261260
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2244656658
Short name T303
Test name
Test status
Simulation time 132875541924 ps
CPU time 1886.37 seconds
Started Jun 21 05:15:42 PM PDT 24
Finished Jun 21 05:47:10 PM PDT 24
Peak memory 283400 kb
Host smart-b468d8c7-e661-4e10-ab25-2ee2fd93cbda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244656658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2244656658
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2697747943
Short name T145
Test name
Test status
Simulation time 29468806665 ps
CPU time 1075.57 seconds
Started Jun 21 05:14:27 PM PDT 24
Finished Jun 21 05:32:24 PM PDT 24
Peak memory 265620 kb
Host smart-0bdbcbdc-3d69-4cad-981e-b5b81ac395df
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697747943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2697747943
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3637737773
Short name T322
Test name
Test status
Simulation time 155283008562 ps
CPU time 2370.3 seconds
Started Jun 21 05:15:48 PM PDT 24
Finished Jun 21 05:55:19 PM PDT 24
Peak memory 273164 kb
Host smart-b22756ab-4e32-4fc6-aea0-14473958f3de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637737773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3637737773
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.554504899
Short name T7
Test name
Test status
Simulation time 101989616131 ps
CPU time 394.29 seconds
Started Jun 21 05:15:58 PM PDT 24
Finished Jun 21 05:22:33 PM PDT 24
Peak memory 248744 kb
Host smart-9f96d9e4-1632-4e80-b3db-58669bb8a3a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554504899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.554504899
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1103365121
Short name T156
Test name
Test status
Simulation time 109292367444 ps
CPU time 962.29 seconds
Started Jun 21 05:14:20 PM PDT 24
Finished Jun 21 05:30:24 PM PDT 24
Peak memory 265672 kb
Host smart-bfd284b3-35d1-4060-a54f-1e07988ff29e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103365121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1103365121
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2227176021
Short name T153
Test name
Test status
Simulation time 12334499008 ps
CPU time 889.23 seconds
Started Jun 21 05:14:23 PM PDT 24
Finished Jun 21 05:29:15 PM PDT 24
Peak memory 265600 kb
Host smart-37450ab8-de75-40aa-8d68-bb66812cdb84
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227176021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.2227176021
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.904856664
Short name T87
Test name
Test status
Simulation time 170256717700 ps
CPU time 2935.01 seconds
Started Jun 21 05:15:16 PM PDT 24
Finished Jun 21 06:04:13 PM PDT 24
Peak memory 288204 kb
Host smart-42e9755b-9b8c-4f3c-bae0-ef7ea15eb6a7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904856664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_han
dler_stress_all.904856664
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1024881352
Short name T508
Test name
Test status
Simulation time 20256354328 ps
CPU time 439.09 seconds
Started Jun 21 05:14:56 PM PDT 24
Finished Jun 21 05:22:19 PM PDT 24
Peak memory 256828 kb
Host smart-c35a4dd2-42e5-43ef-a164-bbbe66e59ee1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024881352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1024881352
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3510081989
Short name T132
Test name
Test status
Simulation time 5139380050 ps
CPU time 337.7 seconds
Started Jun 21 05:14:28 PM PDT 24
Finished Jun 21 05:20:07 PM PDT 24
Peak memory 265624 kb
Host smart-cadfe390-0bc3-47ca-829d-1821023b114c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3510081989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3510081989
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2633515556
Short name T327
Test name
Test status
Simulation time 33887705957 ps
CPU time 2164.73 seconds
Started Jun 21 05:16:05 PM PDT 24
Finished Jun 21 05:52:12 PM PDT 24
Peak memory 281740 kb
Host smart-1d5fd198-3875-40f7-995d-24861b8ef848
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633515556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2633515556
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1088905715
Short name T178
Test name
Test status
Simulation time 5671393489 ps
CPU time 86.07 seconds
Started Jun 21 05:14:35 PM PDT 24
Finished Jun 21 05:16:02 PM PDT 24
Peak memory 240820 kb
Host smart-efe1859b-8795-4573-bf3f-bb84e838e61b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1088905715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1088905715
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1475554595
Short name T9
Test name
Test status
Simulation time 84542315544 ps
CPU time 395.45 seconds
Started Jun 21 05:16:19 PM PDT 24
Finished Jun 21 05:22:57 PM PDT 24
Peak memory 255116 kb
Host smart-640f3cfc-6da7-4bec-8006-eeef9b0d0158
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475554595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1475554595
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.126819908
Short name T22
Test name
Test status
Simulation time 32640898 ps
CPU time 2.61 seconds
Started Jun 21 05:15:23 PM PDT 24
Finished Jun 21 05:15:27 PM PDT 24
Peak memory 249200 kb
Host smart-0f309451-9a1b-4883-a307-ff85e563ae67
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=126819908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.126819908
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.187042086
Short name T263
Test name
Test status
Simulation time 91506423040 ps
CPU time 2534.05 seconds
Started Jun 21 05:17:02 PM PDT 24
Finished Jun 21 05:59:17 PM PDT 24
Peak memory 289884 kb
Host smart-84ec9ef4-932e-494d-b1ca-60d68667b649
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187042086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.187042086
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3855989371
Short name T25
Test name
Test status
Simulation time 11770451934 ps
CPU time 1318.89 seconds
Started Jun 21 05:16:30 PM PDT 24
Finished Jun 21 05:38:30 PM PDT 24
Peak memory 290220 kb
Host smart-b17cc4fb-b927-489b-bb8a-109866f416c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855989371 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3855989371
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.630823335
Short name T330
Test name
Test status
Simulation time 45063777072 ps
CPU time 2616.71 seconds
Started Jun 21 05:16:08 PM PDT 24
Finished Jun 21 05:59:45 PM PDT 24
Peak memory 287716 kb
Host smart-e343d29c-d23a-499e-85d9-0e0f85441455
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630823335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.630823335
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.768991118
Short name T134
Test name
Test status
Simulation time 3556166795 ps
CPU time 136.13 seconds
Started Jun 21 05:14:25 PM PDT 24
Finished Jun 21 05:16:43 PM PDT 24
Peak memory 266592 kb
Host smart-2b44060d-19a7-40f8-aa11-a1c228ef8d96
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=768991118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.768991118
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.65459439
Short name T166
Test name
Test status
Simulation time 23160005 ps
CPU time 1.29 seconds
Started Jun 21 05:14:37 PM PDT 24
Finished Jun 21 05:14:40 PM PDT 24
Peak memory 236200 kb
Host smart-b933a7ac-9b10-4e52-9faa-2e722c4d8c66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=65459439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.65459439
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2139551492
Short name T301
Test name
Test status
Simulation time 43223924592 ps
CPU time 2309.5 seconds
Started Jun 21 05:16:46 PM PDT 24
Finished Jun 21 05:55:17 PM PDT 24
Peak memory 273640 kb
Host smart-04f8ef0b-765c-4530-b83c-b3966372911e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139551492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2139551492
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.729299177
Short name T324
Test name
Test status
Simulation time 24615782423 ps
CPU time 403.12 seconds
Started Jun 21 05:16:53 PM PDT 24
Finished Jun 21 05:23:37 PM PDT 24
Peak memory 248516 kb
Host smart-39ca3f01-5cef-457f-bc15-28369c239c2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729299177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.729299177
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1906591182
Short name T75
Test name
Test status
Simulation time 49348223010 ps
CPU time 801.29 seconds
Started Jun 21 05:15:06 PM PDT 24
Finished Jun 21 05:28:30 PM PDT 24
Peak memory 269876 kb
Host smart-66a50441-ceb1-4322-a9a4-7f106f8f8d75
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906591182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1906591182
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3257717547
Short name T162
Test name
Test status
Simulation time 13835054935 ps
CPU time 157.11 seconds
Started Jun 21 05:14:39 PM PDT 24
Finished Jun 21 05:17:18 PM PDT 24
Peak memory 257444 kb
Host smart-55ad3e0c-0ff8-40ae-91ba-44c68cf8f2a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3257717547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3257717547
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.1474475135
Short name T96
Test name
Test status
Simulation time 16803320695 ps
CPU time 2084.05 seconds
Started Jun 21 05:14:58 PM PDT 24
Finished Jun 21 05:49:45 PM PDT 24
Peak memory 305956 kb
Host smart-82f945d1-eed9-4bc0-9e5d-7307c534534e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474475135 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.1474475135
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1893765740
Short name T125
Test name
Test status
Simulation time 2219737091 ps
CPU time 322.93 seconds
Started Jun 21 05:14:40 PM PDT 24
Finished Jun 21 05:20:05 PM PDT 24
Peak memory 272856 kb
Host smart-3c9b7a58-1305-4a2a-88f7-4fcfca187646
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893765740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1893765740
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.97692614
Short name T321
Test name
Test status
Simulation time 77007858795 ps
CPU time 1245.35 seconds
Started Jun 21 05:15:08 PM PDT 24
Finished Jun 21 05:35:55 PM PDT 24
Peak memory 265432 kb
Host smart-63254826-4205-4c21-9c92-940e27994765
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97692614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.97692614
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.876181549
Short name T315
Test name
Test status
Simulation time 57574865492 ps
CPU time 599.04 seconds
Started Jun 21 05:15:20 PM PDT 24
Finished Jun 21 05:25:21 PM PDT 24
Peak memory 248304 kb
Host smart-f1e90d6b-823c-42be-b03f-0682d4e63f70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876181549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.876181549
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.992944853
Short name T630
Test name
Test status
Simulation time 52795448689 ps
CPU time 543.18 seconds
Started Jun 21 05:15:20 PM PDT 24
Finished Jun 21 05:24:25 PM PDT 24
Peak memory 248688 kb
Host smart-a78e6a3d-1eb9-433c-bea7-860b9f01bddf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992944853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.992944853
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.1038433018
Short name T260
Test name
Test status
Simulation time 43931799958 ps
CPU time 4107.91 seconds
Started Jun 21 05:15:38 PM PDT 24
Finished Jun 21 06:24:08 PM PDT 24
Peak memory 338952 kb
Host smart-3945edc3-2d59-4a7f-aace-91c03e8e7b09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038433018 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.1038433018
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3823632420
Short name T289
Test name
Test status
Simulation time 27591908153 ps
CPU time 1161.46 seconds
Started Jun 21 05:17:24 PM PDT 24
Finished Jun 21 05:36:47 PM PDT 24
Peak memory 290072 kb
Host smart-338d5646-346c-43b7-a25c-dbb38d29b2d9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823632420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3823632420
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.4154504748
Short name T158
Test name
Test status
Simulation time 16522291431 ps
CPU time 291.91 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 05:19:39 PM PDT 24
Peak memory 273692 kb
Host smart-72117229-c4cb-4583-9029-76706953926a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4154504748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.4154504748
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2990221145
Short name T146
Test name
Test status
Simulation time 12709964317 ps
CPU time 954.09 seconds
Started Jun 21 05:14:21 PM PDT 24
Finished Jun 21 05:30:18 PM PDT 24
Peak memory 265756 kb
Host smart-909f18fd-5b0a-4f3c-a563-29619b0219ff
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990221145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2990221145
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.415272386
Short name T175
Test name
Test status
Simulation time 179966647 ps
CPU time 3.44 seconds
Started Jun 21 05:14:21 PM PDT 24
Finished Jun 21 05:14:27 PM PDT 24
Peak memory 237408 kb
Host smart-2a4f5dd1-af33-4f7a-bd8a-a7f6b2439003
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=415272386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.415272386
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2114066692
Short name T220
Test name
Test status
Simulation time 112248353 ps
CPU time 3.33 seconds
Started Jun 21 05:14:49 PM PDT 24
Finished Jun 21 05:14:57 PM PDT 24
Peak memory 249116 kb
Host smart-032473fd-291a-49bc-8a08-5377a3b741f2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2114066692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2114066692
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3394665983
Short name T216
Test name
Test status
Simulation time 21667337 ps
CPU time 2.49 seconds
Started Jun 21 05:14:51 PM PDT 24
Finished Jun 21 05:14:57 PM PDT 24
Peak memory 249216 kb
Host smart-fa2b8f6a-96ce-4665-8cb8-c15d8ad7b097
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3394665983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3394665983
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.928363648
Short name T221
Test name
Test status
Simulation time 64873513 ps
CPU time 2.42 seconds
Started Jun 21 05:15:19 PM PDT 24
Finished Jun 21 05:15:22 PM PDT 24
Peak memory 249176 kb
Host smart-e800852f-cab5-42e7-9ed9-b26024283ff1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=928363648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.928363648
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.675563793
Short name T64
Test name
Test status
Simulation time 121166083390 ps
CPU time 3543 seconds
Started Jun 21 05:15:17 PM PDT 24
Finished Jun 21 06:14:22 PM PDT 24
Peak memory 322320 kb
Host smart-9583190f-e1be-4642-aac6-7eb14883e0ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675563793 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.675563793
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2858556927
Short name T329
Test name
Test status
Simulation time 58398039952 ps
CPU time 1894.01 seconds
Started Jun 21 05:15:24 PM PDT 24
Finished Jun 21 05:47:01 PM PDT 24
Peak memory 273660 kb
Host smart-173cf1fa-010c-4b80-bf93-02d76c768fbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858556927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2858556927
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.497271850
Short name T248
Test name
Test status
Simulation time 46011217534 ps
CPU time 460.31 seconds
Started Jun 21 05:15:32 PM PDT 24
Finished Jun 21 05:23:16 PM PDT 24
Peak memory 248616 kb
Host smart-3943f61d-43cc-4dbf-954a-a44f99471883
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497271850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.497271850
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.2135888189
Short name T253
Test name
Test status
Simulation time 107423125266 ps
CPU time 1604.98 seconds
Started Jun 21 05:15:58 PM PDT 24
Finished Jun 21 05:42:44 PM PDT 24
Peak memory 281696 kb
Host smart-364ca626-ea1f-4577-ab06-0bf0d5d68f79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135888189 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.2135888189
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2831893360
Short name T148
Test name
Test status
Simulation time 1691395214 ps
CPU time 202.75 seconds
Started Jun 21 05:14:42 PM PDT 24
Finished Jun 21 05:18:08 PM PDT 24
Peak memory 265600 kb
Host smart-aae21f83-4b05-486a-af8a-97eecbf41437
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2831893360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2831893360
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.522505540
Short name T276
Test name
Test status
Simulation time 227293377 ps
CPU time 16.18 seconds
Started Jun 21 05:15:16 PM PDT 24
Finished Jun 21 05:15:34 PM PDT 24
Peak memory 253352 kb
Host smart-4ed4fb52-9581-4065-abfa-bfad44f69c02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52250
5540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.522505540
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.4008777670
Short name T402
Test name
Test status
Simulation time 1579327729 ps
CPU time 59.74 seconds
Started Jun 21 05:15:23 PM PDT 24
Finished Jun 21 05:16:24 PM PDT 24
Peak memory 249000 kb
Host smart-f3fe66cd-d743-4aa0-b6b1-6b174f8a2a5f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4008777670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.4008777670
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1471725910
Short name T144
Test name
Test status
Simulation time 30369461172 ps
CPU time 965.52 seconds
Started Jun 21 05:14:24 PM PDT 24
Finished Jun 21 05:30:32 PM PDT 24
Peak memory 265656 kb
Host smart-19769686-a997-4aa9-a999-2a92c4b6b630
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471725910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1471725910
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3848782664
Short name T736
Test name
Test status
Simulation time 14243242 ps
CPU time 1.33 seconds
Started Jun 21 05:14:38 PM PDT 24
Finished Jun 21 05:14:40 PM PDT 24
Peak memory 237332 kb
Host smart-57fc1952-b314-4aed-b956-65e817fb21ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3848782664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3848782664
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.670088196
Short name T298
Test name
Test status
Simulation time 172243555544 ps
CPU time 2360.38 seconds
Started Jun 21 05:15:23 PM PDT 24
Finished Jun 21 05:54:45 PM PDT 24
Peak memory 273668 kb
Host smart-9702ff41-a12c-4917-ae23-c6bd1247ff27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670088196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.670088196
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2989461333
Short name T513
Test name
Test status
Simulation time 38061571963 ps
CPU time 342.81 seconds
Started Jun 21 05:15:26 PM PDT 24
Finished Jun 21 05:21:11 PM PDT 24
Peak memory 255476 kb
Host smart-20faa18d-2b22-4add-bec9-8f4a6a7c2e48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989461333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2989461333
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.96469309
Short name T286
Test name
Test status
Simulation time 4166923901 ps
CPU time 52.01 seconds
Started Jun 21 05:15:30 PM PDT 24
Finished Jun 21 05:16:23 PM PDT 24
Peak memory 256020 kb
Host smart-e38180a7-2838-4a9c-b96c-92bbf1061436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96469
309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.96469309
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.153279925
Short name T293
Test name
Test status
Simulation time 185941164127 ps
CPU time 1009.43 seconds
Started Jun 21 05:15:41 PM PDT 24
Finished Jun 21 05:32:31 PM PDT 24
Peak memory 271948 kb
Host smart-fff2ae61-cce3-40e2-9d75-b7c80e0c597a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153279925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.153279925
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1944319344
Short name T277
Test name
Test status
Simulation time 1041125282 ps
CPU time 33.88 seconds
Started Jun 21 05:15:45 PM PDT 24
Finished Jun 21 05:16:20 PM PDT 24
Peak memory 256036 kb
Host smart-9fedce6e-9518-4064-ac59-1e33736d090a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19443
19344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1944319344
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1995632430
Short name T285
Test name
Test status
Simulation time 36233833491 ps
CPU time 2062.93 seconds
Started Jun 21 05:15:55 PM PDT 24
Finished Jun 21 05:50:19 PM PDT 24
Peak memory 305484 kb
Host smart-34a8c9ef-b143-4bb2-a429-eb4801a19daa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995632430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1995632430
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.3327658005
Short name T186
Test name
Test status
Simulation time 184833044127 ps
CPU time 3127.24 seconds
Started Jun 21 05:16:01 PM PDT 24
Finished Jun 21 06:08:10 PM PDT 24
Peak memory 298348 kb
Host smart-2d328da3-d53d-4096-aa55-50d2b33aa0db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327658005 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.3327658005
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2770302048
Short name T109
Test name
Test status
Simulation time 2166366557 ps
CPU time 42.98 seconds
Started Jun 21 05:16:09 PM PDT 24
Finished Jun 21 05:16:53 PM PDT 24
Peak memory 256020 kb
Host smart-5075d5a4-a8c8-4f2a-843e-849f414f4762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27703
02048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2770302048
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.416278652
Short name T278
Test name
Test status
Simulation time 218357639166 ps
CPU time 3293.75 seconds
Started Jun 21 05:16:32 PM PDT 24
Finished Jun 21 06:11:26 PM PDT 24
Peak memory 306228 kb
Host smart-1f5471ee-75b3-4b5d-8380-fe7c74f5e649
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416278652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.416278652
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1589115586
Short name T261
Test name
Test status
Simulation time 26309959946 ps
CPU time 1185.58 seconds
Started Jun 21 05:16:40 PM PDT 24
Finished Jun 21 05:36:27 PM PDT 24
Peak memory 288268 kb
Host smart-845ecd28-81b8-4f22-8cbc-4a56170aabac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589115586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1589115586
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.421730610
Short name T273
Test name
Test status
Simulation time 50537876854 ps
CPU time 2926.22 seconds
Started Jun 21 05:16:45 PM PDT 24
Finished Jun 21 06:05:33 PM PDT 24
Peak memory 289344 kb
Host smart-41b93930-143d-4105-a935-bab1283630ea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421730610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.421730610
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.291121835
Short name T279
Test name
Test status
Simulation time 4536460859 ps
CPU time 266.76 seconds
Started Jun 21 05:16:46 PM PDT 24
Finished Jun 21 05:21:14 PM PDT 24
Peak memory 250224 kb
Host smart-d5b47a89-da04-400b-923b-d7d78b8b4620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29112
1835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.291121835
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.3787133325
Short name T100
Test name
Test status
Simulation time 54453874615 ps
CPU time 3783.22 seconds
Started Jun 21 05:16:44 PM PDT 24
Finished Jun 21 06:19:49 PM PDT 24
Peak memory 305224 kb
Host smart-b96f5933-18d2-4dea-bac2-eb1d85af17ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787133325 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.3787133325
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2345371966
Short name T150
Test name
Test status
Simulation time 7921893212 ps
CPU time 302.94 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 05:19:49 PM PDT 24
Peak memory 272712 kb
Host smart-a09232b2-a342-4893-88c5-90a217809804
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2345371966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2345371966
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3072366337
Short name T170
Test name
Test status
Simulation time 109183415 ps
CPU time 2.79 seconds
Started Jun 21 05:14:38 PM PDT 24
Finished Jun 21 05:14:42 PM PDT 24
Peak memory 237320 kb
Host smart-09de0cea-fc24-4a5a-9c14-aea466ee7d24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3072366337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3072366337
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.4269044057
Short name T172
Test name
Test status
Simulation time 130571865 ps
CPU time 3.83 seconds
Started Jun 21 05:14:24 PM PDT 24
Finished Jun 21 05:14:31 PM PDT 24
Peak memory 237420 kb
Host smart-9b953fe5-36fb-41ee-8a56-cc07af107d18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4269044057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.4269044057
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4180006742
Short name T169
Test name
Test status
Simulation time 157150659 ps
CPU time 2.98 seconds
Started Jun 21 05:14:22 PM PDT 24
Finished Jun 21 05:14:28 PM PDT 24
Peak memory 237376 kb
Host smart-56c222c8-1991-44cb-b277-7d3dfb9ff104
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4180006742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.4180006742
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3957779911
Short name T184
Test name
Test status
Simulation time 2031782761 ps
CPU time 37.04 seconds
Started Jun 21 05:14:21 PM PDT 24
Finished Jun 21 05:15:01 PM PDT 24
Peak memory 237496 kb
Host smart-cd5ae694-577f-4d7d-b396-7aa578bee714
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3957779911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3957779911
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3763189911
Short name T164
Test name
Test status
Simulation time 127218444 ps
CPU time 6.88 seconds
Started Jun 21 05:14:28 PM PDT 24
Finished Jun 21 05:14:36 PM PDT 24
Peak memory 237448 kb
Host smart-2932f7d8-8edc-43a2-9286-96465c90650b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3763189911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3763189911
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2800250877
Short name T176
Test name
Test status
Simulation time 1302067471 ps
CPU time 86.79 seconds
Started Jun 21 05:14:41 PM PDT 24
Finished Jun 21 05:16:10 PM PDT 24
Peak memory 240752 kb
Host smart-0bdc815d-f1da-4b3d-9c61-7ace6596a9e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2800250877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2800250877
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2472744328
Short name T174
Test name
Test status
Simulation time 112908375 ps
CPU time 3.04 seconds
Started Jun 21 05:14:35 PM PDT 24
Finished Jun 21 05:14:39 PM PDT 24
Peak memory 237512 kb
Host smart-f80ff655-6ba3-4db7-8134-30bae182a3c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2472744328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2472744328
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2831648475
Short name T171
Test name
Test status
Simulation time 139326125 ps
CPU time 4.31 seconds
Started Jun 21 05:14:30 PM PDT 24
Finished Jun 21 05:14:36 PM PDT 24
Peak memory 237440 kb
Host smart-bba20c5e-a922-4b7e-9b3d-25d6c1a91be9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2831648475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2831648475
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1344815065
Short name T133
Test name
Test status
Simulation time 17434493494 ps
CPU time 643.47 seconds
Started Jun 21 05:14:37 PM PDT 24
Finished Jun 21 05:25:22 PM PDT 24
Peak memory 273456 kb
Host smart-7fd2070c-697d-496b-a656-3393ab97ba53
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344815065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1344815065
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3157838701
Short name T177
Test name
Test status
Simulation time 38209877 ps
CPU time 3.58 seconds
Started Jun 21 05:14:40 PM PDT 24
Finished Jun 21 05:14:46 PM PDT 24
Peak memory 237332 kb
Host smart-9169dcad-f43d-41fb-83e1-fa479417b72d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3157838701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3157838701
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.619439941
Short name T130
Test name
Test status
Simulation time 5601167313 ps
CPU time 197.79 seconds
Started Jun 21 05:14:41 PM PDT 24
Finished Jun 21 05:18:01 PM PDT 24
Peak memory 265636 kb
Host smart-9cc7372c-dbdc-4c3f-9c40-357a408db89a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=619439941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.619439941
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1520215567
Short name T165
Test name
Test status
Simulation time 560888402 ps
CPU time 35.44 seconds
Started Jun 21 05:14:38 PM PDT 24
Finished Jun 21 05:15:16 PM PDT 24
Peak memory 240752 kb
Host smart-f8651bb0-5cfc-4e21-a498-797bf213b8c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1520215567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1520215567
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.112915417
Short name T180
Test name
Test status
Simulation time 56996446 ps
CPU time 2.87 seconds
Started Jun 21 05:14:25 PM PDT 24
Finished Jun 21 05:14:30 PM PDT 24
Peak memory 237156 kb
Host smart-544b231c-ece7-4118-9ff5-125c9af479e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=112915417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.112915417
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1281290213
Short name T181
Test name
Test status
Simulation time 2518121805 ps
CPU time 40.89 seconds
Started Jun 21 05:14:30 PM PDT 24
Finished Jun 21 05:15:12 PM PDT 24
Peak memory 245912 kb
Host smart-592b60e3-d6de-408d-836f-c6d7cf7bbe01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1281290213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1281290213
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2843772701
Short name T185
Test name
Test status
Simulation time 61481729 ps
CPU time 2.13 seconds
Started Jun 21 05:14:22 PM PDT 24
Finished Jun 21 05:14:27 PM PDT 24
Peak memory 237320 kb
Host smart-c88d4027-c524-4ebc-af9f-eaa3ba442999
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2843772701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2843772701
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.2622984920
Short name T30
Test name
Test status
Simulation time 177936172282 ps
CPU time 2067.23 seconds
Started Jun 21 05:15:25 PM PDT 24
Finished Jun 21 05:49:54 PM PDT 24
Peak memory 321912 kb
Host smart-502fa995-8fc9-47b5-bdee-564b767e934f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622984920 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.2622984920
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3338409060
Short name T31
Test name
Test status
Simulation time 2262678018 ps
CPU time 36.43 seconds
Started Jun 21 05:15:43 PM PDT 24
Finished Jun 21 05:16:20 PM PDT 24
Peak memory 256472 kb
Host smart-f475b64e-5c93-483a-bbe2-d9e1636a5559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33384
09060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3338409060
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.486419171
Short name T776
Test name
Test status
Simulation time 2001715026 ps
CPU time 116.37 seconds
Started Jun 21 05:14:20 PM PDT 24
Finished Jun 21 05:16:18 PM PDT 24
Peak memory 237348 kb
Host smart-68cd0209-e1b6-4aa0-9d83-2c3ff863b408
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=486419171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.486419171
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.4078387322
Short name T766
Test name
Test status
Simulation time 821274468 ps
CPU time 99.93 seconds
Started Jun 21 05:14:19 PM PDT 24
Finished Jun 21 05:16:00 PM PDT 24
Peak memory 237256 kb
Host smart-e063d420-d523-49dd-8798-0d11399c2192
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4078387322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.4078387322
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1092187046
Short name T765
Test name
Test status
Simulation time 211275659 ps
CPU time 5.69 seconds
Started Jun 21 05:14:23 PM PDT 24
Finished Jun 21 05:14:32 PM PDT 24
Peak memory 240640 kb
Host smart-b90803e8-c97f-4c44-92d1-6b6fad443f68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1092187046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1092187046
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2502873920
Short name T182
Test name
Test status
Simulation time 42708861 ps
CPU time 6.19 seconds
Started Jun 21 05:14:21 PM PDT 24
Finished Jun 21 05:14:30 PM PDT 24
Peak memory 242920 kb
Host smart-4034db3c-fe98-4c21-b358-2db6b2906f75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502873920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2502873920
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.136337180
Short name T348
Test name
Test status
Simulation time 49447004 ps
CPU time 4.42 seconds
Started Jun 21 05:14:24 PM PDT 24
Finished Jun 21 05:14:31 PM PDT 24
Peak memory 237268 kb
Host smart-949abf25-9170-4914-9b18-8333a7e7fe36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=136337180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.136337180
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1531359835
Short name T782
Test name
Test status
Simulation time 8506391 ps
CPU time 1.55 seconds
Started Jun 21 05:14:20 PM PDT 24
Finished Jun 21 05:14:24 PM PDT 24
Peak memory 237316 kb
Host smart-c1ccfeca-830f-4677-96d0-7e5bff7f1bd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1531359835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1531359835
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3346351204
Short name T726
Test name
Test status
Simulation time 733568352 ps
CPU time 19.89 seconds
Started Jun 21 05:14:23 PM PDT 24
Finished Jun 21 05:14:46 PM PDT 24
Peak memory 248952 kb
Host smart-73e7c507-d1d1-4fc5-a9b8-13591f26ea07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3346351204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3346351204
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3350961071
Short name T789
Test name
Test status
Simulation time 269555527 ps
CPU time 9.65 seconds
Started Jun 21 05:14:24 PM PDT 24
Finished Jun 21 05:14:36 PM PDT 24
Peak memory 247996 kb
Host smart-5e969e22-390d-400c-b737-b28203064bfa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3350961071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3350961071
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3376310208
Short name T718
Test name
Test status
Simulation time 8192596811 ps
CPU time 138.23 seconds
Started Jun 21 05:14:22 PM PDT 24
Finished Jun 21 05:16:43 PM PDT 24
Peak memory 237316 kb
Host smart-49f04fa4-b564-4b59-a2da-08dee358bb48
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3376310208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3376310208
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2712805053
Short name T788
Test name
Test status
Simulation time 4456259988 ps
CPU time 196.13 seconds
Started Jun 21 05:14:19 PM PDT 24
Finished Jun 21 05:17:37 PM PDT 24
Peak memory 240748 kb
Host smart-e6a32720-ece0-4d7f-aac8-96c44392177b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2712805053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2712805053
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1944952946
Short name T754
Test name
Test status
Simulation time 43449968 ps
CPU time 6.4 seconds
Started Jun 21 05:14:24 PM PDT 24
Finished Jun 21 05:14:34 PM PDT 24
Peak memory 240696 kb
Host smart-dbc9e747-1d92-4d49-89d4-f4fcc4cc714f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1944952946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1944952946
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.670473400
Short name T740
Test name
Test status
Simulation time 102584662 ps
CPU time 7.21 seconds
Started Jun 21 05:14:20 PM PDT 24
Finished Jun 21 05:14:29 PM PDT 24
Peak memory 238360 kb
Host smart-21d8ba7f-43ab-4798-a11e-78d8d705f755
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670473400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.670473400
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1416336822
Short name T724
Test name
Test status
Simulation time 1540427348 ps
CPU time 8.28 seconds
Started Jun 21 05:14:20 PM PDT 24
Finished Jun 21 05:14:30 PM PDT 24
Peak memory 236156 kb
Host smart-6a9bcb5b-3af2-466c-bc45-664443603897
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1416336822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1416336822
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3259108965
Short name T761
Test name
Test status
Simulation time 7687198 ps
CPU time 1.32 seconds
Started Jun 21 05:14:25 PM PDT 24
Finished Jun 21 05:14:29 PM PDT 24
Peak memory 236416 kb
Host smart-8959a15d-825c-47f7-acc4-ae09a5da8d8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3259108965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3259108965
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.933327434
Short name T759
Test name
Test status
Simulation time 2053931123 ps
CPU time 37.24 seconds
Started Jun 21 05:14:19 PM PDT 24
Finished Jun 21 05:14:58 PM PDT 24
Peak memory 248928 kb
Host smart-bac16894-8d64-40f1-83b3-6b5ed8230baf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=933327434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outs
tanding.933327434
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3159262905
Short name T152
Test name
Test status
Simulation time 5044263809 ps
CPU time 174.07 seconds
Started Jun 21 05:14:21 PM PDT 24
Finished Jun 21 05:17:17 PM PDT 24
Peak memory 257448 kb
Host smart-11df60e3-3480-4765-9940-df54eb81a791
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3159262905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3159262905
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3241855192
Short name T830
Test name
Test status
Simulation time 358105829 ps
CPU time 13.11 seconds
Started Jun 21 05:14:20 PM PDT 24
Finished Jun 21 05:14:36 PM PDT 24
Peak memory 248980 kb
Host smart-898aa140-0893-45ce-b347-120ce4710566
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3241855192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3241855192
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1376365035
Short name T777
Test name
Test status
Simulation time 110522097 ps
CPU time 7.92 seconds
Started Jun 21 05:14:36 PM PDT 24
Finished Jun 21 05:14:45 PM PDT 24
Peak memory 241000 kb
Host smart-571449a3-46ea-417d-b29e-86399c1259a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376365035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1376365035
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3044170042
Short name T741
Test name
Test status
Simulation time 94324708 ps
CPU time 4.22 seconds
Started Jun 21 05:14:40 PM PDT 24
Finished Jun 21 05:14:46 PM PDT 24
Peak memory 236312 kb
Host smart-e9e5665d-3336-44b7-b9f2-37b18e555750
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3044170042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3044170042
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.14134791
Short name T198
Test name
Test status
Simulation time 88437891 ps
CPU time 11.29 seconds
Started Jun 21 05:14:30 PM PDT 24
Finished Jun 21 05:14:43 PM PDT 24
Peak memory 244592 kb
Host smart-da63d6d8-d68b-484a-9db2-891b13fd7038
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=14134791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_outs
tanding.14134791
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.856338090
Short name T800
Test name
Test status
Simulation time 740596219 ps
CPU time 14.82 seconds
Started Jun 21 05:14:36 PM PDT 24
Finished Jun 21 05:14:52 PM PDT 24
Peak memory 249088 kb
Host smart-846b5261-c35c-4807-bc0f-fbd84507aeed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=856338090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.856338090
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3604046462
Short name T827
Test name
Test status
Simulation time 57612867 ps
CPU time 4.78 seconds
Started Jun 21 05:14:29 PM PDT 24
Finished Jun 21 05:14:34 PM PDT 24
Peak memory 240796 kb
Host smart-f221a43d-541f-4169-802c-bc5d2d8cbad1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604046462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3604046462
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2365148468
Short name T200
Test name
Test status
Simulation time 2074367170 ps
CPU time 8.52 seconds
Started Jun 21 05:14:29 PM PDT 24
Finished Jun 21 05:14:39 PM PDT 24
Peak memory 236176 kb
Host smart-23d27f8b-0a9c-43fd-91a9-66cac95f754e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2365148468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2365148468
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.985422124
Short name T810
Test name
Test status
Simulation time 523973043 ps
CPU time 38.31 seconds
Started Jun 21 05:14:39 PM PDT 24
Finished Jun 21 05:15:20 PM PDT 24
Peak memory 245532 kb
Host smart-6501138a-e2b3-47b9-b2d1-e4f14f53e906
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=985422124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_out
standing.985422124
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3645092882
Short name T151
Test name
Test status
Simulation time 4460283797 ps
CPU time 147.32 seconds
Started Jun 21 05:14:36 PM PDT 24
Finished Jun 21 05:17:04 PM PDT 24
Peak memory 257472 kb
Host smart-9dfaa763-1579-457f-a614-f2f063751f06
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3645092882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3645092882
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2199166957
Short name T778
Test name
Test status
Simulation time 179941099 ps
CPU time 12.38 seconds
Started Jun 21 05:14:30 PM PDT 24
Finished Jun 21 05:14:44 PM PDT 24
Peak memory 253568 kb
Host smart-47ec2b74-45bf-4f05-91ec-e87bcafee68b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2199166957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2199166957
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.746339203
Short name T823
Test name
Test status
Simulation time 154988457 ps
CPU time 4.44 seconds
Started Jun 21 05:14:32 PM PDT 24
Finished Jun 21 05:14:37 PM PDT 24
Peak memory 240800 kb
Host smart-225441ff-1988-4cb5-806e-dddff515ab47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746339203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.746339203
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1073750015
Short name T831
Test name
Test status
Simulation time 215277711 ps
CPU time 4.41 seconds
Started Jun 21 05:14:40 PM PDT 24
Finished Jun 21 05:14:47 PM PDT 24
Peak memory 237260 kb
Host smart-e08a997a-cb4f-4936-b5c6-c3618a93ca02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1073750015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1073750015
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2985750896
Short name T745
Test name
Test status
Simulation time 7663877 ps
CPU time 1.46 seconds
Started Jun 21 05:14:29 PM PDT 24
Finished Jun 21 05:14:32 PM PDT 24
Peak memory 237340 kb
Host smart-e7a809c2-ac0c-411b-9035-4c192d4dc97f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2985750896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2985750896
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3648157410
Short name T201
Test name
Test status
Simulation time 668938481 ps
CPU time 46.1 seconds
Started Jun 21 05:14:40 PM PDT 24
Finished Jun 21 05:15:28 PM PDT 24
Peak memory 245532 kb
Host smart-9554ab9b-938c-4a01-b3d9-076472a39072
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3648157410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3648157410
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.993348826
Short name T129
Test name
Test status
Simulation time 15680415015 ps
CPU time 1042.57 seconds
Started Jun 21 05:14:31 PM PDT 24
Finished Jun 21 05:31:55 PM PDT 24
Peak memory 265640 kb
Host smart-2db027d5-faa7-457d-a420-3c40fc52e1a8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993348826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.993348826
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.115531971
Short name T767
Test name
Test status
Simulation time 1841162203 ps
CPU time 13.82 seconds
Started Jun 21 05:14:31 PM PDT 24
Finished Jun 21 05:14:46 PM PDT 24
Peak memory 247972 kb
Host smart-0ddd9afd-c719-435a-8dcf-8f5dfb6d486b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=115531971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.115531971
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.961531026
Short name T183
Test name
Test status
Simulation time 69214057 ps
CPU time 7.19 seconds
Started Jun 21 05:14:41 PM PDT 24
Finished Jun 21 05:14:50 PM PDT 24
Peak memory 257164 kb
Host smart-e2b6b2ea-149a-423d-8fd4-6333811470fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961531026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.961531026
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.4059530526
Short name T716
Test name
Test status
Simulation time 126250985 ps
CPU time 5.28 seconds
Started Jun 21 05:14:30 PM PDT 24
Finished Jun 21 05:14:36 PM PDT 24
Peak memory 237248 kb
Host smart-7aa76899-8623-4ec4-a4f1-f2bd42aef042
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4059530526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.4059530526
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1446978626
Short name T795
Test name
Test status
Simulation time 8214483 ps
CPU time 1.55 seconds
Started Jun 21 05:14:30 PM PDT 24
Finished Jun 21 05:14:33 PM PDT 24
Peak memory 237372 kb
Host smart-db0f9ab7-04b3-4616-99f1-2e6af3df2ff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1446978626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1446978626
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2113297133
Short name T762
Test name
Test status
Simulation time 502607386 ps
CPU time 18.4 seconds
Started Jun 21 05:14:31 PM PDT 24
Finished Jun 21 05:14:51 PM PDT 24
Peak memory 245532 kb
Host smart-eab44e38-6ea0-4958-aefb-4bed1fd68c2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2113297133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2113297133
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2410930646
Short name T744
Test name
Test status
Simulation time 183459897 ps
CPU time 9.12 seconds
Started Jun 21 05:14:41 PM PDT 24
Finished Jun 21 05:14:52 PM PDT 24
Peak memory 248876 kb
Host smart-5a16ad76-3689-43b5-9fbb-47565fe80dc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2410930646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2410930646
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1961588944
Short name T818
Test name
Test status
Simulation time 585632750 ps
CPU time 11.94 seconds
Started Jun 21 05:14:49 PM PDT 24
Finished Jun 21 05:15:06 PM PDT 24
Peak memory 250928 kb
Host smart-49674930-b05e-48de-a1b5-cd124d1b933d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961588944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1961588944
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.711539563
Short name T351
Test name
Test status
Simulation time 138326381 ps
CPU time 8.97 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 05:14:56 PM PDT 24
Peak memory 237248 kb
Host smart-d84d14a0-5a72-4b27-92ce-f641f38409e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=711539563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.711539563
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2594377339
Short name T735
Test name
Test status
Simulation time 13938771 ps
CPU time 1.35 seconds
Started Jun 21 05:14:44 PM PDT 24
Finished Jun 21 05:14:49 PM PDT 24
Peak memory 235416 kb
Host smart-2e669c42-0314-4b4f-9a5b-3c5ff384a283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2594377339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2594377339
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.61867232
Short name T728
Test name
Test status
Simulation time 501126805 ps
CPU time 36.2 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 05:15:22 PM PDT 24
Peak memory 248932 kb
Host smart-980b13c8-8589-4aa8-896c-fbadecdec0e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=61867232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outs
tanding.61867232
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2985235496
Short name T140
Test name
Test status
Simulation time 7973196727 ps
CPU time 582.7 seconds
Started Jun 21 05:14:38 PM PDT 24
Finished Jun 21 05:24:23 PM PDT 24
Peak memory 265528 kb
Host smart-6328b417-71e3-40b2-90c4-9af054bd383e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985235496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2985235496
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1108997974
Short name T813
Test name
Test status
Simulation time 734681224 ps
CPU time 14.69 seconds
Started Jun 21 05:14:41 PM PDT 24
Finished Jun 21 05:14:58 PM PDT 24
Peak memory 249040 kb
Host smart-370fdb63-3ddb-44cd-95b6-4d304b443a98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1108997974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1108997974
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2486945922
Short name T173
Test name
Test status
Simulation time 1245248347 ps
CPU time 40.66 seconds
Started Jun 21 05:14:50 PM PDT 24
Finished Jun 21 05:15:35 PM PDT 24
Peak memory 237052 kb
Host smart-58754bee-36bf-4476-9c8d-48ebe8961638
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2486945922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2486945922
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.936423965
Short name T204
Test name
Test status
Simulation time 529609136 ps
CPU time 9.52 seconds
Started Jun 21 05:14:44 PM PDT 24
Finished Jun 21 05:14:58 PM PDT 24
Peak memory 252620 kb
Host smart-39d8876b-41d5-42c2-862c-cbaa226f4025
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936423965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.936423965
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3194175424
Short name T791
Test name
Test status
Simulation time 126969612 ps
CPU time 9.36 seconds
Started Jun 21 05:14:36 PM PDT 24
Finished Jun 21 05:14:46 PM PDT 24
Peak memory 237256 kb
Host smart-26b6430f-ffb9-4741-88bc-ab568fa89ebc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3194175424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3194175424
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.182990872
Short name T725
Test name
Test status
Simulation time 242574349 ps
CPU time 19.34 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 05:15:07 PM PDT 24
Peak memory 245488 kb
Host smart-69294e95-5c1d-4514-aff0-3e2f247689bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=182990872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.182990872
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1431789557
Short name T136
Test name
Test status
Simulation time 32188395019 ps
CPU time 676.75 seconds
Started Jun 21 05:14:38 PM PDT 24
Finished Jun 21 05:25:57 PM PDT 24
Peak memory 265956 kb
Host smart-01f55632-8443-420d-a0f1-dd567ae097b3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431789557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1431789557
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3391361784
Short name T783
Test name
Test status
Simulation time 321821649 ps
CPU time 17.72 seconds
Started Jun 21 05:14:39 PM PDT 24
Finished Jun 21 05:14:59 PM PDT 24
Peak memory 249096 kb
Host smart-5f8ead63-fa69-46b8-8674-039f3c53a9d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3391361784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3391361784
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3956673179
Short name T179
Test name
Test status
Simulation time 1277081791 ps
CPU time 44.53 seconds
Started Jun 21 05:14:38 PM PDT 24
Finished Jun 21 05:15:24 PM PDT 24
Peak memory 245864 kb
Host smart-be7addd1-330e-461e-b5da-05cc7eb3d966
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3956673179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3956673179
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2673680422
Short name T821
Test name
Test status
Simulation time 30509756 ps
CPU time 5.2 seconds
Started Jun 21 05:14:40 PM PDT 24
Finished Jun 21 05:14:47 PM PDT 24
Peak memory 240780 kb
Host smart-ac4ac420-0791-421d-b27b-abf1b881ed3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673680422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2673680422
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3642090348
Short name T749
Test name
Test status
Simulation time 52653650 ps
CPU time 5.13 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 05:14:53 PM PDT 24
Peak memory 240100 kb
Host smart-ce07b787-2042-4da4-911b-f7ef5604a9ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3642090348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3642090348
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.327558517
Short name T721
Test name
Test status
Simulation time 14742347 ps
CPU time 1.46 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 05:14:49 PM PDT 24
Peak memory 237332 kb
Host smart-84fdf5c7-dab1-4a75-8847-9718fefba504
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=327558517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.327558517
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2114700118
Short name T774
Test name
Test status
Simulation time 314588964 ps
CPU time 21.54 seconds
Started Jun 21 05:14:40 PM PDT 24
Finished Jun 21 05:15:03 PM PDT 24
Peak memory 244584 kb
Host smart-209abe6f-6476-4737-941d-46eb8205f000
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2114700118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2114700118
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.159052676
Short name T161
Test name
Test status
Simulation time 21189229142 ps
CPU time 310.29 seconds
Started Jun 21 05:14:46 PM PDT 24
Finished Jun 21 05:20:00 PM PDT 24
Peak memory 265756 kb
Host smart-5c04b71f-3883-4d7a-9921-53d8675ed2bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=159052676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.159052676
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3704987972
Short name T160
Test name
Test status
Simulation time 17145571182 ps
CPU time 1276.75 seconds
Started Jun 21 05:14:38 PM PDT 24
Finished Jun 21 05:35:56 PM PDT 24
Peak memory 265756 kb
Host smart-2fdd0b10-e732-442e-ad3c-d4963d40c7f7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704987972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3704987972
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.483748854
Short name T822
Test name
Test status
Simulation time 722456383 ps
CPU time 12.65 seconds
Started Jun 21 05:14:42 PM PDT 24
Finished Jun 21 05:14:56 PM PDT 24
Peak memory 248432 kb
Host smart-a2f50de7-badd-4775-9409-70aab7390c69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=483748854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.483748854
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.143101659
Short name T739
Test name
Test status
Simulation time 58961205 ps
CPU time 3.82 seconds
Started Jun 21 05:14:37 PM PDT 24
Finished Jun 21 05:14:42 PM PDT 24
Peak memory 237336 kb
Host smart-f10fbc90-a9ca-450d-8849-76b6060c1959
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=143101659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.143101659
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2224932631
Short name T775
Test name
Test status
Simulation time 286043511 ps
CPU time 11.65 seconds
Started Jun 21 05:14:41 PM PDT 24
Finished Jun 21 05:14:55 PM PDT 24
Peak memory 248980 kb
Host smart-a2a941e8-51d0-4de6-87ad-49c56257989c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224932631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2224932631
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1415685548
Short name T826
Test name
Test status
Simulation time 92815069 ps
CPU time 7.39 seconds
Started Jun 21 05:14:38 PM PDT 24
Finished Jun 21 05:14:47 PM PDT 24
Peak memory 237260 kb
Host smart-721dd8e9-97b9-4930-a582-78b8f089bea3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1415685548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1415685548
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2594123152
Short name T772
Test name
Test status
Simulation time 15279668 ps
CPU time 1.33 seconds
Started Jun 21 05:14:38 PM PDT 24
Finished Jun 21 05:14:42 PM PDT 24
Peak memory 236404 kb
Host smart-6d7f5f76-ae4a-4e13-ab78-45be6ad900d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2594123152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2594123152
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1115141075
Short name T717
Test name
Test status
Simulation time 346896142 ps
CPU time 21.43 seconds
Started Jun 21 05:14:39 PM PDT 24
Finished Jun 21 05:15:03 PM PDT 24
Peak memory 244580 kb
Host smart-68a4f8e6-357a-4ffa-83e4-487355307db6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1115141075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1115141075
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1837131024
Short name T139
Test name
Test status
Simulation time 4889138749 ps
CPU time 143.93 seconds
Started Jun 21 05:14:39 PM PDT 24
Finished Jun 21 05:17:05 PM PDT 24
Peak memory 265732 kb
Host smart-047d0b50-6d58-4604-ad28-12912f59269e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1837131024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1837131024
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3387556158
Short name T155
Test name
Test status
Simulation time 31037626627 ps
CPU time 1166.34 seconds
Started Jun 21 05:14:39 PM PDT 24
Finished Jun 21 05:34:08 PM PDT 24
Peak memory 265720 kb
Host smart-5f0be5ef-fead-4832-9fc0-8628c0c3009a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387556158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3387556158
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.295350057
Short name T770
Test name
Test status
Simulation time 191106032 ps
CPU time 13.46 seconds
Started Jun 21 05:14:37 PM PDT 24
Finished Jun 21 05:14:51 PM PDT 24
Peak memory 248964 kb
Host smart-b5c4fa21-d636-4a8b-bba1-f02e92afc8bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=295350057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.295350057
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1369762598
Short name T757
Test name
Test status
Simulation time 59535875 ps
CPU time 8.04 seconds
Started Jun 21 05:14:39 PM PDT 24
Finished Jun 21 05:14:49 PM PDT 24
Peak memory 253084 kb
Host smart-0c9ecaa8-7325-45fa-b7f6-724bac5ac651
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369762598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1369762598
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.968914512
Short name T758
Test name
Test status
Simulation time 63433192 ps
CPU time 3.28 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 05:14:50 PM PDT 24
Peak memory 237208 kb
Host smart-bb49e696-2ac0-4f2c-89b9-d7ed9f67aa4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=968914512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.968914512
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1979734376
Short name T719
Test name
Test status
Simulation time 36484653 ps
CPU time 1.29 seconds
Started Jun 21 05:14:42 PM PDT 24
Finished Jun 21 05:14:46 PM PDT 24
Peak memory 237208 kb
Host smart-f246e61e-dff8-443d-a34d-8098931c9d80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1979734376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1979734376
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3295544303
Short name T748
Test name
Test status
Simulation time 1170206714 ps
CPU time 20.32 seconds
Started Jun 21 05:14:40 PM PDT 24
Finished Jun 21 05:15:02 PM PDT 24
Peak memory 244584 kb
Host smart-810b204c-131a-4c18-aad7-0c6cef7fb886
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3295544303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3295544303
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.4269408890
Short name T138
Test name
Test status
Simulation time 1774916453 ps
CPU time 101.04 seconds
Started Jun 21 05:14:34 PM PDT 24
Finished Jun 21 05:16:16 PM PDT 24
Peak memory 265600 kb
Host smart-85eb84b0-b89c-4977-9608-4c31877d1f97
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4269408890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.4269408890
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1338090930
Short name T128
Test name
Test status
Simulation time 3520935795 ps
CPU time 394.83 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 05:21:22 PM PDT 24
Peak memory 265564 kb
Host smart-5bb4d880-11c4-4f1a-ad5d-e1117b54e49e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338090930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1338090930
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.4107188356
Short name T713
Test name
Test status
Simulation time 148080060 ps
CPU time 5.94 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 05:14:53 PM PDT 24
Peak memory 248120 kb
Host smart-3f791987-6d6d-41ab-83aa-1a87c1000d68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4107188356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.4107188356
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3882547627
Short name T747
Test name
Test status
Simulation time 106582677 ps
CPU time 2.6 seconds
Started Jun 21 05:14:42 PM PDT 24
Finished Jun 21 05:14:48 PM PDT 24
Peak memory 237468 kb
Host smart-c8b88144-fc2d-4321-b269-8c903612d6c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3882547627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3882547627
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.454763989
Short name T790
Test name
Test status
Simulation time 502320557 ps
CPU time 6.49 seconds
Started Jun 21 05:14:37 PM PDT 24
Finished Jun 21 05:14:44 PM PDT 24
Peak memory 240264 kb
Host smart-80a1253c-c20e-4afa-9854-9dabd96838d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454763989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.454763989
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3269666434
Short name T797
Test name
Test status
Simulation time 273581796 ps
CPU time 4.71 seconds
Started Jun 21 05:14:49 PM PDT 24
Finished Jun 21 05:14:59 PM PDT 24
Peak memory 240012 kb
Host smart-7898cac1-e173-47e2-a8d6-8d2d1f85c398
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3269666434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3269666434
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.774401356
Short name T345
Test name
Test status
Simulation time 9059378 ps
CPU time 1.52 seconds
Started Jun 21 05:14:38 PM PDT 24
Finished Jun 21 05:14:41 PM PDT 24
Peak memory 237344 kb
Host smart-0a741e69-8174-4b06-a5fc-5b66f4722608
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=774401356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.774401356
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3520635387
Short name T202
Test name
Test status
Simulation time 259504593 ps
CPU time 17.88 seconds
Started Jun 21 05:14:39 PM PDT 24
Finished Jun 21 05:14:59 PM PDT 24
Peak memory 244620 kb
Host smart-6e263284-5cc9-4f8a-891d-e8509ed058e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3520635387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3520635387
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.696629301
Short name T147
Test name
Test status
Simulation time 47973368857 ps
CPU time 565.93 seconds
Started Jun 21 05:14:37 PM PDT 24
Finished Jun 21 05:24:04 PM PDT 24
Peak memory 265564 kb
Host smart-05cf6796-87f9-4600-91b3-85f29f7bd3fb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696629301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.696629301
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.1719066984
Short name T255
Test name
Test status
Simulation time 1090348660 ps
CPU time 22.42 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 05:15:09 PM PDT 24
Peak memory 249004 kb
Host smart-6b9cfbcd-fb2c-46ea-bb1f-5d9818720dd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1719066984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.1719066984
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3401058041
Short name T199
Test name
Test status
Simulation time 4856456979 ps
CPU time 312.1 seconds
Started Jun 21 05:14:21 PM PDT 24
Finished Jun 21 05:19:36 PM PDT 24
Peak memory 241384 kb
Host smart-f2402b22-0d42-4816-9579-928b20a4a051
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3401058041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3401058041
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3509854777
Short name T811
Test name
Test status
Simulation time 22837583653 ps
CPU time 400.76 seconds
Started Jun 21 05:14:23 PM PDT 24
Finished Jun 21 05:21:07 PM PDT 24
Peak memory 236380 kb
Host smart-94f4e3da-6852-424e-ac0f-1002b051f4fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3509854777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3509854777
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2409054316
Short name T806
Test name
Test status
Simulation time 40816959 ps
CPU time 5.66 seconds
Started Jun 21 05:14:22 PM PDT 24
Finished Jun 21 05:14:31 PM PDT 24
Peak memory 240684 kb
Host smart-a50d9b23-7ef0-4366-abdc-9a4ca6f7f102
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2409054316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2409054316
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3916996330
Short name T352
Test name
Test status
Simulation time 116671181 ps
CPU time 10.26 seconds
Started Jun 21 05:14:22 PM PDT 24
Finished Jun 21 05:14:35 PM PDT 24
Peak memory 255392 kb
Host smart-5026f22c-db03-4d15-8ca1-8a85d24541b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916996330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3916996330
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2664745385
Short name T732
Test name
Test status
Simulation time 490960610 ps
CPU time 9.75 seconds
Started Jun 21 05:14:19 PM PDT 24
Finished Jun 21 05:14:30 PM PDT 24
Peak memory 237112 kb
Host smart-d19a71b8-05d4-4834-9b84-9d628455bd09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2664745385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2664745385
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1410794164
Short name T812
Test name
Test status
Simulation time 8741220 ps
CPU time 1.55 seconds
Started Jun 21 05:14:20 PM PDT 24
Finished Jun 21 05:14:24 PM PDT 24
Peak memory 237332 kb
Host smart-670bfe7c-c2d2-4967-8f25-13ab0dcfa148
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1410794164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1410794164
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2372814402
Short name T785
Test name
Test status
Simulation time 184357869 ps
CPU time 12.57 seconds
Started Jun 21 05:14:21 PM PDT 24
Finished Jun 21 05:14:36 PM PDT 24
Peak memory 248896 kb
Host smart-8c7e80ba-315b-4990-af7b-7e272bc1b97e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2372814402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2372814402
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.431808117
Short name T159
Test name
Test status
Simulation time 4644514856 ps
CPU time 172.24 seconds
Started Jun 21 05:14:22 PM PDT 24
Finished Jun 21 05:17:17 PM PDT 24
Peak memory 265756 kb
Host smart-ca82011e-1028-450b-a0d0-c7b42d0a1e8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=431808117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.431808117
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3034953805
Short name T137
Test name
Test status
Simulation time 8645205574 ps
CPU time 334.7 seconds
Started Jun 21 05:14:22 PM PDT 24
Finished Jun 21 05:20:00 PM PDT 24
Peak memory 265604 kb
Host smart-a22eeabd-2afb-47ae-8d12-df2a32442d00
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034953805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.3034953805
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3512552291
Short name T828
Test name
Test status
Simulation time 307474090 ps
CPU time 20.32 seconds
Started Jun 21 05:14:20 PM PDT 24
Finished Jun 21 05:14:43 PM PDT 24
Peak memory 248980 kb
Host smart-01c9b79f-b9e9-4379-8553-a84f9bcb8dc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3512552291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3512552291
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3141917250
Short name T807
Test name
Test status
Simulation time 9062550 ps
CPU time 1.51 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 05:14:48 PM PDT 24
Peak memory 237332 kb
Host smart-a247dc3e-5d85-423d-adb0-194358cf1e36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3141917250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3141917250
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3299566867
Short name T756
Test name
Test status
Simulation time 8839468 ps
CPU time 1.32 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 05:14:49 PM PDT 24
Peak memory 237332 kb
Host smart-af08f58c-af4a-4823-8685-8cc50d68697b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3299566867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3299566867
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2626514703
Short name T787
Test name
Test status
Simulation time 21315988 ps
CPU time 1.41 seconds
Started Jun 21 05:14:44 PM PDT 24
Finished Jun 21 05:14:49 PM PDT 24
Peak memory 237344 kb
Host smart-157e53d6-5cf1-4a78-a821-a31d8851d096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2626514703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2626514703
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.476634966
Short name T816
Test name
Test status
Simulation time 6679267 ps
CPU time 1.38 seconds
Started Jun 21 05:14:50 PM PDT 24
Finished Jun 21 05:14:56 PM PDT 24
Peak memory 235856 kb
Host smart-6da4b558-ba39-4572-bfd2-dd26055055c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=476634966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.476634966
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2421996224
Short name T167
Test name
Test status
Simulation time 18906125 ps
CPU time 1.46 seconds
Started Jun 21 05:14:44 PM PDT 24
Finished Jun 21 05:14:49 PM PDT 24
Peak memory 237324 kb
Host smart-c0668044-ab92-46d9-ab88-0eacb13f7329
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2421996224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2421996224
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3352499778
Short name T779
Test name
Test status
Simulation time 7347326 ps
CPU time 1.42 seconds
Started Jun 21 05:14:49 PM PDT 24
Finished Jun 21 05:14:55 PM PDT 24
Peak memory 237268 kb
Host smart-faf0524b-2a82-4c0d-a423-bf6fde7c207e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3352499778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3352499778
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2563143991
Short name T256
Test name
Test status
Simulation time 47842226 ps
CPU time 1.4 seconds
Started Jun 21 05:14:49 PM PDT 24
Finished Jun 21 05:14:55 PM PDT 24
Peak memory 236336 kb
Host smart-d1c90c45-6d71-41db-8097-064baef821ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2563143991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2563143991
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.571904504
Short name T799
Test name
Test status
Simulation time 6688501 ps
CPU time 1.48 seconds
Started Jun 21 05:14:49 PM PDT 24
Finished Jun 21 05:14:55 PM PDT 24
Peak memory 236336 kb
Host smart-ede1b75f-306c-4dcf-bb78-c9a6a650e6fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=571904504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.571904504
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1698951217
Short name T750
Test name
Test status
Simulation time 25360898 ps
CPU time 1.51 seconds
Started Jun 21 05:14:44 PM PDT 24
Finished Jun 21 05:14:49 PM PDT 24
Peak memory 237344 kb
Host smart-6d364008-b0b5-4d32-9809-3e3d42c6168b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1698951217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1698951217
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2895031137
Short name T825
Test name
Test status
Simulation time 17448810 ps
CPU time 1.33 seconds
Started Jun 21 05:14:41 PM PDT 24
Finished Jun 21 05:14:44 PM PDT 24
Peak memory 237344 kb
Host smart-79640d33-3516-400f-9ee4-f2dace0e56c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2895031137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2895031137
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2165045831
Short name T197
Test name
Test status
Simulation time 573569259 ps
CPU time 84.37 seconds
Started Jun 21 05:14:19 PM PDT 24
Finished Jun 21 05:15:45 PM PDT 24
Peak memory 237256 kb
Host smart-bde479a3-400b-4d5f-9f18-54a803fa3129
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2165045831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2165045831
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2337258795
Short name T802
Test name
Test status
Simulation time 3271300823 ps
CPU time 209.75 seconds
Started Jun 21 05:14:25 PM PDT 24
Finished Jun 21 05:17:57 PM PDT 24
Peak memory 240676 kb
Host smart-9130bae5-5301-4873-b0bb-8b21c8ded623
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2337258795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2337258795
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2857151208
Short name T737
Test name
Test status
Simulation time 80989896 ps
CPU time 3.6 seconds
Started Jun 21 05:14:22 PM PDT 24
Finished Jun 21 05:14:29 PM PDT 24
Peak memory 240692 kb
Host smart-c2c0a399-4de7-4c6d-b534-5e0fac7c8548
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2857151208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2857151208
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3062018986
Short name T829
Test name
Test status
Simulation time 1434451439 ps
CPU time 6.39 seconds
Started Jun 21 05:14:26 PM PDT 24
Finished Jun 21 05:14:34 PM PDT 24
Peak memory 240056 kb
Host smart-41b1a901-bc89-4686-8809-71cb47827246
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062018986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3062018986
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2518657439
Short name T814
Test name
Test status
Simulation time 20346712 ps
CPU time 3.75 seconds
Started Jun 21 05:14:23 PM PDT 24
Finished Jun 21 05:14:30 PM PDT 24
Peak memory 237236 kb
Host smart-eff2298f-d9d8-469b-ac13-f6d25e966204
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2518657439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2518657439
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1191110812
Short name T715
Test name
Test status
Simulation time 6618954 ps
CPU time 1.42 seconds
Started Jun 21 05:14:21 PM PDT 24
Finished Jun 21 05:14:25 PM PDT 24
Peak memory 236396 kb
Host smart-fae1d018-7b3a-4973-b7cb-ccafc0095896
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1191110812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1191110812
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2712603261
Short name T203
Test name
Test status
Simulation time 709195676 ps
CPU time 19.5 seconds
Started Jun 21 05:14:21 PM PDT 24
Finished Jun 21 05:14:43 PM PDT 24
Peak memory 240748 kb
Host smart-7abf0fc8-3280-491e-8fed-16f1aa1d07c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2712603261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2712603261
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3188990868
Short name T157
Test name
Test status
Simulation time 1069934488 ps
CPU time 100.95 seconds
Started Jun 21 05:14:20 PM PDT 24
Finished Jun 21 05:16:03 PM PDT 24
Peak memory 257116 kb
Host smart-c7dccd1c-e7ac-446c-b22e-6576cb71ff11
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3188990868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3188990868
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.724678620
Short name T149
Test name
Test status
Simulation time 8338679193 ps
CPU time 342.79 seconds
Started Jun 21 05:14:21 PM PDT 24
Finished Jun 21 05:20:07 PM PDT 24
Peak memory 273840 kb
Host smart-50072c80-9335-441a-8adf-41c46a84af94
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724678620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.724678620
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.4223583522
Short name T820
Test name
Test status
Simulation time 150517786 ps
CPU time 11.26 seconds
Started Jun 21 05:14:23 PM PDT 24
Finished Jun 21 05:14:38 PM PDT 24
Peak memory 248932 kb
Host smart-dbdf6d91-f92f-425e-a0af-369e65b50903
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4223583522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.4223583522
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3183117807
Short name T794
Test name
Test status
Simulation time 6657263 ps
CPU time 1.39 seconds
Started Jun 21 05:14:46 PM PDT 24
Finished Jun 21 05:14:51 PM PDT 24
Peak memory 236408 kb
Host smart-5c10d8a1-09eb-433d-9a0d-fa3d4e8ce32a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3183117807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3183117807
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.696316106
Short name T346
Test name
Test status
Simulation time 11458128 ps
CPU time 1.36 seconds
Started Jun 21 05:14:39 PM PDT 24
Finished Jun 21 05:14:43 PM PDT 24
Peak memory 235360 kb
Host smart-f3f75a31-acf3-4aef-87b0-eaf59eeb0cc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=696316106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.696316106
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2453600498
Short name T343
Test name
Test status
Simulation time 12799500 ps
CPU time 1.53 seconds
Started Jun 21 05:14:44 PM PDT 24
Finished Jun 21 05:14:49 PM PDT 24
Peak memory 237324 kb
Host smart-daff7503-e492-4606-994c-f27a4faffb18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2453600498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2453600498
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.872701241
Short name T752
Test name
Test status
Simulation time 7599143 ps
CPU time 1.32 seconds
Started Jun 21 05:14:47 PM PDT 24
Finished Jun 21 05:14:52 PM PDT 24
Peak memory 237340 kb
Host smart-099972e3-7b27-4d6d-b4e9-9220a01cd4c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=872701241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.872701241
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.609657868
Short name T793
Test name
Test status
Simulation time 30763303 ps
CPU time 1.37 seconds
Started Jun 21 05:14:47 PM PDT 24
Finished Jun 21 05:14:52 PM PDT 24
Peak memory 237332 kb
Host smart-227c556b-0780-422e-bcff-a6cc19f2e116
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=609657868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.609657868
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.647802886
Short name T347
Test name
Test status
Simulation time 12059443 ps
CPU time 1.42 seconds
Started Jun 21 05:14:47 PM PDT 24
Finished Jun 21 05:14:52 PM PDT 24
Peak memory 237332 kb
Host smart-653e4be5-89a0-4ebb-a05d-5718c793f99d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=647802886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.647802886
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1757157276
Short name T342
Test name
Test status
Simulation time 10544724 ps
CPU time 1.28 seconds
Started Jun 21 05:14:37 PM PDT 24
Finished Jun 21 05:14:40 PM PDT 24
Peak memory 237332 kb
Host smart-f214f667-f52f-4880-ba09-95e95685638d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1757157276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1757157276
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1937435799
Short name T344
Test name
Test status
Simulation time 11133258 ps
CPU time 1.38 seconds
Started Jun 21 05:14:45 PM PDT 24
Finished Jun 21 05:14:50 PM PDT 24
Peak memory 235360 kb
Host smart-e170ad1c-2212-45ab-bd0d-b7c817376a75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1937435799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1937435799
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3570454483
Short name T801
Test name
Test status
Simulation time 9190092 ps
CPU time 1.44 seconds
Started Jun 21 05:14:46 PM PDT 24
Finished Jun 21 05:14:52 PM PDT 24
Peak memory 236404 kb
Host smart-a8874232-69f1-40ce-89cd-2ec0623f67a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3570454483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3570454483
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2042507469
Short name T819
Test name
Test status
Simulation time 7488678 ps
CPU time 1.37 seconds
Started Jun 21 05:14:46 PM PDT 24
Finished Jun 21 05:14:52 PM PDT 24
Peak memory 235380 kb
Host smart-97461886-74da-47fa-9963-b2ff7659728f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2042507469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2042507469
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3734264962
Short name T730
Test name
Test status
Simulation time 4010114627 ps
CPU time 152.74 seconds
Started Jun 21 05:14:22 PM PDT 24
Finished Jun 21 05:16:58 PM PDT 24
Peak memory 240732 kb
Host smart-56c08662-3642-48ba-ac55-1b25781ac1ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3734264962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3734264962
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1494442737
Short name T817
Test name
Test status
Simulation time 4276724026 ps
CPU time 256.21 seconds
Started Jun 21 05:14:25 PM PDT 24
Finished Jun 21 05:18:44 PM PDT 24
Peak memory 237236 kb
Host smart-d9783781-4948-4c81-87c7-b276d057779d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1494442737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1494442737
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.648820202
Short name T743
Test name
Test status
Simulation time 27922065 ps
CPU time 4.14 seconds
Started Jun 21 05:14:22 PM PDT 24
Finished Jun 21 05:14:29 PM PDT 24
Peak memory 240696 kb
Host smart-35fca4f6-8a9d-425f-af22-e262534f3316
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=648820202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.648820202
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1751744388
Short name T824
Test name
Test status
Simulation time 78262024 ps
CPU time 7.4 seconds
Started Jun 21 05:14:26 PM PDT 24
Finished Jun 21 05:14:35 PM PDT 24
Peak memory 240676 kb
Host smart-8a882850-fbe8-4211-a61f-288f4d42b67b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751744388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1751744388
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3793558925
Short name T805
Test name
Test status
Simulation time 85350803 ps
CPU time 3.28 seconds
Started Jun 21 05:14:21 PM PDT 24
Finished Jun 21 05:14:28 PM PDT 24
Peak memory 239940 kb
Host smart-4432e96e-14ca-44e7-a85b-71e374801e1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3793558925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3793558925
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.805445111
Short name T763
Test name
Test status
Simulation time 9328302 ps
CPU time 1.29 seconds
Started Jun 21 05:14:20 PM PDT 24
Finished Jun 21 05:14:23 PM PDT 24
Peak memory 237344 kb
Host smart-73a726c8-04ac-441b-a832-1111886f06ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=805445111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.805445111
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2558452294
Short name T731
Test name
Test status
Simulation time 5397662404 ps
CPU time 48.38 seconds
Started Jun 21 05:14:23 PM PDT 24
Finished Jun 21 05:15:15 PM PDT 24
Peak memory 245604 kb
Host smart-fb4ace6b-8b87-4023-95ab-81310c5557a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2558452294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2558452294
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2001497684
Short name T126
Test name
Test status
Simulation time 10010213896 ps
CPU time 181.21 seconds
Started Jun 21 05:14:20 PM PDT 24
Finished Jun 21 05:17:24 PM PDT 24
Peak memory 265804 kb
Host smart-e83573f7-da34-41c0-82f9-dde19ec43aeb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2001497684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2001497684
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.679475479
Short name T755
Test name
Test status
Simulation time 187106675 ps
CPU time 7.04 seconds
Started Jun 21 05:14:22 PM PDT 24
Finished Jun 21 05:14:32 PM PDT 24
Peak memory 251020 kb
Host smart-ecc2a767-6f0b-444d-bc8c-82057079f029
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=679475479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.679475479
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3156261295
Short name T803
Test name
Test status
Simulation time 8573646 ps
CPU time 1.34 seconds
Started Jun 21 05:14:44 PM PDT 24
Finished Jun 21 05:14:49 PM PDT 24
Peak memory 236384 kb
Host smart-7b862cf1-a837-4ca4-b6e0-cf7d347643c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3156261295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3156261295
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2188967109
Short name T786
Test name
Test status
Simulation time 6055517 ps
CPU time 1.4 seconds
Started Jun 21 05:14:47 PM PDT 24
Finished Jun 21 05:14:53 PM PDT 24
Peak memory 237332 kb
Host smart-8be6fcc0-74be-4e99-b8ad-838b8a9b5b16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2188967109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2188967109
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2841247597
Short name T792
Test name
Test status
Simulation time 9021066 ps
CPU time 1.46 seconds
Started Jun 21 05:14:51 PM PDT 24
Finished Jun 21 05:14:58 PM PDT 24
Peak memory 235360 kb
Host smart-7d3a0485-a775-4449-be6f-b37d53b994de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2841247597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2841247597
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3544690686
Short name T720
Test name
Test status
Simulation time 7182451 ps
CPU time 1.36 seconds
Started Jun 21 05:14:44 PM PDT 24
Finished Jun 21 05:14:49 PM PDT 24
Peak memory 237292 kb
Host smart-2feec237-9d29-4c96-9e3f-83f9b63a0fdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3544690686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3544690686
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1486564091
Short name T738
Test name
Test status
Simulation time 39618587 ps
CPU time 1.39 seconds
Started Jun 21 05:14:46 PM PDT 24
Finished Jun 21 05:14:51 PM PDT 24
Peak memory 236404 kb
Host smart-8449f079-01b6-4e77-93c2-e0d3868b02ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1486564091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1486564091
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3350856472
Short name T773
Test name
Test status
Simulation time 6355734 ps
CPU time 1.46 seconds
Started Jun 21 05:14:45 PM PDT 24
Finished Jun 21 05:14:50 PM PDT 24
Peak memory 237456 kb
Host smart-a78327f9-ceba-4d0a-a212-23a9ba0b55e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3350856472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3350856472
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.4169095128
Short name T768
Test name
Test status
Simulation time 8530004 ps
CPU time 1.51 seconds
Started Jun 21 05:14:45 PM PDT 24
Finished Jun 21 05:14:50 PM PDT 24
Peak memory 237332 kb
Host smart-18313100-7abf-4dc8-96b2-3338c0edc992
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4169095128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.4169095128
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1417517900
Short name T722
Test name
Test status
Simulation time 6856664 ps
CPU time 1.49 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 05:14:47 PM PDT 24
Peak memory 236336 kb
Host smart-358fa965-4812-4b50-a28e-0acc0f408541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1417517900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1417517900
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.4232308295
Short name T246
Test name
Test status
Simulation time 8795297 ps
CPU time 1.52 seconds
Started Jun 21 05:14:52 PM PDT 24
Finished Jun 21 05:14:58 PM PDT 24
Peak memory 237312 kb
Host smart-5ae55604-a5a8-4606-92f7-f27071f4368a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4232308295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.4232308295
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1019894215
Short name T764
Test name
Test status
Simulation time 6356095 ps
CPU time 1.39 seconds
Started Jun 21 05:14:44 PM PDT 24
Finished Jun 21 05:14:49 PM PDT 24
Peak memory 237332 kb
Host smart-4d65c670-c201-4a13-99f6-b3fcde95a6d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1019894215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1019894215
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3654525110
Short name T349
Test name
Test status
Simulation time 358973577 ps
CPU time 8.17 seconds
Started Jun 21 05:14:22 PM PDT 24
Finished Jun 21 05:14:34 PM PDT 24
Peak memory 240656 kb
Host smart-863529f1-73a6-4612-b4a2-6d2baa80cee6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654525110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3654525110
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3324412189
Short name T753
Test name
Test status
Simulation time 89913937 ps
CPU time 5.63 seconds
Started Jun 21 05:14:23 PM PDT 24
Finished Jun 21 05:14:31 PM PDT 24
Peak memory 237248 kb
Host smart-f0fafd49-7659-4884-917c-6834b836e80c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3324412189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3324412189
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.323643516
Short name T769
Test name
Test status
Simulation time 9369973 ps
CPU time 1.37 seconds
Started Jun 21 05:14:23 PM PDT 24
Finished Jun 21 05:14:27 PM PDT 24
Peak memory 235372 kb
Host smart-b6a05770-c8b6-4f5e-abfb-3dcc09746f6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=323643516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.323643516
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3993392188
Short name T781
Test name
Test status
Simulation time 541707271 ps
CPU time 38.59 seconds
Started Jun 21 05:14:24 PM PDT 24
Finished Jun 21 05:15:05 PM PDT 24
Peak memory 248964 kb
Host smart-e6819d65-0f12-4a4d-ab97-1bbf00d4aa79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3993392188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3993392188
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3460194312
Short name T723
Test name
Test status
Simulation time 958731897 ps
CPU time 17.54 seconds
Started Jun 21 05:14:23 PM PDT 24
Finished Jun 21 05:14:44 PM PDT 24
Peak memory 249020 kb
Host smart-b3e6535c-73f1-4165-b139-cb746da34bbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3460194312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3460194312
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2848301711
Short name T809
Test name
Test status
Simulation time 1244769019 ps
CPU time 8.6 seconds
Started Jun 21 05:14:24 PM PDT 24
Finished Jun 21 05:14:35 PM PDT 24
Peak memory 240916 kb
Host smart-9d75bf5e-1df6-4118-aace-85aaaca6e8c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848301711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2848301711
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1641366285
Short name T733
Test name
Test status
Simulation time 33920994 ps
CPU time 5.18 seconds
Started Jun 21 05:14:23 PM PDT 24
Finished Jun 21 05:14:31 PM PDT 24
Peak memory 240640 kb
Host smart-35eba6af-0a2a-487e-acc4-61dfa8f468e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1641366285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1641366285
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2850194526
Short name T771
Test name
Test status
Simulation time 9656438 ps
CPU time 1.38 seconds
Started Jun 21 05:14:21 PM PDT 24
Finished Jun 21 05:14:25 PM PDT 24
Peak memory 237332 kb
Host smart-40fad2ee-1f28-48a1-bb69-1db4ad36639f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2850194526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2850194526
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2749608005
Short name T804
Test name
Test status
Simulation time 672700832 ps
CPU time 40.2 seconds
Started Jun 21 05:14:22 PM PDT 24
Finished Jun 21 05:15:05 PM PDT 24
Peak memory 248964 kb
Host smart-a2394c95-b713-45a8-a992-076dc5fad3d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2749608005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2749608005
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3528671496
Short name T123
Test name
Test status
Simulation time 735445621 ps
CPU time 86.45 seconds
Started Jun 21 05:14:24 PM PDT 24
Finished Jun 21 05:15:54 PM PDT 24
Peak memory 257404 kb
Host smart-710b2182-504a-42ac-93e7-c0e689478f46
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3528671496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3528671496
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3626083221
Short name T712
Test name
Test status
Simulation time 95691994 ps
CPU time 12.94 seconds
Started Jun 21 05:14:24 PM PDT 24
Finished Jun 21 05:14:40 PM PDT 24
Peak memory 248812 kb
Host smart-7017315c-e47f-4fd7-893f-62b8b55bd5c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3626083221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3626083221
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3483074723
Short name T727
Test name
Test status
Simulation time 82133614 ps
CPU time 5.98 seconds
Started Jun 21 05:14:38 PM PDT 24
Finished Jun 21 05:14:45 PM PDT 24
Peak memory 239768 kb
Host smart-88255d0b-57e8-4c3b-ba80-c7168a0cdabb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483074723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3483074723
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1196628691
Short name T815
Test name
Test status
Simulation time 63646045 ps
CPU time 5.13 seconds
Started Jun 21 05:14:29 PM PDT 24
Finished Jun 21 05:14:35 PM PDT 24
Peak memory 237244 kb
Host smart-89bf5e89-c4a1-4fc6-aed3-69ac58e54f27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1196628691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1196628691
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1568403920
Short name T734
Test name
Test status
Simulation time 6119689 ps
CPU time 1.45 seconds
Started Jun 21 05:14:27 PM PDT 24
Finished Jun 21 05:14:30 PM PDT 24
Peak memory 235380 kb
Host smart-1ac67980-3beb-47b4-84f0-db36601cad04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1568403920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1568403920
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2910013337
Short name T780
Test name
Test status
Simulation time 471885593 ps
CPU time 10.94 seconds
Started Jun 21 05:14:29 PM PDT 24
Finished Jun 21 05:14:41 PM PDT 24
Peak memory 245540 kb
Host smart-2cf6c21e-dcf8-4eda-b925-fb9f293de444
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2910013337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2910013337
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1792944252
Short name T142
Test name
Test status
Simulation time 25399105541 ps
CPU time 180.85 seconds
Started Jun 21 05:14:24 PM PDT 24
Finished Jun 21 05:17:28 PM PDT 24
Peak memory 265724 kb
Host smart-9c696aac-3e96-49c1-a664-68124b891b29
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1792944252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1792944252
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.4065575068
Short name T143
Test name
Test status
Simulation time 37130900963 ps
CPU time 638.37 seconds
Started Jun 21 05:14:23 PM PDT 24
Finished Jun 21 05:25:05 PM PDT 24
Peak memory 268484 kb
Host smart-c8d32e69-07ca-47fc-9e85-066802c88de0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065575068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.4065575068
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1727210750
Short name T729
Test name
Test status
Simulation time 129273313 ps
CPU time 11.33 seconds
Started Jun 21 05:14:22 PM PDT 24
Finished Jun 21 05:14:37 PM PDT 24
Peak memory 249012 kb
Host smart-2569eb0c-68db-40a8-b8eb-bf79075ecf06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1727210750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1727210750
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2498740236
Short name T746
Test name
Test status
Simulation time 69558407 ps
CPU time 5.96 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 05:14:53 PM PDT 24
Peak memory 238268 kb
Host smart-03c9e96c-ad91-49d7-a195-a8466a922053
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498740236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2498740236
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.441874114
Short name T796
Test name
Test status
Simulation time 195341230 ps
CPU time 7.67 seconds
Started Jun 21 05:14:30 PM PDT 24
Finished Jun 21 05:14:39 PM PDT 24
Peak memory 240648 kb
Host smart-0a6f3219-f26f-458c-bfe0-5297cd4c8618
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=441874114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.441874114
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1395368798
Short name T784
Test name
Test status
Simulation time 11025789 ps
CPU time 1.6 seconds
Started Jun 21 05:14:29 PM PDT 24
Finished Jun 21 05:14:32 PM PDT 24
Peak memory 237332 kb
Host smart-202eb83c-72d1-4c4e-b102-c37c6b8d4f14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1395368798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1395368798
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3498416573
Short name T751
Test name
Test status
Simulation time 2531787492 ps
CPU time 38.06 seconds
Started Jun 21 05:14:37 PM PDT 24
Finished Jun 21 05:15:16 PM PDT 24
Peak memory 245584 kb
Host smart-fec74f94-9b0a-4fc6-98de-b23e32c8a904
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3498416573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.3498416573
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3130506976
Short name T742
Test name
Test status
Simulation time 62942680 ps
CPU time 9.9 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 05:14:57 PM PDT 24
Peak memory 248888 kb
Host smart-95e1f63a-a103-4482-844c-5ffcb9e1f046
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3130506976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3130506976
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1108396030
Short name T760
Test name
Test status
Simulation time 646167457 ps
CPU time 6.53 seconds
Started Jun 21 05:14:29 PM PDT 24
Finished Jun 21 05:14:37 PM PDT 24
Peak memory 240140 kb
Host smart-6c47e7d3-0616-4abb-8618-609b61744993
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108396030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1108396030
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3089307701
Short name T350
Test name
Test status
Simulation time 36817950 ps
CPU time 5.5 seconds
Started Jun 21 05:14:30 PM PDT 24
Finished Jun 21 05:14:37 PM PDT 24
Peak memory 240648 kb
Host smart-8d49567f-6640-42c6-a8e1-a8bb44f897de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3089307701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3089307701
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1936763244
Short name T808
Test name
Test status
Simulation time 11126031 ps
CPU time 1.4 seconds
Started Jun 21 05:14:35 PM PDT 24
Finished Jun 21 05:14:38 PM PDT 24
Peak memory 236404 kb
Host smart-b173bc89-53a7-482c-877f-36553fb14c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1936763244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1936763244
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3277539853
Short name T798
Test name
Test status
Simulation time 1054144476 ps
CPU time 18.07 seconds
Started Jun 21 05:14:40 PM PDT 24
Finished Jun 21 05:15:00 PM PDT 24
Peak memory 248948 kb
Host smart-1a7b23b6-c9e8-44a1-baa1-994caa223211
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3277539853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.3277539853
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.4080617639
Short name T154
Test name
Test status
Simulation time 8710610508 ps
CPU time 179.17 seconds
Started Jun 21 05:14:38 PM PDT 24
Finished Jun 21 05:17:40 PM PDT 24
Peak memory 265652 kb
Host smart-30164cb8-88f9-42d3-951e-9a8376d0a2a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4080617639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.4080617639
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.181361831
Short name T135
Test name
Test status
Simulation time 2324486727 ps
CPU time 339.96 seconds
Started Jun 21 05:14:30 PM PDT 24
Finished Jun 21 05:20:12 PM PDT 24
Peak memory 273108 kb
Host smart-b34d44f1-8b8a-481f-b53f-8c5759ffab92
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181361831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.181361831
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3444403743
Short name T714
Test name
Test status
Simulation time 112783410 ps
CPU time 7.79 seconds
Started Jun 21 05:14:39 PM PDT 24
Finished Jun 21 05:14:49 PM PDT 24
Peak memory 248516 kb
Host smart-9654734b-3b8b-4716-9d47-ecc6689593ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3444403743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3444403743
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3828509702
Short name T383
Test name
Test status
Simulation time 101472387652 ps
CPU time 3015.4 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 06:05:02 PM PDT 24
Peak memory 287420 kb
Host smart-9da6913d-b9d0-4996-989a-a310c54b3de3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828509702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3828509702
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2749419284
Short name T477
Test name
Test status
Simulation time 190281422 ps
CPU time 10.49 seconds
Started Jun 21 05:14:51 PM PDT 24
Finished Jun 21 05:15:07 PM PDT 24
Peak memory 249000 kb
Host smart-ac922456-c120-41f4-9880-f6cb7909f55c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2749419284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2749419284
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2626172387
Short name T431
Test name
Test status
Simulation time 22722952341 ps
CPU time 126.17 seconds
Started Jun 21 05:14:51 PM PDT 24
Finished Jun 21 05:17:02 PM PDT 24
Peak memory 251308 kb
Host smart-cd3b1a17-286e-48ed-8554-03effd0eac24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26261
72387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2626172387
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2883254536
Short name T427
Test name
Test status
Simulation time 4605375645 ps
CPU time 66.57 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 05:15:52 PM PDT 24
Peak memory 256196 kb
Host smart-ea8f104d-06a8-4de0-9e68-17f26657a1b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28832
54536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2883254536
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2352789861
Short name T622
Test name
Test status
Simulation time 119391169009 ps
CPU time 1234.74 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 05:35:21 PM PDT 24
Peak memory 272612 kb
Host smart-30d4c7b2-3458-41ff-8e41-0bdaafc04092
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352789861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2352789861
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3926166048
Short name T391
Test name
Test status
Simulation time 7954497057 ps
CPU time 843.94 seconds
Started Jun 21 05:14:47 PM PDT 24
Finished Jun 21 05:28:56 PM PDT 24
Peak memory 266564 kb
Host smart-a9fcad77-02fa-4c8f-8329-a133c5d8e340
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926166048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3926166048
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1712302063
Short name T318
Test name
Test status
Simulation time 14230395943 ps
CPU time 158.59 seconds
Started Jun 21 05:14:48 PM PDT 24
Finished Jun 21 05:17:31 PM PDT 24
Peak memory 248504 kb
Host smart-7a69f42c-4dbd-4332-bca0-704527ecf708
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712302063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1712302063
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3704107583
Short name T101
Test name
Test status
Simulation time 142355543 ps
CPU time 13.33 seconds
Started Jun 21 05:14:45 PM PDT 24
Finished Jun 21 05:15:02 PM PDT 24
Peak memory 249044 kb
Host smart-3d9556a9-1191-4c54-88e7-786453045d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37041
07583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3704107583
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.1786042968
Short name T572
Test name
Test status
Simulation time 29951020 ps
CPU time 2.95 seconds
Started Jun 21 05:14:50 PM PDT 24
Finished Jun 21 05:14:58 PM PDT 24
Peak memory 239712 kb
Host smart-b8ee11a4-2376-4c15-83ce-bfce0a608f1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17860
42968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1786042968
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2961475539
Short name T641
Test name
Test status
Simulation time 271782602 ps
CPU time 30.96 seconds
Started Jun 21 05:14:43 PM PDT 24
Finished Jun 21 05:15:18 PM PDT 24
Peak memory 247856 kb
Host smart-e28bc531-ba38-4b7f-8554-22a315a19653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29614
75539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2961475539
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3980972561
Short name T687
Test name
Test status
Simulation time 818003385 ps
CPU time 18.12 seconds
Started Jun 21 05:14:50 PM PDT 24
Finished Jun 21 05:15:13 PM PDT 24
Peak memory 248996 kb
Host smart-0b42c8cc-23ef-4524-8271-7c4aa8df6220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39809
72561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3980972561
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2973236274
Short name T417
Test name
Test status
Simulation time 212699736102 ps
CPU time 1623.72 seconds
Started Jun 21 05:14:52 PM PDT 24
Finished Jun 21 05:42:01 PM PDT 24
Peak memory 298244 kb
Host smart-3a7eb58a-df1a-4e0e-98c0-4a0e17393558
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973236274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2973236274
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.2615225989
Short name T526
Test name
Test status
Simulation time 72692352953 ps
CPU time 6630.03 seconds
Started Jun 21 05:14:56 PM PDT 24
Finished Jun 21 07:05:30 PM PDT 24
Peak memory 338896 kb
Host smart-9123c1ed-22ad-429d-bc06-f65e2292a9b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615225989 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.2615225989
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1063143657
Short name T429
Test name
Test status
Simulation time 40527767926 ps
CPU time 1279.88 seconds
Started Jun 21 05:14:52 PM PDT 24
Finished Jun 21 05:36:17 PM PDT 24
Peak memory 273128 kb
Host smart-f38aa1ff-da6b-496e-b1a9-4892506d9112
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063143657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1063143657
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.222588541
Short name T559
Test name
Test status
Simulation time 392392811 ps
CPU time 17.78 seconds
Started Jun 21 05:14:51 PM PDT 24
Finished Jun 21 05:15:13 PM PDT 24
Peak memory 249072 kb
Host smart-8ca48efd-8b6a-4fd6-8a1f-2bdc690f33f8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=222588541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.222588541
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.385941712
Short name T288
Test name
Test status
Simulation time 1675942527 ps
CPU time 115.62 seconds
Started Jun 21 05:14:53 PM PDT 24
Finished Jun 21 05:16:53 PM PDT 24
Peak memory 250100 kb
Host smart-7805831a-cac1-408b-85b9-e5b8c0e40ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38594
1712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.385941712
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.697602524
Short name T655
Test name
Test status
Simulation time 475060985 ps
CPU time 22.44 seconds
Started Jun 21 05:14:52 PM PDT 24
Finished Jun 21 05:15:19 PM PDT 24
Peak memory 248948 kb
Host smart-bf9687b0-1460-435a-ba51-b2e5c5d0d85f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69760
2524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.697602524
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.455033913
Short name T530
Test name
Test status
Simulation time 27802597056 ps
CPU time 1606.28 seconds
Started Jun 21 05:14:52 PM PDT 24
Finished Jun 21 05:41:43 PM PDT 24
Peak memory 273696 kb
Host smart-148816b4-c9fa-4b08-93d2-fe1246f2a7ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455033913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.455033913
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.4284765696
Short name T482
Test name
Test status
Simulation time 123895732232 ps
CPU time 2359.77 seconds
Started Jun 21 05:14:49 PM PDT 24
Finished Jun 21 05:54:14 PM PDT 24
Peak memory 290016 kb
Host smart-85bf1b50-3bc5-40cd-88a9-1dda5376e77b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284765696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.4284765696
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.730006574
Short name T444
Test name
Test status
Simulation time 40291969 ps
CPU time 4.88 seconds
Started Jun 21 05:14:50 PM PDT 24
Finished Jun 21 05:14:59 PM PDT 24
Peak memory 249044 kb
Host smart-e21cbc54-2f34-4bec-8edf-21d7246d050b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73000
6574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.730006574
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1045507269
Short name T83
Test name
Test status
Simulation time 369329208 ps
CPU time 17.2 seconds
Started Jun 21 05:14:49 PM PDT 24
Finished Jun 21 05:15:11 PM PDT 24
Peak memory 255968 kb
Host smart-cd66b978-0c99-4638-84b2-115b2cd13f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10455
07269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1045507269
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1794657825
Short name T42
Test name
Test status
Simulation time 706694093 ps
CPU time 19.62 seconds
Started Jun 21 05:14:48 PM PDT 24
Finished Jun 21 05:15:12 PM PDT 24
Peak memory 274832 kb
Host smart-5a51d1a3-3e77-4fd7-9b35-50a170a2aa4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1794657825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1794657825
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1442693320
Short name T373
Test name
Test status
Simulation time 171232181 ps
CPU time 8.06 seconds
Started Jun 21 05:14:51 PM PDT 24
Finished Jun 21 05:15:05 PM PDT 24
Peak memory 247852 kb
Host smart-8ccb1624-74ee-40cf-bc6d-dfdda1e3e285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14426
93320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1442693320
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2720160085
Short name T421
Test name
Test status
Simulation time 443684667 ps
CPU time 11.98 seconds
Started Jun 21 05:15:00 PM PDT 24
Finished Jun 21 05:15:14 PM PDT 24
Peak memory 248940 kb
Host smart-210065f7-f4fa-4a74-98ce-3e642f7bed47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27201
60085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2720160085
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.1928599280
Short name T269
Test name
Test status
Simulation time 133255408720 ps
CPU time 2116.03 seconds
Started Jun 21 05:14:51 PM PDT 24
Finished Jun 21 05:50:12 PM PDT 24
Peak memory 287508 kb
Host smart-310ae981-38b1-429d-9abf-a8d784b0b106
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928599280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.1928599280
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.541879897
Short name T102
Test name
Test status
Simulation time 8979794478 ps
CPU time 803.04 seconds
Started Jun 21 05:15:05 PM PDT 24
Finished Jun 21 05:28:29 PM PDT 24
Peak memory 265388 kb
Host smart-96995d53-12c3-4158-8380-92ceab972908
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541879897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.541879897
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.342900682
Short name T579
Test name
Test status
Simulation time 673132345 ps
CPU time 9.93 seconds
Started Jun 21 05:15:19 PM PDT 24
Finished Jun 21 05:15:31 PM PDT 24
Peak memory 249016 kb
Host smart-42314fda-db00-4ace-a4cc-00b468de1eac
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=342900682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.342900682
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3241352568
Short name T287
Test name
Test status
Simulation time 2081436963 ps
CPU time 62.09 seconds
Started Jun 21 05:15:06 PM PDT 24
Finished Jun 21 05:16:10 PM PDT 24
Peak memory 257224 kb
Host smart-a7036102-a11b-4aaa-8d75-7fc1a2db56e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32413
52568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3241352568
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.794853485
Short name T115
Test name
Test status
Simulation time 262041424 ps
CPU time 20.3 seconds
Started Jun 21 05:15:09 PM PDT 24
Finished Jun 21 05:15:30 PM PDT 24
Peak memory 255068 kb
Host smart-661253de-c4e7-4f2d-9bbb-7a1689b65502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79485
3485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.794853485
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1736534585
Short name T506
Test name
Test status
Simulation time 79501900935 ps
CPU time 1356.14 seconds
Started Jun 21 05:15:07 PM PDT 24
Finished Jun 21 05:37:45 PM PDT 24
Peak memory 266508 kb
Host smart-ac99ed81-5ad7-4cc4-936c-3c997ab0bae8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736534585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1736534585
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3956708344
Short name T320
Test name
Test status
Simulation time 4776508645 ps
CPU time 200.17 seconds
Started Jun 21 05:15:06 PM PDT 24
Finished Jun 21 05:18:29 PM PDT 24
Peak memory 248320 kb
Host smart-f632aec8-19c5-4969-a339-df8f278c5a0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956708344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3956708344
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1172270254
Short name T573
Test name
Test status
Simulation time 187200553 ps
CPU time 12.59 seconds
Started Jun 21 05:15:10 PM PDT 24
Finished Jun 21 05:15:23 PM PDT 24
Peak memory 254648 kb
Host smart-5644585d-b589-427c-9513-c59b702a61bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11722
70254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1172270254
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3437701402
Short name T283
Test name
Test status
Simulation time 426884602 ps
CPU time 36.23 seconds
Started Jun 21 05:15:08 PM PDT 24
Finished Jun 21 05:15:46 PM PDT 24
Peak memory 247944 kb
Host smart-58d9c3cc-064a-42c3-a7c8-b1f8aea51558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34377
01402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3437701402
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2846632162
Short name T284
Test name
Test status
Simulation time 3414907195 ps
CPU time 59.53 seconds
Started Jun 21 05:15:05 PM PDT 24
Finished Jun 21 05:16:05 PM PDT 24
Peak memory 256884 kb
Host smart-cd717b0c-8c8b-4d94-b5f9-a3bd26a1ff61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28466
32162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2846632162
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2090653559
Short name T478
Test name
Test status
Simulation time 211234009 ps
CPU time 19.14 seconds
Started Jun 21 05:15:10 PM PDT 24
Finished Jun 21 05:15:30 PM PDT 24
Peak memory 256116 kb
Host smart-32af66ae-22b1-4f67-9ee5-7bac0509bc36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20906
53559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2090653559
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.4195623113
Short name T558
Test name
Test status
Simulation time 211749598612 ps
CPU time 3755.16 seconds
Started Jun 21 05:15:16 PM PDT 24
Finished Jun 21 06:17:53 PM PDT 24
Peak memory 306072 kb
Host smart-5224794a-3651-4788-b18d-1b8f1c5efd65
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195623113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.4195623113
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.853514206
Short name T196
Test name
Test status
Simulation time 41252834374 ps
CPU time 747.51 seconds
Started Jun 21 05:15:20 PM PDT 24
Finished Jun 21 05:27:49 PM PDT 24
Peak memory 271276 kb
Host smart-55c050f1-55b1-4167-9b23-c8a8f2d0d0c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853514206 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.853514206
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3402881403
Short name T217
Test name
Test status
Simulation time 46654642 ps
CPU time 3.55 seconds
Started Jun 21 05:15:17 PM PDT 24
Finished Jun 21 05:15:22 PM PDT 24
Peak memory 249164 kb
Host smart-0257f2ca-51b3-4c81-b60f-abf7c4726369
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3402881403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3402881403
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.898484200
Short name T701
Test name
Test status
Simulation time 32338517609 ps
CPU time 1934.06 seconds
Started Jun 21 05:15:18 PM PDT 24
Finished Jun 21 05:47:34 PM PDT 24
Peak memory 284472 kb
Host smart-de3b045a-35c5-4e05-b10f-7173c3fe58f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898484200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.898484200
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1298075804
Short name T436
Test name
Test status
Simulation time 688387706 ps
CPU time 16.94 seconds
Started Jun 21 05:15:15 PM PDT 24
Finished Jun 21 05:15:33 PM PDT 24
Peak memory 249032 kb
Host smart-550eba63-83a0-4eb6-8afe-00d07995ce77
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1298075804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1298075804
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.4135964962
Short name T547
Test name
Test status
Simulation time 3945715581 ps
CPU time 93.51 seconds
Started Jun 21 05:15:14 PM PDT 24
Finished Jun 21 05:16:49 PM PDT 24
Peak memory 257260 kb
Host smart-40afc2c4-7a1e-4bbf-8d95-a90a20a158fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41359
64962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.4135964962
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3205832465
Short name T281
Test name
Test status
Simulation time 556413308 ps
CPU time 13.84 seconds
Started Jun 21 05:15:20 PM PDT 24
Finished Jun 21 05:15:35 PM PDT 24
Peak memory 257112 kb
Host smart-66d48a99-fa6b-489c-9375-a659fd471f93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32058
32465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3205832465
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3578109885
Short name T296
Test name
Test status
Simulation time 34220071568 ps
CPU time 680.22 seconds
Started Jun 21 05:15:14 PM PDT 24
Finished Jun 21 05:26:36 PM PDT 24
Peak memory 265504 kb
Host smart-a34ed3cd-a05b-48a2-83fa-48e16e471046
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578109885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3578109885
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2768414333
Short name T398
Test name
Test status
Simulation time 2359605246 ps
CPU time 28.75 seconds
Started Jun 21 05:15:16 PM PDT 24
Finished Jun 21 05:15:45 PM PDT 24
Peak memory 249204 kb
Host smart-6677f816-cca9-4278-80fc-8c9caa9cd396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27684
14333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2768414333
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.25434504
Short name T77
Test name
Test status
Simulation time 334103900 ps
CPU time 17.94 seconds
Started Jun 21 05:15:20 PM PDT 24
Finished Jun 21 05:15:39 PM PDT 24
Peak memory 248432 kb
Host smart-adcc7e06-8247-4d3c-8451-6f4628a165a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25434
504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.25434504
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1055733352
Short name T413
Test name
Test status
Simulation time 1206908291 ps
CPU time 25.86 seconds
Started Jun 21 05:15:16 PM PDT 24
Finished Jun 21 05:15:43 PM PDT 24
Peak memory 248980 kb
Host smart-1352abff-64ce-46be-b561-445eece76051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10557
33352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1055733352
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2096854134
Short name T52
Test name
Test status
Simulation time 34333500 ps
CPU time 3.35 seconds
Started Jun 21 05:15:20 PM PDT 24
Finished Jun 21 05:15:25 PM PDT 24
Peak memory 248708 kb
Host smart-6d6c2b85-4d1a-4a8f-b5db-111fd45087d0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2096854134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2096854134
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3108229683
Short name T644
Test name
Test status
Simulation time 71861818345 ps
CPU time 2268.67 seconds
Started Jun 21 05:15:19 PM PDT 24
Finished Jun 21 05:53:09 PM PDT 24
Peak memory 289508 kb
Host smart-b46dfc09-5e1f-4da3-9f20-c910979eac5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108229683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3108229683
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3301912059
Short name T473
Test name
Test status
Simulation time 188463932 ps
CPU time 9.71 seconds
Started Jun 21 05:15:18 PM PDT 24
Finished Jun 21 05:15:29 PM PDT 24
Peak memory 248956 kb
Host smart-8e8153f0-f38a-45dc-84b7-ae6dec2bea03
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3301912059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3301912059
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3512043251
Short name T651
Test name
Test status
Simulation time 32755401063 ps
CPU time 243.42 seconds
Started Jun 21 05:15:15 PM PDT 24
Finished Jun 21 05:19:19 PM PDT 24
Peak memory 257288 kb
Host smart-f812e1b8-1532-4960-91db-850dc578df14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35120
43251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3512043251
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2591527071
Short name T587
Test name
Test status
Simulation time 513278060 ps
CPU time 30.74 seconds
Started Jun 21 05:15:15 PM PDT 24
Finished Jun 21 05:15:47 PM PDT 24
Peak memory 249284 kb
Host smart-af308dbe-5f60-42a5-ae87-732426fb3ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25915
27071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2591527071
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2528483882
Short name T47
Test name
Test status
Simulation time 128737586744 ps
CPU time 1948.12 seconds
Started Jun 21 05:15:21 PM PDT 24
Finished Jun 21 05:47:50 PM PDT 24
Peak memory 281836 kb
Host smart-a06bff56-2016-4280-a7bf-4405f98c0f7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528483882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2528483882
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.591726943
Short name T49
Test name
Test status
Simulation time 14789815851 ps
CPU time 1448.41 seconds
Started Jun 21 05:15:17 PM PDT 24
Finished Jun 21 05:39:27 PM PDT 24
Peak memory 288596 kb
Host smart-2d03649e-1d0b-4a6a-8dcc-e45f2b05aaf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591726943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.591726943
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3716195422
Short name T433
Test name
Test status
Simulation time 3369343400 ps
CPU time 33.07 seconds
Started Jun 21 05:15:19 PM PDT 24
Finished Jun 21 05:15:53 PM PDT 24
Peak memory 256824 kb
Host smart-c156ec4d-bcbf-4c24-80a0-73e4027fcf76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37161
95422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3716195422
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.581242608
Short name T620
Test name
Test status
Simulation time 599334302 ps
CPU time 33.37 seconds
Started Jun 21 05:15:14 PM PDT 24
Finished Jun 21 05:15:49 PM PDT 24
Peak memory 249208 kb
Host smart-9f80c51a-2d54-4c0b-ba28-755caf52d116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58124
2608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.581242608
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2996312464
Short name T258
Test name
Test status
Simulation time 1344421780 ps
CPU time 9.19 seconds
Started Jun 21 05:15:20 PM PDT 24
Finished Jun 21 05:15:31 PM PDT 24
Peak memory 247840 kb
Host smart-172eb52c-42f0-47d0-b27c-4dd80f3f1664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29963
12464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2996312464
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3271043572
Short name T567
Test name
Test status
Simulation time 1997367918 ps
CPU time 58.82 seconds
Started Jun 21 05:15:17 PM PDT 24
Finished Jun 21 05:16:18 PM PDT 24
Peak memory 257208 kb
Host smart-11c17526-091e-4232-aec4-0ff7ed29dec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32710
43572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3271043572
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1586338428
Short name T294
Test name
Test status
Simulation time 8636196029 ps
CPU time 955.34 seconds
Started Jun 21 05:15:16 PM PDT 24
Finished Jun 21 05:31:12 PM PDT 24
Peak memory 285680 kb
Host smart-738aaf1e-0bce-4c73-abe3-c0c091144c7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586338428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1586338428
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2666967580
Short name T384
Test name
Test status
Simulation time 3768811334 ps
CPU time 214.62 seconds
Started Jun 21 05:15:20 PM PDT 24
Finished Jun 21 05:18:57 PM PDT 24
Peak memory 257232 kb
Host smart-65aec132-e149-4b0f-95ad-3a048372b6a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26669
67580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2666967580
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3354412407
Short name T86
Test name
Test status
Simulation time 401229387 ps
CPU time 25.19 seconds
Started Jun 21 05:15:17 PM PDT 24
Finished Jun 21 05:15:44 PM PDT 24
Peak memory 256876 kb
Host smart-7162b65a-68c4-43a2-9584-5747d43f95ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33544
12407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3354412407
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.86804288
Short name T406
Test name
Test status
Simulation time 15172733946 ps
CPU time 740.39 seconds
Started Jun 21 05:15:24 PM PDT 24
Finished Jun 21 05:27:47 PM PDT 24
Peak memory 273076 kb
Host smart-0529bbbf-0efd-4931-a9b4-42a4a8a2d14f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86804288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.86804288
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.937190193
Short name T633
Test name
Test status
Simulation time 3611618353 ps
CPU time 143.36 seconds
Started Jun 21 05:15:17 PM PDT 24
Finished Jun 21 05:17:41 PM PDT 24
Peak memory 248476 kb
Host smart-80836a26-3999-44d8-b183-762319faa86c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937190193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.937190193
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.712364345
Short name T645
Test name
Test status
Simulation time 3567932984 ps
CPU time 37.16 seconds
Started Jun 21 05:15:17 PM PDT 24
Finished Jun 21 05:15:55 PM PDT 24
Peak memory 249236 kb
Host smart-173e4bbc-f77e-4efd-8387-4819d9a31eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71236
4345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.712364345
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.981118004
Short name T53
Test name
Test status
Simulation time 533147163 ps
CPU time 29.3 seconds
Started Jun 21 05:15:19 PM PDT 24
Finished Jun 21 05:15:50 PM PDT 24
Peak memory 247968 kb
Host smart-d9736b6d-028e-4607-8d2d-d93b07201f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98111
8004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.981118004
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3500344854
Short name T271
Test name
Test status
Simulation time 78785940 ps
CPU time 9.01 seconds
Started Jun 21 05:15:19 PM PDT 24
Finished Jun 21 05:15:30 PM PDT 24
Peak memory 248152 kb
Host smart-9613e199-f478-4607-9415-ec089111de8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35003
44854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3500344854
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3803979258
Short name T475
Test name
Test status
Simulation time 2542396077 ps
CPU time 36.09 seconds
Started Jun 21 05:15:17 PM PDT 24
Finished Jun 21 05:15:55 PM PDT 24
Peak memory 257224 kb
Host smart-402a6808-7e8b-46f2-bd90-de1ea67b559b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38039
79258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3803979258
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.4242779574
Short name T501
Test name
Test status
Simulation time 44451581726 ps
CPU time 2768 seconds
Started Jun 21 05:15:25 PM PDT 24
Finished Jun 21 06:01:36 PM PDT 24
Peak memory 299040 kb
Host smart-34a888a1-ba1a-4eac-abaf-3bfa4b4b996e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242779574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.4242779574
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3224917726
Short name T491
Test name
Test status
Simulation time 322370984806 ps
CPU time 5375.33 seconds
Started Jun 21 05:15:26 PM PDT 24
Finished Jun 21 06:45:04 PM PDT 24
Peak memory 318164 kb
Host smart-414fdd1f-e352-4c05-8a71-d9874fa54170
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224917726 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3224917726
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3560583956
Short name T210
Test name
Test status
Simulation time 35857722 ps
CPU time 3.26 seconds
Started Jun 21 05:15:24 PM PDT 24
Finished Jun 21 05:15:29 PM PDT 24
Peak memory 249148 kb
Host smart-b464bbfb-9cd6-4ca0-8333-bb081ddea602
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3560583956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3560583956
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3218962361
Short name T399
Test name
Test status
Simulation time 205293238093 ps
CPU time 2562.53 seconds
Started Jun 21 05:15:27 PM PDT 24
Finished Jun 21 05:58:12 PM PDT 24
Peak memory 290044 kb
Host smart-804a403d-ab62-4388-b359-6113f39850a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218962361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3218962361
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.935536227
Short name T592
Test name
Test status
Simulation time 459122265 ps
CPU time 7.09 seconds
Started Jun 21 05:15:23 PM PDT 24
Finished Jun 21 05:15:32 PM PDT 24
Peak memory 249000 kb
Host smart-34d487db-a5b2-4eea-b6ef-92052f6d0e8e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=935536227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.935536227
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.739836795
Short name T708
Test name
Test status
Simulation time 6327288831 ps
CPU time 132.33 seconds
Started Jun 21 05:15:24 PM PDT 24
Finished Jun 21 05:17:39 PM PDT 24
Peak memory 257256 kb
Host smart-606fd64b-5f07-4e02-973d-ff8562194316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73983
6795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.739836795
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3591715060
Short name T652
Test name
Test status
Simulation time 2242107562 ps
CPU time 30.04 seconds
Started Jun 21 05:15:24 PM PDT 24
Finished Jun 21 05:15:55 PM PDT 24
Peak memory 255852 kb
Host smart-a48aa07c-817f-42ef-bfad-648a5d57f300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35917
15060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3591715060
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3264469827
Short name T45
Test name
Test status
Simulation time 44343223766 ps
CPU time 1059.9 seconds
Started Jun 21 05:15:26 PM PDT 24
Finished Jun 21 05:33:08 PM PDT 24
Peak memory 273640 kb
Host smart-01899d7f-c9be-4c8e-a94f-22010c5e2549
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264469827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3264469827
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3178770552
Short name T578
Test name
Test status
Simulation time 2203776959 ps
CPU time 87.07 seconds
Started Jun 21 05:15:25 PM PDT 24
Finished Jun 21 05:16:54 PM PDT 24
Peak memory 248668 kb
Host smart-5d4949cc-e3dc-4471-83c9-ae643f6c9a24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178770552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3178770552
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2195485236
Short name T62
Test name
Test status
Simulation time 581658815 ps
CPU time 30.43 seconds
Started Jun 21 05:15:24 PM PDT 24
Finished Jun 21 05:15:56 PM PDT 24
Peak memory 249052 kb
Host smart-92b5852b-2b9c-44b3-94d4-b03e36e28832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21954
85236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2195485236
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2084332375
Short name T3
Test name
Test status
Simulation time 1154275157 ps
CPU time 24.73 seconds
Started Jun 21 05:15:24 PM PDT 24
Finished Jun 21 05:15:50 PM PDT 24
Peak memory 256128 kb
Host smart-940ee58e-5b81-4921-a5b7-ebd13ce1f656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20843
32375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2084332375
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.4202993560
Short name T55
Test name
Test status
Simulation time 954564493 ps
CPU time 30.72 seconds
Started Jun 21 05:15:25 PM PDT 24
Finished Jun 21 05:15:58 PM PDT 24
Peak memory 247912 kb
Host smart-d507951b-7ca3-4ccb-8a9f-14b3a272f996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42029
93560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.4202993560
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1372116743
Short name T582
Test name
Test status
Simulation time 930548967 ps
CPU time 14.18 seconds
Started Jun 21 05:15:25 PM PDT 24
Finished Jun 21 05:15:41 PM PDT 24
Peak memory 249040 kb
Host smart-b71e2503-ee0a-4524-a756-85994067eaca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13721
16743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1372116743
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3207946653
Short name T604
Test name
Test status
Simulation time 3295126113 ps
CPU time 172.43 seconds
Started Jun 21 05:15:22 PM PDT 24
Finished Jun 21 05:18:16 PM PDT 24
Peak memory 257292 kb
Host smart-29b77ed5-1b51-44e3-b4c7-e3e05d7da67e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207946653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3207946653
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3585495141
Short name T213
Test name
Test status
Simulation time 29719646 ps
CPU time 2.49 seconds
Started Jun 21 05:15:25 PM PDT 24
Finished Jun 21 05:15:30 PM PDT 24
Peak memory 249152 kb
Host smart-c6d61f73-6a7b-44f8-a94b-7beb75cc98df
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3585495141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3585495141
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.505451765
Short name T528
Test name
Test status
Simulation time 6986998741 ps
CPU time 631.75 seconds
Started Jun 21 05:15:26 PM PDT 24
Finished Jun 21 05:26:00 PM PDT 24
Peak memory 272712 kb
Host smart-2302e666-5a93-4e92-8294-d29052a377cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505451765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.505451765
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1131564515
Short name T589
Test name
Test status
Simulation time 1317687604 ps
CPU time 28.89 seconds
Started Jun 21 05:15:25 PM PDT 24
Finished Jun 21 05:15:56 PM PDT 24
Peak memory 249012 kb
Host smart-0d08ff14-bdc6-4f01-9929-315ea51429b6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1131564515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1131564515
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.86845029
Short name T484
Test name
Test status
Simulation time 4087965497 ps
CPU time 86.85 seconds
Started Jun 21 05:15:27 PM PDT 24
Finished Jun 21 05:16:55 PM PDT 24
Peak memory 257268 kb
Host smart-447d02bb-489b-4560-933e-f9a60f5e8148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86845
029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.86845029
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2554463532
Short name T354
Test name
Test status
Simulation time 115287282 ps
CPU time 9.27 seconds
Started Jun 21 05:15:25 PM PDT 24
Finished Jun 21 05:15:37 PM PDT 24
Peak memory 255168 kb
Host smart-4f908ae3-2ae4-496f-b1c9-368326b36c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25544
63532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2554463532
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.496642910
Short name T339
Test name
Test status
Simulation time 100586631449 ps
CPU time 2889 seconds
Started Jun 21 05:15:22 PM PDT 24
Finished Jun 21 06:03:32 PM PDT 24
Peak memory 281916 kb
Host smart-716f60c2-4565-4abd-b18c-329093006e82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496642910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.496642910
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2376089117
Short name T234
Test name
Test status
Simulation time 16815188251 ps
CPU time 1077.29 seconds
Started Jun 21 05:15:25 PM PDT 24
Finished Jun 21 05:33:25 PM PDT 24
Peak memory 273340 kb
Host smart-2cdde8fd-6695-4934-9726-d3189cfd0d8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376089117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2376089117
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3325097557
Short name T63
Test name
Test status
Simulation time 593999902 ps
CPU time 17.1 seconds
Started Jun 21 05:15:23 PM PDT 24
Finished Jun 21 05:15:42 PM PDT 24
Peak memory 257220 kb
Host smart-d6bd2ccd-62e0-4162-81e8-878924a4c192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33250
97557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3325097557
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3438659148
Short name T674
Test name
Test status
Simulation time 738382872 ps
CPU time 14.47 seconds
Started Jun 21 05:15:27 PM PDT 24
Finished Jun 21 05:15:43 PM PDT 24
Peak memory 247724 kb
Host smart-40375499-d117-4e7c-a9e8-711f4ba9ba4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34386
59148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3438659148
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.494371196
Short name T242
Test name
Test status
Simulation time 911991836 ps
CPU time 13.36 seconds
Started Jun 21 05:15:23 PM PDT 24
Finished Jun 21 05:15:38 PM PDT 24
Peak memory 255136 kb
Host smart-b9cf9d55-ee8b-488c-81f4-60ea3241f5b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49437
1196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.494371196
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.730738157
Short name T505
Test name
Test status
Simulation time 41661178 ps
CPU time 3.75 seconds
Started Jun 21 05:15:23 PM PDT 24
Finished Jun 21 05:15:28 PM PDT 24
Peak memory 240720 kb
Host smart-df8cac06-cabf-4ecf-8051-20b683594427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73073
8157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.730738157
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2431920863
Short name T658
Test name
Test status
Simulation time 457488123 ps
CPU time 37.53 seconds
Started Jun 21 05:15:23 PM PDT 24
Finished Jun 21 05:16:03 PM PDT 24
Peak memory 256568 kb
Host smart-4a303e7d-4d28-4d80-a9b6-cef5878ee5b8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431920863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2431920863
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.999685148
Short name T116
Test name
Test status
Simulation time 312002806793 ps
CPU time 2954.22 seconds
Started Jun 21 05:15:23 PM PDT 24
Finished Jun 21 06:04:39 PM PDT 24
Peak memory 306320 kb
Host smart-e6250826-82b6-4b75-aacd-38d2e394dbd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999685148 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.999685148
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3970258322
Short name T211
Test name
Test status
Simulation time 35841738 ps
CPU time 3.47 seconds
Started Jun 21 05:15:33 PM PDT 24
Finished Jun 21 05:15:39 PM PDT 24
Peak memory 249208 kb
Host smart-650b3abb-01af-4914-8a87-60e309f3bb44
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3970258322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3970258322
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.221182484
Short name T554
Test name
Test status
Simulation time 8068882330 ps
CPU time 866.7 seconds
Started Jun 21 05:15:36 PM PDT 24
Finished Jun 21 05:30:05 PM PDT 24
Peak memory 281508 kb
Host smart-9ab6e314-3ad8-4a5d-82d1-5fba19896991
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221182484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.221182484
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3317802158
Short name T223
Test name
Test status
Simulation time 1269157073 ps
CPU time 16.37 seconds
Started Jun 21 05:15:32 PM PDT 24
Finished Jun 21 05:15:50 PM PDT 24
Peak memory 249036 kb
Host smart-9424456e-6c89-49dd-8076-75b16b0a7c82
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3317802158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3317802158
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3773333908
Short name T450
Test name
Test status
Simulation time 8018192939 ps
CPU time 192.29 seconds
Started Jun 21 05:15:32 PM PDT 24
Finished Jun 21 05:18:46 PM PDT 24
Peak memory 257276 kb
Host smart-256003e0-d9c5-4b7f-8267-b64359720d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37733
33908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3773333908
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2944691968
Short name T336
Test name
Test status
Simulation time 41224038473 ps
CPU time 1323.52 seconds
Started Jun 21 05:15:38 PM PDT 24
Finished Jun 21 05:37:43 PM PDT 24
Peak memory 289636 kb
Host smart-ebcbef3d-030d-42d2-b63f-37ae9bf3e8f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944691968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2944691968
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3945698405
Short name T700
Test name
Test status
Simulation time 31961180444 ps
CPU time 1897.82 seconds
Started Jun 21 05:15:32 PM PDT 24
Finished Jun 21 05:47:13 PM PDT 24
Peak memory 273676 kb
Host smart-478059e2-846c-4b07-8bb0-35b31ccbab3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945698405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3945698405
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1296230260
Short name T543
Test name
Test status
Simulation time 632069161 ps
CPU time 38.91 seconds
Started Jun 21 05:15:23 PM PDT 24
Finished Jun 21 05:16:03 PM PDT 24
Peak memory 256764 kb
Host smart-e1ccae44-85e2-4f65-a58f-d34f72f8830d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12962
30260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1296230260
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2525573288
Short name T379
Test name
Test status
Simulation time 1043693509 ps
CPU time 23.42 seconds
Started Jun 21 05:15:25 PM PDT 24
Finished Jun 21 05:15:50 PM PDT 24
Peak memory 256444 kb
Host smart-0eb85631-ad3e-429b-8036-ae43f366e04c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25255
73288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2525573288
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.341855865
Short name T523
Test name
Test status
Simulation time 406158345 ps
CPU time 26.94 seconds
Started Jun 21 05:15:26 PM PDT 24
Finished Jun 21 05:15:55 PM PDT 24
Peak memory 248976 kb
Host smart-a7a92ae0-26fa-464d-9e07-ab7fadf4632d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34185
5865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.341855865
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1476580254
Short name T631
Test name
Test status
Simulation time 1470090957 ps
CPU time 109.8 seconds
Started Jun 21 05:15:37 PM PDT 24
Finished Jun 21 05:17:28 PM PDT 24
Peak memory 257156 kb
Host smart-1786282b-9020-46ef-91fb-ada2ebed7f04
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476580254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1476580254
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3763374988
Short name T218
Test name
Test status
Simulation time 23462621 ps
CPU time 2.28 seconds
Started Jun 21 05:15:32 PM PDT 24
Finished Jun 21 05:15:37 PM PDT 24
Peak memory 249164 kb
Host smart-7e44bbee-e439-4020-8ee9-c1dc343b7890
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3763374988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3763374988
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3037343516
Short name T425
Test name
Test status
Simulation time 66775297307 ps
CPU time 2036.09 seconds
Started Jun 21 05:15:31 PM PDT 24
Finished Jun 21 05:49:28 PM PDT 24
Peak memory 289728 kb
Host smart-968f3e41-f7c3-43ae-9b30-e78be645bd0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037343516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3037343516
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1294347536
Short name T487
Test name
Test status
Simulation time 657278505 ps
CPU time 18.82 seconds
Started Jun 21 05:15:29 PM PDT 24
Finished Jun 21 05:15:49 PM PDT 24
Peak memory 249036 kb
Host smart-c3e74bdc-c9d6-44a4-a302-2c78a7db5a6d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1294347536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1294347536
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2530472202
Short name T282
Test name
Test status
Simulation time 8788049819 ps
CPU time 170.25 seconds
Started Jun 21 05:15:34 PM PDT 24
Finished Jun 21 05:18:27 PM PDT 24
Peak memory 251900 kb
Host smart-2edc02b8-1096-49d0-be27-6256857e8c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25304
72202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2530472202
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.4015251817
Short name T458
Test name
Test status
Simulation time 235170846 ps
CPU time 31.57 seconds
Started Jun 21 05:15:35 PM PDT 24
Finished Jun 21 05:16:09 PM PDT 24
Peak memory 256052 kb
Host smart-73615395-013c-4293-b940-d35dc8bfaf21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40152
51817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.4015251817
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.595721817
Short name T190
Test name
Test status
Simulation time 19993483087 ps
CPU time 1322.6 seconds
Started Jun 21 05:15:33 PM PDT 24
Finished Jun 21 05:37:39 PM PDT 24
Peak memory 289080 kb
Host smart-856190aa-ce79-4b32-a38b-20bd58facae3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595721817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.595721817
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.692548718
Short name T596
Test name
Test status
Simulation time 275473776245 ps
CPU time 2031.59 seconds
Started Jun 21 05:15:39 PM PDT 24
Finished Jun 21 05:49:33 PM PDT 24
Peak memory 272952 kb
Host smart-bed3ab67-861c-44ac-be84-c09af562718f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692548718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.692548718
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3466637623
Short name T194
Test name
Test status
Simulation time 11999980812 ps
CPU time 487.19 seconds
Started Jun 21 05:15:36 PM PDT 24
Finished Jun 21 05:23:45 PM PDT 24
Peak memory 248684 kb
Host smart-6c157e38-0407-4f39-a67a-231cdbf78722
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466637623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3466637623
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.2647250624
Short name T476
Test name
Test status
Simulation time 393331745 ps
CPU time 21.95 seconds
Started Jun 21 05:15:34 PM PDT 24
Finished Jun 21 05:15:58 PM PDT 24
Peak memory 249168 kb
Host smart-b51cfc2d-c010-49d1-8dc8-c4d23001d96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26472
50624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2647250624
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.402868554
Short name T609
Test name
Test status
Simulation time 88400230 ps
CPU time 6.64 seconds
Started Jun 21 05:15:30 PM PDT 24
Finished Jun 21 05:15:38 PM PDT 24
Peak memory 247816 kb
Host smart-0692fdc6-b6b2-4bed-b068-6057729a6a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40286
8554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.402868554
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1593450149
Short name T408
Test name
Test status
Simulation time 294940168 ps
CPU time 32.09 seconds
Started Jun 21 05:15:33 PM PDT 24
Finished Jun 21 05:16:08 PM PDT 24
Peak memory 257120 kb
Host smart-d54cc173-a948-4784-9193-c4374997310d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15934
50149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1593450149
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1418565751
Short name T378
Test name
Test status
Simulation time 20774124 ps
CPU time 3.76 seconds
Started Jun 21 05:15:31 PM PDT 24
Finished Jun 21 05:15:37 PM PDT 24
Peak memory 240740 kb
Host smart-ef96a028-e558-4543-8ff0-79a2a7d1cf69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14185
65751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1418565751
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1767025768
Short name T445
Test name
Test status
Simulation time 263306384773 ps
CPU time 2264.2 seconds
Started Jun 21 05:15:30 PM PDT 24
Finished Jun 21 05:53:16 PM PDT 24
Peak memory 273588 kb
Host smart-efa7896e-54a0-453c-9ae3-2dc8e04feda6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767025768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1767025768
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2928756951
Short name T222
Test name
Test status
Simulation time 37336794 ps
CPU time 3.37 seconds
Started Jun 21 05:15:32 PM PDT 24
Finished Jun 21 05:15:39 PM PDT 24
Peak memory 249200 kb
Host smart-562b54e1-6f76-46e5-ad22-617d14cc2cfa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2928756951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2928756951
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.932042447
Short name T461
Test name
Test status
Simulation time 156299195320 ps
CPU time 2401.11 seconds
Started Jun 21 05:15:33 PM PDT 24
Finished Jun 21 05:55:37 PM PDT 24
Peak memory 289076 kb
Host smart-b3766157-b082-47cf-ab35-b33afd3a6835
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932042447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.932042447
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3694229902
Short name T376
Test name
Test status
Simulation time 3660628010 ps
CPU time 39.44 seconds
Started Jun 21 05:15:33 PM PDT 24
Finished Jun 21 05:16:15 PM PDT 24
Peak memory 249104 kb
Host smart-c75d0722-1bb4-4579-be66-bb691fcdd675
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3694229902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3694229902
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2533969052
Short name T488
Test name
Test status
Simulation time 1056180494 ps
CPU time 109.79 seconds
Started Jun 21 05:15:32 PM PDT 24
Finished Jun 21 05:17:25 PM PDT 24
Peak memory 250404 kb
Host smart-312bba0c-3f99-4d72-a21c-46006e242582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25339
69052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2533969052
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2826036258
Short name T460
Test name
Test status
Simulation time 138537103 ps
CPU time 4.73 seconds
Started Jun 21 05:15:31 PM PDT 24
Finished Jun 21 05:15:38 PM PDT 24
Peak memory 241000 kb
Host smart-966d4481-a55f-4547-a17f-815a5dbed577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28260
36258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2826036258
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1745804409
Short name T331
Test name
Test status
Simulation time 51654968064 ps
CPU time 2553.18 seconds
Started Jun 21 05:15:32 PM PDT 24
Finished Jun 21 05:58:09 PM PDT 24
Peak memory 289592 kb
Host smart-5513756c-1688-4249-8537-26c18028da63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745804409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1745804409
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3058716204
Short name T695
Test name
Test status
Simulation time 186116333310 ps
CPU time 1663.84 seconds
Started Jun 21 05:15:33 PM PDT 24
Finished Jun 21 05:43:20 PM PDT 24
Peak memory 270616 kb
Host smart-1175cb81-701e-442e-803d-2f3c7da87b83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058716204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3058716204
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2250171027
Short name T73
Test name
Test status
Simulation time 133485310 ps
CPU time 8.71 seconds
Started Jun 21 05:15:32 PM PDT 24
Finished Jun 21 05:15:43 PM PDT 24
Peak memory 251296 kb
Host smart-03aadc41-5f9c-488d-8759-b03e7b248936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22501
71027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2250171027
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.502794360
Short name T666
Test name
Test status
Simulation time 75502013 ps
CPU time 5.5 seconds
Started Jun 21 05:15:38 PM PDT 24
Finished Jun 21 05:15:46 PM PDT 24
Peak memory 239652 kb
Host smart-90b56018-526e-4625-af62-066619a8b3da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50279
4360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.502794360
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2219420307
Short name T643
Test name
Test status
Simulation time 479094005 ps
CPU time 26.18 seconds
Started Jun 21 05:15:35 PM PDT 24
Finished Jun 21 05:16:04 PM PDT 24
Peak memory 255776 kb
Host smart-95bdbe26-3e72-4286-bafd-8bf208b6463a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22194
20307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2219420307
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2687698023
Short name T472
Test name
Test status
Simulation time 1353721268 ps
CPU time 29.72 seconds
Started Jun 21 05:15:36 PM PDT 24
Finished Jun 21 05:16:08 PM PDT 24
Peak memory 249120 kb
Host smart-e3ade6eb-6866-4cc5-89ee-8190008ae61d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26876
98023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2687698023
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.22136218
Short name T502
Test name
Test status
Simulation time 42312242867 ps
CPU time 2748.82 seconds
Started Jun 21 05:15:29 PM PDT 24
Finished Jun 21 06:01:19 PM PDT 24
Peak memory 290108 kb
Host smart-b38c3b3c-0122-411b-8c17-9d03276ee18a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22136218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_hand
ler_stress_all.22136218
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2605483230
Short name T209
Test name
Test status
Simulation time 48940963 ps
CPU time 2.74 seconds
Started Jun 21 05:15:39 PM PDT 24
Finished Jun 21 05:15:43 PM PDT 24
Peak memory 249212 kb
Host smart-af7c51ae-e700-42b9-934a-78c13872579d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2605483230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2605483230
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1630356298
Short name T466
Test name
Test status
Simulation time 223412378502 ps
CPU time 1834.75 seconds
Started Jun 21 05:15:35 PM PDT 24
Finished Jun 21 05:46:12 PM PDT 24
Peak memory 287472 kb
Host smart-9b094b6d-53eb-4c94-88fb-802806863a0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630356298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1630356298
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.105234025
Short name T241
Test name
Test status
Simulation time 1117191481 ps
CPU time 15.34 seconds
Started Jun 21 05:15:37 PM PDT 24
Finished Jun 21 05:15:54 PM PDT 24
Peak memory 248968 kb
Host smart-e9bc5ce1-832a-4c10-97ec-3d8991065e96
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=105234025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.105234025
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.945775536
Short name T662
Test name
Test status
Simulation time 216174816 ps
CPU time 14.08 seconds
Started Jun 21 05:15:31 PM PDT 24
Finished Jun 21 05:15:46 PM PDT 24
Peak memory 254628 kb
Host smart-3e8d0dcc-925b-4819-b374-811b0a82de32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94577
5536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.945775536
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2136996676
Short name T70
Test name
Test status
Simulation time 3469375543 ps
CPU time 42.87 seconds
Started Jun 21 05:15:31 PM PDT 24
Finished Jun 21 05:16:16 PM PDT 24
Peak memory 256804 kb
Host smart-a1d5ad9a-4c79-4956-beea-3b90c4c4b9fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21369
96676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2136996676
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2910231963
Short name T326
Test name
Test status
Simulation time 53169489579 ps
CPU time 1663.06 seconds
Started Jun 21 05:15:36 PM PDT 24
Finished Jun 21 05:43:21 PM PDT 24
Peak memory 273724 kb
Host smart-2a5f17a0-5955-4014-87d6-cdcfd1deb85e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910231963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2910231963
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2254536865
Short name T634
Test name
Test status
Simulation time 104660032513 ps
CPU time 1459.72 seconds
Started Jun 21 05:15:33 PM PDT 24
Finished Jun 21 05:39:55 PM PDT 24
Peak memory 273020 kb
Host smart-d6f1f273-e30f-4534-b379-68aebdd176d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254536865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2254536865
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3160148252
Short name T317
Test name
Test status
Simulation time 19263032137 ps
CPU time 192.55 seconds
Started Jun 21 05:15:35 PM PDT 24
Finished Jun 21 05:18:50 PM PDT 24
Peak memory 248336 kb
Host smart-1b086348-1e9c-46f1-8758-ed0800d471de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160148252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3160148252
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.332415576
Short name T122
Test name
Test status
Simulation time 373437405 ps
CPU time 41.62 seconds
Started Jun 21 05:15:36 PM PDT 24
Finished Jun 21 05:16:19 PM PDT 24
Peak memory 248968 kb
Host smart-a94023e4-55f0-4c9f-82ec-d1258603c36b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33241
5576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.332415576
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3137394711
Short name T58
Test name
Test status
Simulation time 799926679 ps
CPU time 23.11 seconds
Started Jun 21 05:15:36 PM PDT 24
Finished Jun 21 05:16:01 PM PDT 24
Peak memory 255896 kb
Host smart-2637bc0a-5f52-4a5b-aa31-0cb41e81f9a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31373
94711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3137394711
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2115463180
Short name T670
Test name
Test status
Simulation time 142547326 ps
CPU time 5.6 seconds
Started Jun 21 05:15:31 PM PDT 24
Finished Jun 21 05:15:38 PM PDT 24
Peak memory 254120 kb
Host smart-0a916a4f-37e5-4a35-94d2-65ea194b011a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21154
63180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2115463180
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3240707966
Short name T677
Test name
Test status
Simulation time 739459072 ps
CPU time 21.41 seconds
Started Jun 21 05:15:31 PM PDT 24
Finished Jun 21 05:15:53 PM PDT 24
Peak memory 249024 kb
Host smart-d6257da8-47a4-44a8-95e2-65e2506fce9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32407
07966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3240707966
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1428154999
Short name T249
Test name
Test status
Simulation time 105190037449 ps
CPU time 1798.25 seconds
Started Jun 21 05:15:36 PM PDT 24
Finished Jun 21 05:45:36 PM PDT 24
Peak memory 273724 kb
Host smart-d7dc03e9-081a-47b1-a500-c61a54a9a6de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428154999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1428154999
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.3895325217
Short name T266
Test name
Test status
Simulation time 78188464214 ps
CPU time 1325.83 seconds
Started Jun 21 05:15:43 PM PDT 24
Finished Jun 21 05:37:50 PM PDT 24
Peak memory 289948 kb
Host smart-d1ed6803-49b9-42b2-bd6a-bed04b9e778a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895325217 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.3895325217
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.93906212
Short name T206
Test name
Test status
Simulation time 145143910 ps
CPU time 3.6 seconds
Started Jun 21 05:14:55 PM PDT 24
Finished Jun 21 05:15:03 PM PDT 24
Peak memory 248980 kb
Host smart-bbb4ba0f-e7ec-448b-b696-668850f7d633
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=93906212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.93906212
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.766912080
Short name T414
Test name
Test status
Simulation time 17136749443 ps
CPU time 1371.5 seconds
Started Jun 21 05:14:51 PM PDT 24
Finished Jun 21 05:37:48 PM PDT 24
Peak memory 289612 kb
Host smart-da70b720-30ac-455e-821e-5bab3d4ce009
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766912080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.766912080
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.528462897
Short name T243
Test name
Test status
Simulation time 203838128 ps
CPU time 10.83 seconds
Started Jun 21 05:14:51 PM PDT 24
Finished Jun 21 05:15:07 PM PDT 24
Peak memory 240820 kb
Host smart-36a16dbf-c18c-40ad-9423-c5d89b0ed085
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=528462897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.528462897
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3704712032
Short name T442
Test name
Test status
Simulation time 18480562373 ps
CPU time 131.63 seconds
Started Jun 21 05:14:54 PM PDT 24
Finished Jun 21 05:17:10 PM PDT 24
Peak memory 250280 kb
Host smart-60077557-ae65-423c-af31-56c7dc11d31f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37047
12032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3704712032
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3528131539
Short name T224
Test name
Test status
Simulation time 818368839 ps
CPU time 35.69 seconds
Started Jun 21 05:15:00 PM PDT 24
Finished Jun 21 05:15:38 PM PDT 24
Peak memory 249408 kb
Host smart-d02e9886-2115-4eb1-88a4-979c123e8936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35281
31539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3528131539
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1619302223
Short name T671
Test name
Test status
Simulation time 102592217316 ps
CPU time 2828 seconds
Started Jun 21 05:14:53 PM PDT 24
Finished Jun 21 06:02:06 PM PDT 24
Peak memory 289580 kb
Host smart-253f8271-b183-4ecb-ada7-f0ec0ffb147a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619302223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1619302223
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3941368500
Short name T545
Test name
Test status
Simulation time 81214286676 ps
CPU time 1120.84 seconds
Started Jun 21 05:14:51 PM PDT 24
Finished Jun 21 05:33:37 PM PDT 24
Peak memory 284348 kb
Host smart-3bd47514-627e-4bea-8914-b0fcb237c05f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941368500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3941368500
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.80574884
Short name T245
Test name
Test status
Simulation time 128825997430 ps
CPU time 540.74 seconds
Started Jun 21 05:14:48 PM PDT 24
Finished Jun 21 05:23:53 PM PDT 24
Peak memory 248660 kb
Host smart-7e1ac3ce-34c3-447c-9f2a-e8b89cc923a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80574884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.80574884
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2862808291
Short name T57
Test name
Test status
Simulation time 452902695 ps
CPU time 15.97 seconds
Started Jun 21 05:14:53 PM PDT 24
Finished Jun 21 05:15:14 PM PDT 24
Peak memory 255224 kb
Host smart-aef819cf-97c6-418f-b89f-62f52bd2cd7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28628
08291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2862808291
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.569182340
Short name T359
Test name
Test status
Simulation time 161086994 ps
CPU time 2.54 seconds
Started Jun 21 05:14:52 PM PDT 24
Finished Jun 21 05:14:59 PM PDT 24
Peak memory 240784 kb
Host smart-6783d997-a032-427e-8e9f-e48a8e6fe8d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56918
2340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.569182340
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2745915258
Short name T10
Test name
Test status
Simulation time 1829348132 ps
CPU time 22.46 seconds
Started Jun 21 05:14:53 PM PDT 24
Finished Jun 21 05:15:20 PM PDT 24
Peak memory 276736 kb
Host smart-f33baa15-0c2e-4c0c-ae14-352a45a12b32
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2745915258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2745915258
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.652725631
Short name T272
Test name
Test status
Simulation time 2231608022 ps
CPU time 37.99 seconds
Started Jun 21 05:14:52 PM PDT 24
Finished Jun 21 05:15:34 PM PDT 24
Peak memory 248164 kb
Host smart-9db05291-f65f-4679-82cf-3213b57ece0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65272
5631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.652725631
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3939409433
Short name T385
Test name
Test status
Simulation time 508373777 ps
CPU time 34.26 seconds
Started Jun 21 05:14:50 PM PDT 24
Finished Jun 21 05:15:29 PM PDT 24
Peak memory 257192 kb
Host smart-526e205d-22b8-4fab-a982-d0f301b29213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39394
09433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3939409433
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3982188508
Short name T650
Test name
Test status
Simulation time 444159599312 ps
CPU time 2480.78 seconds
Started Jun 21 05:14:53 PM PDT 24
Finished Jun 21 05:56:19 PM PDT 24
Peak memory 289924 kb
Host smart-6d222d6c-0c3b-4b3f-af7c-53d7825e258c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982188508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3982188508
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3150316935
Short name T91
Test name
Test status
Simulation time 21044465172 ps
CPU time 1191.88 seconds
Started Jun 21 05:15:40 PM PDT 24
Finished Jun 21 05:35:34 PM PDT 24
Peak memory 289180 kb
Host smart-17353821-87ba-4259-9837-134e9c60024b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150316935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3150316935
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2980040563
Short name T448
Test name
Test status
Simulation time 121393819418 ps
CPU time 296.13 seconds
Started Jun 21 05:15:38 PM PDT 24
Finished Jun 21 05:20:36 PM PDT 24
Peak memory 257212 kb
Host smart-5ac9f5b3-297e-4ef9-b737-fd3f29aceeca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29800
40563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2980040563
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3553273786
Short name T692
Test name
Test status
Simulation time 715750714 ps
CPU time 21.67 seconds
Started Jun 21 05:15:36 PM PDT 24
Finished Jun 21 05:16:00 PM PDT 24
Peak memory 249060 kb
Host smart-76cff724-efb5-4a19-b080-94e7fdabc87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35532
73786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3553273786
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.3246050950
Short name T333
Test name
Test status
Simulation time 108936102892 ps
CPU time 3293.23 seconds
Started Jun 21 05:15:39 PM PDT 24
Finished Jun 21 06:10:34 PM PDT 24
Peak memory 289240 kb
Host smart-8d49ad6c-b467-4e59-80a8-09bbed01ac49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246050950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3246050950
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1445374892
Short name T551
Test name
Test status
Simulation time 41110023928 ps
CPU time 2258.61 seconds
Started Jun 21 05:15:40 PM PDT 24
Finished Jun 21 05:53:20 PM PDT 24
Peak memory 286336 kb
Host smart-7eb5f30d-f2c3-467d-84bb-3a146f37e03f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445374892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1445374892
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1955537304
Short name T325
Test name
Test status
Simulation time 146386000015 ps
CPU time 429.09 seconds
Started Jun 21 05:15:37 PM PDT 24
Finished Jun 21 05:22:48 PM PDT 24
Peak memory 248392 kb
Host smart-0b1adf5f-ce40-4d26-93ba-560ef4774233
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955537304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1955537304
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2300256618
Short name T374
Test name
Test status
Simulation time 1752061130 ps
CPU time 32.76 seconds
Started Jun 21 05:15:40 PM PDT 24
Finished Jun 21 05:16:14 PM PDT 24
Peak memory 256548 kb
Host smart-f131466b-fc86-4ec4-9349-1eeae4375742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23002
56618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2300256618
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.327919374
Short name T496
Test name
Test status
Simulation time 402543139 ps
CPU time 22.46 seconds
Started Jun 21 05:15:40 PM PDT 24
Finished Jun 21 05:16:04 PM PDT 24
Peak memory 255936 kb
Host smart-7d3238f8-977e-44b0-87e5-f61b5e7a01e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32791
9374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.327919374
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1422123443
Short name T67
Test name
Test status
Simulation time 319657157 ps
CPU time 41.08 seconds
Started Jun 21 05:15:42 PM PDT 24
Finished Jun 21 05:16:24 PM PDT 24
Peak memory 256084 kb
Host smart-2160d9f0-3677-4542-a3a3-6bb56d9d9732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14221
23443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1422123443
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1582662785
Short name T368
Test name
Test status
Simulation time 58588043 ps
CPU time 7.03 seconds
Started Jun 21 05:15:39 PM PDT 24
Finished Jun 21 05:15:48 PM PDT 24
Peak memory 253640 kb
Host smart-904b417d-6359-406b-a7ab-32674fc2436e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15826
62785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1582662785
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.56886619
Short name T270
Test name
Test status
Simulation time 10747029032 ps
CPU time 180.53 seconds
Started Jun 21 05:15:45 PM PDT 24
Finished Jun 21 05:18:46 PM PDT 24
Peak memory 257268 kb
Host smart-f6b7bf03-fe5f-4f8e-ab00-cfed6b2081bd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56886619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_hand
ler_stress_all.56886619
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.290009843
Short name T480
Test name
Test status
Simulation time 19685874428 ps
CPU time 1023.22 seconds
Started Jun 21 05:15:42 PM PDT 24
Finished Jun 21 05:32:47 PM PDT 24
Peak memory 289388 kb
Host smart-88371c82-63de-446b-a614-9325dfc71716
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290009843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.290009843
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2183647520
Short name T257
Test name
Test status
Simulation time 9601516347 ps
CPU time 275.34 seconds
Started Jun 21 05:15:37 PM PDT 24
Finished Jun 21 05:20:14 PM PDT 24
Peak memory 257320 kb
Host smart-a723f0ea-03a8-4c0c-813c-5f7c36dfad4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21836
47520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2183647520
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3647724640
Short name T664
Test name
Test status
Simulation time 2371341172 ps
CPU time 51.72 seconds
Started Jun 21 05:15:39 PM PDT 24
Finished Jun 21 05:16:33 PM PDT 24
Peak memory 255628 kb
Host smart-edfe3ce9-4f94-4534-b2d9-a926595344a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36477
24640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3647724640
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.95138318
Short name T584
Test name
Test status
Simulation time 60282976996 ps
CPU time 1610.01 seconds
Started Jun 21 05:15:38 PM PDT 24
Finished Jun 21 05:42:30 PM PDT 24
Peak memory 289240 kb
Host smart-bdb4fb4e-ea95-4692-9453-2724ae5bbf1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95138318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.95138318
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3948485227
Short name T307
Test name
Test status
Simulation time 6527364365 ps
CPU time 247.06 seconds
Started Jun 21 05:15:39 PM PDT 24
Finished Jun 21 05:19:48 PM PDT 24
Peak memory 248476 kb
Host smart-e2865021-4d76-4402-9349-6af2941818d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948485227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3948485227
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.209813468
Short name T594
Test name
Test status
Simulation time 3891846790 ps
CPU time 55.65 seconds
Started Jun 21 05:15:39 PM PDT 24
Finished Jun 21 05:16:36 PM PDT 24
Peak memory 257248 kb
Host smart-af56a9eb-95e9-49a6-866b-151f3b6a3566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20981
3468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.209813468
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1328016378
Short name T467
Test name
Test status
Simulation time 1334084678 ps
CPU time 45.43 seconds
Started Jun 21 05:15:40 PM PDT 24
Finished Jun 21 05:16:27 PM PDT 24
Peak memory 255436 kb
Host smart-e448faaf-0e45-4a44-9545-e9fa30d37e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13280
16378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1328016378
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.79977658
Short name T510
Test name
Test status
Simulation time 490285851 ps
CPU time 16.1 seconds
Started Jun 21 05:15:39 PM PDT 24
Finished Jun 21 05:15:57 PM PDT 24
Peak memory 249032 kb
Host smart-f6e5de2d-4025-4aff-b04d-92cfa696e53b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79977
658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.79977658
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3971031270
Short name T268
Test name
Test status
Simulation time 12241996020 ps
CPU time 1286.88 seconds
Started Jun 21 05:15:45 PM PDT 24
Finished Jun 21 05:37:13 PM PDT 24
Peak memory 286036 kb
Host smart-364090a2-bb25-4c6f-a504-ae9af31a8d46
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971031270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3971031270
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.4271401064
Short name T410
Test name
Test status
Simulation time 1073564139 ps
CPU time 46.84 seconds
Started Jun 21 05:15:38 PM PDT 24
Finished Jun 21 05:16:27 PM PDT 24
Peak memory 257212 kb
Host smart-9c704c71-6988-427a-9fad-f1f528e47fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42714
01064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.4271401064
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2564968742
Short name T247
Test name
Test status
Simulation time 93698730248 ps
CPU time 1280.73 seconds
Started Jun 21 05:15:50 PM PDT 24
Finished Jun 21 05:37:12 PM PDT 24
Peak memory 273736 kb
Host smart-8295edc6-a481-43c8-b748-d6f8d99dc13b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564968742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2564968742
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2039086668
Short name T231
Test name
Test status
Simulation time 34585193792 ps
CPU time 221.74 seconds
Started Jun 21 05:15:47 PM PDT 24
Finished Jun 21 05:19:30 PM PDT 24
Peak memory 248124 kb
Host smart-3de9536c-6d2b-45fb-b117-0f78e128f2f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039086668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2039086668
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.313290910
Short name T358
Test name
Test status
Simulation time 644755614 ps
CPU time 27.27 seconds
Started Jun 21 05:15:45 PM PDT 24
Finished Jun 21 05:16:13 PM PDT 24
Peak memory 256832 kb
Host smart-be5aeab6-a7f3-4990-abd1-14ec741097f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31329
0910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.313290910
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.173218180
Short name T18
Test name
Test status
Simulation time 2109453092 ps
CPU time 32.71 seconds
Started Jun 21 05:15:40 PM PDT 24
Finished Jun 21 05:16:15 PM PDT 24
Peak memory 248964 kb
Host smart-0044d693-06d0-49ea-8739-06af68a4c188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17321
8180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.173218180
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2196183022
Short name T259
Test name
Test status
Simulation time 2042281000 ps
CPU time 26.05 seconds
Started Jun 21 05:15:38 PM PDT 24
Finished Jun 21 05:16:06 PM PDT 24
Peak memory 247864 kb
Host smart-c23fb63a-d341-4137-93af-461a26d1f23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21961
83022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2196183022
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.928713354
Short name T360
Test name
Test status
Simulation time 200259061 ps
CPU time 11.71 seconds
Started Jun 21 05:15:39 PM PDT 24
Finished Jun 21 05:15:52 PM PDT 24
Peak memory 248988 kb
Host smart-76c3b775-0009-4415-800a-984b6bafc919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92871
3354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.928713354
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3773294924
Short name T601
Test name
Test status
Simulation time 578893456450 ps
CPU time 3292.84 seconds
Started Jun 21 05:15:44 PM PDT 24
Finished Jun 21 06:10:38 PM PDT 24
Peak memory 306420 kb
Host smart-55c8c559-ea65-462f-82af-823dcb01185d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773294924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3773294924
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2138456199
Short name T682
Test name
Test status
Simulation time 4948643167 ps
CPU time 508.33 seconds
Started Jun 21 05:15:44 PM PDT 24
Finished Jun 21 05:24:13 PM PDT 24
Peak memory 272932 kb
Host smart-5452f896-8497-4434-b336-243b69e2372d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138456199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2138456199
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.48238158
Short name T571
Test name
Test status
Simulation time 3622643919 ps
CPU time 241.65 seconds
Started Jun 21 05:15:46 PM PDT 24
Finished Jun 21 05:19:49 PM PDT 24
Peak memory 257292 kb
Host smart-4d0a4b56-2d58-4990-90da-8be328a05c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48238
158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.48238158
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2455585204
Short name T493
Test name
Test status
Simulation time 573561867 ps
CPU time 27.81 seconds
Started Jun 21 05:15:45 PM PDT 24
Finished Jun 21 05:16:14 PM PDT 24
Peak memory 256308 kb
Host smart-b43479a0-7dd8-48f9-b65a-65f850516799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24555
85204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2455585204
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1505689875
Short name T338
Test name
Test status
Simulation time 33293994695 ps
CPU time 1562.09 seconds
Started Jun 21 05:15:48 PM PDT 24
Finished Jun 21 05:41:51 PM PDT 24
Peak memory 281864 kb
Host smart-784ff803-c8fa-4373-81b6-18dae3ddebc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505689875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1505689875
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1914524700
Short name T561
Test name
Test status
Simulation time 26176836849 ps
CPU time 704.2 seconds
Started Jun 21 05:15:47 PM PDT 24
Finished Jun 21 05:27:32 PM PDT 24
Peak memory 266456 kb
Host smart-c78dbb2f-8b90-49b5-ac9d-9fe7616bdebe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914524700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1914524700
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2094246884
Short name T586
Test name
Test status
Simulation time 35289753404 ps
CPU time 356.2 seconds
Started Jun 21 05:15:45 PM PDT 24
Finished Jun 21 05:21:43 PM PDT 24
Peak memory 248260 kb
Host smart-3de3876f-6834-4bf5-af2a-ee12c5ee6e2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094246884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2094246884
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1016489286
Short name T121
Test name
Test status
Simulation time 225310217 ps
CPU time 21.27 seconds
Started Jun 21 05:15:47 PM PDT 24
Finished Jun 21 05:16:10 PM PDT 24
Peak memory 249040 kb
Host smart-5a5be788-b548-49c5-a963-4f979773621f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10164
89286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1016489286
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3801023238
Short name T706
Test name
Test status
Simulation time 3372419873 ps
CPU time 52.16 seconds
Started Jun 21 05:15:50 PM PDT 24
Finished Jun 21 05:16:43 PM PDT 24
Peak memory 256496 kb
Host smart-c8e1de30-a50f-47da-8be8-448857572ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38010
23238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3801023238
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2555795295
Short name T597
Test name
Test status
Simulation time 2083842290 ps
CPU time 39.33 seconds
Started Jun 21 05:15:46 PM PDT 24
Finished Jun 21 05:16:26 PM PDT 24
Peak memory 248076 kb
Host smart-bec1a942-187d-4322-a2f8-54d8d9391083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25557
95295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2555795295
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.797747470
Short name T675
Test name
Test status
Simulation time 253715056 ps
CPU time 17.42 seconds
Started Jun 21 05:15:47 PM PDT 24
Finished Jun 21 05:16:06 PM PDT 24
Peak memory 257136 kb
Host smart-4e6c84ae-5227-4f2a-bd63-8e31a08244b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79774
7470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.797747470
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3103671354
Short name T608
Test name
Test status
Simulation time 18193334580 ps
CPU time 1756.54 seconds
Started Jun 21 05:15:46 PM PDT 24
Finished Jun 21 05:45:04 PM PDT 24
Peak memory 289444 kb
Host smart-d1994a39-5664-4f59-b704-5c83e3e5c7d5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103671354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3103671354
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.1250325353
Short name T297
Test name
Test status
Simulation time 53200124931 ps
CPU time 4907.79 seconds
Started Jun 21 05:15:45 PM PDT 24
Finished Jun 21 06:37:35 PM PDT 24
Peak memory 322956 kb
Host smart-30902467-6de2-4094-9187-7e85d71bf35d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250325353 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.1250325353
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.177892350
Short name T111
Test name
Test status
Simulation time 60537588288 ps
CPU time 1745.94 seconds
Started Jun 21 05:15:46 PM PDT 24
Finished Jun 21 05:44:54 PM PDT 24
Peak memory 266552 kb
Host smart-8d8561eb-fc83-40d1-823c-5a9988a14ac7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177892350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.177892350
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1343766405
Short name T443
Test name
Test status
Simulation time 66068070 ps
CPU time 4.69 seconds
Started Jun 21 05:15:45 PM PDT 24
Finished Jun 21 05:15:51 PM PDT 24
Peak memory 241064 kb
Host smart-0bf49c9b-280c-4d3d-b98c-f12dd92f7b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13437
66405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1343766405
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.503922147
Short name T647
Test name
Test status
Simulation time 946253022 ps
CPU time 17.75 seconds
Started Jun 21 05:15:50 PM PDT 24
Finished Jun 21 05:16:08 PM PDT 24
Peak memory 249056 kb
Host smart-cf7af606-1e68-4e17-81c3-47c49da89c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50392
2147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.503922147
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1824894965
Short name T611
Test name
Test status
Simulation time 118824660215 ps
CPU time 3244.24 seconds
Started Jun 21 05:15:57 PM PDT 24
Finished Jun 21 06:10:03 PM PDT 24
Peak memory 289072 kb
Host smart-3317392d-e070-4fcd-a1c9-e5196b3a4192
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824894965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1824894965
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2021967184
Short name T514
Test name
Test status
Simulation time 34906964634 ps
CPU time 2261.28 seconds
Started Jun 21 05:15:54 PM PDT 24
Finished Jun 21 05:53:36 PM PDT 24
Peak memory 281872 kb
Host smart-94e3efff-b083-4b4e-9aa4-04479c4f178e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021967184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2021967184
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1308178154
Short name T522
Test name
Test status
Simulation time 506826963 ps
CPU time 35.2 seconds
Started Jun 21 05:15:50 PM PDT 24
Finished Jun 21 05:16:26 PM PDT 24
Peak memory 255848 kb
Host smart-133a6cf8-0090-492e-b43c-11e00adb7a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13081
78154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1308178154
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3144009194
Short name T593
Test name
Test status
Simulation time 2153528623 ps
CPU time 31.17 seconds
Started Jun 21 05:15:47 PM PDT 24
Finished Jun 21 05:16:19 PM PDT 24
Peak memory 255116 kb
Host smart-e65c37b8-f9e4-43bd-a6cb-b892d1781c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31440
09194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3144009194
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3759939509
Short name T88
Test name
Test status
Simulation time 388346941 ps
CPU time 22.53 seconds
Started Jun 21 05:15:45 PM PDT 24
Finished Jun 21 05:16:08 PM PDT 24
Peak memory 247852 kb
Host smart-5b806d7b-0b36-49af-8aa4-5bb3011b5196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37599
39509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3759939509
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.4021465640
Short name T191
Test name
Test status
Simulation time 666706287 ps
CPU time 40.33 seconds
Started Jun 21 05:15:47 PM PDT 24
Finished Jun 21 05:16:29 PM PDT 24
Peak memory 257320 kb
Host smart-2a736666-62ad-44a6-905c-7b5cd1ec5a0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40214
65640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.4021465640
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.71649011
Short name T424
Test name
Test status
Simulation time 47593003894 ps
CPU time 2750.16 seconds
Started Jun 21 05:15:56 PM PDT 24
Finished Jun 21 06:01:48 PM PDT 24
Peak memory 289104 kb
Host smart-bf4fbe68-92f2-48be-a967-778822086528
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71649011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.71649011
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.2570095274
Short name T711
Test name
Test status
Simulation time 4491196978 ps
CPU time 235.05 seconds
Started Jun 21 05:15:57 PM PDT 24
Finished Jun 21 05:19:53 PM PDT 24
Peak memory 257240 kb
Host smart-a820eb59-b6c1-4faa-b573-25b436630164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25700
95274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2570095274
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2274429585
Short name T628
Test name
Test status
Simulation time 17256793413 ps
CPU time 68.22 seconds
Started Jun 21 05:15:59 PM PDT 24
Finished Jun 21 05:17:08 PM PDT 24
Peak memory 249060 kb
Host smart-6c557ad4-1f4b-4684-a174-72974b015752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22744
29585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2274429585
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.422976155
Short name T299
Test name
Test status
Simulation time 417015753506 ps
CPU time 1643.91 seconds
Started Jun 21 05:15:56 PM PDT 24
Finished Jun 21 05:43:21 PM PDT 24
Peak memory 289256 kb
Host smart-0ed79a2d-0b2e-4780-9091-a38f42ab03cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422976155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.422976155
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1550664119
Short name T236
Test name
Test status
Simulation time 362318504529 ps
CPU time 2667.82 seconds
Started Jun 21 05:15:56 PM PDT 24
Finished Jun 21 06:00:25 PM PDT 24
Peak memory 289388 kb
Host smart-c6108bcb-0e17-49c8-ae9a-89fe529d333f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550664119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1550664119
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.621520632
Short name T515
Test name
Test status
Simulation time 125418899812 ps
CPU time 538.21 seconds
Started Jun 21 05:16:00 PM PDT 24
Finished Jun 21 05:24:59 PM PDT 24
Peak memory 248188 kb
Host smart-6e8606c7-b4cd-4317-8731-995f160e5620
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621520632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.621520632
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1477535833
Short name T531
Test name
Test status
Simulation time 4767271687 ps
CPU time 33.85 seconds
Started Jun 21 05:15:55 PM PDT 24
Finished Jun 21 05:16:30 PM PDT 24
Peak memory 255668 kb
Host smart-db1c29a7-59a9-4a63-9601-5d8ed52a9d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14775
35833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1477535833
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2684246155
Short name T56
Test name
Test status
Simulation time 848697677 ps
CPU time 28.66 seconds
Started Jun 21 05:15:56 PM PDT 24
Finished Jun 21 05:16:26 PM PDT 24
Peak memory 256044 kb
Host smart-da0f1356-b02a-42af-80ca-e649deb981a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26842
46155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2684246155
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3975513382
Short name T372
Test name
Test status
Simulation time 127311067 ps
CPU time 15.7 seconds
Started Jun 21 05:15:56 PM PDT 24
Finished Jun 21 05:16:13 PM PDT 24
Peak memory 248968 kb
Host smart-21074f61-df39-47e4-b86b-41e193974b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39755
13382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3975513382
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3684642798
Short name T552
Test name
Test status
Simulation time 1206219437 ps
CPU time 54.2 seconds
Started Jun 21 05:15:58 PM PDT 24
Finished Jun 21 05:16:53 PM PDT 24
Peak memory 257204 kb
Host smart-c1a581ee-cd02-4278-9a49-5f039a403024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36846
42798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3684642798
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3495165589
Short name T110
Test name
Test status
Simulation time 57781145030 ps
CPU time 1401.15 seconds
Started Jun 21 05:15:56 PM PDT 24
Finished Jun 21 05:39:19 PM PDT 24
Peak memory 287052 kb
Host smart-85563270-234b-40f5-bbc8-acb26ad28583
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495165589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3495165589
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.989215855
Short name T698
Test name
Test status
Simulation time 41477035388 ps
CPU time 694.65 seconds
Started Jun 21 05:16:02 PM PDT 24
Finished Jun 21 05:27:38 PM PDT 24
Peak memory 271992 kb
Host smart-1424346a-e484-432e-80c3-e66a084e1d11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989215855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.989215855
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.648188120
Short name T646
Test name
Test status
Simulation time 464693102 ps
CPU time 21.79 seconds
Started Jun 21 05:15:56 PM PDT 24
Finished Jun 21 05:16:19 PM PDT 24
Peak memory 255684 kb
Host smart-578f45e4-3942-4507-befc-9260e5a50e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64818
8120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.648188120
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1373148452
Short name T290
Test name
Test status
Simulation time 10431770062 ps
CPU time 59.49 seconds
Started Jun 21 05:15:57 PM PDT 24
Finished Jun 21 05:16:57 PM PDT 24
Peak memory 255840 kb
Host smart-11bb5263-41b8-4833-9846-26d1871ef8aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13731
48452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1373148452
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.2756663231
Short name T340
Test name
Test status
Simulation time 149538560694 ps
CPU time 2414.68 seconds
Started Jun 21 05:16:05 PM PDT 24
Finished Jun 21 05:56:22 PM PDT 24
Peak memory 281888 kb
Host smart-35e0b101-3e75-4f59-8587-867b5b2d68ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756663231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2756663231
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1974911234
Short name T380
Test name
Test status
Simulation time 28500454833 ps
CPU time 2080.33 seconds
Started Jun 21 05:16:02 PM PDT 24
Finished Jun 21 05:50:43 PM PDT 24
Peak memory 286344 kb
Host smart-4968dd75-3944-4529-9f10-3d16b030c470
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974911234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1974911234
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.665929930
Short name T672
Test name
Test status
Simulation time 6048785693 ps
CPU time 245.45 seconds
Started Jun 21 05:16:05 PM PDT 24
Finished Jun 21 05:20:12 PM PDT 24
Peak memory 255888 kb
Host smart-7a272cde-de50-4a0f-9f14-c9d296987da3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665929930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.665929930
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3681042143
Short name T576
Test name
Test status
Simulation time 1530548626 ps
CPU time 21.02 seconds
Started Jun 21 05:15:55 PM PDT 24
Finished Jun 21 05:16:18 PM PDT 24
Peak memory 249052 kb
Host smart-1f3edae6-075c-49b6-ad71-482a34e25181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36810
42143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3681042143
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3193767000
Short name T457
Test name
Test status
Simulation time 3259607117 ps
CPU time 28.12 seconds
Started Jun 21 05:15:58 PM PDT 24
Finished Jun 21 05:16:27 PM PDT 24
Peak memory 249328 kb
Host smart-83af0c59-f87b-46bd-9019-d7720ec0c0de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31937
67000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3193767000
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.783858838
Short name T389
Test name
Test status
Simulation time 62902887 ps
CPU time 4.51 seconds
Started Jun 21 05:15:55 PM PDT 24
Finished Jun 21 05:16:00 PM PDT 24
Peak memory 239740 kb
Host smart-6a5a734b-c17d-47f2-8361-11f33d351de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78385
8838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.783858838
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2216744115
Short name T405
Test name
Test status
Simulation time 16842100 ps
CPU time 2.84 seconds
Started Jun 21 05:15:55 PM PDT 24
Finished Jun 21 05:15:59 PM PDT 24
Peak memory 240828 kb
Host smart-2b7120e2-04b1-4a9b-93fc-3eca3de7c7c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22167
44115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2216744115
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1692267921
Short name T23
Test name
Test status
Simulation time 6337896675 ps
CPU time 339.97 seconds
Started Jun 21 05:16:01 PM PDT 24
Finished Jun 21 05:21:42 PM PDT 24
Peak memory 257288 kb
Host smart-8ccb77ae-c993-4809-ae0f-ad92e2065438
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692267921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1692267921
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2312520817
Short name T2
Test name
Test status
Simulation time 65842552993 ps
CPU time 1123.22 seconds
Started Jun 21 05:16:05 PM PDT 24
Finished Jun 21 05:34:50 PM PDT 24
Peak memory 265480 kb
Host smart-43e35ba2-9590-4034-b91f-ac5393972c08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312520817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2312520817
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3000734162
Short name T189
Test name
Test status
Simulation time 1872092627 ps
CPU time 146.68 seconds
Started Jun 21 05:16:06 PM PDT 24
Finished Jun 21 05:18:34 PM PDT 24
Peak memory 256400 kb
Host smart-4514fb3e-ab4f-4541-890b-ea21b70d093f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30007
34162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3000734162
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2215965382
Short name T226
Test name
Test status
Simulation time 665379881 ps
CPU time 18.21 seconds
Started Jun 21 05:16:00 PM PDT 24
Finished Jun 21 05:16:19 PM PDT 24
Peak memory 249164 kb
Host smart-8e95c45a-82b5-4dc0-a005-addca5f43fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22159
65382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2215965382
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.67067081
Short name T13
Test name
Test status
Simulation time 57783327321 ps
CPU time 1820.03 seconds
Started Jun 21 05:16:05 PM PDT 24
Finished Jun 21 05:46:27 PM PDT 24
Peak memory 281756 kb
Host smart-d6d94e2b-2465-456b-ba93-ffabc9a5dd8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67067081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.67067081
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2083933747
Short name T426
Test name
Test status
Simulation time 34200505279 ps
CPU time 1897.87 seconds
Started Jun 21 05:16:05 PM PDT 24
Finished Jun 21 05:47:44 PM PDT 24
Peak memory 283320 kb
Host smart-88cb7b8e-e28c-467b-ac94-9e76ab60b020
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083933747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2083933747
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1547678710
Short name T308
Test name
Test status
Simulation time 12843971786 ps
CPU time 241.43 seconds
Started Jun 21 05:16:01 PM PDT 24
Finished Jun 21 05:20:04 PM PDT 24
Peak memory 248568 kb
Host smart-e2c81ccd-2105-4229-b759-42989c94d00d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547678710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1547678710
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2869983507
Short name T462
Test name
Test status
Simulation time 307829878 ps
CPU time 24.41 seconds
Started Jun 21 05:16:04 PM PDT 24
Finished Jun 21 05:16:29 PM PDT 24
Peak memory 257220 kb
Host smart-87dd61a6-2a15-4fc3-8fb7-65bfa8671c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28699
83507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2869983507
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.169579235
Short name T415
Test name
Test status
Simulation time 2270102807 ps
CPU time 36.28 seconds
Started Jun 21 05:16:05 PM PDT 24
Finished Jun 21 05:16:43 PM PDT 24
Peak memory 255708 kb
Host smart-f810b8d3-07fd-43a7-8fe5-46fefb41851a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16957
9235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.169579235
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1593752157
Short name T59
Test name
Test status
Simulation time 170440563 ps
CPU time 20.29 seconds
Started Jun 21 05:16:04 PM PDT 24
Finished Jun 21 05:16:25 PM PDT 24
Peak memory 256008 kb
Host smart-22eb3d08-929a-48ef-b400-66c6340474ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15937
52157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1593752157
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2358993873
Short name T629
Test name
Test status
Simulation time 582198978 ps
CPU time 9.21 seconds
Started Jun 21 05:16:01 PM PDT 24
Finished Jun 21 05:16:11 PM PDT 24
Peak memory 251416 kb
Host smart-7e69815f-d6a0-430d-a658-42633d559858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23589
93873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2358993873
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.3752287601
Short name T187
Test name
Test status
Simulation time 229662263806 ps
CPU time 4613.1 seconds
Started Jun 21 05:16:01 PM PDT 24
Finished Jun 21 06:32:56 PM PDT 24
Peak memory 338760 kb
Host smart-749c4eac-59fc-4d40-b713-903cea6eff93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752287601 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.3752287601
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2095364986
Short name T627
Test name
Test status
Simulation time 163779572824 ps
CPU time 808.83 seconds
Started Jun 21 05:16:04 PM PDT 24
Finished Jun 21 05:29:34 PM PDT 24
Peak memory 273560 kb
Host smart-83fc3391-0121-49a5-b427-de53b76f55e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095364986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2095364986
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2943238481
Short name T640
Test name
Test status
Simulation time 1615788230 ps
CPU time 58.26 seconds
Started Jun 21 05:16:05 PM PDT 24
Finished Jun 21 05:17:05 PM PDT 24
Peak memory 248976 kb
Host smart-99373892-c4a9-4f96-97fb-e2e09d4e99b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29432
38481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2943238481
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3056016802
Short name T519
Test name
Test status
Simulation time 1351232836 ps
CPU time 34.4 seconds
Started Jun 21 05:16:05 PM PDT 24
Finished Jun 21 05:16:41 PM PDT 24
Peak memory 256384 kb
Host smart-0df57fd2-78d2-4e0d-b916-aa746513549f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30560
16802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3056016802
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.4189283178
Short name T93
Test name
Test status
Simulation time 32930397306 ps
CPU time 1108.86 seconds
Started Jun 21 05:16:08 PM PDT 24
Finished Jun 21 05:34:38 PM PDT 24
Peak memory 288652 kb
Host smart-a6dd7c26-2021-4a8e-a9d5-a5cef1a277c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189283178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.4189283178
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2451440986
Short name T251
Test name
Test status
Simulation time 19378746125 ps
CPU time 400.52 seconds
Started Jun 21 05:16:01 PM PDT 24
Finished Jun 21 05:22:43 PM PDT 24
Peak memory 249048 kb
Host smart-bb604941-9328-4464-867c-fe09b181e8aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451440986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2451440986
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2905131576
Short name T17
Test name
Test status
Simulation time 763461179 ps
CPU time 50.11 seconds
Started Jun 21 05:16:05 PM PDT 24
Finished Jun 21 05:16:57 PM PDT 24
Peak memory 249044 kb
Host smart-a7a45fdf-a5a9-4704-994c-fe5cf9ff9d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29051
31576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2905131576
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2344854794
Short name T395
Test name
Test status
Simulation time 688388417 ps
CPU time 22.06 seconds
Started Jun 21 05:16:03 PM PDT 24
Finished Jun 21 05:16:26 PM PDT 24
Peak memory 247956 kb
Host smart-62c3af94-c9bb-4b97-b233-41c37dc76af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23448
54794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2344854794
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1329699509
Short name T386
Test name
Test status
Simulation time 2175285731 ps
CPU time 32.8 seconds
Started Jun 21 05:16:04 PM PDT 24
Finished Jun 21 05:16:38 PM PDT 24
Peak memory 256092 kb
Host smart-f2f5eede-5f85-43dc-be18-01a7e4b04fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13296
99509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1329699509
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.781869166
Short name T371
Test name
Test status
Simulation time 5743364886 ps
CPU time 50.48 seconds
Started Jun 21 05:16:03 PM PDT 24
Finished Jun 21 05:16:55 PM PDT 24
Peak memory 257204 kb
Host smart-58f215f6-70b8-4dbb-9a40-907f78d92a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78186
9166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.781869166
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.1022219346
Short name T438
Test name
Test status
Simulation time 118482364523 ps
CPU time 1987.55 seconds
Started Jun 21 05:16:09 PM PDT 24
Finished Jun 21 05:49:18 PM PDT 24
Peak memory 282996 kb
Host smart-5f04960f-b168-4b68-b5f4-1518d2f76a99
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022219346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.1022219346
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3281574507
Short name T676
Test name
Test status
Simulation time 34987472547 ps
CPU time 2280.6 seconds
Started Jun 21 05:16:10 PM PDT 24
Finished Jun 21 05:54:12 PM PDT 24
Peak memory 285360 kb
Host smart-77fe2827-9f44-4a34-8c14-04ed361aa6d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281574507 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3281574507
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3303545378
Short name T113
Test name
Test status
Simulation time 490609691761 ps
CPU time 2769.74 seconds
Started Jun 21 05:16:08 PM PDT 24
Finished Jun 21 06:02:19 PM PDT 24
Peak memory 281876 kb
Host smart-fdf1c761-886b-4351-8550-8c4460615e60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303545378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3303545378
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2303997566
Short name T499
Test name
Test status
Simulation time 1472023436 ps
CPU time 124.88 seconds
Started Jun 21 05:16:11 PM PDT 24
Finished Jun 21 05:18:17 PM PDT 24
Peak memory 250448 kb
Host smart-5e7bfbcf-7d2b-4c24-aa48-6b4d19cfdb30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23039
97566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2303997566
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2249071597
Short name T585
Test name
Test status
Simulation time 3523316408 ps
CPU time 48.38 seconds
Started Jun 21 05:16:10 PM PDT 24
Finished Jun 21 05:16:59 PM PDT 24
Peak memory 255680 kb
Host smart-1b32720f-9293-46d2-a2ca-56d858b318df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22490
71597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2249071597
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1930092997
Short name T449
Test name
Test status
Simulation time 47238024218 ps
CPU time 1249.16 seconds
Started Jun 21 05:16:10 PM PDT 24
Finished Jun 21 05:37:01 PM PDT 24
Peak memory 289792 kb
Host smart-7ed77696-287e-45cb-9ab6-2fddd13296d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930092997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1930092997
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3908758840
Short name T305
Test name
Test status
Simulation time 11225115476 ps
CPU time 183.25 seconds
Started Jun 21 05:16:10 PM PDT 24
Finished Jun 21 05:19:14 PM PDT 24
Peak memory 248568 kb
Host smart-b9dddab7-2af1-4562-85ac-b2160e4475c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908758840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3908758840
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.66587815
Short name T240
Test name
Test status
Simulation time 486704068 ps
CPU time 9.11 seconds
Started Jun 21 05:16:09 PM PDT 24
Finished Jun 21 05:16:20 PM PDT 24
Peak memory 252672 kb
Host smart-78efe9c2-1cce-4ee2-9838-6ab62294fc72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66587
815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.66587815
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.576528746
Short name T19
Test name
Test status
Simulation time 186148335 ps
CPU time 8.72 seconds
Started Jun 21 05:16:09 PM PDT 24
Finished Jun 21 05:16:18 PM PDT 24
Peak memory 248964 kb
Host smart-461442a0-7fe1-4944-a8c1-9470b0c1ee43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57652
8746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.576528746
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.4152874124
Short name T507
Test name
Test status
Simulation time 2230300666 ps
CPU time 40.7 seconds
Started Jun 21 05:16:11 PM PDT 24
Finished Jun 21 05:16:53 PM PDT 24
Peak memory 249096 kb
Host smart-ffbc120f-ef5e-445d-b073-c1317963de23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41528
74124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.4152874124
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.379301206
Short name T97
Test name
Test status
Simulation time 63990689302 ps
CPU time 2732.93 seconds
Started Jun 21 05:16:10 PM PDT 24
Finished Jun 21 06:01:44 PM PDT 24
Peak memory 289392 kb
Host smart-577f21b3-28d4-4e48-a3fa-edbc664190a3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379301206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.379301206
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.3390072627
Short name T254
Test name
Test status
Simulation time 120599129236 ps
CPU time 1962.67 seconds
Started Jun 21 05:16:10 PM PDT 24
Finished Jun 21 05:48:54 PM PDT 24
Peak memory 281964 kb
Host smart-f9a9f778-207d-4132-af0f-028bd4a858d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390072627 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.3390072627
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.211028143
Short name T207
Test name
Test status
Simulation time 291435114 ps
CPU time 2.65 seconds
Started Jun 21 05:14:55 PM PDT 24
Finished Jun 21 05:15:01 PM PDT 24
Peak memory 249220 kb
Host smart-6e28aacc-4d8b-4fce-8d37-2c3bdce4e5c9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=211028143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.211028143
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1348443756
Short name T235
Test name
Test status
Simulation time 154092410786 ps
CPU time 2829 seconds
Started Jun 21 05:14:59 PM PDT 24
Finished Jun 21 06:02:11 PM PDT 24
Peak memory 285304 kb
Host smart-9ed3852c-e861-4d22-96a0-94efe8e479ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348443756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1348443756
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.4140877226
Short name T603
Test name
Test status
Simulation time 885778851 ps
CPU time 10.67 seconds
Started Jun 21 05:14:52 PM PDT 24
Finished Jun 21 05:15:08 PM PDT 24
Peak memory 249008 kb
Host smart-739e4e5b-c9b0-49f2-99bd-93449f575d95
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4140877226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.4140877226
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.447783683
Short name T21
Test name
Test status
Simulation time 2151554057 ps
CPU time 121.03 seconds
Started Jun 21 05:14:54 PM PDT 24
Finished Jun 21 05:16:59 PM PDT 24
Peak memory 256360 kb
Host smart-347071fb-442b-4ac1-b85b-f18320a3869e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44778
3683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.447783683
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2049657622
Short name T619
Test name
Test status
Simulation time 712699340 ps
CPU time 12.29 seconds
Started Jun 21 05:14:51 PM PDT 24
Finished Jun 21 05:15:08 PM PDT 24
Peak memory 253448 kb
Host smart-5226e9fc-468c-47fa-b412-021348234644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20496
57622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2049657622
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.65850235
Short name T632
Test name
Test status
Simulation time 42355169663 ps
CPU time 2628.1 seconds
Started Jun 21 05:14:57 PM PDT 24
Finished Jun 21 05:58:49 PM PDT 24
Peak memory 289284 kb
Host smart-8c6403f4-5d1b-4dd6-8715-a73329576ad3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65850235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.65850235
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2840328356
Short name T33
Test name
Test status
Simulation time 38416797016 ps
CPU time 2144.13 seconds
Started Jun 21 05:14:57 PM PDT 24
Finished Jun 21 05:50:44 PM PDT 24
Peak memory 281812 kb
Host smart-6b7a4b10-c5bc-46d3-bbf6-436ff60388bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840328356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2840328356
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3155600277
Short name T89
Test name
Test status
Simulation time 12798389494 ps
CPU time 472.51 seconds
Started Jun 21 05:14:51 PM PDT 24
Finished Jun 21 05:22:49 PM PDT 24
Peak memory 248660 kb
Host smart-c92ab027-dd5c-45ab-8cc5-8a752a503951
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155600277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3155600277
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1435085154
Short name T580
Test name
Test status
Simulation time 386744069 ps
CPU time 16.3 seconds
Started Jun 21 05:14:51 PM PDT 24
Finished Jun 21 05:15:12 PM PDT 24
Peak memory 256512 kb
Host smart-c0e8caf9-a3b0-4c2b-83b9-99f76d9d968f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14350
85154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1435085154
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1709340119
Short name T590
Test name
Test status
Simulation time 241526555 ps
CPU time 22.43 seconds
Started Jun 21 05:14:51 PM PDT 24
Finished Jun 21 05:15:19 PM PDT 24
Peak memory 255068 kb
Host smart-2095897b-61fb-4f1c-b76a-78cda51d459e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17093
40119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1709340119
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1015380621
Short name T12
Test name
Test status
Simulation time 655529714 ps
CPU time 19.77 seconds
Started Jun 21 05:14:57 PM PDT 24
Finished Jun 21 05:15:20 PM PDT 24
Peak memory 264432 kb
Host smart-fccbfaac-d30b-4582-ab2d-2499f757e0f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1015380621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1015380621
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.532696976
Short name T624
Test name
Test status
Simulation time 295634743 ps
CPU time 35.02 seconds
Started Jun 21 05:14:54 PM PDT 24
Finished Jun 21 05:15:33 PM PDT 24
Peak memory 247932 kb
Host smart-cb52785a-8318-4c93-bf4c-f882dbd42adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53269
6976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.532696976
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3066246709
Short name T357
Test name
Test status
Simulation time 1706660923 ps
CPU time 27.18 seconds
Started Jun 21 05:14:48 PM PDT 24
Finished Jun 21 05:15:20 PM PDT 24
Peak memory 249028 kb
Host smart-ab54cc00-044f-4cd6-99a8-e46741c26a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30662
46709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3066246709
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3247877270
Short name T264
Test name
Test status
Simulation time 356023863063 ps
CPU time 2732.02 seconds
Started Jun 21 05:14:52 PM PDT 24
Finished Jun 21 06:00:29 PM PDT 24
Peak memory 298308 kb
Host smart-29a3f2eb-bfa6-4b49-8e2c-b784de5c4d3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247877270 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3247877270
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1503196383
Short name T120
Test name
Test status
Simulation time 83153901335 ps
CPU time 1751.9 seconds
Started Jun 21 05:16:08 PM PDT 24
Finished Jun 21 05:45:21 PM PDT 24
Peak memory 289452 kb
Host smart-ba74492d-7f18-4f05-bb6d-212c37c137d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503196383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1503196383
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1207050634
Short name T453
Test name
Test status
Simulation time 11675328585 ps
CPU time 165.4 seconds
Started Jun 21 05:16:09 PM PDT 24
Finished Jun 21 05:18:56 PM PDT 24
Peak memory 257244 kb
Host smart-6d9834ec-35cc-47de-862e-6369f7bbf9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12070
50634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1207050634
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2401432053
Short name T393
Test name
Test status
Simulation time 1020705132 ps
CPU time 32.99 seconds
Started Jun 21 05:16:09 PM PDT 24
Finished Jun 21 05:16:43 PM PDT 24
Peak memory 249052 kb
Host smart-279134d5-9d4c-4e49-9447-8b384e068a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24014
32053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2401432053
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3120859704
Short name T464
Test name
Test status
Simulation time 60987489050 ps
CPU time 1114.09 seconds
Started Jun 21 05:16:09 PM PDT 24
Finished Jun 21 05:34:45 PM PDT 24
Peak memory 286252 kb
Host smart-b43b73c9-6e13-40e3-a095-e22f8f161c7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120859704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3120859704
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3683940664
Short name T15
Test name
Test status
Simulation time 16934212539 ps
CPU time 338.51 seconds
Started Jun 21 05:16:10 PM PDT 24
Finished Jun 21 05:21:50 PM PDT 24
Peak memory 248588 kb
Host smart-1ffe1232-6421-449d-8439-8b50d5f189dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683940664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3683940664
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3648984358
Short name T404
Test name
Test status
Simulation time 699713951 ps
CPU time 12.02 seconds
Started Jun 21 05:16:09 PM PDT 24
Finished Jun 21 05:16:22 PM PDT 24
Peak memory 249276 kb
Host smart-3197df36-ff0c-48b5-9575-9931de7063c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36489
84358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3648984358
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1602052085
Short name T411
Test name
Test status
Simulation time 1036260839 ps
CPU time 28.65 seconds
Started Jun 21 05:16:08 PM PDT 24
Finished Jun 21 05:16:37 PM PDT 24
Peak memory 255292 kb
Host smart-00f3e238-888a-48b3-b3ee-89b53aa4aef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16020
52085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1602052085
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.2131460594
Short name T81
Test name
Test status
Simulation time 100940199 ps
CPU time 3.94 seconds
Started Jun 21 05:16:10 PM PDT 24
Finished Jun 21 05:16:15 PM PDT 24
Peak memory 239640 kb
Host smart-67489fa9-7e9c-4ca5-894d-e179eaa373fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21314
60594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2131460594
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1114036702
Short name T495
Test name
Test status
Simulation time 689851288 ps
CPU time 25.9 seconds
Started Jun 21 05:16:09 PM PDT 24
Finished Jun 21 05:16:36 PM PDT 24
Peak memory 256280 kb
Host smart-5a870125-ffe4-4734-8955-324a89e4a9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11140
36702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1114036702
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2785420135
Short name T37
Test name
Test status
Simulation time 71785477557 ps
CPU time 3990.49 seconds
Started Jun 21 05:16:20 PM PDT 24
Finished Jun 21 06:22:53 PM PDT 24
Peak memory 304588 kb
Host smart-8819fa06-4072-4bd7-9923-6a16a99c30bb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785420135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2785420135
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.729602557
Short name T691
Test name
Test status
Simulation time 28836939869 ps
CPU time 3677.24 seconds
Started Jun 21 05:16:16 PM PDT 24
Finished Jun 21 06:17:35 PM PDT 24
Peak memory 330760 kb
Host smart-e52a47c5-7b57-4d58-b094-8ca69de8b2ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729602557 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.729602557
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3341104508
Short name T535
Test name
Test status
Simulation time 36090660366 ps
CPU time 859.22 seconds
Started Jun 21 05:16:17 PM PDT 24
Finished Jun 21 05:30:37 PM PDT 24
Peak memory 267480 kb
Host smart-04cd4a0d-3791-48d4-a331-047d353f449c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341104508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3341104508
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.110629114
Short name T533
Test name
Test status
Simulation time 943431259 ps
CPU time 94.62 seconds
Started Jun 21 05:16:17 PM PDT 24
Finished Jun 21 05:17:52 PM PDT 24
Peak memory 257228 kb
Host smart-55ad5190-6e0e-487d-acbe-d30b4e3af627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11062
9114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.110629114
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3761033404
Short name T367
Test name
Test status
Simulation time 502102749 ps
CPU time 14.86 seconds
Started Jun 21 05:16:17 PM PDT 24
Finished Jun 21 05:16:33 PM PDT 24
Peak memory 248976 kb
Host smart-da80d9c5-25d2-44e2-a6db-49b6d8042896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37610
33404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3761033404
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1514409979
Short name T341
Test name
Test status
Simulation time 89919828324 ps
CPU time 1501.09 seconds
Started Jun 21 05:16:18 PM PDT 24
Finished Jun 21 05:41:22 PM PDT 24
Peak memory 281860 kb
Host smart-cf5a65a1-cb88-4e3e-8b37-5fb8497d548a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514409979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1514409979
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2342519917
Short name T470
Test name
Test status
Simulation time 34339316060 ps
CPU time 761.47 seconds
Started Jun 21 05:16:18 PM PDT 24
Finished Jun 21 05:29:02 PM PDT 24
Peak memory 272832 kb
Host smart-ae747598-57b8-41d5-ac5f-f15a542773d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342519917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2342519917
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1325518793
Short name T302
Test name
Test status
Simulation time 14973414553 ps
CPU time 617.66 seconds
Started Jun 21 05:16:17 PM PDT 24
Finished Jun 21 05:26:37 PM PDT 24
Peak memory 248792 kb
Host smart-c0e99ae2-7fa1-4e43-b235-d37280c89e5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325518793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1325518793
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2022054554
Short name T500
Test name
Test status
Simulation time 251968347 ps
CPU time 21.77 seconds
Started Jun 21 05:16:19 PM PDT 24
Finished Jun 21 05:16:44 PM PDT 24
Peak memory 248972 kb
Host smart-92d4e31c-9091-4572-aa7a-4691999017fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20220
54554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2022054554
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3865079152
Short name T635
Test name
Test status
Simulation time 254019029 ps
CPU time 15.48 seconds
Started Jun 21 05:16:19 PM PDT 24
Finished Jun 21 05:16:37 PM PDT 24
Peak memory 249100 kb
Host smart-f540d0e9-c3d5-4aad-9a9b-61e3b923dd83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38650
79152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3865079152
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2752671451
Short name T511
Test name
Test status
Simulation time 346867383 ps
CPU time 21.92 seconds
Started Jun 21 05:16:18 PM PDT 24
Finished Jun 21 05:16:42 PM PDT 24
Peak memory 255384 kb
Host smart-0c241738-9b63-4c4f-b16b-34d12e9b0c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27526
71451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2752671451
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.314074596
Short name T353
Test name
Test status
Simulation time 903045417 ps
CPU time 61.4 seconds
Started Jun 21 05:16:18 PM PDT 24
Finished Jun 21 05:17:21 PM PDT 24
Peak memory 248984 kb
Host smart-fc9c9598-0f1c-4615-bc4a-2bc46003bcc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31407
4596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.314074596
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3241424466
Short name T54
Test name
Test status
Simulation time 11638816229 ps
CPU time 608.27 seconds
Started Jun 21 05:16:20 PM PDT 24
Finished Jun 21 05:26:30 PM PDT 24
Peak memory 257392 kb
Host smart-505677c2-86ea-4acb-9b90-96277ef87f41
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241424466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3241424466
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3197264374
Short name T118
Test name
Test status
Simulation time 48942986730 ps
CPU time 2722.78 seconds
Started Jun 21 05:16:19 PM PDT 24
Finished Jun 21 06:01:45 PM PDT 24
Peak memory 289368 kb
Host smart-080352f4-6f03-4304-a459-0432424b670b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197264374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3197264374
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2766809231
Short name T363
Test name
Test status
Simulation time 4055980880 ps
CPU time 72.41 seconds
Started Jun 21 05:16:18 PM PDT 24
Finished Jun 21 05:17:32 PM PDT 24
Peak memory 257288 kb
Host smart-e6bf5fcf-585a-48bd-89f3-7520deae4e70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27668
09231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2766809231
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1496326790
Short name T539
Test name
Test status
Simulation time 3769697785 ps
CPU time 54.01 seconds
Started Jun 21 05:16:18 PM PDT 24
Finished Jun 21 05:17:15 PM PDT 24
Peak memory 256184 kb
Host smart-50ec0972-eeba-4291-aac9-9a648e6fa9c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14963
26790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1496326790
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1352992724
Short name T669
Test name
Test status
Simulation time 11854570434 ps
CPU time 1167.77 seconds
Started Jun 21 05:16:19 PM PDT 24
Finished Jun 21 05:35:50 PM PDT 24
Peak memory 287288 kb
Host smart-07aea832-ebc2-49cc-83eb-7b361ca06a31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352992724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1352992724
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.583982533
Short name T686
Test name
Test status
Simulation time 64237862151 ps
CPU time 2072.89 seconds
Started Jun 21 05:16:17 PM PDT 24
Finished Jun 21 05:50:51 PM PDT 24
Peak memory 289128 kb
Host smart-940e4e17-afe1-498c-8662-49d3e74894bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583982533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.583982533
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3096133920
Short name T542
Test name
Test status
Simulation time 275033481 ps
CPU time 19.24 seconds
Started Jun 21 05:16:18 PM PDT 24
Finished Jun 21 05:16:40 PM PDT 24
Peak memory 249040 kb
Host smart-bed0f3b2-bc1a-49c7-8c4b-7fb34d07a4e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30961
33920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3096133920
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2383661366
Short name T20
Test name
Test status
Simulation time 277839351 ps
CPU time 25.02 seconds
Started Jun 21 05:16:20 PM PDT 24
Finished Jun 21 05:16:47 PM PDT 24
Peak memory 255748 kb
Host smart-ff984033-0315-49a0-870c-7c5d416f3502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23836
61366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2383661366
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3588041290
Short name T244
Test name
Test status
Simulation time 282025386 ps
CPU time 38.72 seconds
Started Jun 21 05:16:17 PM PDT 24
Finished Jun 21 05:16:57 PM PDT 24
Peak memory 255768 kb
Host smart-08935da0-6221-43f0-ba86-30a6e86a36f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35880
41290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3588041290
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3167080473
Short name T229
Test name
Test status
Simulation time 395483894 ps
CPU time 23.98 seconds
Started Jun 21 05:16:20 PM PDT 24
Finished Jun 21 05:16:46 PM PDT 24
Peak memory 257232 kb
Host smart-b9aa2065-b0c7-473f-866c-92fb70efcf0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31670
80473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3167080473
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2495488741
Short name T595
Test name
Test status
Simulation time 28561877339 ps
CPU time 1344.25 seconds
Started Jun 21 05:16:20 PM PDT 24
Finished Jun 21 05:38:46 PM PDT 24
Peak memory 289724 kb
Host smart-240ce3fb-6b46-463b-9efb-9dcfbbb016bb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495488741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2495488741
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2675785899
Short name T707
Test name
Test status
Simulation time 51080882915 ps
CPU time 1463.78 seconds
Started Jun 21 05:16:29 PM PDT 24
Finished Jun 21 05:40:54 PM PDT 24
Peak memory 273008 kb
Host smart-4f70183e-e76a-4a32-a116-a6b2915e02e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675785899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2675785899
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2349569462
Short name T388
Test name
Test status
Simulation time 1634810361 ps
CPU time 136.35 seconds
Started Jun 21 05:16:21 PM PDT 24
Finished Jun 21 05:18:39 PM PDT 24
Peak memory 251044 kb
Host smart-ce72914f-2515-4ee0-933c-4736f5a7bd79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23495
69462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2349569462
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1702286770
Short name T432
Test name
Test status
Simulation time 1921597727 ps
CPU time 53.97 seconds
Started Jun 21 05:16:18 PM PDT 24
Finished Jun 21 05:17:15 PM PDT 24
Peak memory 249052 kb
Host smart-973b5ae2-18d7-4b7e-83b6-bfee99483844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17022
86770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1702286770
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1424332840
Short name T43
Test name
Test status
Simulation time 14125948872 ps
CPU time 1146.55 seconds
Started Jun 21 05:16:29 PM PDT 24
Finished Jun 21 05:35:37 PM PDT 24
Peak memory 273704 kb
Host smart-226e76f0-4c2c-4f30-85cd-9aac07869940
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424332840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1424332840
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3400295371
Short name T456
Test name
Test status
Simulation time 95028888453 ps
CPU time 1441.8 seconds
Started Jun 21 05:16:28 PM PDT 24
Finished Jun 21 05:40:31 PM PDT 24
Peak memory 273272 kb
Host smart-e110f850-4cab-4591-9733-8e85eabfafc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400295371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3400295371
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.275266823
Short name T230
Test name
Test status
Simulation time 32420830404 ps
CPU time 372.39 seconds
Started Jun 21 05:16:30 PM PDT 24
Finished Jun 21 05:22:44 PM PDT 24
Peak memory 248648 kb
Host smart-5c8eb322-4a82-45ac-a79d-9de28052b1e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275266823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.275266823
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.111953128
Short name T524
Test name
Test status
Simulation time 414115929 ps
CPU time 17.65 seconds
Started Jun 21 05:16:19 PM PDT 24
Finished Jun 21 05:16:39 PM PDT 24
Peak memory 249044 kb
Host smart-c635418a-e0a0-4f92-a3d6-d0ba6d583642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11195
3128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.111953128
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2113448842
Short name T95
Test name
Test status
Simulation time 768030092 ps
CPU time 35.79 seconds
Started Jun 21 05:16:19 PM PDT 24
Finished Jun 21 05:16:57 PM PDT 24
Peak memory 255840 kb
Host smart-4155723d-b1c3-4fa6-87c1-4abf9201c87c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21134
48842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2113448842
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3902376904
Short name T492
Test name
Test status
Simulation time 235292533 ps
CPU time 25.39 seconds
Started Jun 21 05:16:28 PM PDT 24
Finished Jun 21 05:16:54 PM PDT 24
Peak memory 248928 kb
Host smart-1bd2fb3b-94e4-4d79-b02c-d51689ddd375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39023
76904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3902376904
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.4209139355
Short name T680
Test name
Test status
Simulation time 4576224827 ps
CPU time 62.37 seconds
Started Jun 21 05:16:18 PM PDT 24
Finished Jun 21 05:17:22 PM PDT 24
Peak memory 256428 kb
Host smart-3194e41f-aa1a-4d17-95ff-9f73a2fd0e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42091
39355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.4209139355
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1823605897
Short name T85
Test name
Test status
Simulation time 66765179928 ps
CPU time 860.14 seconds
Started Jun 21 05:16:29 PM PDT 24
Finished Jun 21 05:30:51 PM PDT 24
Peak memory 265420 kb
Host smart-9db4ab03-bce3-437b-b330-f2df7463beee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823605897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1823605897
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1403434692
Short name T78
Test name
Test status
Simulation time 35529985968 ps
CPU time 1752.33 seconds
Started Jun 21 05:16:30 PM PDT 24
Finished Jun 21 05:45:43 PM PDT 24
Peak memory 287608 kb
Host smart-a4686ea4-20cb-4042-9a96-bb88d4a7270d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403434692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1403434692
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3213567561
Short name T544
Test name
Test status
Simulation time 12071851902 ps
CPU time 150.71 seconds
Started Jun 21 05:16:31 PM PDT 24
Finished Jun 21 05:19:02 PM PDT 24
Peak memory 257268 kb
Host smart-e19dc747-469c-40bb-a383-ce4702f84935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32135
67561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3213567561
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1191845148
Short name T355
Test name
Test status
Simulation time 830491600 ps
CPU time 13.79 seconds
Started Jun 21 05:16:31 PM PDT 24
Finished Jun 21 05:16:46 PM PDT 24
Peak memory 249264 kb
Host smart-4a76284c-0203-40b6-8e47-686d253462c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11918
45148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1191845148
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3524080246
Short name T659
Test name
Test status
Simulation time 115738272064 ps
CPU time 1714.67 seconds
Started Jun 21 05:16:30 PM PDT 24
Finished Jun 21 05:45:06 PM PDT 24
Peak memory 272904 kb
Host smart-4c68893f-7918-4eda-836e-5bbfe6b608eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524080246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3524080246
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1551143186
Short name T4
Test name
Test status
Simulation time 47444809690 ps
CPU time 2553.02 seconds
Started Jun 21 05:16:32 PM PDT 24
Finished Jun 21 05:59:06 PM PDT 24
Peak memory 285688 kb
Host smart-ecba3383-bad2-4cdb-afe7-2b086d68c494
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551143186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1551143186
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.394588858
Short name T588
Test name
Test status
Simulation time 1481069306 ps
CPU time 63.58 seconds
Started Jun 21 05:16:29 PM PDT 24
Finished Jun 21 05:17:33 PM PDT 24
Peak memory 248148 kb
Host smart-d2bac4bf-a0d5-4c47-9c6c-1e3d8f52caf7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394588858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.394588858
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.234813855
Short name T693
Test name
Test status
Simulation time 27801709 ps
CPU time 4.87 seconds
Started Jun 21 05:16:29 PM PDT 24
Finished Jun 21 05:16:35 PM PDT 24
Peak memory 240844 kb
Host smart-5792b0c9-6dce-4141-9ebd-fef671069acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23481
3855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.234813855
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1606059498
Short name T29
Test name
Test status
Simulation time 231306581 ps
CPU time 26.66 seconds
Started Jun 21 05:16:29 PM PDT 24
Finished Jun 21 05:16:56 PM PDT 24
Peak memory 255824 kb
Host smart-16abc919-886d-443c-81a4-adee85a96d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16060
59498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1606059498
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3078933903
Short name T479
Test name
Test status
Simulation time 4358597917 ps
CPU time 47.3 seconds
Started Jun 21 05:16:29 PM PDT 24
Finished Jun 21 05:17:17 PM PDT 24
Peak memory 248616 kb
Host smart-ceea390e-9fc5-4b9d-a6a9-5948958a3a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30789
33903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3078933903
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3897896271
Short name T639
Test name
Test status
Simulation time 42892265 ps
CPU time 3.84 seconds
Started Jun 21 05:16:30 PM PDT 24
Finished Jun 21 05:16:35 PM PDT 24
Peak memory 240880 kb
Host smart-39dde4f1-c9f2-4015-aa8b-5f1f77b31724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38978
96271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3897896271
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.825169453
Short name T66
Test name
Test status
Simulation time 228664357057 ps
CPU time 2387.59 seconds
Started Jun 21 05:16:36 PM PDT 24
Finished Jun 21 05:56:25 PM PDT 24
Peak memory 289368 kb
Host smart-50db807e-e366-4ab0-a656-d2e5c0d68436
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825169453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.825169453
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.675398881
Short name T441
Test name
Test status
Simulation time 1514139563 ps
CPU time 144.44 seconds
Started Jun 21 05:16:29 PM PDT 24
Finished Jun 21 05:18:55 PM PDT 24
Peak memory 257196 kb
Host smart-664f58e4-9387-4375-b501-115f1c910684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67539
8881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.675398881
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.186044296
Short name T549
Test name
Test status
Simulation time 16575975 ps
CPU time 2.95 seconds
Started Jun 21 05:16:29 PM PDT 24
Finished Jun 21 05:16:33 PM PDT 24
Peak memory 240856 kb
Host smart-83a4a13f-ee9c-4388-a633-06491e9e7e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18604
4296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.186044296
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.4107867846
Short name T46
Test name
Test status
Simulation time 15201753561 ps
CPU time 1123.78 seconds
Started Jun 21 05:16:37 PM PDT 24
Finished Jun 21 05:35:22 PM PDT 24
Peak memory 273716 kb
Host smart-d438d69e-23fa-4702-bec0-706b261afa96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107867846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.4107867846
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.784762165
Short name T397
Test name
Test status
Simulation time 19455270205 ps
CPU time 1864.77 seconds
Started Jun 21 05:16:35 PM PDT 24
Finished Jun 21 05:47:41 PM PDT 24
Peak memory 289800 kb
Host smart-61cf5962-1f9d-4045-a43d-c6e02faa2fd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784762165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.784762165
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1013846060
Short name T684
Test name
Test status
Simulation time 2567738169 ps
CPU time 101.83 seconds
Started Jun 21 05:16:37 PM PDT 24
Finished Jun 21 05:18:19 PM PDT 24
Peak memory 248544 kb
Host smart-073a044f-d8be-4949-9ef5-dea7057e28da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013846060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1013846060
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3751074379
Short name T227
Test name
Test status
Simulation time 2269684341 ps
CPU time 66.95 seconds
Started Jun 21 05:16:31 PM PDT 24
Finished Jun 21 05:17:39 PM PDT 24
Peak memory 256616 kb
Host smart-8b525fb6-9ca5-4878-9c70-d0f804878b85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37510
74379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3751074379
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.3551854198
Short name T468
Test name
Test status
Simulation time 852798074 ps
CPU time 50.24 seconds
Started Jun 21 05:16:31 PM PDT 24
Finished Jun 21 05:17:22 PM PDT 24
Peak memory 255836 kb
Host smart-2cfef19c-381b-43ab-9b1d-df280fd2d7b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35518
54198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3551854198
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1481431691
Short name T512
Test name
Test status
Simulation time 1812025343 ps
CPU time 57.44 seconds
Started Jun 21 05:16:29 PM PDT 24
Finished Jun 21 05:17:27 PM PDT 24
Peak memory 256188 kb
Host smart-82a9d16f-be27-4d6d-b40a-e8c19b1d00dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14814
31691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1481431691
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2219699123
Short name T119
Test name
Test status
Simulation time 1961259168 ps
CPU time 26.75 seconds
Started Jun 21 05:16:30 PM PDT 24
Finished Jun 21 05:16:58 PM PDT 24
Peak memory 248988 kb
Host smart-a4f9e6eb-029e-472f-b803-920f39d2ab71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22196
99123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2219699123
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.967447264
Short name T699
Test name
Test status
Simulation time 181027905629 ps
CPU time 1906.58 seconds
Started Jun 21 05:16:37 PM PDT 24
Finished Jun 21 05:48:25 PM PDT 24
Peak memory 289392 kb
Host smart-51548e89-5e13-412d-a4b9-706829c0d1d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967447264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.967447264
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3968074941
Short name T550
Test name
Test status
Simulation time 447015219861 ps
CPU time 1605.07 seconds
Started Jun 21 05:16:34 PM PDT 24
Finished Jun 21 05:43:20 PM PDT 24
Peak memory 267592 kb
Host smart-871056de-33eb-49d6-900b-f5a952f76bec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968074941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3968074941
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3229398028
Short name T685
Test name
Test status
Simulation time 3707692563 ps
CPU time 63.99 seconds
Started Jun 21 05:16:36 PM PDT 24
Finished Jun 21 05:17:41 PM PDT 24
Peak memory 257168 kb
Host smart-b7deee71-aa55-451d-a8d8-8212f9988fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32293
98028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3229398028
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.772931057
Short name T291
Test name
Test status
Simulation time 10856779420 ps
CPU time 68.71 seconds
Started Jun 21 05:16:39 PM PDT 24
Finished Jun 21 05:17:48 PM PDT 24
Peak memory 249112 kb
Host smart-4ebc40ae-22b2-4bfd-a1b7-138f249605a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77293
1057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.772931057
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.4207611568
Short name T300
Test name
Test status
Simulation time 30106336745 ps
CPU time 1329.45 seconds
Started Jun 21 05:16:37 PM PDT 24
Finished Jun 21 05:38:47 PM PDT 24
Peak memory 281808 kb
Host smart-81eeadc1-1e31-4f72-9f2f-1c0c78633b8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207611568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.4207611568
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1882631476
Short name T430
Test name
Test status
Simulation time 120164150292 ps
CPU time 1637.98 seconds
Started Jun 21 05:16:36 PM PDT 24
Finished Jun 21 05:43:56 PM PDT 24
Peak memory 273660 kb
Host smart-918ea091-7859-46a3-aa82-c3711acf83aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882631476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1882631476
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3414579127
Short name T306
Test name
Test status
Simulation time 8040025300 ps
CPU time 328.91 seconds
Started Jun 21 05:16:35 PM PDT 24
Finished Jun 21 05:22:05 PM PDT 24
Peak memory 248668 kb
Host smart-8e2afcd5-0db8-4d98-b508-f5ec76014332
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414579127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3414579127
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3447370297
Short name T602
Test name
Test status
Simulation time 245291537 ps
CPU time 17.22 seconds
Started Jun 21 05:16:36 PM PDT 24
Finished Jun 21 05:16:54 PM PDT 24
Peak memory 249456 kb
Host smart-8a1ab8f0-5de5-45c1-87cc-68df5bb89b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34473
70297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3447370297
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2921924105
Short name T440
Test name
Test status
Simulation time 687735194 ps
CPU time 17.79 seconds
Started Jun 21 05:16:40 PM PDT 24
Finished Jun 21 05:16:59 PM PDT 24
Peak memory 248068 kb
Host smart-41300fbe-3c5b-4e4f-97fc-020eed5a98e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29219
24105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2921924105
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.941974363
Short name T481
Test name
Test status
Simulation time 3041702309 ps
CPU time 57.36 seconds
Started Jun 21 05:16:36 PM PDT 24
Finished Jun 21 05:17:34 PM PDT 24
Peak memory 256744 kb
Host smart-08f38a77-11b1-4765-993a-8e265c2ddd1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94197
4363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.941974363
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2944353266
Short name T642
Test name
Test status
Simulation time 713854894 ps
CPU time 20.19 seconds
Started Jun 21 05:16:37 PM PDT 24
Finished Jun 21 05:16:58 PM PDT 24
Peak memory 257208 kb
Host smart-2b106c01-d589-4af5-9924-ae9811095153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29443
53266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2944353266
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3292287012
Short name T434
Test name
Test status
Simulation time 8572927580 ps
CPU time 738.05 seconds
Started Jun 21 05:16:38 PM PDT 24
Finished Jun 21 05:28:56 PM PDT 24
Peak memory 273176 kb
Host smart-070899de-248a-403a-9366-40bc9a6eadd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292287012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3292287012
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2071260609
Short name T471
Test name
Test status
Simulation time 2275126570 ps
CPU time 39.2 seconds
Started Jun 21 05:16:36 PM PDT 24
Finished Jun 21 05:17:16 PM PDT 24
Peak memory 249076 kb
Host smart-0f67414b-be51-4c13-b065-a1473a382667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20712
60609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2071260609
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1510146398
Short name T454
Test name
Test status
Simulation time 1137949024 ps
CPU time 28.47 seconds
Started Jun 21 05:16:41 PM PDT 24
Finished Jun 21 05:17:10 PM PDT 24
Peak memory 249044 kb
Host smart-360f9088-6dc0-437a-8655-778d12230d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15101
46398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1510146398
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2858443184
Short name T710
Test name
Test status
Simulation time 127587898383 ps
CPU time 1906.05 seconds
Started Jun 21 05:16:44 PM PDT 24
Finished Jun 21 05:48:31 PM PDT 24
Peak memory 273212 kb
Host smart-e9667742-e9de-44a5-b534-cc1d3948e760
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858443184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2858443184
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.4069696294
Short name T447
Test name
Test status
Simulation time 45527439389 ps
CPU time 595.87 seconds
Started Jun 21 05:16:45 PM PDT 24
Finished Jun 21 05:26:42 PM PDT 24
Peak memory 272684 kb
Host smart-589f95a4-6d72-4402-b714-0716c408d33a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069696294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.4069696294
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3239494035
Short name T316
Test name
Test status
Simulation time 21980073998 ps
CPU time 233.47 seconds
Started Jun 21 05:16:45 PM PDT 24
Finished Jun 21 05:20:40 PM PDT 24
Peak memory 248624 kb
Host smart-0e9b650a-2fca-4c11-bf91-7bb1846e9c2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239494035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3239494035
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.687481272
Short name T362
Test name
Test status
Simulation time 514542083 ps
CPU time 26.69 seconds
Started Jun 21 05:16:35 PM PDT 24
Finished Jun 21 05:17:03 PM PDT 24
Peak memory 249044 kb
Host smart-b906875d-22a1-48bc-aa9c-9f514240e812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68748
1272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.687481272
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2016896041
Short name T439
Test name
Test status
Simulation time 5643756745 ps
CPU time 38.17 seconds
Started Jun 21 05:16:37 PM PDT 24
Finished Jun 21 05:17:16 PM PDT 24
Peak memory 256156 kb
Host smart-a27987bc-b3d1-450a-a4a6-ec2a78d86bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20168
96041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2016896041
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1505165439
Short name T27
Test name
Test status
Simulation time 3179390250 ps
CPU time 31.91 seconds
Started Jun 21 05:16:35 PM PDT 24
Finished Jun 21 05:17:08 PM PDT 24
Peak memory 248136 kb
Host smart-38f1ece5-85ae-4b12-ae0f-402439dbf928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15051
65439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1505165439
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3463928155
Short name T400
Test name
Test status
Simulation time 1203443532 ps
CPU time 20.64 seconds
Started Jun 21 05:16:36 PM PDT 24
Finished Jun 21 05:16:58 PM PDT 24
Peak memory 249000 kb
Host smart-6c672ff5-9ef6-465e-ba0a-360ec5dd5919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34639
28155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3463928155
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3803913373
Short name T82
Test name
Test status
Simulation time 56547992045 ps
CPU time 1617.99 seconds
Started Jun 21 05:16:44 PM PDT 24
Finished Jun 21 05:43:44 PM PDT 24
Peak memory 272960 kb
Host smart-936d818f-093d-499f-8e9b-8fbdbbcb50c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803913373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3803913373
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3707808923
Short name T521
Test name
Test status
Simulation time 462112991 ps
CPU time 6.96 seconds
Started Jun 21 05:16:47 PM PDT 24
Finished Jun 21 05:16:55 PM PDT 24
Peak memory 250272 kb
Host smart-bb2abebe-3b76-434e-9b20-1f45502e7c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37078
08923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3707808923
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.397713053
Short name T621
Test name
Test status
Simulation time 167667250904 ps
CPU time 1502.26 seconds
Started Jun 21 05:16:46 PM PDT 24
Finished Jun 21 05:41:49 PM PDT 24
Peak memory 273676 kb
Host smart-bf62f1e4-05b0-49bd-b1d6-77ebc450973a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397713053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.397713053
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2355741450
Short name T311
Test name
Test status
Simulation time 21830127491 ps
CPU time 411.81 seconds
Started Jun 21 05:16:43 PM PDT 24
Finished Jun 21 05:23:36 PM PDT 24
Peak memory 248776 kb
Host smart-8af9f5ad-3cb4-484b-ae36-f9f06c95adbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355741450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2355741450
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.334131649
Short name T452
Test name
Test status
Simulation time 550801399 ps
CPU time 31.52 seconds
Started Jun 21 05:16:45 PM PDT 24
Finished Jun 21 05:17:18 PM PDT 24
Peak memory 249040 kb
Host smart-329f5f9d-09cd-47ed-8780-226cf3dd0832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33413
1649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.334131649
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.4266617124
Short name T412
Test name
Test status
Simulation time 6011931325 ps
CPU time 57.58 seconds
Started Jun 21 05:16:45 PM PDT 24
Finished Jun 21 05:17:43 PM PDT 24
Peak memory 255524 kb
Host smart-81293967-dcba-470a-8e3a-bf6ec88b195a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42666
17124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.4266617124
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3336261899
Short name T232
Test name
Test status
Simulation time 78687363 ps
CPU time 11.87 seconds
Started Jun 21 05:16:44 PM PDT 24
Finished Jun 21 05:16:56 PM PDT 24
Peak memory 249052 kb
Host smart-7e532047-b6dc-4bf4-acf8-9d2c2571c8df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33362
61899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3336261899
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1321374435
Short name T504
Test name
Test status
Simulation time 2999298993 ps
CPU time 39.62 seconds
Started Jun 21 05:16:47 PM PDT 24
Finished Jun 21 05:17:28 PM PDT 24
Peak memory 257196 kb
Host smart-24847abc-3d12-4933-abdd-6319d209a538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13213
74435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1321374435
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1517196623
Short name T663
Test name
Test status
Simulation time 172378790129 ps
CPU time 2533.42 seconds
Started Jun 21 05:16:44 PM PDT 24
Finished Jun 21 05:58:58 PM PDT 24
Peak memory 289288 kb
Host smart-fffdcee9-df81-4ab8-9af5-4ccab41f2e5e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517196623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1517196623
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3301752634
Short name T541
Test name
Test status
Simulation time 67514349905 ps
CPU time 1749.75 seconds
Started Jun 21 05:16:45 PM PDT 24
Finished Jun 21 05:45:55 PM PDT 24
Peak memory 289140 kb
Host smart-49b61daa-e08b-4664-956b-e013219efd92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301752634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3301752634
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3099298561
Short name T618
Test name
Test status
Simulation time 528155391 ps
CPU time 27.47 seconds
Started Jun 21 05:16:46 PM PDT 24
Finished Jun 21 05:17:14 PM PDT 24
Peak memory 249240 kb
Host smart-0194e43e-57d3-4ff2-a741-67dfb7bbf8ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30992
98561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3099298561
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.453273253
Short name T703
Test name
Test status
Simulation time 319502619 ps
CPU time 18.26 seconds
Started Jun 21 05:16:47 PM PDT 24
Finished Jun 21 05:17:06 PM PDT 24
Peak memory 255904 kb
Host smart-fec42b7f-d3c0-4b06-8e7b-bf79fae31e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45327
3253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.453273253
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1108574220
Short name T334
Test name
Test status
Simulation time 45847188835 ps
CPU time 1391.1 seconds
Started Jun 21 05:16:44 PM PDT 24
Finished Jun 21 05:39:57 PM PDT 24
Peak memory 265492 kb
Host smart-5474713a-3cac-4d6e-83fc-700486b83522
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108574220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1108574220
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1901061572
Short name T419
Test name
Test status
Simulation time 77138125190 ps
CPU time 1676.73 seconds
Started Jun 21 05:16:55 PM PDT 24
Finished Jun 21 05:44:53 PM PDT 24
Peak memory 289648 kb
Host smart-6e604a86-b9b7-4f78-9151-780241422ebf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901061572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1901061572
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2011096246
Short name T529
Test name
Test status
Simulation time 21106111443 ps
CPU time 562.6 seconds
Started Jun 21 05:16:44 PM PDT 24
Finished Jun 21 05:26:08 PM PDT 24
Peak memory 248560 kb
Host smart-bc9b8367-e579-4ad1-bba6-122734e5bccf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011096246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2011096246
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3496674008
Short name T540
Test name
Test status
Simulation time 241448031 ps
CPU time 16.4 seconds
Started Jun 21 05:16:44 PM PDT 24
Finished Jun 21 05:17:02 PM PDT 24
Peak memory 256668 kb
Host smart-48fda98a-ea82-44de-a9c4-3448ab55ff32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34966
74008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3496674008
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.3880186213
Short name T486
Test name
Test status
Simulation time 322585094 ps
CPU time 13.05 seconds
Started Jun 21 05:16:47 PM PDT 24
Finished Jun 21 05:17:01 PM PDT 24
Peak memory 255008 kb
Host smart-1cffd687-e8da-4247-ab39-a0367c96ca27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38801
86213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3880186213
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3433135359
Short name T423
Test name
Test status
Simulation time 4601680858 ps
CPU time 48.03 seconds
Started Jun 21 05:16:45 PM PDT 24
Finished Jun 21 05:17:34 PM PDT 24
Peak memory 255976 kb
Host smart-7603341e-e7ed-4a9f-9058-5fc49c39dd35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34331
35359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3433135359
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.179729229
Short name T455
Test name
Test status
Simulation time 749479654 ps
CPU time 32.18 seconds
Started Jun 21 05:16:45 PM PDT 24
Finished Jun 21 05:17:18 PM PDT 24
Peak memory 249032 kb
Host smart-8babacd9-bb50-4c84-8b4b-68b8ce46c417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17972
9229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.179729229
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2830561189
Short name T583
Test name
Test status
Simulation time 43261146853 ps
CPU time 2269.87 seconds
Started Jun 21 05:16:58 PM PDT 24
Finished Jun 21 05:54:48 PM PDT 24
Peak memory 285492 kb
Host smart-7ccc916f-1027-41e6-9cb8-77d79d22dd16
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830561189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2830561189
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.497781405
Short name T208
Test name
Test status
Simulation time 101433397 ps
CPU time 4.44 seconds
Started Jun 21 05:14:54 PM PDT 24
Finished Jun 21 05:15:02 PM PDT 24
Peak memory 249184 kb
Host smart-2e148b93-d60f-4309-9fdb-07bf346409d6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=497781405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.497781405
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1169652308
Short name T678
Test name
Test status
Simulation time 14794729925 ps
CPU time 1104.18 seconds
Started Jun 21 05:14:51 PM PDT 24
Finished Jun 21 05:33:20 PM PDT 24
Peak memory 288808 kb
Host smart-12989840-2326-44ec-b485-906b88b69c47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169652308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1169652308
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.618597441
Short name T696
Test name
Test status
Simulation time 461438329 ps
CPU time 19.96 seconds
Started Jun 21 05:14:55 PM PDT 24
Finished Jun 21 05:15:19 PM PDT 24
Peak memory 249040 kb
Host smart-633b7df6-29f3-4a44-961e-08bf83d2d639
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=618597441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.618597441
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1869940957
Short name T375
Test name
Test status
Simulation time 1528228548 ps
CPU time 140.44 seconds
Started Jun 21 05:14:55 PM PDT 24
Finished Jun 21 05:17:19 PM PDT 24
Peak memory 257108 kb
Host smart-0d01012b-d176-40a6-b78a-70cd8bc37bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18699
40957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1869940957
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2789652183
Short name T503
Test name
Test status
Simulation time 2321989891 ps
CPU time 32.19 seconds
Started Jun 21 05:14:53 PM PDT 24
Finished Jun 21 05:15:30 PM PDT 24
Peak memory 249108 kb
Host smart-3cd28b61-0f89-43dd-bd1d-461fcfb84236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27896
52183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2789652183
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.857359919
Short name T193
Test name
Test status
Simulation time 205475233290 ps
CPU time 1137.01 seconds
Started Jun 21 05:15:00 PM PDT 24
Finished Jun 21 05:33:59 PM PDT 24
Peak memory 265560 kb
Host smart-469cf90e-940a-47cc-9599-3a7b29ac47bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857359919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.857359919
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.391240544
Short name T34
Test name
Test status
Simulation time 74371575585 ps
CPU time 2582.34 seconds
Started Jun 21 05:14:55 PM PDT 24
Finished Jun 21 05:58:02 PM PDT 24
Peak memory 281872 kb
Host smart-72da0376-433b-419b-a5e6-29be59e3248b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391240544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.391240544
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.144330108
Short name T702
Test name
Test status
Simulation time 6616669999 ps
CPU time 281.59 seconds
Started Jun 21 05:14:55 PM PDT 24
Finished Jun 21 05:19:40 PM PDT 24
Peak memory 247508 kb
Host smart-d6e0a03a-2ee4-4f39-a22e-7d37f663efeb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144330108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.144330108
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1179969659
Short name T555
Test name
Test status
Simulation time 407430127 ps
CPU time 29.94 seconds
Started Jun 21 05:14:51 PM PDT 24
Finished Jun 21 05:15:26 PM PDT 24
Peak memory 257156 kb
Host smart-8276b5df-d072-408a-969a-211ffbcd0ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11799
69659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1179969659
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1331146848
Short name T598
Test name
Test status
Simulation time 31260755 ps
CPU time 4.41 seconds
Started Jun 21 05:14:53 PM PDT 24
Finished Jun 21 05:15:02 PM PDT 24
Peak memory 239640 kb
Host smart-8c3d7d19-0cc3-4ce4-9520-1b2d22e2e4c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13311
46848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1331146848
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1171452279
Short name T41
Test name
Test status
Simulation time 944633500 ps
CPU time 14.97 seconds
Started Jun 21 05:14:54 PM PDT 24
Finished Jun 21 05:15:13 PM PDT 24
Peak memory 271308 kb
Host smart-f6ea31e7-c666-42dc-8599-e2d67554e386
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1171452279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1171452279
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.351164770
Short name T71
Test name
Test status
Simulation time 560618161 ps
CPU time 18.05 seconds
Started Jun 21 05:14:55 PM PDT 24
Finished Jun 21 05:15:17 PM PDT 24
Peak memory 255048 kb
Host smart-8f0ddd77-395d-4506-b617-174af9c6c199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35116
4770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.351164770
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.4069987229
Short name T446
Test name
Test status
Simulation time 800273667 ps
CPU time 42.69 seconds
Started Jun 21 05:14:52 PM PDT 24
Finished Jun 21 05:15:40 PM PDT 24
Peak memory 249024 kb
Host smart-3b68c8af-34bb-447a-91eb-837019f74060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40699
87229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.4069987229
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3839065859
Short name T61
Test name
Test status
Simulation time 35037667837 ps
CPU time 1555.01 seconds
Started Jun 21 05:14:54 PM PDT 24
Finished Jun 21 05:40:54 PM PDT 24
Peak memory 290056 kb
Host smart-abf37653-1f26-4e16-95dd-d33b6f3652ca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839065859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3839065859
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.1908684206
Short name T84
Test name
Test status
Simulation time 27318964428 ps
CPU time 3326.5 seconds
Started Jun 21 05:14:59 PM PDT 24
Finished Jun 21 06:10:28 PM PDT 24
Peak memory 318296 kb
Host smart-790aa13b-7e46-4854-a00b-6a1efe32ed0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908684206 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.1908684206
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1062542107
Short name T705
Test name
Test status
Simulation time 5386138071 ps
CPU time 593.58 seconds
Started Jun 21 05:16:55 PM PDT 24
Finished Jun 21 05:26:50 PM PDT 24
Peak memory 272888 kb
Host smart-c8d0450d-df6c-40c0-a7e1-a9a779d3d1fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062542107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1062542107
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1084953019
Short name T564
Test name
Test status
Simulation time 6177191592 ps
CPU time 134.12 seconds
Started Jun 21 05:16:54 PM PDT 24
Finished Jun 21 05:19:09 PM PDT 24
Peak memory 257268 kb
Host smart-dc2d2ccf-464f-4b69-bac9-a18269375664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10849
53019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1084953019
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3542713983
Short name T361
Test name
Test status
Simulation time 1378974392 ps
CPU time 21.64 seconds
Started Jun 21 05:16:54 PM PDT 24
Finished Jun 21 05:17:17 PM PDT 24
Peak memory 255304 kb
Host smart-7d52167d-8a64-4f13-901c-7e9ed8817962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35427
13983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3542713983
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1342365839
Short name T337
Test name
Test status
Simulation time 39576971206 ps
CPU time 904.59 seconds
Started Jun 21 05:16:54 PM PDT 24
Finished Jun 21 05:31:59 PM PDT 24
Peak memory 272800 kb
Host smart-e9165e2d-9a5c-4366-82a4-41bdb954abae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342365839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1342365839
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1339709875
Short name T654
Test name
Test status
Simulation time 26238498866 ps
CPU time 1211.79 seconds
Started Jun 21 05:16:57 PM PDT 24
Finished Jun 21 05:37:10 PM PDT 24
Peak memory 289544 kb
Host smart-38be08d7-082c-4ceb-a686-a45e49724d88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339709875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1339709875
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.4015901934
Short name T494
Test name
Test status
Simulation time 193359532 ps
CPU time 26.02 seconds
Started Jun 21 05:16:53 PM PDT 24
Finished Jun 21 05:17:20 PM PDT 24
Peak memory 248976 kb
Host smart-1eab638a-6d0c-4dad-a042-6ee7e880819d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40159
01934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.4015901934
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3211513572
Short name T238
Test name
Test status
Simulation time 183083833 ps
CPU time 15.83 seconds
Started Jun 21 05:16:52 PM PDT 24
Finished Jun 21 05:17:08 PM PDT 24
Peak memory 249068 kb
Host smart-e069059d-b49a-484e-943c-82818753f0ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32115
13572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3211513572
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1786335076
Short name T636
Test name
Test status
Simulation time 879608868 ps
CPU time 50.67 seconds
Started Jun 21 05:16:52 PM PDT 24
Finished Jun 21 05:17:44 PM PDT 24
Peak memory 248060 kb
Host smart-4435c4f1-611e-4910-b99a-d29925273108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17863
35076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1786335076
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.53948380
Short name T665
Test name
Test status
Simulation time 1507711778 ps
CPU time 34.74 seconds
Started Jun 21 05:16:54 PM PDT 24
Finished Jun 21 05:17:30 PM PDT 24
Peak memory 257164 kb
Host smart-cc13ce5c-2e6f-49b4-bd0c-e82dbc091bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53948
380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.53948380
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.795779798
Short name T657
Test name
Test status
Simulation time 13234585283 ps
CPU time 222.02 seconds
Started Jun 21 05:16:55 PM PDT 24
Finished Jun 21 05:20:38 PM PDT 24
Peak memory 257188 kb
Host smart-9f330584-0a60-496a-9a8b-cccf4f2d0b41
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795779798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.795779798
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.3773064297
Short name T548
Test name
Test status
Simulation time 153458667764 ps
CPU time 3816.38 seconds
Started Jun 21 05:16:58 PM PDT 24
Finished Jun 21 06:20:35 PM PDT 24
Peak memory 339216 kb
Host smart-1108ad46-6511-4896-b039-0642fb2b516e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773064297 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.3773064297
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2440305315
Short name T469
Test name
Test status
Simulation time 11475131572 ps
CPU time 1149.39 seconds
Started Jun 21 05:16:53 PM PDT 24
Finished Jun 21 05:36:03 PM PDT 24
Peak memory 289476 kb
Host smart-ea7882d9-2c96-4a7c-9885-f4dcb9af2682
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440305315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2440305315
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3005821191
Short name T623
Test name
Test status
Simulation time 7904886274 ps
CPU time 128.05 seconds
Started Jun 21 05:16:52 PM PDT 24
Finished Jun 21 05:19:01 PM PDT 24
Peak memory 257244 kb
Host smart-3dab6a82-384b-4f82-af01-36ec16fb4845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30058
21191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3005821191
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2576362126
Short name T74
Test name
Test status
Simulation time 1347700470 ps
CPU time 46.07 seconds
Started Jun 21 05:16:53 PM PDT 24
Finished Jun 21 05:17:41 PM PDT 24
Peak memory 249044 kb
Host smart-57851073-5d8c-4da4-9b40-5ec6a0f80839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25763
62126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2576362126
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.880266581
Short name T239
Test name
Test status
Simulation time 27537657683 ps
CPU time 1375.58 seconds
Started Jun 21 05:16:53 PM PDT 24
Finished Jun 21 05:39:50 PM PDT 24
Peak memory 272312 kb
Host smart-521c4a2f-e4cc-4b83-8e0c-de327fe7e54c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880266581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.880266581
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.601769399
Short name T581
Test name
Test status
Simulation time 20223422829 ps
CPU time 559.3 seconds
Started Jun 21 05:17:00 PM PDT 24
Finished Jun 21 05:26:20 PM PDT 24
Peak memory 272708 kb
Host smart-bf55aa5a-05d2-4ebd-8439-20346604ad33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601769399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.601769399
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3121373334
Short name T323
Test name
Test status
Simulation time 30519964045 ps
CPU time 334.8 seconds
Started Jun 21 05:16:54 PM PDT 24
Finished Jun 21 05:22:30 PM PDT 24
Peak memory 248588 kb
Host smart-914c3203-7cd2-484e-9870-c26a5aff73ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121373334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3121373334
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3980829158
Short name T392
Test name
Test status
Simulation time 146695878 ps
CPU time 12.49 seconds
Started Jun 21 05:16:54 PM PDT 24
Finished Jun 21 05:17:07 PM PDT 24
Peak memory 257220 kb
Host smart-4a4a14c0-79f6-4aec-8997-c8cf4fc1211b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39808
29158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3980829158
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3590713736
Short name T569
Test name
Test status
Simulation time 202678661 ps
CPU time 22.91 seconds
Started Jun 21 05:16:54 PM PDT 24
Finished Jun 21 05:17:18 PM PDT 24
Peak memory 247848 kb
Host smart-6478cd9a-eccf-48b1-bff8-495181640443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35907
13736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3590713736
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.2550733941
Short name T690
Test name
Test status
Simulation time 160290480 ps
CPU time 5.61 seconds
Started Jun 21 05:16:52 PM PDT 24
Finished Jun 21 05:16:59 PM PDT 24
Peak memory 248968 kb
Host smart-e60ae1e0-c55b-43bb-9512-5fc6bf52fddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25507
33941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2550733941
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3877287896
Short name T36
Test name
Test status
Simulation time 713959514 ps
CPU time 41.55 seconds
Started Jun 21 05:16:56 PM PDT 24
Finished Jun 21 05:17:38 PM PDT 24
Peak memory 256132 kb
Host smart-53f40149-5fff-483e-98c5-4da706696127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38772
87896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3877287896
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1545129655
Short name T108
Test name
Test status
Simulation time 86025825536 ps
CPU time 2801.01 seconds
Started Jun 21 05:17:01 PM PDT 24
Finished Jun 21 06:03:43 PM PDT 24
Peak memory 290108 kb
Host smart-13d53c77-cfb0-4ab3-9f34-396ab974d3b1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545129655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1545129655
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.4211412622
Short name T104
Test name
Test status
Simulation time 28596805181 ps
CPU time 969.49 seconds
Started Jun 21 05:17:05 PM PDT 24
Finished Jun 21 05:33:15 PM PDT 24
Peak memory 271852 kb
Host smart-7de02c16-6aa0-4c5c-ba9e-1082c00e6e4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211412622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.4211412622
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3632008407
Short name T459
Test name
Test status
Simulation time 2590772131 ps
CPU time 113.79 seconds
Started Jun 21 05:17:01 PM PDT 24
Finished Jun 21 05:18:56 PM PDT 24
Peak memory 257288 kb
Host smart-fe26c83c-a0fa-4190-9f8b-98eca51ca2bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36320
08407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3632008407
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3399296959
Short name T679
Test name
Test status
Simulation time 342992094 ps
CPU time 6.23 seconds
Started Jun 21 05:17:01 PM PDT 24
Finished Jun 21 05:17:08 PM PDT 24
Peak memory 240808 kb
Host smart-4ce421b7-c495-4ae2-967d-0b0b8b5a60aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33992
96959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3399296959
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.14507861
Short name T5
Test name
Test status
Simulation time 14611272795 ps
CPU time 1199.79 seconds
Started Jun 21 05:17:01 PM PDT 24
Finished Jun 21 05:37:02 PM PDT 24
Peak memory 289596 kb
Host smart-cb8f54f9-6fce-4e19-8959-04139eb96c04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14507861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.14507861
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.379241686
Short name T527
Test name
Test status
Simulation time 50523419226 ps
CPU time 1292.01 seconds
Started Jun 21 05:17:02 PM PDT 24
Finished Jun 21 05:38:35 PM PDT 24
Peak memory 273616 kb
Host smart-8f70f30c-4814-4241-bb23-7bbdec76fa2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379241686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.379241686
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3292451902
Short name T92
Test name
Test status
Simulation time 28078931783 ps
CPU time 198.25 seconds
Started Jun 21 05:17:00 PM PDT 24
Finished Jun 21 05:20:19 PM PDT 24
Peak memory 248628 kb
Host smart-c16d2f9f-90db-4426-9195-b63070bcb3be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292451902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3292451902
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1592122090
Short name T599
Test name
Test status
Simulation time 512567147 ps
CPU time 8.19 seconds
Started Jun 21 05:17:03 PM PDT 24
Finished Jun 21 05:17:12 PM PDT 24
Peak memory 257196 kb
Host smart-49fdf337-9e9c-45e7-9c87-81c9971b2854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15921
22090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1592122090
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1000950857
Short name T520
Test name
Test status
Simulation time 1102632543 ps
CPU time 29.15 seconds
Started Jun 21 05:17:02 PM PDT 24
Finished Jun 21 05:17:32 PM PDT 24
Peak memory 255296 kb
Host smart-51a88421-c038-4926-8a00-bfc756516af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10009
50857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1000950857
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2761858438
Short name T51
Test name
Test status
Simulation time 48967124 ps
CPU time 6.2 seconds
Started Jun 21 05:17:02 PM PDT 24
Finished Jun 21 05:17:09 PM PDT 24
Peak memory 253580 kb
Host smart-d4405dd0-7c34-411a-b881-757656fa65a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27618
58438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2761858438
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2300741997
Short name T661
Test name
Test status
Simulation time 359628842 ps
CPU time 7.39 seconds
Started Jun 21 05:17:02 PM PDT 24
Finished Jun 21 05:17:10 PM PDT 24
Peak memory 257200 kb
Host smart-6bd5979a-7cbb-4157-bbbb-cfe488274dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23007
41997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2300741997
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.696200447
Short name T575
Test name
Test status
Simulation time 48818510891 ps
CPU time 1154.74 seconds
Started Jun 21 05:17:11 PM PDT 24
Finished Jun 21 05:36:27 PM PDT 24
Peak memory 273516 kb
Host smart-374fb462-490d-4e4f-9534-46f577bee839
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696200447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.696200447
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.428409606
Short name T615
Test name
Test status
Simulation time 12542587898 ps
CPU time 160.04 seconds
Started Jun 21 05:17:01 PM PDT 24
Finished Jun 21 05:19:42 PM PDT 24
Peak memory 257272 kb
Host smart-5d296d61-ddda-42b1-8d63-23a05221b273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42840
9606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.428409606
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3984006124
Short name T377
Test name
Test status
Simulation time 762057260 ps
CPU time 32.3 seconds
Started Jun 21 05:17:00 PM PDT 24
Finished Jun 21 05:17:33 PM PDT 24
Peak memory 249448 kb
Host smart-ac776460-03b0-4e63-8d3d-ade4ffb134a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39840
06124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3984006124
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1790244233
Short name T332
Test name
Test status
Simulation time 288993434507 ps
CPU time 1688.23 seconds
Started Jun 21 05:17:12 PM PDT 24
Finished Jun 21 05:45:21 PM PDT 24
Peak memory 289128 kb
Host smart-be5c5ad5-2ab9-4425-9a5a-65e87b215646
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790244233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1790244233
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2640175331
Short name T403
Test name
Test status
Simulation time 33048792092 ps
CPU time 726.33 seconds
Started Jun 21 05:17:11 PM PDT 24
Finished Jun 21 05:29:18 PM PDT 24
Peak memory 271732 kb
Host smart-cd18a611-7001-437c-a763-14570d456a95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640175331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2640175331
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1465118529
Short name T319
Test name
Test status
Simulation time 9537844538 ps
CPU time 373.57 seconds
Started Jun 21 05:17:11 PM PDT 24
Finished Jun 21 05:23:26 PM PDT 24
Peak memory 248688 kb
Host smart-d6c2db94-d847-450c-af55-4515b8dcb400
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465118529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1465118529
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3004085189
Short name T538
Test name
Test status
Simulation time 184411663 ps
CPU time 16.47 seconds
Started Jun 21 05:17:04 PM PDT 24
Finished Jun 21 05:17:21 PM PDT 24
Peak memory 249040 kb
Host smart-8da3c650-8c0f-4790-a417-f9b9ea6330bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30040
85189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3004085189
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1351505772
Short name T638
Test name
Test status
Simulation time 5791818712 ps
CPU time 66.49 seconds
Started Jun 21 05:17:03 PM PDT 24
Finished Jun 21 05:18:10 PM PDT 24
Peak memory 256728 kb
Host smart-e471a9ba-6770-48bc-9ec3-d590ca6fcde5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13515
05772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1351505772
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2813404316
Short name T80
Test name
Test status
Simulation time 2544436017 ps
CPU time 17.09 seconds
Started Jun 21 05:17:03 PM PDT 24
Finished Jun 21 05:17:21 PM PDT 24
Peak memory 255212 kb
Host smart-37eb477b-5c92-42b7-8f76-16dc951f291c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28134
04316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2813404316
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1818297940
Short name T557
Test name
Test status
Simulation time 507658847 ps
CPU time 27.41 seconds
Started Jun 21 05:17:01 PM PDT 24
Finished Jun 21 05:17:30 PM PDT 24
Peak memory 248956 kb
Host smart-f0d98f7d-f952-4634-a8a1-b730f74b3f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18182
97940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1818297940
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2199260771
Short name T280
Test name
Test status
Simulation time 110588994059 ps
CPU time 1193.88 seconds
Started Jun 21 05:17:11 PM PDT 24
Finished Jun 21 05:37:06 PM PDT 24
Peak memory 287440 kb
Host smart-da76b4e5-765f-4afe-b852-ff81e2238549
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199260771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2199260771
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.2553209115
Short name T237
Test name
Test status
Simulation time 110561133926 ps
CPU time 1802.94 seconds
Started Jun 21 05:17:11 PM PDT 24
Finished Jun 21 05:47:14 PM PDT 24
Peak memory 288948 kb
Host smart-04f0c26a-efdb-4d8b-8855-a42c1e8c9063
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553209115 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.2553209115
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.878779746
Short name T418
Test name
Test status
Simulation time 166556456223 ps
CPU time 2425.32 seconds
Started Jun 21 05:17:12 PM PDT 24
Finished Jun 21 05:57:38 PM PDT 24
Peak memory 282992 kb
Host smart-693e0656-a69d-4680-a508-479590b3ea9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878779746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.878779746
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.90654313
Short name T489
Test name
Test status
Simulation time 260396000 ps
CPU time 20.98 seconds
Started Jun 21 05:17:10 PM PDT 24
Finished Jun 21 05:17:31 PM PDT 24
Peak memory 249344 kb
Host smart-a88e9e62-4418-403b-a66b-f8644dd3c4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90654
313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.90654313
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.4198786169
Short name T364
Test name
Test status
Simulation time 245991526 ps
CPU time 7.08 seconds
Started Jun 21 05:17:11 PM PDT 24
Finished Jun 21 05:17:19 PM PDT 24
Peak memory 249356 kb
Host smart-a76e7d2c-c7be-4e23-a95f-75ae3e0362d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41987
86169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.4198786169
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1328575680
Short name T697
Test name
Test status
Simulation time 202636191636 ps
CPU time 1490.32 seconds
Started Jun 21 05:17:13 PM PDT 24
Finished Jun 21 05:42:04 PM PDT 24
Peak memory 265408 kb
Host smart-0544324a-96d7-4fb9-88ac-3eaf4980b2c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328575680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1328575680
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.887341389
Short name T26
Test name
Test status
Simulation time 181878585977 ps
CPU time 2778.25 seconds
Started Jun 21 05:17:12 PM PDT 24
Finished Jun 21 06:03:31 PM PDT 24
Peak memory 289988 kb
Host smart-d951ab93-a1fe-44a1-a333-69b4b480b881
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887341389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.887341389
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.4200925977
Short name T310
Test name
Test status
Simulation time 41773465055 ps
CPU time 295.07 seconds
Started Jun 21 05:17:10 PM PDT 24
Finished Jun 21 05:22:06 PM PDT 24
Peak memory 248416 kb
Host smart-f90ed3dc-30ef-48a5-b19a-943fc2b1b798
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200925977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.4200925977
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.4229146226
Short name T428
Test name
Test status
Simulation time 463883062 ps
CPU time 21.41 seconds
Started Jun 21 05:17:10 PM PDT 24
Finished Jun 21 05:17:32 PM PDT 24
Peak memory 257232 kb
Host smart-2245bf3f-38e6-400f-baee-8f3a857c31f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42291
46226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.4229146226
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3508662980
Short name T625
Test name
Test status
Simulation time 2711907958 ps
CPU time 50.01 seconds
Started Jun 21 05:17:13 PM PDT 24
Finished Jun 21 05:18:04 PM PDT 24
Peak memory 249268 kb
Host smart-526caafe-7e47-4c7e-8ce0-0438241227c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35086
62980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3508662980
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2661500295
Short name T274
Test name
Test status
Simulation time 953011158 ps
CPU time 60.08 seconds
Started Jun 21 05:17:11 PM PDT 24
Finished Jun 21 05:18:11 PM PDT 24
Peak memory 249212 kb
Host smart-4d6de7f8-39ee-4411-8fbc-7f85b0a7c3cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26615
00295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2661500295
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1185179028
Short name T48
Test name
Test status
Simulation time 27332720 ps
CPU time 3.24 seconds
Started Jun 21 05:17:12 PM PDT 24
Finished Jun 21 05:17:16 PM PDT 24
Peak memory 240816 kb
Host smart-7f24c715-d24e-4845-aeba-5eb4f22646b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11851
79028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1185179028
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.96527160
Short name T369
Test name
Test status
Simulation time 13052536433 ps
CPU time 229.05 seconds
Started Jun 21 05:17:11 PM PDT 24
Finished Jun 21 05:21:01 PM PDT 24
Peak memory 257292 kb
Host smart-4ee221c4-ead0-4087-b1f3-1c073797231c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96527160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_hand
ler_stress_all.96527160
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.568015311
Short name T605
Test name
Test status
Simulation time 17957420670 ps
CPU time 1395.1 seconds
Started Jun 21 05:17:11 PM PDT 24
Finished Jun 21 05:40:27 PM PDT 24
Peak memory 290104 kb
Host smart-98b4ce7f-515b-4822-861d-eecdd87225a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568015311 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.568015311
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.97211540
Short name T50
Test name
Test status
Simulation time 27933633324 ps
CPU time 1620.58 seconds
Started Jun 21 05:17:22 PM PDT 24
Finished Jun 21 05:44:23 PM PDT 24
Peak memory 273632 kb
Host smart-df24e77e-bf5a-4c93-81e2-1f1631cca38c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97211540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.97211540
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.279754765
Short name T517
Test name
Test status
Simulation time 2019524764 ps
CPU time 63.24 seconds
Started Jun 21 05:17:24 PM PDT 24
Finished Jun 21 05:18:28 PM PDT 24
Peak memory 249244 kb
Host smart-5b78038c-709f-4347-a7a2-1bb67be40c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27975
4765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.279754765
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.441646511
Short name T382
Test name
Test status
Simulation time 206698869 ps
CPU time 19.6 seconds
Started Jun 21 05:17:26 PM PDT 24
Finished Jun 21 05:17:46 PM PDT 24
Peak memory 247892 kb
Host smart-0429af2c-924a-471d-b336-278b31a3a766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44164
6511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.441646511
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.963252317
Short name T704
Test name
Test status
Simulation time 22737525702 ps
CPU time 1258.6 seconds
Started Jun 21 05:17:24 PM PDT 24
Finished Jun 21 05:38:24 PM PDT 24
Peak memory 273324 kb
Host smart-c1a66692-9a1a-4498-a9ae-1af24bac6661
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963252317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.963252317
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3484675588
Short name T370
Test name
Test status
Simulation time 46080281821 ps
CPU time 1387.87 seconds
Started Jun 21 05:17:24 PM PDT 24
Finished Jun 21 05:40:33 PM PDT 24
Peak memory 265416 kb
Host smart-93b1767a-af6b-49d4-8f83-c578e270ea8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484675588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3484675588
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.515391589
Short name T309
Test name
Test status
Simulation time 41873992328 ps
CPU time 433.86 seconds
Started Jun 21 05:17:23 PM PDT 24
Finished Jun 21 05:24:38 PM PDT 24
Peak memory 248244 kb
Host smart-8cd7ecf6-2ea2-464a-a159-c71ce0ab0a41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515391589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.515391589
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.43743637
Short name T381
Test name
Test status
Simulation time 358770198 ps
CPU time 32.01 seconds
Started Jun 21 05:17:24 PM PDT 24
Finished Jun 21 05:17:57 PM PDT 24
Peak memory 249000 kb
Host smart-cdaac9ff-04eb-4588-ab33-8e425db6809a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43743
637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.43743637
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.116895912
Short name T275
Test name
Test status
Simulation time 319461802 ps
CPU time 21.03 seconds
Started Jun 21 05:17:24 PM PDT 24
Finished Jun 21 05:17:47 PM PDT 24
Peak memory 255696 kb
Host smart-d4b87bec-f8ac-459f-866f-c37c356c4626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11689
5912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.116895912
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3918698749
Short name T617
Test name
Test status
Simulation time 430374177 ps
CPU time 14.69 seconds
Started Jun 21 05:17:23 PM PDT 24
Finished Jun 21 05:17:40 PM PDT 24
Peak memory 247964 kb
Host smart-ee00a7ea-8be8-4d4d-aa59-34cc7c4866fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39186
98749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3918698749
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2612475798
Short name T390
Test name
Test status
Simulation time 3467065699 ps
CPU time 59.37 seconds
Started Jun 21 05:17:13 PM PDT 24
Finished Jun 21 05:18:13 PM PDT 24
Peak memory 256584 kb
Host smart-03aa6604-c153-4db9-964a-b70a08326258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26124
75798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2612475798
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.3814199936
Short name T656
Test name
Test status
Simulation time 27063798259 ps
CPU time 2974.5 seconds
Started Jun 21 05:17:23 PM PDT 24
Finished Jun 21 06:07:00 PM PDT 24
Peak memory 322144 kb
Host smart-df16ef74-5156-43df-9255-1ddd6b8d6acd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814199936 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.3814199936
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3624123417
Short name T79
Test name
Test status
Simulation time 25069052757 ps
CPU time 1509.44 seconds
Started Jun 21 05:17:27 PM PDT 24
Finished Jun 21 05:42:37 PM PDT 24
Peak memory 269620 kb
Host smart-0b5da230-0b7a-4ed3-aed8-b07b29aefbac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624123417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3624123417
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2148185770
Short name T649
Test name
Test status
Simulation time 50724668 ps
CPU time 2.84 seconds
Started Jun 21 05:17:26 PM PDT 24
Finished Jun 21 05:17:29 PM PDT 24
Peak memory 239772 kb
Host smart-c37eab4b-92f2-4252-b52b-e0310d86d6ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21481
85770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2148185770
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.163712923
Short name T387
Test name
Test status
Simulation time 338719843 ps
CPU time 30.08 seconds
Started Jun 21 05:17:27 PM PDT 24
Finished Jun 21 05:17:58 PM PDT 24
Peak memory 248980 kb
Host smart-b05fa843-74b9-49f0-87e8-ad9684ff13e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16371
2923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.163712923
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.846024970
Short name T328
Test name
Test status
Simulation time 30268021255 ps
CPU time 747.6 seconds
Started Jun 21 05:17:24 PM PDT 24
Finished Jun 21 05:29:53 PM PDT 24
Peak memory 272328 kb
Host smart-75720b8f-3c9b-4845-b6a2-a7187377a0cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846024970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.846024970
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2969840880
Short name T483
Test name
Test status
Simulation time 30569925380 ps
CPU time 881.83 seconds
Started Jun 21 05:17:22 PM PDT 24
Finished Jun 21 05:32:05 PM PDT 24
Peak memory 273620 kb
Host smart-6207457c-d2c6-4d5c-a80e-c25e6712f9ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969840880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2969840880
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2740737685
Short name T313
Test name
Test status
Simulation time 26776858301 ps
CPU time 567.6 seconds
Started Jun 21 05:17:26 PM PDT 24
Finished Jun 21 05:26:54 PM PDT 24
Peak memory 248324 kb
Host smart-6f6584d5-9868-4969-b7ec-11b7bba90093
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740737685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2740737685
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.112257980
Short name T44
Test name
Test status
Simulation time 1133450146 ps
CPU time 59.73 seconds
Started Jun 21 05:17:24 PM PDT 24
Finished Jun 21 05:18:25 PM PDT 24
Peak memory 255820 kb
Host smart-51fb9010-645f-40f0-a51b-e441433cc459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11225
7980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.112257980
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1612935848
Short name T668
Test name
Test status
Simulation time 716842494 ps
CPU time 38.21 seconds
Started Jun 21 05:17:26 PM PDT 24
Finished Jun 21 05:18:05 PM PDT 24
Peak memory 255908 kb
Host smart-6b68d14a-b6d2-4490-8ebf-9dbd0d338511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16129
35848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1612935848
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.787617954
Short name T607
Test name
Test status
Simulation time 1165401423 ps
CPU time 32.84 seconds
Started Jun 21 05:17:25 PM PDT 24
Finished Jun 21 05:17:59 PM PDT 24
Peak memory 248956 kb
Host smart-2237f9af-6ea9-40cf-8b80-9aabfc2be9cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78761
7954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.787617954
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3820176435
Short name T267
Test name
Test status
Simulation time 298882115908 ps
CPU time 2928.6 seconds
Started Jun 21 05:17:24 PM PDT 24
Finished Jun 21 06:06:14 PM PDT 24
Peak memory 289952 kb
Host smart-c34163e9-eb85-4578-943a-aaf8feb61a51
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820176435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3820176435
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.3109926444
Short name T60
Test name
Test status
Simulation time 116649230153 ps
CPU time 3333.33 seconds
Started Jun 21 05:17:38 PM PDT 24
Finished Jun 21 06:13:13 PM PDT 24
Peak memory 322788 kb
Host smart-399bf9e3-621c-4441-9728-995aa78bd91a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109926444 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.3109926444
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.169129505
Short name T14
Test name
Test status
Simulation time 47530160583 ps
CPU time 2398.68 seconds
Started Jun 21 05:17:36 PM PDT 24
Finished Jun 21 05:57:36 PM PDT 24
Peak memory 284196 kb
Host smart-dc1b9556-34be-491b-934e-2600fd4bc306
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169129505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.169129505
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2834067925
Short name T562
Test name
Test status
Simulation time 1462253807 ps
CPU time 124.45 seconds
Started Jun 21 05:17:37 PM PDT 24
Finished Jun 21 05:19:42 PM PDT 24
Peak memory 257240 kb
Host smart-97f37ef6-9888-49e1-b204-bae828be5104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28340
67925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2834067925
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.485537458
Short name T394
Test name
Test status
Simulation time 320514947 ps
CPU time 23.29 seconds
Started Jun 21 05:17:33 PM PDT 24
Finished Jun 21 05:17:57 PM PDT 24
Peak memory 256480 kb
Host smart-31810d77-d75e-4809-82fd-3d4e331e36bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48553
7458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.485537458
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.756931903
Short name T556
Test name
Test status
Simulation time 37926204456 ps
CPU time 898.59 seconds
Started Jun 21 05:17:33 PM PDT 24
Finished Jun 21 05:32:32 PM PDT 24
Peak memory 273572 kb
Host smart-51a01e7c-1c9d-4bea-b38e-d583ebb9e345
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756931903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.756931903
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1745265424
Short name T612
Test name
Test status
Simulation time 18900192539 ps
CPU time 870.33 seconds
Started Jun 21 05:17:38 PM PDT 24
Finished Jun 21 05:32:09 PM PDT 24
Peak memory 271640 kb
Host smart-815067a5-611d-4377-85d7-5a8029500519
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745265424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1745265424
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2746199558
Short name T314
Test name
Test status
Simulation time 9045796450 ps
CPU time 289.36 seconds
Started Jun 21 05:17:33 PM PDT 24
Finished Jun 21 05:22:23 PM PDT 24
Peak memory 248632 kb
Host smart-bba445fd-28d5-4ac4-abfc-76af37c968d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746199558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2746199558
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2811803452
Short name T72
Test name
Test status
Simulation time 3532691847 ps
CPU time 28.85 seconds
Started Jun 21 05:17:33 PM PDT 24
Finished Jun 21 05:18:03 PM PDT 24
Peak memory 256628 kb
Host smart-a1fab02b-1431-49c2-a8ea-90d479a0ba38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28118
03452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2811803452
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1687732345
Short name T626
Test name
Test status
Simulation time 1957313886 ps
CPU time 37.49 seconds
Started Jun 21 05:17:36 PM PDT 24
Finished Jun 21 05:18:14 PM PDT 24
Peak memory 255404 kb
Host smart-ca54b7b8-bc83-4c66-92e5-2f6d48c40823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16877
32345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1687732345
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2010108155
Short name T637
Test name
Test status
Simulation time 619132647 ps
CPU time 45.75 seconds
Started Jun 21 05:17:32 PM PDT 24
Finished Jun 21 05:18:19 PM PDT 24
Peak memory 248076 kb
Host smart-a631a2bc-95ca-4cde-b6c2-f3cfd1b49a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20101
08155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2010108155
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3226816828
Short name T396
Test name
Test status
Simulation time 533500566 ps
CPU time 30.61 seconds
Started Jun 21 05:17:33 PM PDT 24
Finished Jun 21 05:18:04 PM PDT 24
Peak memory 249044 kb
Host smart-77d87f7b-9282-4e41-a2f4-43d5669ec3fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32268
16828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3226816828
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1562532435
Short name T76
Test name
Test status
Simulation time 67844691494 ps
CPU time 3828.21 seconds
Started Jun 21 05:17:32 PM PDT 24
Finished Jun 21 06:21:21 PM PDT 24
Peak memory 298284 kb
Host smart-6488be1c-18df-4ce2-801f-c11d790f08d8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562532435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1562532435
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.3048478020
Short name T112
Test name
Test status
Simulation time 229441426102 ps
CPU time 6275.94 seconds
Started Jun 21 05:17:36 PM PDT 24
Finished Jun 21 07:02:13 PM PDT 24
Peak memory 371772 kb
Host smart-64763308-a765-421f-8b85-bf7d490fa217
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048478020 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.3048478020
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1573466708
Short name T667
Test name
Test status
Simulation time 53729071960 ps
CPU time 1605.03 seconds
Started Jun 21 05:17:34 PM PDT 24
Finished Jun 21 05:44:20 PM PDT 24
Peak memory 289684 kb
Host smart-7a339b53-c3f3-4629-a333-f2f872397695
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573466708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1573466708
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1818367249
Short name T356
Test name
Test status
Simulation time 82177258 ps
CPU time 9.91 seconds
Started Jun 21 05:17:34 PM PDT 24
Finished Jun 21 05:17:45 PM PDT 24
Peak memory 254792 kb
Host smart-c087360c-26fe-43fd-8547-60ea5c86aaf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18183
67249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1818367249
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.323203626
Short name T563
Test name
Test status
Simulation time 1923993298 ps
CPU time 33.31 seconds
Started Jun 21 05:17:34 PM PDT 24
Finished Jun 21 05:18:08 PM PDT 24
Peak memory 249000 kb
Host smart-8f0cbac4-f18f-4c15-b4e6-5d45d7122965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32320
3626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.323203626
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2318230119
Short name T566
Test name
Test status
Simulation time 21995811369 ps
CPU time 987.93 seconds
Started Jun 21 05:17:34 PM PDT 24
Finished Jun 21 05:34:03 PM PDT 24
Peak memory 288908 kb
Host smart-ed708967-fd27-416f-9ec1-eea061a529e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318230119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2318230119
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2004106969
Short name T94
Test name
Test status
Simulation time 27123305272 ps
CPU time 1414.2 seconds
Started Jun 21 05:17:41 PM PDT 24
Finished Jun 21 05:41:17 PM PDT 24
Peak memory 285684 kb
Host smart-931f0f8b-abeb-4e70-a8a9-9b066d1fc247
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004106969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2004106969
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3567342666
Short name T660
Test name
Test status
Simulation time 211856410 ps
CPU time 21.45 seconds
Started Jun 21 05:17:33 PM PDT 24
Finished Jun 21 05:17:55 PM PDT 24
Peak memory 249044 kb
Host smart-db70128f-96aa-4bca-88e7-b3a590d32323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35673
42666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3567342666
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.932077345
Short name T568
Test name
Test status
Simulation time 899971607 ps
CPU time 51.63 seconds
Started Jun 21 05:17:36 PM PDT 24
Finished Jun 21 05:18:28 PM PDT 24
Peak memory 249128 kb
Host smart-1beeea60-7fa6-450f-b463-3b4991dc5220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93207
7345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.932077345
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.209319235
Short name T420
Test name
Test status
Simulation time 740437537 ps
CPU time 48.04 seconds
Started Jun 21 05:17:34 PM PDT 24
Finished Jun 21 05:18:23 PM PDT 24
Peak memory 249268 kb
Host smart-05a8faea-87db-4347-89d1-ecf364e49d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20931
9235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.209319235
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1569537156
Short name T401
Test name
Test status
Simulation time 2547398015 ps
CPU time 33.66 seconds
Started Jun 21 05:17:38 PM PDT 24
Finished Jun 21 05:18:13 PM PDT 24
Peak memory 249032 kb
Host smart-f4a43b42-f3a5-4555-9fb3-af306f65ec0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15695
37156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1569537156
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1251039415
Short name T262
Test name
Test status
Simulation time 55759245436 ps
CPU time 1624.9 seconds
Started Jun 21 05:17:41 PM PDT 24
Finished Jun 21 05:44:46 PM PDT 24
Peak memory 273688 kb
Host smart-22505786-3f96-4326-bbf9-5dff6cad5ca8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251039415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1251039415
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.1607700189
Short name T69
Test name
Test status
Simulation time 38202771347 ps
CPU time 4276.22 seconds
Started Jun 21 05:17:42 PM PDT 24
Finished Jun 21 06:28:59 PM PDT 24
Peak memory 338428 kb
Host smart-0cd91a3f-18e6-4ebe-9e2b-6e40772043db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607700189 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.1607700189
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3058607894
Short name T689
Test name
Test status
Simulation time 67820289793 ps
CPU time 2251.59 seconds
Started Jun 21 05:17:41 PM PDT 24
Finished Jun 21 05:55:13 PM PDT 24
Peak memory 272920 kb
Host smart-6d86b6e9-8dd7-48b9-8103-092d73b0b9be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058607894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3058607894
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.4039622914
Short name T509
Test name
Test status
Simulation time 2014451980 ps
CPU time 119.26 seconds
Started Jun 21 05:17:42 PM PDT 24
Finished Jun 21 05:19:42 PM PDT 24
Peak memory 257176 kb
Host smart-e9f17936-417f-4f8d-8b45-88990e33a338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40396
22914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.4039622914
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3631277990
Short name T498
Test name
Test status
Simulation time 265031627 ps
CPU time 9.29 seconds
Started Jun 21 05:17:40 PM PDT 24
Finished Jun 21 05:17:49 PM PDT 24
Peak memory 253444 kb
Host smart-dc0dd04b-290b-4a30-8f42-985119c1e860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36312
77990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3631277990
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2335970107
Short name T312
Test name
Test status
Simulation time 63119921884 ps
CPU time 1505.3 seconds
Started Jun 21 05:17:41 PM PDT 24
Finished Jun 21 05:42:47 PM PDT 24
Peak memory 266428 kb
Host smart-920ba635-ae96-4a44-be3d-aacc097e5f13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335970107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2335970107
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.89551024
Short name T613
Test name
Test status
Simulation time 189743548658 ps
CPU time 2929.7 seconds
Started Jun 21 05:17:40 PM PDT 24
Finished Jun 21 06:06:30 PM PDT 24
Peak memory 285228 kb
Host smart-0d69a7c4-fe66-4d78-a9d0-ac6d6693623a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89551024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.89551024
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.731900457
Short name T600
Test name
Test status
Simulation time 3722059688 ps
CPU time 149.08 seconds
Started Jun 21 05:17:42 PM PDT 24
Finished Jun 21 05:20:12 PM PDT 24
Peak memory 248504 kb
Host smart-4c591e66-5716-4944-b0ea-030bcdabaa58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731900457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.731900457
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1708649266
Short name T534
Test name
Test status
Simulation time 95556571 ps
CPU time 5.5 seconds
Started Jun 21 05:17:43 PM PDT 24
Finished Jun 21 05:17:49 PM PDT 24
Peak memory 252288 kb
Host smart-f31058fb-7982-4d59-8a3a-e98d940c1e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17086
49266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1708649266
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.413651692
Short name T114
Test name
Test status
Simulation time 852483376 ps
CPU time 15.56 seconds
Started Jun 21 05:17:44 PM PDT 24
Finished Jun 21 05:18:00 PM PDT 24
Peak memory 255936 kb
Host smart-e15fb1b6-7bfa-4686-9900-0097ac5a5a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41365
1692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.413651692
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2594394211
Short name T68
Test name
Test status
Simulation time 853403750 ps
CPU time 46.11 seconds
Started Jun 21 05:17:44 PM PDT 24
Finished Jun 21 05:18:31 PM PDT 24
Peak memory 255896 kb
Host smart-64da7e44-822c-40a0-b5af-a6f184a3e302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25943
94211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2594394211
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1780212772
Short name T409
Test name
Test status
Simulation time 273740876 ps
CPU time 30.42 seconds
Started Jun 21 05:17:40 PM PDT 24
Finished Jun 21 05:18:12 PM PDT 24
Peak memory 249020 kb
Host smart-39d2e617-8767-4f54-b9f7-4435f0414cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17802
12772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1780212772
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1955147102
Short name T490
Test name
Test status
Simulation time 1418784672 ps
CPU time 66.39 seconds
Started Jun 21 05:17:42 PM PDT 24
Finished Jun 21 05:18:49 PM PDT 24
Peak memory 249996 kb
Host smart-b7684cd4-e7ab-4970-bc39-31c5cf3b6f10
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955147102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1955147102
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3174487322
Short name T214
Test name
Test status
Simulation time 17572661 ps
CPU time 3.19 seconds
Started Jun 21 05:15:04 PM PDT 24
Finished Jun 21 05:15:09 PM PDT 24
Peak memory 249200 kb
Host smart-1eace05a-8fad-4f51-8349-4834b13566e6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3174487322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3174487322
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.897381305
Short name T105
Test name
Test status
Simulation time 264518037504 ps
CPU time 1614.47 seconds
Started Jun 21 05:15:02 PM PDT 24
Finished Jun 21 05:41:58 PM PDT 24
Peak memory 282400 kb
Host smart-b753f795-6d08-4d36-b04b-9e9628895679
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897381305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.897381305
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3233974780
Short name T250
Test name
Test status
Simulation time 592570880 ps
CPU time 9.74 seconds
Started Jun 21 05:15:01 PM PDT 24
Finished Jun 21 05:15:13 PM PDT 24
Peak memory 249132 kb
Host smart-2046c565-affa-422e-a9ce-3e96af8b47b5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3233974780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3233974780
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.813411066
Short name T188
Test name
Test status
Simulation time 507744499 ps
CPU time 44.07 seconds
Started Jun 21 05:14:57 PM PDT 24
Finished Jun 21 05:15:44 PM PDT 24
Peak memory 257224 kb
Host smart-6c823bdf-2bbf-45a4-859c-855865004755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81341
1066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.813411066
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2437554184
Short name T614
Test name
Test status
Simulation time 869388295 ps
CPU time 16.03 seconds
Started Jun 21 05:14:59 PM PDT 24
Finished Jun 21 05:15:18 PM PDT 24
Peak memory 256008 kb
Host smart-fa03c65c-34d0-42f6-9c3a-35bd658944d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24375
54184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2437554184
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1020901817
Short name T591
Test name
Test status
Simulation time 119129545982 ps
CPU time 1609.34 seconds
Started Jun 21 05:14:58 PM PDT 24
Finished Jun 21 05:41:50 PM PDT 24
Peak memory 272380 kb
Host smart-bbb72fda-7db3-41fd-b4d1-d33ca388c02f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020901817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1020901817
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1533795750
Short name T532
Test name
Test status
Simulation time 84791811414 ps
CPU time 1360.78 seconds
Started Jun 21 05:15:01 PM PDT 24
Finished Jun 21 05:37:44 PM PDT 24
Peak memory 273024 kb
Host smart-8ee8e96f-23fb-4289-80af-4bca4821675d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533795750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1533795750
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1320150421
Short name T465
Test name
Test status
Simulation time 9392188204 ps
CPU time 101.01 seconds
Started Jun 21 05:14:55 PM PDT 24
Finished Jun 21 05:16:40 PM PDT 24
Peak memory 248764 kb
Host smart-00ab2f80-126a-4c4e-9487-d38c2180ce5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320150421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1320150421
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.2087227924
Short name T694
Test name
Test status
Simulation time 1247885165 ps
CPU time 71.43 seconds
Started Jun 21 05:14:56 PM PDT 24
Finished Jun 21 05:16:11 PM PDT 24
Peak memory 256492 kb
Host smart-7afa028c-e43f-48dd-ae2e-8a51267653e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20872
27924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2087227924
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.973559880
Short name T65
Test name
Test status
Simulation time 398404737 ps
CPU time 34.4 seconds
Started Jun 21 05:14:50 PM PDT 24
Finished Jun 21 05:15:29 PM PDT 24
Peak memory 248096 kb
Host smart-efec49e9-f60d-4c98-b899-ece85a291b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97355
9880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.973559880
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.564639281
Short name T366
Test name
Test status
Simulation time 61212100 ps
CPU time 4.6 seconds
Started Jun 21 05:14:58 PM PDT 24
Finished Jun 21 05:15:05 PM PDT 24
Peak memory 239608 kb
Host smart-8426149b-c1b2-45e2-bb2e-915a414144bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56463
9281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.564639281
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2818099394
Short name T407
Test name
Test status
Simulation time 294101723 ps
CPU time 22.36 seconds
Started Jun 21 05:14:54 PM PDT 24
Finished Jun 21 05:15:21 PM PDT 24
Peak memory 249024 kb
Host smart-aa9c6dbb-54f1-4071-8010-6d43406d01a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28180
99394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2818099394
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3404267900
Short name T292
Test name
Test status
Simulation time 950108149 ps
CPU time 28.09 seconds
Started Jun 21 05:15:06 PM PDT 24
Finished Jun 21 05:15:36 PM PDT 24
Peak memory 256652 kb
Host smart-25a12650-1b43-45b0-9123-ba9971170786
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404267900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3404267900
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2279441196
Short name T212
Test name
Test status
Simulation time 76162455 ps
CPU time 3.49 seconds
Started Jun 21 05:15:06 PM PDT 24
Finished Jun 21 05:15:11 PM PDT 24
Peak memory 249200 kb
Host smart-ea2f47b5-3ca5-4b12-840b-9c6a4de0b084
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2279441196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2279441196
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.651285018
Short name T295
Test name
Test status
Simulation time 208798386880 ps
CPU time 3166.69 seconds
Started Jun 21 05:14:59 PM PDT 24
Finished Jun 21 06:07:49 PM PDT 24
Peak memory 290044 kb
Host smart-4baa20fc-97b4-4f13-b149-e80b6214f46c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651285018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.651285018
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3276346061
Short name T565
Test name
Test status
Simulation time 998211760 ps
CPU time 11.91 seconds
Started Jun 21 05:15:04 PM PDT 24
Finished Jun 21 05:15:17 PM PDT 24
Peak memory 249012 kb
Host smart-0ac59a2a-8c56-47e9-ba35-831427432464
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3276346061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3276346061
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3092459261
Short name T570
Test name
Test status
Simulation time 153539442 ps
CPU time 19.57 seconds
Started Jun 21 05:15:04 PM PDT 24
Finished Jun 21 05:15:25 PM PDT 24
Peak memory 256664 kb
Host smart-f55a28e2-a30a-4525-8e7e-98c182061077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30924
59261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3092459261
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2628592396
Short name T365
Test name
Test status
Simulation time 2625292765 ps
CPU time 38.39 seconds
Started Jun 21 05:15:06 PM PDT 24
Finished Jun 21 05:15:46 PM PDT 24
Peak memory 249108 kb
Host smart-0f5be359-a4d7-4dd7-988e-048c2ed3dcb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26285
92396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2628592396
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.4207064563
Short name T192
Test name
Test status
Simulation time 18538508812 ps
CPU time 1362.87 seconds
Started Jun 21 05:15:01 PM PDT 24
Finished Jun 21 05:37:46 PM PDT 24
Peak memory 281416 kb
Host smart-ee0afd92-7f97-41fb-b9ba-bd24aae24469
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207064563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.4207064563
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.73438146
Short name T416
Test name
Test status
Simulation time 12791303267 ps
CPU time 1234.75 seconds
Started Jun 21 05:14:57 PM PDT 24
Finished Jun 21 05:35:35 PM PDT 24
Peak memory 285480 kb
Host smart-a71d0a88-e17b-4d81-8338-fdcfd6734055
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73438146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.73438146
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1281746425
Short name T616
Test name
Test status
Simulation time 16137560732 ps
CPU time 350.98 seconds
Started Jun 21 05:15:06 PM PDT 24
Finished Jun 21 05:20:59 PM PDT 24
Peak memory 248576 kb
Host smart-4db7e4d9-900c-4d9e-af2e-5f0ae67d5242
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281746425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1281746425
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.979745317
Short name T536
Test name
Test status
Simulation time 1008769357 ps
CPU time 28.59 seconds
Started Jun 21 05:15:04 PM PDT 24
Finished Jun 21 05:15:34 PM PDT 24
Peak memory 248968 kb
Host smart-e646b1b6-f191-419a-8935-abd22e21f65b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97974
5317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.979745317
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1390675469
Short name T117
Test name
Test status
Simulation time 342678648 ps
CPU time 26.33 seconds
Started Jun 21 05:15:06 PM PDT 24
Finished Jun 21 05:15:34 PM PDT 24
Peak memory 255744 kb
Host smart-dfb1422f-7efe-4451-8b09-c60d9cc2ff50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13906
75469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1390675469
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1386675510
Short name T304
Test name
Test status
Simulation time 267227688 ps
CPU time 30.97 seconds
Started Jun 21 05:14:58 PM PDT 24
Finished Jun 21 05:15:32 PM PDT 24
Peak memory 256432 kb
Host smart-ba06ed6c-1126-4097-8bf1-3fac01940f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13866
75510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1386675510
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3325330732
Short name T225
Test name
Test status
Simulation time 889640853 ps
CPU time 50.06 seconds
Started Jun 21 05:14:58 PM PDT 24
Finished Jun 21 05:15:51 PM PDT 24
Peak memory 248984 kb
Host smart-1654acda-1316-4448-9399-0a5221ea99ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33253
30732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3325330732
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1858038671
Short name T205
Test name
Test status
Simulation time 17584870 ps
CPU time 2.78 seconds
Started Jun 21 05:14:58 PM PDT 24
Finished Jun 21 05:15:03 PM PDT 24
Peak memory 249236 kb
Host smart-b1d1322e-f234-43c4-8479-acdba752971c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1858038671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1858038671
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2343048490
Short name T90
Test name
Test status
Simulation time 50946179473 ps
CPU time 1143.08 seconds
Started Jun 21 05:15:01 PM PDT 24
Finished Jun 21 05:34:06 PM PDT 24
Peak memory 272272 kb
Host smart-0de2ac84-5c6c-46e9-b4d7-3ae9ef338f4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343048490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2343048490
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1066114375
Short name T252
Test name
Test status
Simulation time 468025697 ps
CPU time 7.35 seconds
Started Jun 21 05:15:02 PM PDT 24
Finished Jun 21 05:15:11 PM PDT 24
Peak memory 248908 kb
Host smart-ea2ed197-7f79-4134-acf5-221cffdc872f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1066114375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1066114375
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.7088747
Short name T673
Test name
Test status
Simulation time 1574627898 ps
CPU time 148.76 seconds
Started Jun 21 05:15:02 PM PDT 24
Finished Jun 21 05:17:33 PM PDT 24
Peak memory 257220 kb
Host smart-3b210efc-b98a-417d-ba64-60ab85a02575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70887
47 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.7088747
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.291659592
Short name T437
Test name
Test status
Simulation time 371947278 ps
CPU time 4.85 seconds
Started Jun 21 05:14:59 PM PDT 24
Finished Jun 21 05:15:06 PM PDT 24
Peak memory 251196 kb
Host smart-e4ecfca5-d6ac-4d47-b64b-6dd0df07e733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29165
9592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.291659592
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3904733698
Short name T106
Test name
Test status
Simulation time 161875117617 ps
CPU time 2520.15 seconds
Started Jun 21 05:15:04 PM PDT 24
Finished Jun 21 05:57:06 PM PDT 24
Peak memory 273664 kb
Host smart-9d254062-f720-4511-8ed8-2bbd04d28129
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904733698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3904733698
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3606031841
Short name T435
Test name
Test status
Simulation time 112297493523 ps
CPU time 1646.46 seconds
Started Jun 21 05:14:58 PM PDT 24
Finished Jun 21 05:42:28 PM PDT 24
Peak memory 273272 kb
Host smart-f7d24b95-49d9-496d-ba25-71cc1ea2ae4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606031841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3606031841
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2793119731
Short name T560
Test name
Test status
Simulation time 2940372910 ps
CPU time 128.49 seconds
Started Jun 21 05:14:58 PM PDT 24
Finished Jun 21 05:17:09 PM PDT 24
Peak memory 254156 kb
Host smart-a2223cb7-4459-426b-94c8-3ef2ea86aa7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793119731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2793119731
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1273884002
Short name T537
Test name
Test status
Simulation time 131697904 ps
CPU time 15.87 seconds
Started Jun 21 05:14:58 PM PDT 24
Finished Jun 21 05:15:17 PM PDT 24
Peak memory 249040 kb
Host smart-0f1deb47-5bf7-4542-9dc0-e679be336c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12738
84002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1273884002
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1089469743
Short name T24
Test name
Test status
Simulation time 917446736 ps
CPU time 6.48 seconds
Started Jun 21 05:15:01 PM PDT 24
Finished Jun 21 05:15:09 PM PDT 24
Peak memory 249112 kb
Host smart-228f49b7-2c5c-4e38-bda6-c90c72b9bf43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10894
69743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1089469743
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3936655024
Short name T28
Test name
Test status
Simulation time 484772255 ps
CPU time 16.99 seconds
Started Jun 21 05:14:59 PM PDT 24
Finished Jun 21 05:15:18 PM PDT 24
Peak memory 254676 kb
Host smart-99ae8fd0-d067-4e72-9be1-7becf9d1ca5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39366
55024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3936655024
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.4096061682
Short name T683
Test name
Test status
Simulation time 371468682 ps
CPU time 8.75 seconds
Started Jun 21 05:15:01 PM PDT 24
Finished Jun 21 05:15:12 PM PDT 24
Peak memory 253696 kb
Host smart-f53404fb-cfed-4205-96dd-2149724e9ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40960
61682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.4096061682
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3733817487
Short name T546
Test name
Test status
Simulation time 9281320072 ps
CPU time 907.93 seconds
Started Jun 21 05:14:58 PM PDT 24
Finished Jun 21 05:30:09 PM PDT 24
Peak memory 273668 kb
Host smart-cdb58a87-8274-47e7-a07e-89fb48d7c9dd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733817487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3733817487
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1932283703
Short name T215
Test name
Test status
Simulation time 18278984 ps
CPU time 2.72 seconds
Started Jun 21 05:15:02 PM PDT 24
Finished Jun 21 05:15:07 PM PDT 24
Peak memory 249132 kb
Host smart-48c5781b-8548-4bbe-bf4e-4eb09ee4cfc2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1932283703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1932283703
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1933722657
Short name T451
Test name
Test status
Simulation time 38683471644 ps
CPU time 806.47 seconds
Started Jun 21 05:15:03 PM PDT 24
Finished Jun 21 05:28:31 PM PDT 24
Peak memory 268580 kb
Host smart-d6548ab0-79eb-4de7-a9fc-5bc474c5b97b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933722657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1933722657
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.830837712
Short name T606
Test name
Test status
Simulation time 224249419 ps
CPU time 11.58 seconds
Started Jun 21 05:15:01 PM PDT 24
Finished Jun 21 05:15:15 PM PDT 24
Peak memory 249056 kb
Host smart-755744a3-ba4b-4471-a015-39dbb5ceaaf2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=830837712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.830837712
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1205149129
Short name T1
Test name
Test status
Simulation time 1905954385 ps
CPU time 109.38 seconds
Started Jun 21 05:15:01 PM PDT 24
Finished Jun 21 05:16:53 PM PDT 24
Peak memory 257216 kb
Host smart-0c9a4ada-e0b3-4387-a081-2cabcb99baab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12051
49129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1205149129
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.4062833310
Short name T422
Test name
Test status
Simulation time 3149770370 ps
CPU time 43.95 seconds
Started Jun 21 05:15:01 PM PDT 24
Finished Jun 21 05:15:47 PM PDT 24
Peak memory 248948 kb
Host smart-c12c7e12-89e9-4595-af88-b58fc26a9d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40628
33310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.4062833310
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3436796302
Short name T335
Test name
Test status
Simulation time 62032943841 ps
CPU time 766.71 seconds
Started Jun 21 05:14:57 PM PDT 24
Finished Jun 21 05:27:47 PM PDT 24
Peak memory 267644 kb
Host smart-20888230-4fb1-4c32-b098-b924fae3b3e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436796302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3436796302
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3093128162
Short name T577
Test name
Test status
Simulation time 162423358974 ps
CPU time 2207.25 seconds
Started Jun 21 05:14:58 PM PDT 24
Finished Jun 21 05:51:48 PM PDT 24
Peak memory 273592 kb
Host smart-a891cf5c-02bc-40b7-8ef5-652a6ac5b8a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093128162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3093128162
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3029238183
Short name T233
Test name
Test status
Simulation time 19036039673 ps
CPU time 204.92 seconds
Started Jun 21 05:15:02 PM PDT 24
Finished Jun 21 05:18:29 PM PDT 24
Peak memory 248292 kb
Host smart-f0226c41-36aa-4382-b014-0bd475b659e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029238183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3029238183
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2308059965
Short name T574
Test name
Test status
Simulation time 49411899 ps
CPU time 6.15 seconds
Started Jun 21 05:14:59 PM PDT 24
Finished Jun 21 05:15:08 PM PDT 24
Peak memory 253668 kb
Host smart-c89dd268-bca1-414b-abc4-2ab26eab8a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23080
59965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2308059965
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1348927058
Short name T653
Test name
Test status
Simulation time 3877044081 ps
CPU time 55.99 seconds
Started Jun 21 05:15:06 PM PDT 24
Finished Jun 21 05:16:04 PM PDT 24
Peak memory 249260 kb
Host smart-1e09e558-1c28-447d-8dda-e95f15a20232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13489
27058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1348927058
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.382585872
Short name T485
Test name
Test status
Simulation time 129604435 ps
CPU time 14.58 seconds
Started Jun 21 05:15:01 PM PDT 24
Finished Jun 21 05:15:18 PM PDT 24
Peak memory 249040 kb
Host smart-217c036e-2461-4e4c-8b2d-a0d7e54e6e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38258
5872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.382585872
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1279976801
Short name T474
Test name
Test status
Simulation time 1230317966 ps
CPU time 44.95 seconds
Started Jun 21 05:15:01 PM PDT 24
Finished Jun 21 05:15:48 PM PDT 24
Peak memory 257120 kb
Host smart-21c99713-cf68-43bc-a117-2daf76f0f5f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12799
76801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1279976801
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1665052140
Short name T709
Test name
Test status
Simulation time 895863726 ps
CPU time 52.92 seconds
Started Jun 21 05:15:06 PM PDT 24
Finished Jun 21 05:16:01 PM PDT 24
Peak memory 255760 kb
Host smart-ef376248-c788-4c57-b62e-49a9a854f2a3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665052140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1665052140
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2758702009
Short name T219
Test name
Test status
Simulation time 32514420 ps
CPU time 3.35 seconds
Started Jun 21 05:15:05 PM PDT 24
Finished Jun 21 05:15:09 PM PDT 24
Peak memory 249064 kb
Host smart-6efc412d-b435-4d3d-b4d2-a6c4cee34923
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2758702009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2758702009
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.4255360561
Short name T518
Test name
Test status
Simulation time 20316949883 ps
CPU time 1502.7 seconds
Started Jun 21 05:15:07 PM PDT 24
Finished Jun 21 05:40:12 PM PDT 24
Peak memory 289308 kb
Host smart-747eb0e5-f6a3-4c95-bd72-d23e82da6eb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255360561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.4255360561
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1794948608
Short name T553
Test name
Test status
Simulation time 219767306 ps
CPU time 11.42 seconds
Started Jun 21 05:15:07 PM PDT 24
Finished Jun 21 05:15:20 PM PDT 24
Peak memory 240868 kb
Host smart-9e43f26d-4553-4179-a6d5-cb9e0f276f1f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1794948608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1794948608
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.139389828
Short name T463
Test name
Test status
Simulation time 6398924046 ps
CPU time 101.46 seconds
Started Jun 21 05:15:06 PM PDT 24
Finished Jun 21 05:16:49 PM PDT 24
Peak memory 256464 kb
Host smart-989eeeea-24e3-4e25-bbbb-d777527d57f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13938
9828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.139389828
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.637396912
Short name T265
Test name
Test status
Simulation time 1498602016 ps
CPU time 21.75 seconds
Started Jun 21 05:15:08 PM PDT 24
Finished Jun 21 05:15:31 PM PDT 24
Peak memory 249096 kb
Host smart-0b9405e4-0e8c-44f5-8198-00b37a34ee95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63739
6912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.637396912
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1209213192
Short name T497
Test name
Test status
Simulation time 11403222826 ps
CPU time 1166.14 seconds
Started Jun 21 05:15:05 PM PDT 24
Finished Jun 21 05:34:32 PM PDT 24
Peak memory 284472 kb
Host smart-cdb0b08f-a223-48cd-83bc-39c2c7fbfb41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209213192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1209213192
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3197293907
Short name T525
Test name
Test status
Simulation time 37050432900 ps
CPU time 706.73 seconds
Started Jun 21 05:15:05 PM PDT 24
Finished Jun 21 05:26:54 PM PDT 24
Peak memory 266828 kb
Host smart-be5dd52a-1fa6-4bd3-bd19-6d358ddbebc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197293907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3197293907
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3795674043
Short name T516
Test name
Test status
Simulation time 22814837208 ps
CPU time 259.97 seconds
Started Jun 21 05:15:07 PM PDT 24
Finished Jun 21 05:19:28 PM PDT 24
Peak memory 255920 kb
Host smart-c257c554-8b6a-4e67-aaa4-3de408fa7d84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795674043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3795674043
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3493708576
Short name T648
Test name
Test status
Simulation time 201370580 ps
CPU time 19.24 seconds
Started Jun 21 05:15:07 PM PDT 24
Finished Jun 21 05:15:28 PM PDT 24
Peak memory 249044 kb
Host smart-8e933304-27e2-474d-97cd-37c465c51712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34937
08576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3493708576
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.78051542
Short name T228
Test name
Test status
Simulation time 2895644548 ps
CPU time 12.76 seconds
Started Jun 21 05:15:07 PM PDT 24
Finished Jun 21 05:15:21 PM PDT 24
Peak memory 252808 kb
Host smart-313b7711-d6e0-4cfb-b965-bef251ece887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78051
542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.78051542
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.4027293843
Short name T610
Test name
Test status
Simulation time 4340618116 ps
CPU time 27.24 seconds
Started Jun 21 05:15:07 PM PDT 24
Finished Jun 21 05:15:36 PM PDT 24
Peak memory 249224 kb
Host smart-01f09278-9c04-4dc3-95a4-3c8a5036d3b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40272
93843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.4027293843
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1039474254
Short name T688
Test name
Test status
Simulation time 131726251 ps
CPU time 15.51 seconds
Started Jun 21 05:14:56 PM PDT 24
Finished Jun 21 05:15:15 PM PDT 24
Peak memory 249028 kb
Host smart-412f8b58-f6ec-4fe0-9ad9-211f35f6b788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10394
74254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1039474254
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.4195881063
Short name T681
Test name
Test status
Simulation time 16093044514 ps
CPU time 1547.17 seconds
Started Jun 21 05:15:05 PM PDT 24
Finished Jun 21 05:40:54 PM PDT 24
Peak memory 289812 kb
Host smart-7ca94341-31d0-412f-95a3-dcf9c2542032
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195881063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.4195881063
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.2788816073
Short name T195
Test name
Test status
Simulation time 89752127765 ps
CPU time 2742.73 seconds
Started Jun 21 05:15:09 PM PDT 24
Finished Jun 21 06:00:53 PM PDT 24
Peak memory 306456 kb
Host smart-b172518e-ed8b-4c5d-ade6-22c145eb6c0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788816073 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.2788816073
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%