Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	94591	1			T9	225		T10	10		T74	2189
class_i[0x1]	36252	1			T1	272		T6	1		T67	188
class_i[0x2]	33260	1			T10	370		T41	18		T140	135
class_i[0x3]	81902	1			T10	148		T38	4285		T41	8

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	59584	1			T1	1		T6	1		T9	25
alert[0x1]	63492	1			T9	14		T10	5		T38	983
alert[0x2]	59753	1			T9	27		T10	514		T38	1031
alert[0x3]	63176	1			T1	271		T9	159		T10	1

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

245734

1

T1

272

T6

1

T9

225

esc_ping_fail

271

1

T41

8

T143

9

T118

2

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	59509	1			T1	1		T6	1		T9	25
esc_integrity_fail	alert[0x1]	63420	1			T9	14		T10	5		T38	983
esc_integrity_fail	alert[0x2]	59693	1			T9	27		T10	514		T38	1031
esc_integrity_fail	alert[0x3]	63112	1			T1	271		T9	159		T10	1
esc_ping_fail	alert[0x0]	75	1			T41	3		T143	2		T296	2
esc_ping_fail	alert[0x1]	72	1			T41	1		T143	2		T118	1
esc_ping_fail	alert[0x2]	60	1			T41	3		T143	2		T296	1
esc_ping_fail	alert[0x3]	64	1			T41	1		T143	3		T118	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	94555	1			T9	225		T10	10		T74	2189
esc_integrity_fail	class_i[0x1]	36176	1			T1	272		T6	1		T67	188
esc_integrity_fail	class_i[0x2]	33198	1			T10	370		T41	18		T140	135
esc_integrity_fail	class_i[0x3]	81805	1			T10	148		T38	4285		T43	10
esc_ping_fail	class_i[0x0]	36	1			T296	1		T315	7		T321	2
esc_ping_fail	class_i[0x1]	76	1			T296	6		T297	6		T299	3
esc_ping_fail	class_i[0x2]	62	1			T143	7		T118	2		T296	1
esc_ping_fail	class_i[0x3]	97	1			T41	8		T143	2		T316	3