Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	711619072	0	0	632
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	711619072	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	711619072	711457757	0	0
tb.dut.CheckAccuCntDw	0	0	632	632	0	0
tb.dut.CheckEscCntDw	0	0	632	632	0	0
tb.dut.CheckNAlerts	0	0	632	632	0	0
tb.dut.CheckNClasses	0	0	632	632	0	0
tb.dut.CheckNEscSev	0	0	632	632	0	0
tb.dut.CrashdumpKnownO_A	0	0	711619072	711457757	0	0
tb.dut.EdnKnownO_A	0	0	711619072	711457757	0	0
tb.dut.EscPKnownO_A	0	0	711619072	711457757	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	711619072	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	711619072	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	711619072	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	711619072	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	711619072	70	0	0
tb.dut.IrqAKnownO_A	0	0	711619072	711457757	0	0
tb.dut.IrqBKnownO_A	0	0	711619072	711457757	0	0
tb.dut.IrqCKnownO_A	0	0	711619072	711457757	0	0
tb.dut.IrqDKnownO_A	0	0	711619072	711457757	0	0
tb.dut.TlAReadyKnownO_A	0	0	711619072	711457757	0	0
tb.dut.TlDValidKnownO_A	0	0	711619072	711457757	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	737200059	3262725	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	737200059	19620	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	737200059	17105	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	737200059	16936	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	737200059	17862	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	737200059	18050	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	737200059	18074	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	737200059	16676	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	737200059	17258	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	737200059	15619	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	737200059	16859	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	737200059	19307	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	737200059	17688	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	737200059	17037	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	737200059	19143	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	737200059	19388	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	737200059	15542	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	737200059	16933	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	737200059	18114	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	737200059	18206	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	737200059	17576	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	737200059	17050	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	737200059	17922	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	737200059	16650	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	737200059	15877	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	737200059	19027	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	737200059	16889	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	737200059	16817	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	737200059	18325	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	737200059	16835	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	737200059	16883	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	737200059	17051	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	737200059	16915	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	737200059	15327	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	737200059	17194	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	737200059	17790	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	737200059	17770	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	737200059	16888	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	737200059	18095	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	737200059	18954	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	737200059	16874	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	737200059	18241	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	737200059	18025	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	737200059	19202	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	737200059	18848	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	737200059	15783	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	737200059	18523	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	737200059	16806	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	737200059	17321	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	737200059	16726	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	737200059	17896	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	737200059	15727	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	737200059	17728	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	737200059	16577	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	737200059	15507	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	737200059	15554	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	737200059	18048	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	737200059	16783	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	737200059	16904	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	737200059	15892	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	737200059	17594	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	737200059	19160	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	737200059	17447	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	737200059	16830	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	737200059	17739	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	737200059	17229	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	737200059	17643	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	737200059	17795	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	737200059	16937	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	737200059	17139	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	737200059	33737	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	737200059	15775	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	737200059	16534	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	737200059	17935	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	737200059	16861	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	737200059	17054	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	737200059	18097	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	737200059	16979	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	737200059	16925	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	711619072	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	711619072	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	711619072	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	711619072	4152	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	711619072	234006	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	711619072	342959776	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	711619072	244	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	711619072	873	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	711619072	45	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	711619072	418	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	711479820	276515311	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	711619072	951	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	711619072	926	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	711619072	908	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	711619072	894	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	711619072	791	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	711619072	102261	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	711619072	694	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	711619072	51	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	711619072	1229	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	711619072	1019	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	711478397	711407211	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	632	632	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	711619072	711457757	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	711619072	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	711619072	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	711619072	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	711619072	4368	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	711619072	184999	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	711619072	418742072	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	711619072	218	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	711619072	496	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	711619072	23	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	711619072	203	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	711479820	323516965	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	711619072	560	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	711619072	541	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	711619072	530	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	711619072	525	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	711619072	521	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	711619072	59702	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	711619072	443	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	711619072	55	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	711619072	1269	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	711619072	1059	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	711478397	711407211	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	632	632	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	711619072	711457757	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	711619072	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	711619072	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	711619072	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	711619072	2004	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	711619072	177072	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	711619072	401506309	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	711619072	254	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	711619072	467	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	711619072	17	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	711619072	182	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	711479820	298223601	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	711619072	529	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	711619072	522	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	711619072	512	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	711619072	506	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	711619072	1100	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	711619072	142404	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	711619072	1030	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	711619072	50	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	711619072	1303	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	711619072	1093	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	711478397	711407211	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	632	632	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	711619072	711457757	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	711619072	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	711619072	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	711619072	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	711619072	2350	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	711619072	185680	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	711619072	414603662	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	711619072	236	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	711619072	511	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	711619072	17	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	711619072	238	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	711479820	340002903	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	711619072	581	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	711619072	574	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	711619072	567	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	711619072	556	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	711619072	804	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	711619072	97214	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	711619072	718	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	711619072	66	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	711619072	1223	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	711619072	1013	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	711478397	711407211	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	632	632	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	711619072	711457757	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	737200059	135624498	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	737200059	736526331	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	737200059	736526331	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	737200059	190425072	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	737200059	736526331	0	0
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