Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	3	41	93.18

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	3	41	93.18	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	192	1			T40	2		T41	1		T140	1
index[0x1]	144	1			T2	1		T4	1		T9	1
index[0x2]	142	1			T1	1		T2	1		T6	1
index[0x3]	166	1			T6	3		T10	3		T36	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	194	1			T9	1		T10	3		T37	1
lens_less_than_1000[1]	114	1			T1	1		T2	1		T4	1
lens_less_than_1000[2]	112	1			T6	1		T40	2		T16	1
lens_less_than_1000[3]	67	1			T10	1		T36	1		T41	1
lens_less_than_1000[4]	45	1			T6	1		T48	1		T242	1
lens_less_than_1000[5]	26	1			T20	1		T268	1		T269	1
lens_less_than_1000[6]	35	1			T10	1		T75	1		T49	1
lens_less_than_1000[7]	17	1			T7	1		T249	1		T270	1
lens_less_than_1000[8]	12	1			T10	1		T53	1		T94	1
lens_less_than_1000[9]	12	1			T49	2		T53	8		T252	1
len_2	10	1			T2	1		T27	1		T271	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	3	41	93.18	3

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[len_2]	0	1	1
[index[0x1]]	[lens_less_than_1000[7]]	0	1	1
[index[0x1]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	59	1			T140	1		T19	1		T23	2
index[0x0]	lens_less_than_1000[1]	35	1			T272	1		T20	1		T242	1
index[0x0]	lens_less_than_1000[2]	33	1			T40	2		T27	1		T98	1
index[0x0]	lens_less_than_1000[3]	26	1			T41	1		T74	1		T48	1
index[0x0]	lens_less_than_1000[4]	12	1			T242	1		T108	1		T84	1
index[0x0]	lens_less_than_1000[5]	7	1			T129	1		T273	1		T131	1
index[0x0]	lens_less_than_1000[6]	8	1			T56	1		T107	1		T100	1
index[0x0]	lens_less_than_1000[7]	6	1			T249	1		T274	1		T113	1
index[0x0]	lens_less_than_1000[8]	3	1			T53	1		T275	1		T276	1
index[0x0]	lens_less_than_1000[9]	3	1			T49	2		T252	1		-	-
index[0x1]	lens_less_than_1000[0]	46	1			T9	1		T10	1		T72	1
index[0x1]	lens_less_than_1000[1]	27	1			T4	1		T10	3		T108	1
index[0x1]	lens_less_than_1000[2]	24	1			T24	2		T97	1		T29	1
index[0x1]	lens_less_than_1000[3]	10	1			T49	1		T87	1		T270	1
index[0x1]	lens_less_than_1000[4]	9	1			T270	1		T100	1		T273	1
index[0x1]	lens_less_than_1000[5]	8	1			T269	1		T131	1		T277	1
index[0x1]	lens_less_than_1000[6]	10	1			T49	1		T93	1		T88	2
index[0x1]	lens_less_than_1000[8]	6	1			T10	1		T275	1		T278	1
index[0x1]	len_2	4	1			T2	1		T271	1		T95	1
index[0x2]	lens_less_than_1000[0]	39	1			T14	1		T15	1		T72	1
index[0x2]	lens_less_than_1000[1]	27	1			T1	1		T2	1		T49	1
index[0x2]	lens_less_than_1000[2]	21	1			T16	1		T279	1		T239	1
index[0x2]	lens_less_than_1000[3]	13	1			T10	1		T53	1		T32	1
index[0x2]	lens_less_than_1000[4]	13	1			T6	1		T84	1		T95	1
index[0x2]	lens_less_than_1000[5]	3	1			T280	1		T131	1		T281	1
index[0x2]	lens_less_than_1000[6]	9	1			T75	1		T87	2		T282	1
index[0x2]	lens_less_than_1000[7]	5	1			T7	1		T283	1		T284	1
index[0x2]	lens_less_than_1000[8]	1	1			T283	1		-	-		-	-
index[0x2]	lens_less_than_1000[9]	8	1			T53	8		-	-		-	-
index[0x2]	len_2	3	1			T27	1		T132	1		T285	1
index[0x3]	lens_less_than_1000[0]	50	1			T10	2		T37	1		T286	1
index[0x3]	lens_less_than_1000[1]	25	1			T6	2		T74	1		T19	1
index[0x3]	lens_less_than_1000[2]	34	1			T6	1		T24	2		T84	1
index[0x3]	lens_less_than_1000[3]	18	1			T36	1		T53	2		T287	1
index[0x3]	lens_less_than_1000[4]	11	1			T48	1		T55	1		T263	1
index[0x3]	lens_less_than_1000[5]	8	1			T20	1		T268	1		T288	1
index[0x3]	lens_less_than_1000[6]	8	1			T10	1		T289	1		T290	1
index[0x3]	lens_less_than_1000[7]	6	1			T270	1		T273	1		T291	1
index[0x3]	lens_less_than_1000[8]	2	1			T94	1		T264	1		-	-
index[0x3]	lens_less_than_1000[9]	1	1			T292	1		-	-		-	-
index[0x3]	len_2	3	1			T95	1		T293	1		T294	1