Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	51	1			T74	1		T78	1		T79	1
class_index[0x1]	55	1			T10	4		T14	1		T24	2
class_index[0x2]	50	1			T6	1		T10	1		T40	2
class_index[0x3]	66	1			T8	1		T75	2		T16	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	93	1			T6	1		T8	1		T10	4
intr_timeout_cnt[1]	50	1			T14	1		T75	1		T64	1
intr_timeout_cnt[2]	21	1			T84	1		T86	1		T135	2
intr_timeout_cnt[3]	14	1			T80	1		T239	1		T87	1
intr_timeout_cnt[4]	6	1			T47	1		T83	1		T252	1
intr_timeout_cnt[5]	9	1			T74	1		T50	1		T120	1
intr_timeout_cnt[6]	8	1			T10	1		T253	1		T252	1
intr_timeout_cnt[7]	7	1			T84	1		T249	1		T129	1
intr_timeout_cnt[8]	6	1			T74	1		T47	1		T84	1
intr_timeout_cnt[9]	8	1			T27	1		T249	1		T117	4

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[4]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[7] , intr_timeout_cnt[8]]	--	--	2

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	16	1			T78	1		T79	1		T85	3
class_index[0x0]	intr_timeout_cnt[1]	15	1			T49	1		T50	1		T27	1
class_index[0x0]	intr_timeout_cnt[2]	5	1			T84	1		T122	1		T254	1
class_index[0x0]	intr_timeout_cnt[3]	3	1			T80	1		T252	1		T131	1
class_index[0x0]	intr_timeout_cnt[4]	1	1			T83	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[5]	1	1			T18	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	1	1			T253	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	4	1			T84	1		T249	1		T255	2
class_index[0x0]	intr_timeout_cnt[8]	2	1			T74	1		T256	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	3	1			T117	2		T251	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	26	1			T10	3		T24	2		T20	1
class_index[0x1]	intr_timeout_cnt[1]	10	1			T14	1		T49	1		T87	2
class_index[0x1]	intr_timeout_cnt[2]	4	1			T86	1		T113	1		T257	2
class_index[0x1]	intr_timeout_cnt[3]	5	1			T131	4		T18	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	3	1			T258	1		T259	1		T256	1
class_index[0x1]	intr_timeout_cnt[5]	2	1			T50	1		T260	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	1	1			T10	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T261	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T251	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T27	1		T262	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	26	1			T6	1		T10	1		T40	2
class_index[0x2]	intr_timeout_cnt[1]	7	1			T24	1		T248	1		T129	1
class_index[0x2]	intr_timeout_cnt[2]	2	1			T93	1		T129	1		-	-
class_index[0x2]	intr_timeout_cnt[3]	5	1			T239	1		T87	1		T263	1
class_index[0x2]	intr_timeout_cnt[4]	2	1			T47	1		T252	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	2	1			T74	1		T264	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	1	1			T252	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T129	1		T265	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	3	1			T47	1		T84	1		T88	1
class_index[0x3]	intr_timeout_cnt[0]	25	1			T8	1		T75	1		T16	1
class_index[0x3]	intr_timeout_cnt[1]	18	1			T75	1		T64	1		T50	4
class_index[0x3]	intr_timeout_cnt[2]	10	1			T135	2		T266	1		T249	1
class_index[0x3]	intr_timeout_cnt[3]	1	1			T131	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	4	1			T120	1		T131	1		T256	1
class_index[0x3]	intr_timeout_cnt[6]	5	1			T267	1		T117	1		T17	2
class_index[0x3]	intr_timeout_cnt[9]	3	1			T249	1		T117	2		-	-