Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	350370	1			T1	7		T2	1469		T3	7
all_values[1]	350370	1			T1	7		T2	1469		T3	7
all_values[2]	350370	1			T1	7		T2	1469		T3	7
all_values[3]	350370	1			T1	7		T2	1469		T3	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

697393

1

T1

14

T2

2876

T3

19

auto[1]

704087

1

T1

14

T2

3000

T3

9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

836104

1

T1

6

T2

3043

T3

25

auto[1]

565376

1

T1

22

T2

2833

T3

3

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	98924	1			T1	1		T2	365		T3	4
all_values[0]	auto[0]	auto[1]	75268	1			T1	3		T2	316		T3	3
all_values[0]	auto[1]	auto[0]	100687	1			T1	1		T2	418		T4	248
all_values[0]	auto[1]	auto[1]	75491	1			T1	2		T2	370		T4	247
all_values[1]	auto[0]	auto[0]	105941	1			T2	356		T3	2		T4	235
all_values[1]	auto[0]	auto[1]	68119	1			T1	3		T2	356		T4	232
all_values[1]	auto[1]	auto[0]	107584	1			T1	1		T2	380		T3	5
all_values[1]	auto[1]	auto[1]	68726	1			T1	3		T2	377		T4	262
all_values[2]	auto[0]	auto[0]	105242	1			T2	397		T3	5		T4	271
all_values[2]	auto[0]	auto[1]	69327	1			T1	2		T2	344		T4	255
all_values[2]	auto[1]	auto[0]	106279	1			T1	2		T2	390		T3	2
all_values[2]	auto[1]	auto[1]	69522	1			T1	3		T2	338		T4	224
all_values[3]	auto[0]	auto[0]	105175	1			T1	1		T2	373		T3	5
all_values[3]	auto[0]	auto[1]	69397	1			T1	4		T2	369		T4	262
all_values[3]	auto[1]	auto[0]	106272	1			T2	364		T3	2		T4	236
all_values[3]	auto[1]	auto[1]	69526	1			T1	2		T2	363		T4	230