Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	350370	1			T1	7		T2	1469		T3	7
all_pins[1]	350370	1			T1	7		T2	1469		T3	7
all_pins[2]	350370	1			T1	7		T2	1469		T3	7
all_pins[3]	350370	1			T1	7		T2	1469		T3	7

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1118215	1			T1	18		T2	4428		T3	28
values[0x1]	283265	1			T1	10		T2	1448		T4	963
transitions[0x0=>0x1]	188483	1			T1	7		T2	911		T4	616
transitions[0x1=>0x0]	188719	1			T1	7		T2	912		T4	617

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	274879	1			T1	5		T2	1099		T3	7
all_pins[0]	values[0x1]	75491	1			T1	2		T2	370		T4	247
all_pins[0]	transitions[0x0=>0x1]	74893	1			T1	2		T2	369		T4	246
all_pins[0]	transitions[0x1=>0x0]	69164	1			T1	2		T2	363		T4	230
all_pins[1]	values[0x0]	281644	1			T1	4		T2	1092		T3	7
all_pins[1]	values[0x1]	68726	1			T1	3		T2	377		T4	262
all_pins[1]	transitions[0x0=>0x1]	37295	1			T1	1		T2	185		T4	133
all_pins[1]	transitions[0x1=>0x0]	44060	1			T2	178		T4	118		T6	326
all_pins[2]	values[0x0]	280848	1			T1	4		T2	1131		T3	7
all_pins[2]	values[0x1]	69522	1			T1	3		T2	338		T4	224
all_pins[2]	transitions[0x0=>0x1]	38285	1			T1	2		T2	171		T4	110
all_pins[2]	transitions[0x1=>0x0]	37489	1			T1	2		T2	210		T4	148
all_pins[3]	values[0x0]	280844	1			T1	5		T2	1106		T3	7
all_pins[3]	values[0x1]	69526	1			T1	2		T2	363		T4	230
all_pins[3]	transitions[0x0=>0x1]	38010	1			T1	2		T2	186		T4	127
all_pins[3]	transitions[0x1=>0x0]	38006	1			T1	3		T2	161		T4	121