Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	87630	1			T2	711		T4	302		T6	2155
accum_cnt_1000	214883	1			T1	1		T2	1357		T4	392
accum_cnt_100	26550	1			T2	73		T4	19		T6	247
accum_cnt_50	49660	1			T1	6		T2	54		T3	2
accum_cnt_10	189233	1			T1	22		T2	1141		T3	2
accum_cnt_0	419634	1			T1	7		T2	1136		T3	16

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	258048	1			T1	9		T2	1118		T3	5
class_index[0x1]	258048	1			T1	9		T2	1118		T3	5
class_index[0x2]	258048	1			T1	9		T2	1118		T3	5
class_index[0x3]	258048	1			T1	9		T2	1118		T3	5

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	22139	1			T2	170		T4	302		T6	194
class_index[0x0]	accum_cnt_1000	63824	1			T2	851		T4	392		T6	257
class_index[0x0]	accum_cnt_100	8572	1			T2	41		T4	19		T6	48
class_index[0x0]	accum_cnt_50	12736	1			T1	6		T2	34		T3	2
class_index[0x0]	accum_cnt_10	45063	1			T1	3		T2	18		T3	2
class_index[0x0]	accum_cnt_0	91108	1			T2	4		T3	1		T4	4
class_index[0x1]	accum_cnt_2000	23725	1			T2	541		T6	684		T16	456
class_index[0x1]	accum_cnt_1000	46491	1			T1	1		T2	506		T6	692
class_index[0x1]	accum_cnt_100	5574	1			T2	32		T6	84		T10	97
class_index[0x1]	accum_cnt_50	11109	1			T2	20		T6	71		T7	79
class_index[0x1]	accum_cnt_10	50177	1			T1	1		T2	5		T4	6
class_index[0x1]	accum_cnt_0	111009	1			T1	7		T2	14		T3	5
class_index[0x2]	accum_cnt_2000	22519	1			T6	681		T38	120		T43	192
class_index[0x2]	accum_cnt_1000	54402	1			T6	764		T10	36		T36	28
class_index[0x2]	accum_cnt_100	5936	1			T6	65		T10	39		T36	27
class_index[0x2]	accum_cnt_50	11183	1			T6	54		T9	13		T10	31
class_index[0x2]	accum_cnt_10	51265	1			T1	9		T2	1118		T4	2
class_index[0x2]	accum_cnt_0	104474	1			T3	5		T4	739		T6	72
class_index[0x3]	accum_cnt_2000	19247	1			T6	596		T38	227		T43	200
class_index[0x3]	accum_cnt_1000	50166	1			T6	573		T7	48		T10	649
class_index[0x3]	accum_cnt_100	6468	1			T6	50		T7	18		T10	67
class_index[0x3]	accum_cnt_50	14632	1			T6	43		T7	13		T10	93
class_index[0x3]	accum_cnt_10	42728	1			T1	9		T6	218		T7	4
class_index[0x3]	accum_cnt_0	113043	1			T2	1118		T3	5		T4	741