Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3555	1			T38	27		T43	107		T23	199
alert[0x1]	8810	1			T6	834		T9	1		T38	460
alert[0x2]	5873	1			T38	21		T23	721		T143	1
alert[0x3]	7059	1			T43	961		T140	1		T16	149
alert[0x4]	9806	1			T6	659		T74	53		T143	1
alert[0x5]	12201	1			T6	16		T43	43		T74	162
alert[0x6]	8763	1			T9	6		T38	45		T43	7
alert[0x7]	6894	1			T6	41		T38	1160		T43	522
alert[0x8]	6083	1			T6	1855		T21	1		T16	70
alert[0x9]	5563	1			T1	2		T9	2		T10	5
alert[0xa]	4002	1			T6	42		T38	74		T67	1
alert[0xb]	17553	1			T6	385		T38	39		T41	1
alert[0xc]	9506	1			T43	12		T140	2		T16	66
alert[0xd]	8935	1			T6	32		T9	1		T38	80
alert[0xe]	11667	1			T1	7		T6	29		T41	1
alert[0xf]	9749	1			T43	15		T23	3		T48	4
alert[0x10]	4160	1			T38	102		T43	6		T16	145
alert[0x11]	4770	1			T6	50		T38	110		T43	13
alert[0x12]	14515	1			T1	3		T74	53		T16	3024
alert[0x13]	17464	1			T38	423		T41	1		T43	20
alert[0x14]	17511	1			T6	13		T16	106		T23	76
alert[0x15]	9149	1			T38	198		T41	1		T16	4781
alert[0x16]	4563	1			T41	1		T16	683		T20	1236
alert[0x17]	4224	1			T9	5		T23	47		T20	88
alert[0x18]	11880	1			T38	162		T43	90		T23	43
alert[0x19]	7462	1			T9	3		T74	32		T20	927
alert[0x1a]	7763	1			T38	3055		T49	1		T97	5
alert[0x1b]	9649	1			T38	382		T74	43		T16	198
alert[0x1c]	7106	1			T6	11		T41	1		T43	26
alert[0x1d]	10025	1			T9	1		T41	3		T140	5
alert[0x1e]	3740	1			T6	28		T41	1		T43	17
alert[0x1f]	3788	1			T43	524		T23	71		T48	6
alert[0x20]	3786	1			T38	6		T43	318		T74	128
alert[0x21]	9947	1			T38	21		T74	385		T16	216
alert[0x22]	6333	1			T38	487		T43	78		T16	15
alert[0x23]	5258	1			T6	32		T38	278		T16	202
alert[0x24]	7250	1			T6	88		T74	30		T16	126
alert[0x25]	10885	1			T6	649		T16	79		T20	9
alert[0x26]	7995	1			T6	22		T38	31		T20	34
alert[0x27]	9644	1			T6	76		T38	50		T43	30
alert[0x28]	7941	1			T9	3		T10	6		T38	88
alert[0x29]	4496	1			T38	1023		T16	281		T20	101
alert[0x2a]	3440	1			T74	31		T70	2		T16	28
alert[0x2b]	14985	1			T6	170		T23	1		T20	393
alert[0x2c]	10795	1			T38	477		T43	264		T16	18
alert[0x2d]	3042	1			T6	41		T9	1		T38	10
alert[0x2e]	6852	1			T38	175		T40	2		T41	1
alert[0x2f]	8401	1			T38	161		T74	40		T16	356
alert[0x30]	7723	1			T41	1		T43	245		T74	28
alert[0x31]	9873	1			T43	8		T74	233		T16	2
alert[0x32]	11820	1			T16	14		T143	2		T48	3
alert[0x33]	19229	1			T6	190		T16	847		T143	1
alert[0x34]	3206	1			T9	3		T43	38		T23	636
alert[0x35]	5247	1			T1	9		T38	1027		T16	95
alert[0x36]	6698	1			T6	21		T38	205		T140	4
alert[0x37]	7701	1			T41	1		T74	25		T16	10
alert[0x38]	5367	1			T6	2158		T41	1		T43	24
alert[0x39]	3638	1			T43	421		T20	6		T296	1
alert[0x3a]	7662	1			T74	10		T16	12		T50	451
alert[0x3b]	6968	1			T38	27		T296	1		T108	150
alert[0x3c]	4448	1			T38	8		T41	3		T23	63
alert[0x3d]	8811	1			T6	10		T9	5		T38	31
alert[0x3e]	5181	1			T20	175		T108	409		T50	996
alert[0x3f]	8705	1			T6	264		T40	4		T16	21
alert[0x40]	5802	1			T6	432		T43	57		T70	4

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	140412	1			T1	12		T6	8109		T9	8
class_i[0x1]	114517	1			T6	12		T9	1		T10	11
class_i[0x2]	140302	1			T1	9		T6	27		T9	7
class_i[0x3]	127686	1			T9	15		T40	6		T41	18

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

522267

1

T1

21

T6

8148

T9

31

alert_ping_fail

650

1

T41

18

T68

3

T21

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3548	1			T38	27		T43	107		T23	199
alert_integrity_fail	alert[0x1]	8802	1			T6	834		T9	1		T38	460
alert_integrity_fail	alert[0x2]	5860	1			T38	21		T23	721		T239	6
alert_integrity_fail	alert[0x3]	7055	1			T43	961		T140	1		T16	149
alert_integrity_fail	alert[0x4]	9799	1			T6	659		T74	53		T48	1
alert_integrity_fail	alert[0x5]	12184	1			T6	16		T43	43		T74	162
alert_integrity_fail	alert[0x6]	8743	1			T9	6		T38	45		T43	7
alert_integrity_fail	alert[0x7]	6887	1			T6	41		T38	1160		T43	522
alert_integrity_fail	alert[0x8]	6068	1			T6	1855		T16	70		T23	18
alert_integrity_fail	alert[0x9]	5559	1			T1	2		T9	2		T10	5
alert_integrity_fail	alert[0xa]	3995	1			T6	42		T38	74		T67	1
alert_integrity_fail	alert[0xb]	17542	1			T6	385		T38	39		T43	30
alert_integrity_fail	alert[0xc]	9497	1			T43	12		T140	2		T16	66
alert_integrity_fail	alert[0xd]	8923	1			T6	32		T9	1		T38	80
alert_integrity_fail	alert[0xe]	11656	1			T1	7		T6	29		T84	1
alert_integrity_fail	alert[0xf]	9737	1			T43	15		T23	3		T48	4
alert_integrity_fail	alert[0x10]	4152	1			T38	102		T43	6		T16	145
alert_integrity_fail	alert[0x11]	4759	1			T6	50		T38	110		T43	13
alert_integrity_fail	alert[0x12]	14507	1			T1	3		T74	53		T16	3024
alert_integrity_fail	alert[0x13]	17450	1			T38	423		T43	20		T74	1090
alert_integrity_fail	alert[0x14]	17497	1			T6	13		T16	106		T23	76
alert_integrity_fail	alert[0x15]	9140	1			T38	198		T16	4781		T108	21
alert_integrity_fail	alert[0x16]	4557	1			T16	683		T20	1236		T47	94
alert_integrity_fail	alert[0x17]	4214	1			T9	5		T23	47		T20	88
alert_integrity_fail	alert[0x18]	11870	1			T38	162		T43	90		T23	43
alert_integrity_fail	alert[0x19]	7455	1			T9	3		T74	32		T20	927
alert_integrity_fail	alert[0x1a]	7760	1			T38	3055		T49	1		T97	5
alert_integrity_fail	alert[0x1b]	9631	1			T38	382		T74	43		T16	198
alert_integrity_fail	alert[0x1c]	7092	1			T6	11		T43	26		T23	49
alert_integrity_fail	alert[0x1d]	10012	1			T9	1		T140	5		T16	28
alert_integrity_fail	alert[0x1e]	3729	1			T6	28		T43	17		T16	24
alert_integrity_fail	alert[0x1f]	3778	1			T43	524		T23	71		T48	6
alert_integrity_fail	alert[0x20]	3773	1			T38	6		T43	318		T74	128
alert_integrity_fail	alert[0x21]	9939	1			T38	21		T74	385		T16	216
alert_integrity_fail	alert[0x22]	6320	1			T38	487		T43	78		T16	15
alert_integrity_fail	alert[0x23]	5243	1			T6	32		T38	278		T16	202
alert_integrity_fail	alert[0x24]	7240	1			T6	88		T74	30		T16	126
alert_integrity_fail	alert[0x25]	10875	1			T6	649		T16	79		T20	9
alert_integrity_fail	alert[0x26]	7982	1			T6	22		T38	31		T20	34
alert_integrity_fail	alert[0x27]	9634	1			T6	76		T38	50		T43	30
alert_integrity_fail	alert[0x28]	7926	1			T9	3		T10	6		T38	88
alert_integrity_fail	alert[0x29]	4483	1			T38	1023		T16	281		T20	101
alert_integrity_fail	alert[0x2a]	3433	1			T74	31		T70	2		T16	28
alert_integrity_fail	alert[0x2b]	14973	1			T6	170		T23	1		T20	393
alert_integrity_fail	alert[0x2c]	10784	1			T38	477		T43	264		T16	18
alert_integrity_fail	alert[0x2d]	3030	1			T6	41		T9	1		T38	10
alert_integrity_fail	alert[0x2e]	6845	1			T38	175		T40	2		T140	1
alert_integrity_fail	alert[0x2f]	8389	1			T38	161		T74	40		T16	356
alert_integrity_fail	alert[0x30]	7713	1			T43	245		T74	28		T20	57
alert_integrity_fail	alert[0x31]	9868	1			T43	8		T74	233		T16	2
alert_integrity_fail	alert[0x32]	11812	1			T16	14		T48	3		T93	35
alert_integrity_fail	alert[0x33]	19221	1			T6	190		T16	847		T49	2
alert_integrity_fail	alert[0x34]	3196	1			T9	3		T43	38		T23	636
alert_integrity_fail	alert[0x35]	5238	1			T1	9		T38	1027		T16	95
alert_integrity_fail	alert[0x36]	6690	1			T6	21		T38	205		T140	4
alert_integrity_fail	alert[0x37]	7691	1			T74	25		T16	10		T23	72
alert_integrity_fail	alert[0x38]	5354	1			T6	2158		T43	24		T16	114
alert_integrity_fail	alert[0x39]	3631	1			T43	421		T20	6		T108	85
alert_integrity_fail	alert[0x3a]	7660	1			T74	10		T16	12		T50	451
alert_integrity_fail	alert[0x3b]	6958	1			T38	27		T108	150		T84	1
alert_integrity_fail	alert[0x3c]	4434	1			T38	8		T23	63		T20	40
alert_integrity_fail	alert[0x3d]	8798	1			T6	10		T9	5		T38	31
alert_integrity_fail	alert[0x3e]	5175	1			T20	175		T108	409		T50	996
alert_integrity_fail	alert[0x3f]	8703	1			T6	264		T40	4		T16	21
alert_integrity_fail	alert[0x40]	5798	1			T6	432		T43	57		T70	4
alert_ping_fail	alert[0x0]	7	1			T297	1		T110	1		T298	2
alert_ping_fail	alert[0x1]	8	1			T296	1		T299	1		T300	1
alert_ping_fail	alert[0x2]	13	1			T143	1		T301	1		T302	1
alert_ping_fail	alert[0x3]	4	1			T303	1		T304	1		T305	2
alert_ping_fail	alert[0x4]	7	1			T143	1		T296	1		T268	1
alert_ping_fail	alert[0x5]	17	1			T296	1		T29	1		T268	1
alert_ping_fail	alert[0x6]	20	1			T68	1		T306	1		T307	3
alert_ping_fail	alert[0x7]	7	1			T308	1		T309	1		T310	1
alert_ping_fail	alert[0x8]	15	1			T21	1		T307	1		T110	1
alert_ping_fail	alert[0x9]	4	1			T311	1		T312	1		T309	1
alert_ping_fail	alert[0xa]	7	1			T313	2		T298	1		T304	1
alert_ping_fail	alert[0xb]	11	1			T41	1		T314	1		T315	1
alert_ping_fail	alert[0xc]	9	1			T315	1		T312	1		T309	1
alert_ping_fail	alert[0xd]	12	1			T41	1		T143	1		T268	1
alert_ping_fail	alert[0xe]	11	1			T41	1		T316	1		T314	1
alert_ping_fail	alert[0xf]	12	1			T296	3		T299	1		T317	1
alert_ping_fail	alert[0x10]	8	1			T143	1		T118	1		T315	1
alert_ping_fail	alert[0x11]	11	1			T296	1		T302	1		T318	1
alert_ping_fail	alert[0x12]	8	1			T143	1		T268	1		T297	1
alert_ping_fail	alert[0x13]	14	1			T41	1		T296	1		T316	1
alert_ping_fail	alert[0x14]	14	1			T316	1		T315	1		T319	2
alert_ping_fail	alert[0x15]	9	1			T41	1		T118	1		T306	1
alert_ping_fail	alert[0x16]	6	1			T41	1		T306	1		T320	1
alert_ping_fail	alert[0x17]	10	1			T297	1		T303	1		T300	2
alert_ping_fail	alert[0x18]	10	1			T299	1		T321	1		T322	1
alert_ping_fail	alert[0x19]	7	1			T297	1		T313	1		T323	1
alert_ping_fail	alert[0x1a]	3	1			T312	1		T319	1		T324	1
alert_ping_fail	alert[0x1b]	18	1			T296	1		T297	1		T299	1
alert_ping_fail	alert[0x1c]	14	1			T41	1		T68	2		T306	1
alert_ping_fail	alert[0x1d]	13	1			T41	3		T243	1		T296	1
alert_ping_fail	alert[0x1e]	11	1			T41	1		T314	2		T306	1
alert_ping_fail	alert[0x1f]	10	1			T296	1		T297	1		T291	1
alert_ping_fail	alert[0x20]	13	1			T118	1		T297	1		T299	1
alert_ping_fail	alert[0x21]	8	1			T317	1		T318	1		T300	1
alert_ping_fail	alert[0x22]	13	1			T296	1		T314	1		T297	1
alert_ping_fail	alert[0x23]	15	1			T316	1		T314	1		T297	1
alert_ping_fail	alert[0x24]	10	1			T268	1		T302	2		T318	1
alert_ping_fail	alert[0x25]	10	1			T317	1		T321	1		T311	1
alert_ping_fail	alert[0x26]	13	1			T314	1		T306	1		T322	1
alert_ping_fail	alert[0x27]	10	1			T296	1		T297	1		T301	1
alert_ping_fail	alert[0x28]	15	1			T143	1		T307	1		T110	1
alert_ping_fail	alert[0x29]	13	1			T268	1		T315	1		T321	1
alert_ping_fail	alert[0x2a]	7	1			T317	1		T325	1		T318	2
alert_ping_fail	alert[0x2b]	12	1			T297	1		T299	1		T321	1
alert_ping_fail	alert[0x2c]	11	1			T143	1		T296	1		T315	1
alert_ping_fail	alert[0x2d]	12	1			T118	2		T301	1		T307	1
alert_ping_fail	alert[0x2e]	7	1			T41	1		T309	1		T318	1
alert_ping_fail	alert[0x2f]	12	1			T296	2		T295	1		T326	2
alert_ping_fail	alert[0x30]	10	1			T41	1		T219	1		T268	1
alert_ping_fail	alert[0x31]	5	1			T297	1		T317	1		T315	1
alert_ping_fail	alert[0x32]	8	1			T143	2		T309	1		T323	2
alert_ping_fail	alert[0x33]	8	1			T143	1		T296	1		T314	1
alert_ping_fail	alert[0x34]	10	1			T300	2		T313	1		T327	1
alert_ping_fail	alert[0x35]	9	1			T268	1		T299	1		T317	1
alert_ping_fail	alert[0x36]	8	1			T143	1		T297	1		T322	1
alert_ping_fail	alert[0x37]	10	1			T41	1		T314	1		T297	1
alert_ping_fail	alert[0x38]	13	1			T41	1		T316	1		T268	1
alert_ping_fail	alert[0x39]	7	1			T296	1		T299	1		T301	1
alert_ping_fail	alert[0x3a]	2	1			T321	1		T323	1		-	-
alert_ping_fail	alert[0x3b]	10	1			T296	1		T320	1		T328	1
alert_ping_fail	alert[0x3c]	14	1			T41	3		T316	1		T301	1
alert_ping_fail	alert[0x3d]	13	1			T314	2		T297	1		T322	1
alert_ping_fail	alert[0x3e]	6	1			T314	1		T299	1		T301	1
alert_ping_fail	alert[0x3f]	2	1			T320	1		T309	1		-	-
alert_ping_fail	alert[0x40]	4	1			T143	1		T325	1		T300	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	140337	1			T1	12		T6	8109		T9	8
alert_integrity_fail	class_i[0x1]	114329	1			T6	12		T9	1		T10	11
alert_integrity_fail	class_i[0x2]	140137	1			T1	9		T6	27		T9	7
alert_integrity_fail	class_i[0x3]	127464	1			T9	15		T40	6		T43	4090
alert_ping_fail	class_i[0x0]	75	1			T68	3		T314	1		T268	9
alert_ping_fail	class_i[0x1]	188	1			T21	1		T314	10		T297	17
alert_ping_fail	class_i[0x2]	165	1			T219	1		T118	5		T316	6
alert_ping_fail	class_i[0x3]	222	1			T41	18		T143	12		T243	1