Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 99.99 98.69 99.97 100.00 100.00 99.38 99.52


Total test records in report: 837
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T774 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.537523106 Jun 22 04:54:49 PM PDT 24 Jun 22 04:55:32 PM PDT 24 1296632914 ps
T775 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3699580935 Jun 22 04:54:50 PM PDT 24 Jun 22 04:54:58 PM PDT 24 87650659 ps
T776 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2397583979 Jun 22 04:55:06 PM PDT 24 Jun 22 04:55:27 PM PDT 24 1952416203 ps
T168 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3702093502 Jun 22 04:54:51 PM PDT 24 Jun 22 04:57:37 PM PDT 24 5005473887 ps
T777 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2855033717 Jun 22 04:55:10 PM PDT 24 Jun 22 04:55:12 PM PDT 24 15583139 ps
T175 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1594267254 Jun 22 04:54:50 PM PDT 24 Jun 22 05:00:15 PM PDT 24 13123164427 ps
T195 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3748995050 Jun 22 04:54:45 PM PDT 24 Jun 22 04:55:17 PM PDT 24 469267610 ps
T778 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2687290441 Jun 22 04:55:08 PM PDT 24 Jun 22 04:55:11 PM PDT 24 7515919 ps
T779 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2037676392 Jun 22 04:54:53 PM PDT 24 Jun 22 04:55:34 PM PDT 24 592531748 ps
T780 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1679535133 Jun 22 04:54:42 PM PDT 24 Jun 22 04:55:06 PM PDT 24 1480797051 ps
T781 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3069937496 Jun 22 04:55:07 PM PDT 24 Jun 22 04:55:10 PM PDT 24 9948026 ps
T782 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.17915639 Jun 22 04:55:02 PM PDT 24 Jun 22 04:55:08 PM PDT 24 52364669 ps
T171 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3591186496 Jun 22 04:54:53 PM PDT 24 Jun 22 05:05:32 PM PDT 24 6919989226 ps
T169 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2599800943 Jun 22 04:54:48 PM PDT 24 Jun 22 05:02:40 PM PDT 24 7199464181 ps
T191 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.4199846953 Jun 22 04:54:53 PM PDT 24 Jun 22 04:54:58 PM PDT 24 107178546 ps
T783 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.153493397 Jun 22 04:54:53 PM PDT 24 Jun 22 04:55:01 PM PDT 24 73267796 ps
T784 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3047033936 Jun 22 04:55:07 PM PDT 24 Jun 22 04:55:16 PM PDT 24 2436004178 ps
T785 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1325839379 Jun 22 04:54:54 PM PDT 24 Jun 22 04:55:10 PM PDT 24 894386005 ps
T786 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3884607996 Jun 22 04:55:07 PM PDT 24 Jun 22 04:55:10 PM PDT 24 9532429 ps
T787 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2238439311 Jun 22 04:54:59 PM PDT 24 Jun 22 04:55:13 PM PDT 24 698622728 ps
T788 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3639936539 Jun 22 04:54:58 PM PDT 24 Jun 22 04:55:12 PM PDT 24 211644793 ps
T789 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2997380483 Jun 22 04:54:52 PM PDT 24 Jun 22 04:55:18 PM PDT 24 167184879 ps
T172 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1507079726 Jun 22 04:55:08 PM PDT 24 Jun 22 04:58:00 PM PDT 24 6040401687 ps
T177 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3592508490 Jun 22 04:54:57 PM PDT 24 Jun 22 05:05:21 PM PDT 24 8932532086 ps
T182 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.54375589 Jun 22 04:55:00 PM PDT 24 Jun 22 04:56:34 PM PDT 24 2945009130 ps
T790 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3632794207 Jun 22 04:55:07 PM PDT 24 Jun 22 04:55:09 PM PDT 24 12120345 ps
T791 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1094905208 Jun 22 04:55:06 PM PDT 24 Jun 22 04:55:08 PM PDT 24 11346808 ps
T792 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3332866635 Jun 22 04:55:11 PM PDT 24 Jun 22 04:55:13 PM PDT 24 8007485 ps
T793 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3907296649 Jun 22 04:54:48 PM PDT 24 Jun 22 04:54:57 PM PDT 24 442155390 ps
T794 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2518747649 Jun 22 04:55:10 PM PDT 24 Jun 22 04:55:12 PM PDT 24 8511404 ps
T190 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3444348702 Jun 22 04:55:02 PM PDT 24 Jun 22 04:56:20 PM PDT 24 4949784074 ps
T795 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2325640708 Jun 22 04:55:18 PM PDT 24 Jun 22 04:55:24 PM PDT 24 70747353 ps
T197 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1772956719 Jun 22 04:54:45 PM PDT 24 Jun 22 04:54:48 PM PDT 24 86422504 ps
T796 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.4044134404 Jun 22 04:54:55 PM PDT 24 Jun 22 04:55:07 PM PDT 24 141566922 ps
T797 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.610725100 Jun 22 04:55:02 PM PDT 24 Jun 22 04:55:25 PM PDT 24 1134872687 ps
T798 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1034960734 Jun 22 04:54:51 PM PDT 24 Jun 22 04:54:59 PM PDT 24 39270342 ps
T799 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.510767000 Jun 22 04:54:55 PM PDT 24 Jun 22 04:55:02 PM PDT 24 285522649 ps
T173 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2072424442 Jun 22 04:55:02 PM PDT 24 Jun 22 04:56:37 PM PDT 24 1658522017 ps
T800 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1532851794 Jun 22 04:54:54 PM PDT 24 Jun 22 04:55:01 PM PDT 24 33922001 ps
T801 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1640088643 Jun 22 04:55:08 PM PDT 24 Jun 22 04:55:11 PM PDT 24 26890659 ps
T802 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1083386776 Jun 22 04:55:06 PM PDT 24 Jun 22 04:55:10 PM PDT 24 92508298 ps
T803 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1210729563 Jun 22 04:55:07 PM PDT 24 Jun 22 04:55:10 PM PDT 24 6377572 ps
T804 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.177309295 Jun 22 04:55:07 PM PDT 24 Jun 22 04:55:09 PM PDT 24 10665641 ps
T805 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3136262413 Jun 22 04:54:55 PM PDT 24 Jun 22 04:54:58 PM PDT 24 10297598 ps
T806 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2501720060 Jun 22 04:55:10 PM PDT 24 Jun 22 04:55:12 PM PDT 24 15002227 ps
T807 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.4212944917 Jun 22 04:54:52 PM PDT 24 Jun 22 04:55:15 PM PDT 24 658087650 ps
T176 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2389875786 Jun 22 04:54:50 PM PDT 24 Jun 22 05:15:36 PM PDT 24 69305379632 ps
T164 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1270397632 Jun 22 04:54:56 PM PDT 24 Jun 22 04:58:33 PM PDT 24 6882804678 ps
T808 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1790368327 Jun 22 04:54:56 PM PDT 24 Jun 22 04:55:03 PM PDT 24 420037891 ps
T809 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.993230118 Jun 22 04:55:11 PM PDT 24 Jun 22 04:55:13 PM PDT 24 6302669 ps
T810 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2248345471 Jun 22 04:54:56 PM PDT 24 Jun 22 04:55:06 PM PDT 24 125060611 ps
T811 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2590510258 Jun 22 04:54:55 PM PDT 24 Jun 22 04:54:58 PM PDT 24 13791551 ps
T812 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1833756726 Jun 22 04:54:50 PM PDT 24 Jun 22 04:57:17 PM PDT 24 2189369129 ps
T203 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.811948348 Jun 22 04:54:44 PM PDT 24 Jun 22 04:54:47 PM PDT 24 60574168 ps
T813 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1885135287 Jun 22 04:55:11 PM PDT 24 Jun 22 04:55:13 PM PDT 24 12301294 ps
T814 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3901491132 Jun 22 04:54:51 PM PDT 24 Jun 22 04:59:46 PM PDT 24 4281029200 ps
T178 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2951176876 Jun 22 04:55:02 PM PDT 24 Jun 22 04:59:41 PM PDT 24 4373087861 ps
T815 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1332711723 Jun 22 04:55:08 PM PDT 24 Jun 22 04:55:11 PM PDT 24 17179851 ps
T816 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.592295368 Jun 22 04:55:05 PM PDT 24 Jun 22 04:55:24 PM PDT 24 555028848 ps
T200 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1444432503 Jun 22 04:55:02 PM PDT 24 Jun 22 04:55:38 PM PDT 24 470716444 ps
T817 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3139678521 Jun 22 04:55:01 PM PDT 24 Jun 22 04:55:15 PM PDT 24 290932942 ps
T201 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1832904448 Jun 22 04:54:56 PM PDT 24 Jun 22 04:55:02 PM PDT 24 55963983 ps
T818 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2550580130 Jun 22 04:54:51 PM PDT 24 Jun 22 04:55:01 PM PDT 24 355084621 ps
T183 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.4040460895 Jun 22 04:55:06 PM PDT 24 Jun 22 05:03:59 PM PDT 24 31947298482 ps
T819 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2893495624 Jun 22 04:54:45 PM PDT 24 Jun 22 04:54:50 PM PDT 24 29346107 ps
T820 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.4107707298 Jun 22 04:54:52 PM PDT 24 Jun 22 04:55:17 PM PDT 24 177163194 ps
T821 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.50240895 Jun 22 04:55:02 PM PDT 24 Jun 22 04:55:27 PM PDT 24 177107007 ps
T822 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1896939813 Jun 22 04:55:00 PM PDT 24 Jun 22 04:55:07 PM PDT 24 38538522 ps
T823 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2001133205 Jun 22 04:54:55 PM PDT 24 Jun 22 04:55:02 PM PDT 24 51409044 ps
T824 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2944054983 Jun 22 04:54:45 PM PDT 24 Jun 22 04:54:53 PM PDT 24 659139952 ps
T825 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3659465089 Jun 22 04:55:08 PM PDT 24 Jun 22 04:55:10 PM PDT 24 6406107 ps
T826 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.344948959 Jun 22 04:54:52 PM PDT 24 Jun 22 04:55:01 PM PDT 24 940070969 ps
T827 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2563905702 Jun 22 04:55:01 PM PDT 24 Jun 22 04:55:20 PM PDT 24 510612380 ps
T179 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1426746552 Jun 22 04:55:12 PM PDT 24 Jun 22 04:56:57 PM PDT 24 852272417 ps
T828 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3262016666 Jun 22 04:55:06 PM PDT 24 Jun 22 04:55:08 PM PDT 24 8946385 ps
T829 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3670339985 Jun 22 04:54:59 PM PDT 24 Jun 22 04:55:03 PM PDT 24 164411377 ps
T830 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1300203848 Jun 22 04:54:51 PM PDT 24 Jun 22 04:58:18 PM PDT 24 1639810246 ps
T831 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3979635727 Jun 22 04:55:02 PM PDT 24 Jun 22 04:55:08 PM PDT 24 49048658 ps
T832 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3232384059 Jun 22 04:54:55 PM PDT 24 Jun 22 04:57:21 PM PDT 24 2304141036 ps
T181 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3624521682 Jun 22 04:55:01 PM PDT 24 Jun 22 05:12:08 PM PDT 24 51479911421 ps
T833 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.4257567041 Jun 22 04:54:48 PM PDT 24 Jun 22 04:54:59 PM PDT 24 60215611 ps
T180 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1263336748 Jun 22 04:54:52 PM PDT 24 Jun 22 05:06:12 PM PDT 24 7803628759 ps
T834 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2424563430 Jun 22 04:54:59 PM PDT 24 Jun 22 04:55:22 PM PDT 24 522245366 ps
T194 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3902460389 Jun 22 04:54:53 PM PDT 24 Jun 22 04:55:33 PM PDT 24 621693807 ps
T835 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3882011272 Jun 22 04:55:07 PM PDT 24 Jun 22 04:55:09 PM PDT 24 6668502 ps
T836 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.596295903 Jun 22 04:54:47 PM PDT 24 Jun 22 04:54:56 PM PDT 24 104794454 ps
T837 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3271861348 Jun 22 04:54:51 PM PDT 24 Jun 22 05:00:32 PM PDT 24 23782248115 ps

Test location /workspace/coverage/default/34.alert_handler_stress_all.3452489135
Short name T6
Test name
Test status
Simulation time 76781531531 ps
CPU time 1861.75 seconds
Started Jun 22 05:03:03 PM PDT 24
Finished Jun 22 05:34:05 PM PDT 24
Peak memory 298228 kb
Host smart-458a6ef5-11ab-4036-aa31-280682970902
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452489135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3452489135
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.2249155079
Short name T93
Test name
Test status
Simulation time 655916316463 ps
CPU time 4006.86 seconds
Started Jun 22 05:02:34 PM PDT 24
Finished Jun 22 06:09:22 PM PDT 24
Peak memory 305948 kb
Host smart-acdb970b-a49b-460b-9b76-3fb78006968c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249155079 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.2249155079
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3297491414
Short name T11
Test name
Test status
Simulation time 2159084403 ps
CPU time 24.86 seconds
Started Jun 22 05:01:47 PM PDT 24
Finished Jun 22 05:02:13 PM PDT 24
Peak memory 269640 kb
Host smart-56415b5e-bb26-428a-ba72-d862f3fb46e4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3297491414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3297491414
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2982464725
Short name T74
Test name
Test status
Simulation time 176076359658 ps
CPU time 1913.85 seconds
Started Jun 22 05:02:26 PM PDT 24
Finished Jun 22 05:34:21 PM PDT 24
Peak memory 286560 kb
Host smart-a36bb161-27bd-449e-82a0-e6555f78af3a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982464725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2982464725
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.4161738668
Short name T185
Test name
Test status
Simulation time 1346486734 ps
CPU time 81.35 seconds
Started Jun 22 04:54:56 PM PDT 24
Finished Jun 22 04:56:19 PM PDT 24
Peak memory 237556 kb
Host smart-007f54a4-9b60-401f-81e6-175414d6f528
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4161738668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.4161738668
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3111376521
Short name T53
Test name
Test status
Simulation time 236522202569 ps
CPU time 3141.89 seconds
Started Jun 22 05:01:34 PM PDT 24
Finished Jun 22 05:53:57 PM PDT 24
Peak memory 290228 kb
Host smart-86e0ef4f-a38c-46ea-8529-0c38c15f6bbb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111376521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3111376521
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.133802562
Short name T38
Test name
Test status
Simulation time 165382998380 ps
CPU time 2926.1 seconds
Started Jun 22 05:01:56 PM PDT 24
Finished Jun 22 05:50:44 PM PDT 24
Peak memory 288676 kb
Host smart-a1d1fee4-555f-42ca-b2e7-92c8895200ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133802562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.133802562
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.4286587223
Short name T49
Test name
Test status
Simulation time 190402031002 ps
CPU time 3634.32 seconds
Started Jun 22 05:02:08 PM PDT 24
Finished Jun 22 06:02:43 PM PDT 24
Peak memory 322240 kb
Host smart-2a097fc8-16f1-40fc-83b1-49d1e0082b54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286587223 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.4286587223
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2178697776
Short name T295
Test name
Test status
Simulation time 70943626631 ps
CPU time 2297.26 seconds
Started Jun 22 05:01:46 PM PDT 24
Finished Jun 22 05:40:04 PM PDT 24
Peak memory 289460 kb
Host smart-bcd55674-85b3-4648-94b8-6f456dc76496
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178697776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2178697776
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2635278566
Short name T159
Test name
Test status
Simulation time 8185237035 ps
CPU time 301.11 seconds
Started Jun 22 04:54:58 PM PDT 24
Finished Jun 22 05:00:00 PM PDT 24
Peak memory 272840 kb
Host smart-0c7628a5-4931-4bf9-8089-2eb030f85609
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2635278566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2635278566
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3084772784
Short name T129
Test name
Test status
Simulation time 483452880399 ps
CPU time 4690.68 seconds
Started Jun 22 05:02:51 PM PDT 24
Finished Jun 22 06:21:03 PM PDT 24
Peak memory 306064 kb
Host smart-eaaf1a1d-5908-427b-874a-f60238838f8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084772784 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3084772784
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1687456111
Short name T151
Test name
Test status
Simulation time 4451651598 ps
CPU time 559.3 seconds
Started Jun 22 04:54:51 PM PDT 24
Finished Jun 22 05:04:13 PM PDT 24
Peak memory 265628 kb
Host smart-d70ec71c-3d71-48a3-bb47-bef625f3997b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687456111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1687456111
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.4276858435
Short name T126
Test name
Test status
Simulation time 20037263117 ps
CPU time 1120.37 seconds
Started Jun 22 05:03:53 PM PDT 24
Finished Jun 22 05:22:34 PM PDT 24
Peak memory 282072 kb
Host smart-ed81d9e2-0986-4a67-8ad2-4ee0307fab86
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276858435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.4276858435
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2304358420
Short name T145
Test name
Test status
Simulation time 16309101635 ps
CPU time 287.88 seconds
Started Jun 22 04:55:02 PM PDT 24
Finished Jun 22 04:59:51 PM PDT 24
Peak memory 265580 kb
Host smart-5b7d9431-a0f4-41ad-a31d-aa8c8ea5b39b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2304358420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2304358420
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1610415541
Short name T219
Test name
Test status
Simulation time 18825388436 ps
CPU time 1566 seconds
Started Jun 22 05:03:02 PM PDT 24
Finished Jun 22 05:29:08 PM PDT 24
Peak memory 288744 kb
Host smart-a01ac666-c8e5-402a-b5c3-c4e17824b7a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610415541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1610415541
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2353761828
Short name T161
Test name
Test status
Simulation time 90424884954 ps
CPU time 1167.03 seconds
Started Jun 22 04:54:52 PM PDT 24
Finished Jun 22 05:14:22 PM PDT 24
Peak memory 265792 kb
Host smart-dd4bfe40-7138-45b2-add4-4d8aba10d45c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353761828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2353761828
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1792587188
Short name T352
Test name
Test status
Simulation time 21141250 ps
CPU time 1.43 seconds
Started Jun 22 04:54:45 PM PDT 24
Finished Jun 22 04:54:47 PM PDT 24
Peak memory 237316 kb
Host smart-7bcfcd6e-13e7-4a83-be96-f6ba5d7b121b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1792587188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1792587188
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3664748306
Short name T10
Test name
Test status
Simulation time 135794653825 ps
CPU time 2472.28 seconds
Started Jun 22 05:03:31 PM PDT 24
Finished Jun 22 05:44:44 PM PDT 24
Peak memory 290012 kb
Host smart-ba765778-5a2f-4aeb-b619-26170ee7cf24
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664748306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3664748306
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1239767557
Short name T297
Test name
Test status
Simulation time 18943599840 ps
CPU time 564.75 seconds
Started Jun 22 05:03:53 PM PDT 24
Finished Jun 22 05:13:18 PM PDT 24
Peak memory 248736 kb
Host smart-fe1c2af2-6727-4016-acab-62099ac0cdbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239767557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1239767557
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3281650730
Short name T282
Test name
Test status
Simulation time 31141156902 ps
CPU time 1759.6 seconds
Started Jun 22 05:02:31 PM PDT 24
Finished Jun 22 05:31:52 PM PDT 24
Peak memory 272812 kb
Host smart-4f0cf241-b4f4-4a44-877f-1ee42468a936
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281650730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3281650730
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1507079726
Short name T172
Test name
Test status
Simulation time 6040401687 ps
CPU time 170.28 seconds
Started Jun 22 04:55:08 PM PDT 24
Finished Jun 22 04:58:00 PM PDT 24
Peak memory 271348 kb
Host smart-d8b6c7f3-9896-4fcb-b467-d92ce2d97af5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1507079726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1507079726
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2281962062
Short name T174
Test name
Test status
Simulation time 12875652056 ps
CPU time 1033.75 seconds
Started Jun 22 04:55:05 PM PDT 24
Finished Jun 22 05:12:19 PM PDT 24
Peak memory 273492 kb
Host smart-8cdad3ac-f127-4005-a0a3-c511baf88850
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281962062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2281962062
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2531599431
Short name T41
Test name
Test status
Simulation time 21318679582 ps
CPU time 464.99 seconds
Started Jun 22 05:02:30 PM PDT 24
Finished Jun 22 05:10:17 PM PDT 24
Peak memory 248692 kb
Host smart-513895a5-f36f-47c6-b312-526a58e5482b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531599431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2531599431
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1029816065
Short name T68
Test name
Test status
Simulation time 45975714650 ps
CPU time 2243.76 seconds
Started Jun 22 05:02:28 PM PDT 24
Finished Jun 22 05:39:52 PM PDT 24
Peak memory 289504 kb
Host smart-cfec429a-0a77-40ea-9ba2-7ad3ebf33a5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029816065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1029816065
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3488131459
Short name T300
Test name
Test status
Simulation time 14297723421 ps
CPU time 574.64 seconds
Started Jun 22 05:02:16 PM PDT 24
Finished Jun 22 05:11:53 PM PDT 24
Peak memory 255756 kb
Host smart-174cada7-9963-414a-96bd-69d59809b223
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488131459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3488131459
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3016284200
Short name T153
Test name
Test status
Simulation time 69026809236 ps
CPU time 1096.17 seconds
Started Jun 22 04:54:58 PM PDT 24
Finished Jun 22 05:13:15 PM PDT 24
Peak memory 265636 kb
Host smart-2ab81d06-299b-4aec-8269-79ecb04a1ac9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016284200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3016284200
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3507519399
Short name T307
Test name
Test status
Simulation time 62794307525 ps
CPU time 3539.56 seconds
Started Jun 22 05:01:52 PM PDT 24
Finished Jun 22 06:00:53 PM PDT 24
Peak memory 290040 kb
Host smart-554164bc-17e6-4fc5-87f7-24d95054c226
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507519399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3507519399
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2392154543
Short name T309
Test name
Test status
Simulation time 68495472967 ps
CPU time 527.98 seconds
Started Jun 22 05:02:10 PM PDT 24
Finished Jun 22 05:10:59 PM PDT 24
Peak memory 248880 kb
Host smart-c36716fb-8af0-49fc-bbe2-6bf4273ffc27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392154543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2392154543
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.2898779033
Short name T131
Test name
Test status
Simulation time 200093738254 ps
CPU time 3324.56 seconds
Started Jun 22 05:01:41 PM PDT 24
Finished Jun 22 05:57:07 PM PDT 24
Peak memory 302288 kb
Host smart-9f6fec5e-a9b2-4233-8b21-126aa15ce337
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898779033 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.2898779033
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3170967608
Short name T50
Test name
Test status
Simulation time 217013674637 ps
CPU time 3134.51 seconds
Started Jun 22 05:03:11 PM PDT 24
Finished Jun 22 05:55:26 PM PDT 24
Peak memory 303896 kb
Host smart-08d59779-5fa5-47ba-b676-f6aefab617de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170967608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3170967608
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1601203798
Short name T157
Test name
Test status
Simulation time 7160253664 ps
CPU time 220.81 seconds
Started Jun 22 04:54:52 PM PDT 24
Finished Jun 22 04:58:35 PM PDT 24
Peak memory 273560 kb
Host smart-6a85b7d4-264c-4eae-b83a-1af4bdef8490
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1601203798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1601203798
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1935576977
Short name T117
Test name
Test status
Simulation time 281471815206 ps
CPU time 4841.65 seconds
Started Jun 22 05:01:46 PM PDT 24
Finished Jun 22 06:22:29 PM PDT 24
Peak memory 297840 kb
Host smart-419bb159-ee99-4410-bd44-ee80e9bdd4cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935576977 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1935576977
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3726409858
Short name T336
Test name
Test status
Simulation time 31800843511 ps
CPU time 1728.1 seconds
Started Jun 22 05:03:24 PM PDT 24
Finished Jun 22 05:32:13 PM PDT 24
Peak memory 267620 kb
Host smart-abf99f32-a553-4ec8-a963-3a17fbdbb663
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726409858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3726409858
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3942483024
Short name T724
Test name
Test status
Simulation time 6855334 ps
CPU time 1.4 seconds
Started Jun 22 04:55:06 PM PDT 24
Finished Jun 22 04:55:08 PM PDT 24
Peak memory 237264 kb
Host smart-fb1b7e91-96d9-4b58-99d7-05d42769d775
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3942483024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3942483024
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.200085600
Short name T305
Test name
Test status
Simulation time 11067876029 ps
CPU time 450.39 seconds
Started Jun 22 05:02:52 PM PDT 24
Finished Jun 22 05:10:23 PM PDT 24
Peak memory 248780 kb
Host smart-aac87372-a391-4383-830e-34a4da9060cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200085600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.200085600
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3698938209
Short name T150
Test name
Test status
Simulation time 55223448735 ps
CPU time 289.89 seconds
Started Jun 22 04:54:47 PM PDT 24
Finished Jun 22 04:59:38 PM PDT 24
Peak memory 265696 kb
Host smart-e79877fe-b4ac-4c5f-b1d2-be7b0fec0c3f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3698938209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3698938209
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1832904448
Short name T201
Test name
Test status
Simulation time 55963983 ps
CPU time 4.34 seconds
Started Jun 22 04:54:56 PM PDT 24
Finished Jun 22 04:55:02 PM PDT 24
Peak memory 237436 kb
Host smart-e5c66d35-260a-472d-a662-63ca45e7ce97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1832904448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1832904448
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.2216008178
Short name T252
Test name
Test status
Simulation time 78509658724 ps
CPU time 2870.11 seconds
Started Jun 22 05:02:31 PM PDT 24
Finished Jun 22 05:50:23 PM PDT 24
Peak memory 306264 kb
Host smart-79202489-3983-4a31-9015-aef8cedac29b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216008178 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.2216008178
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3425783373
Short name T281
Test name
Test status
Simulation time 134076081656 ps
CPU time 1996.46 seconds
Started Jun 22 05:01:48 PM PDT 24
Finished Jun 22 05:35:05 PM PDT 24
Peak memory 267736 kb
Host smart-7f7d6c1f-5cf2-4306-9132-d4d8c32fe2aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425783373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3425783373
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.2150021498
Short name T27
Test name
Test status
Simulation time 81086318355 ps
CPU time 8895.08 seconds
Started Jun 22 05:01:48 PM PDT 24
Finished Jun 22 07:30:06 PM PDT 24
Peak memory 387464 kb
Host smart-850a300c-27ee-4a1e-832d-f589a707113a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150021498 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.2150021498
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3950855629
Short name T147
Test name
Test status
Simulation time 64238327911 ps
CPU time 1064.66 seconds
Started Jun 22 04:55:02 PM PDT 24
Finished Jun 22 05:12:48 PM PDT 24
Peak memory 265628 kb
Host smart-18013084-b8a4-4787-96d1-b5e2a7773f42
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950855629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3950855629
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2714081672
Short name T100
Test name
Test status
Simulation time 41940174607 ps
CPU time 1219.99 seconds
Started Jun 22 05:01:36 PM PDT 24
Finished Jun 22 05:21:57 PM PDT 24
Peak memory 284756 kb
Host smart-64962975-b4f2-4c21-901b-ee4d26a2c704
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714081672 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2714081672
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.699856067
Short name T84
Test name
Test status
Simulation time 87342618765 ps
CPU time 6049.86 seconds
Started Jun 22 05:02:37 PM PDT 24
Finished Jun 22 06:43:27 PM PDT 24
Peak memory 322304 kb
Host smart-d2341565-b9b2-4ed0-959f-eaa7ebe16808
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699856067 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.699856067
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.776554843
Short name T69
Test name
Test status
Simulation time 3567840964 ps
CPU time 197.16 seconds
Started Jun 22 05:03:10 PM PDT 24
Finished Jun 22 05:06:28 PM PDT 24
Peak memory 257360 kb
Host smart-38ae214e-3582-4b97-8d82-a2686e82b495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77655
4843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.776554843
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1853458279
Short name T89
Test name
Test status
Simulation time 37030257033 ps
CPU time 2137.76 seconds
Started Jun 22 05:02:21 PM PDT 24
Finished Jun 22 05:38:00 PM PDT 24
Peak memory 285680 kb
Host smart-24ab5d70-78cb-409e-9f44-829ffe7eb0e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853458279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1853458279
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.54375589
Short name T182
Test name
Test status
Simulation time 2945009130 ps
CPU time 92.98 seconds
Started Jun 22 04:55:00 PM PDT 24
Finished Jun 22 04:56:34 PM PDT 24
Peak memory 257432 kb
Host smart-660b6d61-4530-49f9-a77c-d94c06a10eb1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=54375589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_error
s.54375589
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.545799795
Short name T160
Test name
Test status
Simulation time 2868841299 ps
CPU time 343.83 seconds
Started Jun 22 04:55:02 PM PDT 24
Finished Jun 22 05:00:47 PM PDT 24
Peak memory 269948 kb
Host smart-9e07b8c2-dbfa-4f81-84bb-6be7bc70c52f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545799795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.545799795
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3322974456
Short name T234
Test name
Test status
Simulation time 14178254 ps
CPU time 2.33 seconds
Started Jun 22 05:01:48 PM PDT 24
Finished Jun 22 05:01:51 PM PDT 24
Peak memory 249256 kb
Host smart-f80e85a9-d065-439f-9889-99073c5a5d80
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3322974456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3322974456
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3557594300
Short name T228
Test name
Test status
Simulation time 39517635 ps
CPU time 3.39 seconds
Started Jun 22 05:01:59 PM PDT 24
Finished Jun 22 05:02:08 PM PDT 24
Peak memory 249264 kb
Host smart-23f809ea-2ad3-41f5-81ed-032e651b9072
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3557594300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3557594300
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.564296203
Short name T236
Test name
Test status
Simulation time 39741755 ps
CPU time 3.45 seconds
Started Jun 22 05:02:10 PM PDT 24
Finished Jun 22 05:02:14 PM PDT 24
Peak memory 249144 kb
Host smart-13c776a6-7646-4687-a236-6e390c0ea5c4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=564296203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.564296203
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2125195797
Short name T237
Test name
Test status
Simulation time 85663696 ps
CPU time 3.8 seconds
Started Jun 22 05:02:07 PM PDT 24
Finished Jun 22 05:02:11 PM PDT 24
Peak memory 249184 kb
Host smart-007242e4-df6f-4052-8209-a6749aec3a0d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2125195797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2125195797
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.396898822
Short name T321
Test name
Test status
Simulation time 11405637962 ps
CPU time 442.93 seconds
Started Jun 22 05:01:52 PM PDT 24
Finished Jun 22 05:09:16 PM PDT 24
Peak memory 248304 kb
Host smart-b9fcbb02-73cb-4eb8-8db3-3484b8d54795
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396898822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.396898822
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.1603484354
Short name T95
Test name
Test status
Simulation time 152388420647 ps
CPU time 4754.45 seconds
Started Jun 22 05:02:16 PM PDT 24
Finished Jun 22 06:21:32 PM PDT 24
Peak memory 319008 kb
Host smart-265fa998-76c1-4b0e-a1a9-f4265106f673
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603484354 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.1603484354
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1904209441
Short name T113
Test name
Test status
Simulation time 29937083753 ps
CPU time 2136.66 seconds
Started Jun 22 05:02:16 PM PDT 24
Finished Jun 22 05:37:54 PM PDT 24
Peak memory 286288 kb
Host smart-dad2be25-985a-4fa9-9307-d41fb56fe4d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904209441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1904209441
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2996316968
Short name T330
Test name
Test status
Simulation time 234600086225 ps
CPU time 3434.56 seconds
Started Jun 22 05:02:29 PM PDT 24
Finished Jun 22 05:59:45 PM PDT 24
Peak memory 289752 kb
Host smart-7f5762aa-c51d-4fc2-b4a6-80cbc0656905
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996316968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2996316968
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.118402551
Short name T283
Test name
Test status
Simulation time 19610793335 ps
CPU time 1918.84 seconds
Started Jun 22 05:03:02 PM PDT 24
Finished Jun 22 05:35:01 PM PDT 24
Peak memory 289624 kb
Host smart-b8501dff-9d96-41b9-a75a-0deccdb4caf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118402551 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.118402551
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.811948348
Short name T203
Test name
Test status
Simulation time 60574168 ps
CPU time 2.8 seconds
Started Jun 22 04:54:44 PM PDT 24
Finished Jun 22 04:54:47 PM PDT 24
Peak memory 237432 kb
Host smart-e3389b9b-7a12-4384-b477-bcf233913173
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=811948348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.811948348
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2951176876
Short name T178
Test name
Test status
Simulation time 4373087861 ps
CPU time 277.66 seconds
Started Jun 22 04:55:02 PM PDT 24
Finished Jun 22 04:59:41 PM PDT 24
Peak memory 270008 kb
Host smart-3ccdede5-eaa8-4541-90e6-f81365f048ed
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951176876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2951176876
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3918600003
Short name T155
Test name
Test status
Simulation time 10695456983 ps
CPU time 172.68 seconds
Started Jun 22 04:54:54 PM PDT 24
Finished Jun 22 04:57:48 PM PDT 24
Peak memory 265536 kb
Host smart-f17337e5-6691-494b-a79f-c7dd2ffdd6cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3918600003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3918600003
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.399417241
Short name T18
Test name
Test status
Simulation time 81291941922 ps
CPU time 1204.46 seconds
Started Jun 22 05:01:58 PM PDT 24
Finished Jun 22 05:22:04 PM PDT 24
Peak memory 290196 kb
Host smart-0edb8f5f-eef3-4157-9c85-dbba71b46079
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399417241 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.399417241
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1570848313
Short name T748
Test name
Test status
Simulation time 29293902 ps
CPU time 1.8 seconds
Started Jun 22 04:54:55 PM PDT 24
Finished Jun 22 04:54:58 PM PDT 24
Peak memory 237352 kb
Host smart-b70b19ea-33cf-473c-bb8c-1dc14caf5faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1570848313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1570848313
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1179054109
Short name T270
Test name
Test status
Simulation time 453008160359 ps
CPU time 3250.87 seconds
Started Jun 22 05:01:51 PM PDT 24
Finished Jun 22 05:56:03 PM PDT 24
Peak memory 338524 kb
Host smart-d80ed66d-a5a3-4ed7-98b0-70b608c9db2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179054109 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1179054109
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1573187591
Short name T679
Test name
Test status
Simulation time 83164590488 ps
CPU time 1354.23 seconds
Started Jun 22 05:02:07 PM PDT 24
Finished Jun 22 05:24:43 PM PDT 24
Peak memory 267848 kb
Host smart-94144895-3b20-4eea-9141-69946f7f27e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573187591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1573187591
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1070381672
Short name T301
Test name
Test status
Simulation time 21121939557 ps
CPU time 216.38 seconds
Started Jun 22 05:01:52 PM PDT 24
Finished Jun 22 05:05:29 PM PDT 24
Peak memory 248628 kb
Host smart-c1b5058a-e9de-4cd9-a8c9-ecbda6b660d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070381672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1070381672
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2018790198
Short name T256
Test name
Test status
Simulation time 2167975757 ps
CPU time 66.85 seconds
Started Jun 22 05:02:11 PM PDT 24
Finished Jun 22 05:03:19 PM PDT 24
Peak memory 249388 kb
Host smart-9938af5d-4623-4097-a3d1-2a2acaf2e1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20187
90198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2018790198
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2469825012
Short name T94
Test name
Test status
Simulation time 55660366605 ps
CPU time 6199.02 seconds
Started Jun 22 05:01:44 PM PDT 24
Finished Jun 22 06:45:04 PM PDT 24
Peak memory 354784 kb
Host smart-ab08384d-ae80-4d0c-bb24-8e2deecd0719
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469825012 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2469825012
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3178074416
Short name T312
Test name
Test status
Simulation time 6694027699 ps
CPU time 141 seconds
Started Jun 22 05:02:23 PM PDT 24
Finished Jun 22 05:04:45 PM PDT 24
Peak memory 248680 kb
Host smart-1c8ea1e0-5e9f-482f-a574-ceaec35c0e2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178074416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3178074416
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3798592681
Short name T347
Test name
Test status
Simulation time 34194308260 ps
CPU time 1877.89 seconds
Started Jun 22 05:02:33 PM PDT 24
Finished Jun 22 05:33:52 PM PDT 24
Peak memory 289612 kb
Host smart-f54ad455-896e-425c-9413-a240d2bcab0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798592681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3798592681
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3610856946
Short name T261
Test name
Test status
Simulation time 57839855444 ps
CPU time 2893.6 seconds
Started Jun 22 05:02:32 PM PDT 24
Finished Jun 22 05:50:47 PM PDT 24
Peak memory 289516 kb
Host smart-c2a6db42-9b8c-4880-ae40-3008984284cd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610856946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3610856946
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3704583037
Short name T83
Test name
Test status
Simulation time 498963057 ps
CPU time 15.79 seconds
Started Jun 22 05:02:44 PM PDT 24
Finished Jun 22 05:03:00 PM PDT 24
Peak memory 249108 kb
Host smart-f6cacab8-286e-43f8-b073-8979712d0683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37045
83037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3704583037
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.3068958125
Short name T251
Test name
Test status
Simulation time 11809184119 ps
CPU time 744.59 seconds
Started Jun 22 05:02:45 PM PDT 24
Finished Jun 22 05:15:10 PM PDT 24
Peak memory 267664 kb
Host smart-b8a0248d-2d91-4394-a51c-527d69fca964
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068958125 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.3068958125
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2590346615
Short name T292
Test name
Test status
Simulation time 2068382588 ps
CPU time 120.73 seconds
Started Jun 22 05:02:53 PM PDT 24
Finished Jun 22 05:04:54 PM PDT 24
Peak memory 257236 kb
Host smart-db320cb1-0b49-4a86-a49d-aad38d94c6c9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590346615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2590346615
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.263780651
Short name T253
Test name
Test status
Simulation time 741129551 ps
CPU time 44 seconds
Started Jun 22 05:01:58 PM PDT 24
Finished Jun 22 05:02:43 PM PDT 24
Peak memory 257264 kb
Host smart-3bc16954-2528-46dc-bfd9-80c791408f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26378
0651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.263780651
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1173359012
Short name T109
Test name
Test status
Simulation time 72553963389 ps
CPU time 2065.21 seconds
Started Jun 22 05:02:11 PM PDT 24
Finished Jun 22 05:36:38 PM PDT 24
Peak memory 273720 kb
Host smart-a06f8304-9cfa-405d-9042-502187c0ca07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173359012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1173359012
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.154373692
Short name T651
Test name
Test status
Simulation time 13431219293 ps
CPU time 973 seconds
Started Jun 22 05:02:01 PM PDT 24
Finished Jun 22 05:18:14 PM PDT 24
Peak memory 273008 kb
Host smart-f4d3a821-d45e-4f5e-8ff1-2d37bc63d655
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154373692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.154373692
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1270397632
Short name T164
Test name
Test status
Simulation time 6882804678 ps
CPU time 215.34 seconds
Started Jun 22 04:54:56 PM PDT 24
Finished Jun 22 04:58:33 PM PDT 24
Peak memory 265616 kb
Host smart-7cc0c092-1c2e-45d2-b267-f01d2f31db2d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1270397632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1270397632
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.4237264597
Short name T184
Test name
Test status
Simulation time 2806934271 ps
CPU time 31.67 seconds
Started Jun 22 04:54:56 PM PDT 24
Finished Jun 22 04:55:29 PM PDT 24
Peak memory 240100 kb
Host smart-8a1d0529-92ff-4469-ba54-36c3290079b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4237264597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.4237264597
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3444348702
Short name T190
Test name
Test status
Simulation time 4949784074 ps
CPU time 77.21 seconds
Started Jun 22 04:55:02 PM PDT 24
Finished Jun 22 04:56:20 PM PDT 24
Peak memory 238584 kb
Host smart-90c530d4-d78e-4c63-9361-51a4672268cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3444348702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3444348702
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3748995050
Short name T195
Test name
Test status
Simulation time 469267610 ps
CPU time 31.37 seconds
Started Jun 22 04:54:45 PM PDT 24
Finished Jun 22 04:55:17 PM PDT 24
Peak memory 240660 kb
Host smart-042a89ad-d5f7-4005-903e-84857512bec2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3748995050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3748995050
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.747906763
Short name T199
Test name
Test status
Simulation time 1290264563 ps
CPU time 81.21 seconds
Started Jun 22 04:55:01 PM PDT 24
Finished Jun 22 04:56:24 PM PDT 24
Peak memory 240772 kb
Host smart-92edc9db-7ba8-4d15-a655-981cd1d72520
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=747906763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.747906763
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1444432503
Short name T200
Test name
Test status
Simulation time 470716444 ps
CPU time 34.5 seconds
Started Jun 22 04:55:02 PM PDT 24
Finished Jun 22 04:55:38 PM PDT 24
Peak memory 240788 kb
Host smart-d309545c-4eca-4a8f-83e6-877d7cb09cbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1444432503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1444432503
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1808651973
Short name T167
Test name
Test status
Simulation time 8333412451 ps
CPU time 301.65 seconds
Started Jun 22 04:54:58 PM PDT 24
Finished Jun 22 05:00:01 PM PDT 24
Peak memory 265864 kb
Host smart-c5f9d2df-2374-4e8a-87f4-4e2a50c0389f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1808651973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1808651973
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1440076175
Short name T193
Test name
Test status
Simulation time 62354216 ps
CPU time 4.23 seconds
Started Jun 22 04:54:45 PM PDT 24
Finished Jun 22 04:54:50 PM PDT 24
Peak memory 237388 kb
Host smart-9a7f66b3-bd77-4a29-a28c-0a1a260adc8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1440076175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1440076175
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3585329770
Short name T192
Test name
Test status
Simulation time 39432083 ps
CPU time 3.65 seconds
Started Jun 22 04:54:51 PM PDT 24
Finished Jun 22 04:54:57 PM PDT 24
Peak memory 237344 kb
Host smart-4212023f-e3fb-4eed-90f5-822127be34b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3585329770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3585329770
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.4020899264
Short name T202
Test name
Test status
Simulation time 635837070 ps
CPU time 25.39 seconds
Started Jun 22 04:54:51 PM PDT 24
Finished Jun 22 04:55:18 PM PDT 24
Peak memory 245548 kb
Host smart-57e7de77-b260-4ddd-a73c-21ecb0c99534
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4020899264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.4020899264
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3902460389
Short name T194
Test name
Test status
Simulation time 621693807 ps
CPU time 37.94 seconds
Started Jun 22 04:54:53 PM PDT 24
Finished Jun 22 04:55:33 PM PDT 24
Peak memory 237520 kb
Host smart-45a46674-3003-4750-8a20-ff0bcab45d56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3902460389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3902460389
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3742877949
Short name T198
Test name
Test status
Simulation time 99264244 ps
CPU time 2.46 seconds
Started Jun 22 04:55:00 PM PDT 24
Finished Jun 22 04:55:03 PM PDT 24
Peak memory 236404 kb
Host smart-ee579ebc-3a61-4a1f-b8ec-ebd70924dbbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3742877949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3742877949
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2147878922
Short name T196
Test name
Test status
Simulation time 1074698790 ps
CPU time 22.26 seconds
Started Jun 22 04:55:07 PM PDT 24
Finished Jun 22 04:55:30 PM PDT 24
Peak memory 237452 kb
Host smart-d8aa56ae-7cdd-4218-9903-450609f8c885
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2147878922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2147878922
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1772956719
Short name T197
Test name
Test status
Simulation time 86422504 ps
CPU time 2.31 seconds
Started Jun 22 04:54:45 PM PDT 24
Finished Jun 22 04:54:48 PM PDT 24
Peak memory 237028 kb
Host smart-68e353c0-1a01-4d31-a25d-dbdce0126ace
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1772956719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1772956719
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.4199846953
Short name T191
Test name
Test status
Simulation time 107178546 ps
CPU time 2.69 seconds
Started Jun 22 04:54:53 PM PDT 24
Finished Jun 22 04:54:58 PM PDT 24
Peak memory 237336 kb
Host smart-741a8de1-de10-4fd2-85ac-3aaf2a81b111
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4199846953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.4199846953
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1594317296
Short name T105
Test name
Test status
Simulation time 97730110941 ps
CPU time 3091.91 seconds
Started Jun 22 05:02:12 PM PDT 24
Finished Jun 22 05:53:46 PM PDT 24
Peak memory 306072 kb
Host smart-5525d899-6abe-400a-9e23-0e2244504ae9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594317296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1594317296
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.200372315
Short name T210
Test name
Test status
Simulation time 582481448 ps
CPU time 75.28 seconds
Started Jun 22 04:54:50 PM PDT 24
Finished Jun 22 04:56:08 PM PDT 24
Peak memory 237268 kb
Host smart-f9cef5dc-bb5a-4db8-aacd-81b259e0c62e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=200372315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.200372315
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1552955763
Short name T211
Test name
Test status
Simulation time 3270047618 ps
CPU time 106.17 seconds
Started Jun 22 04:54:48 PM PDT 24
Finished Jun 22 04:56:35 PM PDT 24
Peak memory 237344 kb
Host smart-7a8c3199-8d32-428b-be38-1e95fd73e41b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1552955763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1552955763
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2893495624
Short name T819
Test name
Test status
Simulation time 29346107 ps
CPU time 3.8 seconds
Started Jun 22 04:54:45 PM PDT 24
Finished Jun 22 04:54:50 PM PDT 24
Peak memory 240704 kb
Host smart-1fcd7c3f-0f9b-47f2-a513-382dbb94d2dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2893495624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2893495624
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.526264353
Short name T764
Test name
Test status
Simulation time 171517329 ps
CPU time 11.71 seconds
Started Jun 22 04:54:50 PM PDT 24
Finished Jun 22 04:55:02 PM PDT 24
Peak memory 252700 kb
Host smart-f7de8171-ae08-4a2d-9006-fe93785bc040
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526264353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.526264353
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.4103786591
Short name T753
Test name
Test status
Simulation time 37077188 ps
CPU time 3.54 seconds
Started Jun 22 04:54:50 PM PDT 24
Finished Jun 22 04:54:56 PM PDT 24
Peak memory 237280 kb
Host smart-1c31c3b8-c4a2-4376-aad2-077f6d427d71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4103786591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.4103786591
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3539745670
Short name T745
Test name
Test status
Simulation time 84647743 ps
CPU time 1.39 seconds
Started Jun 22 04:55:07 PM PDT 24
Finished Jun 22 04:55:09 PM PDT 24
Peak memory 237224 kb
Host smart-77e602f0-36c1-4642-b9e0-b5a95160dad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3539745670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3539745670
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.537523106
Short name T774
Test name
Test status
Simulation time 1296632914 ps
CPU time 42.5 seconds
Started Jun 22 04:54:49 PM PDT 24
Finished Jun 22 04:55:32 PM PDT 24
Peak memory 245548 kb
Host smart-af3c4bc8-13c0-4a3c-b466-c57906331bdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=537523106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.537523106
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.291590123
Short name T158
Test name
Test status
Simulation time 7118402976 ps
CPU time 397.57 seconds
Started Jun 22 04:54:51 PM PDT 24
Finished Jun 22 05:01:31 PM PDT 24
Peak memory 265680 kb
Host smart-5cae2dab-9a22-4aa1-810c-1ea074040514
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=291590123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.291590123
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2389875786
Short name T176
Test name
Test status
Simulation time 69305379632 ps
CPU time 1245.12 seconds
Started Jun 22 04:54:50 PM PDT 24
Finished Jun 22 05:15:36 PM PDT 24
Peak memory 265636 kb
Host smart-e3a61f7c-818c-49b7-a17c-cc593b6a8a37
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389875786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2389875786
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3822828975
Short name T740
Test name
Test status
Simulation time 359782976 ps
CPU time 23.46 seconds
Started Jun 22 04:54:51 PM PDT 24
Finished Jun 22 04:55:16 PM PDT 24
Peak memory 248760 kb
Host smart-309bc33e-6ebc-4718-9734-868ee89752a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3822828975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3822828975
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3901491132
Short name T814
Test name
Test status
Simulation time 4281029200 ps
CPU time 294.07 seconds
Started Jun 22 04:54:51 PM PDT 24
Finished Jun 22 04:59:46 PM PDT 24
Peak memory 241548 kb
Host smart-499b2709-bd79-4861-b4f2-fc1df5abd333
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3901491132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3901491132
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1813785490
Short name T363
Test name
Test status
Simulation time 11412719605 ps
CPU time 193.55 seconds
Started Jun 22 04:54:47 PM PDT 24
Finished Jun 22 04:58:02 PM PDT 24
Peak memory 240768 kb
Host smart-86aff340-fb5b-41cd-be5e-4d23a3f22a9d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1813785490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1813785490
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.4239495783
Short name T737
Test name
Test status
Simulation time 37929717 ps
CPU time 5.81 seconds
Started Jun 22 04:54:50 PM PDT 24
Finished Jun 22 04:54:57 PM PDT 24
Peak memory 240708 kb
Host smart-0faed81b-fa93-480c-8b8c-b90d43aea337
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4239495783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.4239495783
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.4257567041
Short name T833
Test name
Test status
Simulation time 60215611 ps
CPU time 9.52 seconds
Started Jun 22 04:54:48 PM PDT 24
Finished Jun 22 04:54:59 PM PDT 24
Peak memory 252088 kb
Host smart-284c2081-7d0b-4564-999b-977202fb0fa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257567041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.4257567041
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1478775986
Short name T773
Test name
Test status
Simulation time 920225168 ps
CPU time 4.61 seconds
Started Jun 22 04:54:52 PM PDT 24
Finished Jun 22 04:54:59 PM PDT 24
Peak memory 237140 kb
Host smart-2ea7b39c-dfa8-4bd2-95be-0585d7c38e6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1478775986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1478775986
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3825484602
Short name T247
Test name
Test status
Simulation time 9532781 ps
CPU time 1.53 seconds
Started Jun 22 04:54:50 PM PDT 24
Finished Jun 22 04:54:52 PM PDT 24
Peak memory 237264 kb
Host smart-89f0b8ae-4873-4db8-9f48-484bd8f0d131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3825484602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3825484602
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1151468311
Short name T213
Test name
Test status
Simulation time 2431108654 ps
CPU time 24.03 seconds
Started Jun 22 04:54:49 PM PDT 24
Finished Jun 22 04:55:14 PM PDT 24
Peak memory 245492 kb
Host smart-c36318ef-1b5e-43ae-8193-1ecc14c40dc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1151468311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1151468311
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1594267254
Short name T175
Test name
Test status
Simulation time 13123164427 ps
CPU time 323.05 seconds
Started Jun 22 04:54:50 PM PDT 24
Finished Jun 22 05:00:15 PM PDT 24
Peak memory 265772 kb
Host smart-7a4e589c-d5d5-448c-abdf-ab156cc36798
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594267254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1594267254
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.488500480
Short name T744
Test name
Test status
Simulation time 648782677 ps
CPU time 10.95 seconds
Started Jun 22 04:54:50 PM PDT 24
Finished Jun 22 04:55:01 PM PDT 24
Peak memory 249024 kb
Host smart-b1a11b54-9608-4c70-8ca3-fe143844eac2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=488500480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.488500480
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2248345471
Short name T810
Test name
Test status
Simulation time 125060611 ps
CPU time 8.57 seconds
Started Jun 22 04:54:56 PM PDT 24
Finished Jun 22 04:55:06 PM PDT 24
Peak memory 252828 kb
Host smart-bc3ea3db-882d-42ad-bead-d2dd838bc0b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248345471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2248345471
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3670339985
Short name T829
Test name
Test status
Simulation time 164411377 ps
CPU time 3.31 seconds
Started Jun 22 04:54:59 PM PDT 24
Finished Jun 22 04:55:03 PM PDT 24
Peak memory 236340 kb
Host smart-45472edd-2dcd-4408-b124-4cc4b93c07b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3670339985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3670339985
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2590510258
Short name T811
Test name
Test status
Simulation time 13791551 ps
CPU time 1.47 seconds
Started Jun 22 04:54:55 PM PDT 24
Finished Jun 22 04:54:58 PM PDT 24
Peak memory 236384 kb
Host smart-d7bdec68-6421-4417-aa9c-85fd6d48d820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2590510258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2590510258
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2037676392
Short name T779
Test name
Test status
Simulation time 592531748 ps
CPU time 38.85 seconds
Started Jun 22 04:54:53 PM PDT 24
Finished Jun 22 04:55:34 PM PDT 24
Peak memory 245448 kb
Host smart-d1104527-acf6-42bf-8d0d-cbe62c05d2b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2037676392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2037676392
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.4243608974
Short name T149
Test name
Test status
Simulation time 901006345 ps
CPU time 112.74 seconds
Started Jun 22 04:54:52 PM PDT 24
Finished Jun 22 04:56:48 PM PDT 24
Peak memory 265516 kb
Host smart-3133ade6-38aa-4119-8feb-e2e96a8eeeef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4243608974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.4243608974
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.969991648
Short name T166
Test name
Test status
Simulation time 11693886593 ps
CPU time 530.55 seconds
Started Jun 22 04:54:58 PM PDT 24
Finished Jun 22 05:03:49 PM PDT 24
Peak memory 265636 kb
Host smart-b10e2bb1-235e-46e2-b449-d58924b00473
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969991648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.969991648
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1609150832
Short name T771
Test name
Test status
Simulation time 57139511 ps
CPU time 4.01 seconds
Started Jun 22 04:54:50 PM PDT 24
Finished Jun 22 04:54:56 PM PDT 24
Peak memory 249032 kb
Host smart-46eaa191-78fc-4a8e-bb22-84457fccc659
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1609150832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1609150832
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.153493397
Short name T783
Test name
Test status
Simulation time 73267796 ps
CPU time 6.22 seconds
Started Jun 22 04:54:53 PM PDT 24
Finished Jun 22 04:55:01 PM PDT 24
Peak memory 239340 kb
Host smart-be367a47-ae9f-4a0a-8958-4a18922f8172
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153493397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.alert_handler_csr_mem_rw_with_rand_reset.153493397
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.128837140
Short name T361
Test name
Test status
Simulation time 95012627 ps
CPU time 7.14 seconds
Started Jun 22 04:54:54 PM PDT 24
Finished Jun 22 04:55:03 PM PDT 24
Peak memory 240640 kb
Host smart-ad3f81f4-1253-474e-9464-6d2731779958
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=128837140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.128837140
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3479714490
Short name T750
Test name
Test status
Simulation time 349074891 ps
CPU time 21.39 seconds
Started Jun 22 04:54:55 PM PDT 24
Finished Jun 22 04:55:18 PM PDT 24
Peak memory 245548 kb
Host smart-962643cb-d60b-4f43-8c1c-35569017fd6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3479714490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3479714490
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.74377737
Short name T736
Test name
Test status
Simulation time 395197106 ps
CPU time 11.81 seconds
Started Jun 22 04:54:52 PM PDT 24
Finished Jun 22 04:55:06 PM PDT 24
Peak memory 248164 kb
Host smart-8b61eca7-39ba-43f9-8da4-d724d6e58e04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=74377737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.74377737
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2652612873
Short name T734
Test name
Test status
Simulation time 515086423 ps
CPU time 9.09 seconds
Started Jun 22 04:55:00 PM PDT 24
Finished Jun 22 04:55:09 PM PDT 24
Peak memory 239996 kb
Host smart-20e999d6-4288-4992-9d47-8516fcf54561
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652612873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2652612873
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3359573617
Short name T761
Test name
Test status
Simulation time 72286827 ps
CPU time 4.91 seconds
Started Jun 22 04:54:59 PM PDT 24
Finished Jun 22 04:55:05 PM PDT 24
Peak memory 236344 kb
Host smart-b5695179-2a4a-475a-bb89-afae752abe6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3359573617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3359573617
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1380496395
Short name T356
Test name
Test status
Simulation time 15679930 ps
CPU time 1.4 seconds
Started Jun 22 04:55:00 PM PDT 24
Finished Jun 22 04:55:02 PM PDT 24
Peak memory 235400 kb
Host smart-c30d9bbe-4e2f-418f-b8db-f5ee37d08525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1380496395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1380496395
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.50240895
Short name T821
Test name
Test status
Simulation time 177107007 ps
CPU time 23.72 seconds
Started Jun 22 04:55:02 PM PDT 24
Finished Jun 22 04:55:27 PM PDT 24
Peak memory 245560 kb
Host smart-9292f1e6-6b5b-4a0a-9447-d7c2c0e2d148
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=50240895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_outs
tanding.50240895
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.16019352
Short name T165
Test name
Test status
Simulation time 6152919738 ps
CPU time 456.7 seconds
Started Jun 22 04:54:58 PM PDT 24
Finished Jun 22 05:02:36 PM PDT 24
Peak memory 265640 kb
Host smart-ee61f1b4-057f-4219-9b65-c79a2d5dfb6c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16019352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.16019352
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3639936539
Short name T788
Test name
Test status
Simulation time 211644793 ps
CPU time 13.61 seconds
Started Jun 22 04:54:58 PM PDT 24
Finished Jun 22 04:55:12 PM PDT 24
Peak memory 249032 kb
Host smart-5f687fb9-9f60-4fa9-b5de-6b14cbfb4be6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3639936539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3639936539
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.4172025132
Short name T735
Test name
Test status
Simulation time 323302444 ps
CPU time 6.51 seconds
Started Jun 22 04:54:58 PM PDT 24
Finished Jun 22 04:55:05 PM PDT 24
Peak memory 240724 kb
Host smart-e8855935-319c-4248-affd-c912152009e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172025132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.4172025132
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1083386776
Short name T802
Test name
Test status
Simulation time 92508298 ps
CPU time 4.13 seconds
Started Jun 22 04:55:06 PM PDT 24
Finished Jun 22 04:55:10 PM PDT 24
Peak memory 236344 kb
Host smart-0bf88922-87b1-4aec-9b63-8df45f9a6fcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1083386776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1083386776
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.845010435
Short name T731
Test name
Test status
Simulation time 24959393 ps
CPU time 1.26 seconds
Started Jun 22 04:54:59 PM PDT 24
Finished Jun 22 04:55:01 PM PDT 24
Peak memory 237188 kb
Host smart-7f37268d-a0b1-4514-9e3d-850d66e20e02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=845010435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.845010435
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1320958260
Short name T217
Test name
Test status
Simulation time 655491776 ps
CPU time 21.53 seconds
Started Jun 22 04:55:02 PM PDT 24
Finished Jun 22 04:55:25 PM PDT 24
Peak memory 245536 kb
Host smart-4007b6a9-ef9b-42d9-8376-279db141a583
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1320958260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1320958260
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2072424442
Short name T173
Test name
Test status
Simulation time 1658522017 ps
CPU time 94.01 seconds
Started Jun 22 04:55:02 PM PDT 24
Finished Jun 22 04:56:37 PM PDT 24
Peak memory 265636 kb
Host smart-42d9f399-320a-4fe4-87cb-8201ac3ea39f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2072424442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2072424442
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.610725100
Short name T797
Test name
Test status
Simulation time 1134872687 ps
CPU time 21.33 seconds
Started Jun 22 04:55:02 PM PDT 24
Finished Jun 22 04:55:25 PM PDT 24
Peak memory 248860 kb
Host smart-570b9224-f304-4bc4-a9da-5fac3800c8ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=610725100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.610725100
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3769058488
Short name T206
Test name
Test status
Simulation time 530457161 ps
CPU time 9.69 seconds
Started Jun 22 04:55:01 PM PDT 24
Finished Jun 22 04:55:11 PM PDT 24
Peak memory 240804 kb
Host smart-f46460ae-2431-4034-a391-c966db17c23e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769058488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3769058488
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.423093142
Short name T214
Test name
Test status
Simulation time 35112756 ps
CPU time 3.09 seconds
Started Jun 22 04:55:02 PM PDT 24
Finished Jun 22 04:55:07 PM PDT 24
Peak memory 236348 kb
Host smart-0ec2bd37-1aaf-4c3a-a90d-090b301e2604
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=423093142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.423093142
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.4215172209
Short name T359
Test name
Test status
Simulation time 11158801 ps
CPU time 1.32 seconds
Started Jun 22 04:55:04 PM PDT 24
Finished Jun 22 04:55:05 PM PDT 24
Peak memory 237364 kb
Host smart-2947e7d8-9e57-4d7f-8934-e5c5439bf4a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4215172209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.4215172209
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3369573060
Short name T770
Test name
Test status
Simulation time 496421016 ps
CPU time 18.22 seconds
Started Jun 22 04:55:02 PM PDT 24
Finished Jun 22 04:55:22 PM PDT 24
Peak memory 240708 kb
Host smart-4fb27978-f4a7-437b-bffb-030a6649d85f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3369573060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3369573060
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2238439311
Short name T787
Test name
Test status
Simulation time 698622728 ps
CPU time 13.17 seconds
Started Jun 22 04:54:59 PM PDT 24
Finished Jun 22 04:55:13 PM PDT 24
Peak memory 248180 kb
Host smart-a8fe7b4b-13c1-41f8-8c2a-61f7c644df22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2238439311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2238439311
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3009819137
Short name T762
Test name
Test status
Simulation time 622134135 ps
CPU time 40.02 seconds
Started Jun 22 04:54:58 PM PDT 24
Finished Jun 22 04:55:38 PM PDT 24
Peak memory 240776 kb
Host smart-d67eea85-1b17-4e6d-b263-ce121af9fdf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3009819137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3009819137
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3848362510
Short name T766
Test name
Test status
Simulation time 108297384 ps
CPU time 4.73 seconds
Started Jun 22 04:56:06 PM PDT 24
Finished Jun 22 04:56:13 PM PDT 24
Peak memory 242476 kb
Host smart-c1425f75-f118-4588-9746-e69e1ebb0aba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848362510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3848362510
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.17915639
Short name T782
Test name
Test status
Simulation time 52364669 ps
CPU time 4.79 seconds
Started Jun 22 04:55:02 PM PDT 24
Finished Jun 22 04:55:08 PM PDT 24
Peak memory 237184 kb
Host smart-4e31f450-9245-4e12-b282-c3fcdbc20299
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=17915639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.17915639
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2265506441
Short name T765
Test name
Test status
Simulation time 29975882 ps
CPU time 1.41 seconds
Started Jun 22 04:55:03 PM PDT 24
Finished Jun 22 04:55:05 PM PDT 24
Peak memory 237352 kb
Host smart-a3c41c54-bd7f-49f3-8b1b-c0ec0882f05f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2265506441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2265506441
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2424563430
Short name T834
Test name
Test status
Simulation time 522245366 ps
CPU time 22.07 seconds
Started Jun 22 04:54:59 PM PDT 24
Finished Jun 22 04:55:22 PM PDT 24
Peak memory 248872 kb
Host smart-a1bd90c2-9aab-447f-b8e3-d8e07bdd372b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2424563430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2424563430
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3592508490
Short name T177
Test name
Test status
Simulation time 8932532086 ps
CPU time 622.96 seconds
Started Jun 22 04:54:57 PM PDT 24
Finished Jun 22 05:05:21 PM PDT 24
Peak memory 265784 kb
Host smart-98a053d6-bbcd-4986-9dc6-c0ff6b8dc1e1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592508490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3592508490
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.226849568
Short name T718
Test name
Test status
Simulation time 491985594 ps
CPU time 15.26 seconds
Started Jun 22 04:55:02 PM PDT 24
Finished Jun 22 04:55:19 PM PDT 24
Peak memory 248204 kb
Host smart-1c381438-d83c-4c70-aece-bd3953fcd5d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=226849568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.226849568
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3465877869
Short name T186
Test name
Test status
Simulation time 48167217 ps
CPU time 2.78 seconds
Started Jun 22 04:55:04 PM PDT 24
Finished Jun 22 04:55:08 PM PDT 24
Peak memory 237352 kb
Host smart-779cfe5a-65f1-469f-bf04-641aa49e89e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3465877869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3465877869
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.4014975445
Short name T360
Test name
Test status
Simulation time 33855132 ps
CPU time 5.54 seconds
Started Jun 22 04:55:02 PM PDT 24
Finished Jun 22 04:55:09 PM PDT 24
Peak memory 256796 kb
Host smart-60c00b4d-b10f-455d-9020-6ddb3f4ea985
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014975445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.4014975445
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.607984444
Short name T747
Test name
Test status
Simulation time 61623392 ps
CPU time 5.64 seconds
Started Jun 22 04:54:58 PM PDT 24
Finished Jun 22 04:55:04 PM PDT 24
Peak memory 237184 kb
Host smart-28f82168-ed42-42db-a36a-f920a366abfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=607984444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.607984444
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2738082262
Short name T768
Test name
Test status
Simulation time 11974883 ps
CPU time 1.4 seconds
Started Jun 22 04:55:05 PM PDT 24
Finished Jun 22 04:55:06 PM PDT 24
Peak memory 237364 kb
Host smart-bb80871e-ff0d-4449-aaed-f10ab54d086f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2738082262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2738082262
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1935689177
Short name T215
Test name
Test status
Simulation time 524191390 ps
CPU time 36.32 seconds
Started Jun 22 04:55:00 PM PDT 24
Finished Jun 22 04:55:37 PM PDT 24
Peak memory 245496 kb
Host smart-8ed6b544-44e7-41ec-80a1-de3e8bf08134
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1935689177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1935689177
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3812641113
Short name T162
Test name
Test status
Simulation time 2461286200 ps
CPU time 102.64 seconds
Started Jun 22 04:55:03 PM PDT 24
Finished Jun 22 04:56:46 PM PDT 24
Peak memory 257496 kb
Host smart-2e7593db-cd72-4716-bb00-10ff4cc9c434
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3812641113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3812641113
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2398680696
Short name T726
Test name
Test status
Simulation time 21955509 ps
CPU time 3.52 seconds
Started Jun 22 04:54:59 PM PDT 24
Finished Jun 22 04:55:04 PM PDT 24
Peak memory 240776 kb
Host smart-dcadc88b-72dd-4435-b9c2-86b7153bcbe0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2398680696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2398680696
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1896939813
Short name T822
Test name
Test status
Simulation time 38538522 ps
CPU time 5.75 seconds
Started Jun 22 04:55:00 PM PDT 24
Finished Jun 22 04:55:07 PM PDT 24
Peak memory 240812 kb
Host smart-d8ef1539-ce1a-452d-9344-e248e5b1a364
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896939813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1896939813
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3979635727
Short name T831
Test name
Test status
Simulation time 49048658 ps
CPU time 4.88 seconds
Started Jun 22 04:55:02 PM PDT 24
Finished Jun 22 04:55:08 PM PDT 24
Peak memory 237280 kb
Host smart-612920de-0f01-4cf6-b376-327bb9df525d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3979635727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3979635727
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2285179999
Short name T355
Test name
Test status
Simulation time 11290094 ps
CPU time 1.52 seconds
Started Jun 22 04:55:06 PM PDT 24
Finished Jun 22 04:55:08 PM PDT 24
Peak memory 237360 kb
Host smart-2dc54f08-19e4-4416-ab8b-211c8a4fe7cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2285179999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2285179999
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1901848601
Short name T216
Test name
Test status
Simulation time 171310842 ps
CPU time 22.71 seconds
Started Jun 22 04:54:57 PM PDT 24
Finished Jun 22 04:55:21 PM PDT 24
Peak memory 245448 kb
Host smart-607e6bef-e295-48ea-9246-e61165bd3bdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1901848601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1901848601
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.483134054
Short name T732
Test name
Test status
Simulation time 121294398 ps
CPU time 7.9 seconds
Started Jun 22 04:55:01 PM PDT 24
Finished Jun 22 04:55:10 PM PDT 24
Peak memory 248196 kb
Host smart-69809c4f-f66e-4f36-a3d9-1f78164618fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=483134054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.483134054
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.666393604
Short name T218
Test name
Test status
Simulation time 66808865 ps
CPU time 2.54 seconds
Started Jun 22 04:54:58 PM PDT 24
Finished Jun 22 04:55:01 PM PDT 24
Peak memory 237828 kb
Host smart-e421299a-fbf9-449b-92ae-21add20aab06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=666393604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.666393604
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2325640708
Short name T795
Test name
Test status
Simulation time 70747353 ps
CPU time 6.01 seconds
Started Jun 22 04:55:18 PM PDT 24
Finished Jun 22 04:55:24 PM PDT 24
Peak memory 238416 kb
Host smart-f89ec9bc-361c-40e0-a3c2-34d4b806fc88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325640708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2325640708
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1059216595
Short name T755
Test name
Test status
Simulation time 234636339 ps
CPU time 8.72 seconds
Started Jun 22 04:55:05 PM PDT 24
Finished Jun 22 04:55:14 PM PDT 24
Peak memory 240704 kb
Host smart-7f0e6253-adda-4634-9d92-0c5442ef4e3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1059216595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1059216595
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3262016666
Short name T828
Test name
Test status
Simulation time 8946385 ps
CPU time 1.45 seconds
Started Jun 22 04:55:06 PM PDT 24
Finished Jun 22 04:55:08 PM PDT 24
Peak memory 237364 kb
Host smart-619093c6-8d63-43d8-be43-c22b633cb4a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3262016666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3262016666
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2563905702
Short name T827
Test name
Test status
Simulation time 510612380 ps
CPU time 18.2 seconds
Started Jun 22 04:55:01 PM PDT 24
Finished Jun 22 04:55:20 PM PDT 24
Peak memory 240724 kb
Host smart-e5a8b5a7-3fdc-46ee-ac9a-729d61b8ca08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2563905702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2563905702
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1407183246
Short name T148
Test name
Test status
Simulation time 1553642925 ps
CPU time 88.43 seconds
Started Jun 22 04:54:58 PM PDT 24
Finished Jun 22 04:56:27 PM PDT 24
Peak memory 266084 kb
Host smart-600e9fb2-fa2e-4db4-a37c-752dd9154d09
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1407183246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1407183246
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.4009428592
Short name T721
Test name
Test status
Simulation time 875612832 ps
CPU time 12.23 seconds
Started Jun 22 04:55:01 PM PDT 24
Finished Jun 22 04:55:15 PM PDT 24
Peak memory 248452 kb
Host smart-e32001a3-ceee-4d7a-bd1c-8500eed7363c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4009428592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.4009428592
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.445868088
Short name T730
Test name
Test status
Simulation time 101877632 ps
CPU time 8.07 seconds
Started Jun 22 04:55:05 PM PDT 24
Finished Jun 22 04:55:13 PM PDT 24
Peak memory 244252 kb
Host smart-6a01a5b1-8404-47c8-a6f2-e95b2106019f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445868088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.445868088
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.964726036
Short name T738
Test name
Test status
Simulation time 63104338 ps
CPU time 3.44 seconds
Started Jun 22 04:55:08 PM PDT 24
Finished Jun 22 04:55:13 PM PDT 24
Peak memory 237280 kb
Host smart-4ac115cb-4d90-47ff-9c18-e262c30cfee7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=964726036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.964726036
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.177309295
Short name T804
Test name
Test status
Simulation time 10665641 ps
CPU time 1.25 seconds
Started Jun 22 04:55:07 PM PDT 24
Finished Jun 22 04:55:09 PM PDT 24
Peak memory 235312 kb
Host smart-5a5a01a0-0052-4131-83f1-3c65c9c28ed3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=177309295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.177309295
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.592295368
Short name T816
Test name
Test status
Simulation time 555028848 ps
CPU time 18.37 seconds
Started Jun 22 04:55:05 PM PDT 24
Finished Jun 22 04:55:24 PM PDT 24
Peak memory 244520 kb
Host smart-77f97029-cc84-4bd5-b46d-0d92bdebe041
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=592295368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.592295368
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.4040460895
Short name T183
Test name
Test status
Simulation time 31947298482 ps
CPU time 532.84 seconds
Started Jun 22 04:55:06 PM PDT 24
Finished Jun 22 05:03:59 PM PDT 24
Peak memory 265556 kb
Host smart-e2a705cf-f4d4-4416-a132-f03882e781d5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040460895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.4040460895
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2397583979
Short name T776
Test name
Test status
Simulation time 1952416203 ps
CPU time 20.25 seconds
Started Jun 22 04:55:06 PM PDT 24
Finished Jun 22 04:55:27 PM PDT 24
Peak memory 246360 kb
Host smart-e32ece4e-5cd8-4148-acc3-65be7c32c98b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2397583979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2397583979
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1833756726
Short name T812
Test name
Test status
Simulation time 2189369129 ps
CPU time 144.35 seconds
Started Jun 22 04:54:50 PM PDT 24
Finished Jun 22 04:57:17 PM PDT 24
Peak memory 240772 kb
Host smart-ff0c1b6e-76d0-4392-aeae-c795e5610cd6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1833756726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1833756726
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3271861348
Short name T837
Test name
Test status
Simulation time 23782248115 ps
CPU time 339.83 seconds
Started Jun 22 04:54:51 PM PDT 24
Finished Jun 22 05:00:32 PM PDT 24
Peak memory 240172 kb
Host smart-9262266c-4cc7-4af2-9d16-f9beb4397c20
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3271861348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3271861348
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1034960734
Short name T798
Test name
Test status
Simulation time 39270342 ps
CPU time 6.53 seconds
Started Jun 22 04:54:51 PM PDT 24
Finished Jun 22 04:54:59 PM PDT 24
Peak memory 240776 kb
Host smart-b2093d76-7698-4007-a728-e0ed66ab0aa8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1034960734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1034960734
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.344948959
Short name T826
Test name
Test status
Simulation time 940070969 ps
CPU time 7.21 seconds
Started Jun 22 04:54:52 PM PDT 24
Finished Jun 22 04:55:01 PM PDT 24
Peak memory 240900 kb
Host smart-524bc646-c174-4ba1-b2d9-bc7483435d0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344948959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.alert_handler_csr_mem_rw_with_rand_reset.344948959
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3344212717
Short name T742
Test name
Test status
Simulation time 97751066 ps
CPU time 7.94 seconds
Started Jun 22 04:54:50 PM PDT 24
Finished Jun 22 04:54:59 PM PDT 24
Peak memory 237280 kb
Host smart-6c3a94fc-d8a2-45b5-980c-ddfac1f1ab52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3344212717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3344212717
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.449060710
Short name T763
Test name
Test status
Simulation time 11601876 ps
CPU time 1.43 seconds
Started Jun 22 04:54:43 PM PDT 24
Finished Jun 22 04:54:45 PM PDT 24
Peak memory 236256 kb
Host smart-2b7a8088-d172-42f3-9dcc-3fd81d7ba998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=449060710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.449060710
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1679535133
Short name T780
Test name
Test status
Simulation time 1480797051 ps
CPU time 23.73 seconds
Started Jun 22 04:54:42 PM PDT 24
Finished Jun 22 04:55:06 PM PDT 24
Peak memory 245552 kb
Host smart-4bf2cecd-284b-4b5d-b596-c60056975f25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1679535133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1679535133
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2599800943
Short name T169
Test name
Test status
Simulation time 7199464181 ps
CPU time 471.25 seconds
Started Jun 22 04:54:48 PM PDT 24
Finished Jun 22 05:02:40 PM PDT 24
Peak memory 273172 kb
Host smart-bb96ff0f-4ce6-4a2e-88cd-28e4bdfef139
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599800943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2599800943
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1768663592
Short name T739
Test name
Test status
Simulation time 193228085 ps
CPU time 7.35 seconds
Started Jun 22 04:54:46 PM PDT 24
Finished Jun 22 04:54:54 PM PDT 24
Peak memory 249032 kb
Host smart-c9f68f52-b6ab-4596-9317-bb2a5326b08d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1768663592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1768663592
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.4192913364
Short name T187
Test name
Test status
Simulation time 11881584 ps
CPU time 1.3 seconds
Started Jun 22 04:55:08 PM PDT 24
Finished Jun 22 04:55:10 PM PDT 24
Peak memory 237364 kb
Host smart-6da1449a-88be-4589-b752-c2f9289bac5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4192913364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.4192913364
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1332711723
Short name T815
Test name
Test status
Simulation time 17179851 ps
CPU time 1.4 seconds
Started Jun 22 04:55:08 PM PDT 24
Finished Jun 22 04:55:11 PM PDT 24
Peak memory 235516 kb
Host smart-f7cebe75-06b6-40fd-ba28-3de80c78c4b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1332711723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1332711723
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3884607996
Short name T786
Test name
Test status
Simulation time 9532429 ps
CPU time 1.42 seconds
Started Jun 22 04:55:07 PM PDT 24
Finished Jun 22 04:55:10 PM PDT 24
Peak memory 235368 kb
Host smart-39ea5787-4e7f-4a86-bbae-8a29c8779730
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3884607996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3884607996
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1916808343
Short name T746
Test name
Test status
Simulation time 6268147 ps
CPU time 1.38 seconds
Started Jun 22 04:55:08 PM PDT 24
Finished Jun 22 04:55:11 PM PDT 24
Peak memory 235412 kb
Host smart-ad5fb85f-43eb-4b14-9e44-1014749413ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1916808343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1916808343
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3382134986
Short name T358
Test name
Test status
Simulation time 24243866 ps
CPU time 1.38 seconds
Started Jun 22 04:55:12 PM PDT 24
Finished Jun 22 04:55:14 PM PDT 24
Peak memory 236436 kb
Host smart-c9d5f269-e0ef-487b-ac57-2504fe91e520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3382134986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3382134986
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3858529402
Short name T752
Test name
Test status
Simulation time 8938056 ps
CPU time 1.59 seconds
Started Jun 22 04:55:07 PM PDT 24
Finished Jun 22 04:55:10 PM PDT 24
Peak memory 236436 kb
Host smart-711028c1-c91c-447c-a4a2-bc3f212d2f5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3858529402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3858529402
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3332866635
Short name T792
Test name
Test status
Simulation time 8007485 ps
CPU time 1.32 seconds
Started Jun 22 04:55:11 PM PDT 24
Finished Jun 22 04:55:13 PM PDT 24
Peak memory 237332 kb
Host smart-d5174b9a-0cd9-4a6f-a931-2df402f6099a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3332866635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3332866635
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1210729563
Short name T803
Test name
Test status
Simulation time 6377572 ps
CPU time 1.33 seconds
Started Jun 22 04:55:07 PM PDT 24
Finished Jun 22 04:55:10 PM PDT 24
Peak memory 235264 kb
Host smart-ec5c7347-212c-478a-9fd5-68c0323dbd24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1210729563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1210729563
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3632794207
Short name T790
Test name
Test status
Simulation time 12120345 ps
CPU time 1.43 seconds
Started Jun 22 04:55:07 PM PDT 24
Finished Jun 22 04:55:09 PM PDT 24
Peak memory 237352 kb
Host smart-a3f33de1-945b-48b2-aae1-97ff9f8e3e5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3632794207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3632794207
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.4128050352
Short name T758
Test name
Test status
Simulation time 19008638573 ps
CPU time 314.3 seconds
Started Jun 22 04:54:51 PM PDT 24
Finished Jun 22 05:00:08 PM PDT 24
Peak memory 240736 kb
Host smart-e1bc3f12-5e56-4a07-bc95-7332b627326e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4128050352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.4128050352
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1267858477
Short name T362
Test name
Test status
Simulation time 34236082464 ps
CPU time 500.66 seconds
Started Jun 22 04:54:52 PM PDT 24
Finished Jun 22 05:03:15 PM PDT 24
Peak memory 240648 kb
Host smart-44548195-a448-4bec-8db3-5362b072b71d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1267858477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1267858477
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2001133205
Short name T823
Test name
Test status
Simulation time 51409044 ps
CPU time 5.33 seconds
Started Jun 22 04:54:55 PM PDT 24
Finished Jun 22 04:55:02 PM PDT 24
Peak memory 240708 kb
Host smart-7b19a8a9-a98a-4fed-b6f4-292cb837b497
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2001133205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2001133205
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2944054983
Short name T824
Test name
Test status
Simulation time 659139952 ps
CPU time 8.21 seconds
Started Jun 22 04:54:45 PM PDT 24
Finished Jun 22 04:54:53 PM PDT 24
Peak memory 253620 kb
Host smart-ce3c44c3-ae97-4367-815a-51e2c68203f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944054983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2944054983
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2550580130
Short name T818
Test name
Test status
Simulation time 355084621 ps
CPU time 7.56 seconds
Started Jun 22 04:54:51 PM PDT 24
Finished Jun 22 04:55:01 PM PDT 24
Peak memory 237180 kb
Host smart-f1d6df4b-91e5-4160-b068-bc3153be145d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2550580130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2550580130
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1730927516
Short name T769
Test name
Test status
Simulation time 246657047 ps
CPU time 16.96 seconds
Started Jun 22 04:56:11 PM PDT 24
Finished Jun 22 04:56:28 PM PDT 24
Peak memory 248980 kb
Host smart-d4592501-e523-4c14-9484-029077b61ca7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1730927516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1730927516
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1426746552
Short name T179
Test name
Test status
Simulation time 852272417 ps
CPU time 105.33 seconds
Started Jun 22 04:55:12 PM PDT 24
Finished Jun 22 04:56:57 PM PDT 24
Peak memory 265620 kb
Host smart-3b1fb5ad-0f05-4504-922a-13bb891047c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1426746552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1426746552
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3907296649
Short name T793
Test name
Test status
Simulation time 442155390 ps
CPU time 8.71 seconds
Started Jun 22 04:54:48 PM PDT 24
Finished Jun 22 04:54:57 PM PDT 24
Peak memory 249036 kb
Host smart-5a42945a-b5bb-4f6c-9cf3-c33e163748c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3907296649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3907296649
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2714762590
Short name T756
Test name
Test status
Simulation time 17497806 ps
CPU time 1.35 seconds
Started Jun 22 04:55:07 PM PDT 24
Finished Jun 22 04:55:09 PM PDT 24
Peak memory 236424 kb
Host smart-812bd0e4-583d-4357-9523-bd12ddb4018b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2714762590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2714762590
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1134855018
Short name T189
Test name
Test status
Simulation time 13877844 ps
CPU time 1.4 seconds
Started Jun 22 04:55:09 PM PDT 24
Finished Jun 22 04:55:12 PM PDT 24
Peak memory 235388 kb
Host smart-1a4c5f3b-4e47-415d-8584-14dd2e3cee11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1134855018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1134855018
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1796520241
Short name T767
Test name
Test status
Simulation time 31500208 ps
CPU time 1.44 seconds
Started Jun 22 04:55:07 PM PDT 24
Finished Jun 22 04:55:10 PM PDT 24
Peak memory 237372 kb
Host smart-aed18c87-1b5d-4795-b1d7-fdf0ed6459fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1796520241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1796520241
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2406193178
Short name T741
Test name
Test status
Simulation time 11787569 ps
CPU time 1.61 seconds
Started Jun 22 04:55:09 PM PDT 24
Finished Jun 22 04:55:12 PM PDT 24
Peak memory 237360 kb
Host smart-8e8282ff-32bd-4d5b-afc1-3ef0561e00ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2406193178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2406193178
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3208845428
Short name T728
Test name
Test status
Simulation time 10305900 ps
CPU time 1.3 seconds
Started Jun 22 04:55:06 PM PDT 24
Finished Jun 22 04:55:08 PM PDT 24
Peak memory 236436 kb
Host smart-beff00e7-1226-4544-8e90-549265f4b075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3208845428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3208845428
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2408649581
Short name T353
Test name
Test status
Simulation time 12490710 ps
CPU time 1.68 seconds
Started Jun 22 04:55:07 PM PDT 24
Finished Jun 22 04:55:10 PM PDT 24
Peak memory 237364 kb
Host smart-dac2175c-87b4-4c1d-b9f0-6de37d79d35d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2408649581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2408649581
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3882011272
Short name T835
Test name
Test status
Simulation time 6668502 ps
CPU time 1.48 seconds
Started Jun 22 04:55:07 PM PDT 24
Finished Jun 22 04:55:09 PM PDT 24
Peak memory 237364 kb
Host smart-a0cc4425-cf21-4647-a18e-5de5b7e38626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3882011272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3882011272
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1094905208
Short name T791
Test name
Test status
Simulation time 11346808 ps
CPU time 1.34 seconds
Started Jun 22 04:55:06 PM PDT 24
Finished Jun 22 04:55:08 PM PDT 24
Peak memory 237364 kb
Host smart-bb741e00-22e4-47da-82cb-071705c89b34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1094905208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1094905208
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2855033717
Short name T777
Test name
Test status
Simulation time 15583139 ps
CPU time 1.5 seconds
Started Jun 22 04:55:10 PM PDT 24
Finished Jun 22 04:55:12 PM PDT 24
Peak memory 237344 kb
Host smart-b0f57a1f-89f1-4356-9820-24af659a0ccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2855033717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2855033717
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2687290441
Short name T778
Test name
Test status
Simulation time 7515919 ps
CPU time 1.48 seconds
Started Jun 22 04:55:08 PM PDT 24
Finished Jun 22 04:55:11 PM PDT 24
Peak memory 236420 kb
Host smart-f4fdfecb-941d-4e4d-a1d3-406ac315d23c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2687290441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2687290441
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3232384059
Short name T832
Test name
Test status
Simulation time 2304141036 ps
CPU time 144.52 seconds
Started Jun 22 04:54:55 PM PDT 24
Finished Jun 22 04:57:21 PM PDT 24
Peak memory 237344 kb
Host smart-c32b203a-bafa-4ff9-8029-ac63a137c00e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3232384059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3232384059
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1300203848
Short name T830
Test name
Test status
Simulation time 1639810246 ps
CPU time 204.01 seconds
Started Jun 22 04:54:51 PM PDT 24
Finished Jun 22 04:58:18 PM PDT 24
Peak memory 237184 kb
Host smart-31c8f955-c600-448c-ab6e-d1e40b3db444
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1300203848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1300203848
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.596295903
Short name T836
Test name
Test status
Simulation time 104794454 ps
CPU time 8.27 seconds
Started Jun 22 04:54:47 PM PDT 24
Finished Jun 22 04:54:56 PM PDT 24
Peak memory 240712 kb
Host smart-ce4d4b16-2ece-4ad0-b050-ac01b782ef63
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=596295903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.596295903
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3542090329
Short name T760
Test name
Test status
Simulation time 302229553 ps
CPU time 6.91 seconds
Started Jun 22 04:54:47 PM PDT 24
Finished Jun 22 04:54:54 PM PDT 24
Peak memory 240992 kb
Host smart-55109385-cf4a-4573-b4dc-cc450d6ba2a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542090329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3542090329
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2581900562
Short name T754
Test name
Test status
Simulation time 70472002 ps
CPU time 3.25 seconds
Started Jun 22 04:54:52 PM PDT 24
Finished Jun 22 04:54:58 PM PDT 24
Peak memory 239272 kb
Host smart-041928b1-31e4-44bf-99e2-85a2044e9cc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2581900562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2581900562
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.556833821
Short name T354
Test name
Test status
Simulation time 8766537 ps
CPU time 1.41 seconds
Started Jun 22 04:54:52 PM PDT 24
Finished Jun 22 04:54:56 PM PDT 24
Peak memory 237240 kb
Host smart-f8cb3bd1-636b-426a-a915-64e6efe441ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=556833821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.556833821
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2725805587
Short name T212
Test name
Test status
Simulation time 93097590 ps
CPU time 10.84 seconds
Started Jun 22 04:54:51 PM PDT 24
Finished Jun 22 04:55:03 PM PDT 24
Peak memory 244588 kb
Host smart-8877af4c-8143-45b0-9cf1-edc93f4b2d02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2725805587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2725805587
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3702093502
Short name T168
Test name
Test status
Simulation time 5005473887 ps
CPU time 163.74 seconds
Started Jun 22 04:54:51 PM PDT 24
Finished Jun 22 04:57:37 PM PDT 24
Peak memory 257052 kb
Host smart-ee2e2e1d-aca5-4834-9424-e73abd715bd8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3702093502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3702093502
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1263336748
Short name T180
Test name
Test status
Simulation time 7803628759 ps
CPU time 678.41 seconds
Started Jun 22 04:54:52 PM PDT 24
Finished Jun 22 05:06:12 PM PDT 24
Peak memory 273492 kb
Host smart-7a05b50d-98be-4502-8f3f-d942e3bf2bcf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263336748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1263336748
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.776670153
Short name T719
Test name
Test status
Simulation time 397654033 ps
CPU time 23.99 seconds
Started Jun 22 04:54:52 PM PDT 24
Finished Jun 22 04:55:18 PM PDT 24
Peak memory 249132 kb
Host smart-743d1828-da21-4dbd-989a-1b0b765181ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=776670153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.776670153
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2541601835
Short name T188
Test name
Test status
Simulation time 25932150 ps
CPU time 1.49 seconds
Started Jun 22 04:55:06 PM PDT 24
Finished Jun 22 04:55:09 PM PDT 24
Peak memory 236444 kb
Host smart-d5a70d94-51a7-4f83-892d-5498986b9133
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2541601835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2541601835
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.499731156
Short name T722
Test name
Test status
Simulation time 9855383 ps
CPU time 1.36 seconds
Started Jun 22 04:55:07 PM PDT 24
Finished Jun 22 04:55:09 PM PDT 24
Peak memory 235368 kb
Host smart-79330f94-a94b-412e-aada-57d3e1df507d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=499731156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.499731156
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1885135287
Short name T813
Test name
Test status
Simulation time 12301294 ps
CPU time 1.59 seconds
Started Jun 22 04:55:11 PM PDT 24
Finished Jun 22 04:55:13 PM PDT 24
Peak memory 236404 kb
Host smart-38334e49-56cf-422a-9f21-4cb2ecd77498
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1885135287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1885135287
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3659465089
Short name T825
Test name
Test status
Simulation time 6406107 ps
CPU time 1.41 seconds
Started Jun 22 04:55:08 PM PDT 24
Finished Jun 22 04:55:10 PM PDT 24
Peak memory 237488 kb
Host smart-1f38acbc-b242-4004-8a66-34f673988213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3659465089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3659465089
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1140126714
Short name T772
Test name
Test status
Simulation time 8985958 ps
CPU time 1.45 seconds
Started Jun 22 04:55:10 PM PDT 24
Finished Jun 22 04:55:12 PM PDT 24
Peak memory 235372 kb
Host smart-030788be-15ac-4fe9-bbd3-998c1626bf33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1140126714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1140126714
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.993230118
Short name T809
Test name
Test status
Simulation time 6302669 ps
CPU time 1.37 seconds
Started Jun 22 04:55:11 PM PDT 24
Finished Jun 22 04:55:13 PM PDT 24
Peak memory 237340 kb
Host smart-3adb4c7c-7f4d-4e02-b3e2-995c9e710bc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=993230118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.993230118
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2501720060
Short name T806
Test name
Test status
Simulation time 15002227 ps
CPU time 1.4 seconds
Started Jun 22 04:55:10 PM PDT 24
Finished Jun 22 04:55:12 PM PDT 24
Peak memory 235364 kb
Host smart-4496eec7-208d-45c1-a02b-5c9db32783af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2501720060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2501720060
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3069937496
Short name T781
Test name
Test status
Simulation time 9948026 ps
CPU time 1.41 seconds
Started Jun 22 04:55:07 PM PDT 24
Finished Jun 22 04:55:10 PM PDT 24
Peak memory 237364 kb
Host smart-82970485-ef26-4456-ba38-0eb81e9819bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3069937496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3069937496
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1640088643
Short name T801
Test name
Test status
Simulation time 26890659 ps
CPU time 1.49 seconds
Started Jun 22 04:55:08 PM PDT 24
Finished Jun 22 04:55:11 PM PDT 24
Peak memory 236420 kb
Host smart-075ff1dc-e115-490a-9d64-1e039ddf9020
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1640088643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1640088643
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2518747649
Short name T794
Test name
Test status
Simulation time 8511404 ps
CPU time 1.5 seconds
Started Jun 22 04:55:10 PM PDT 24
Finished Jun 22 04:55:12 PM PDT 24
Peak memory 235400 kb
Host smart-214e8a32-cdb4-4517-aa10-69f5047d67c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2518747649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2518747649
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.4044134404
Short name T796
Test name
Test status
Simulation time 141566922 ps
CPU time 10.86 seconds
Started Jun 22 04:54:55 PM PDT 24
Finished Jun 22 04:55:07 PM PDT 24
Peak memory 253600 kb
Host smart-8b49665c-8de7-43ac-8007-2e19d8a0a881
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044134404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.4044134404
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1368830009
Short name T759
Test name
Test status
Simulation time 67280024 ps
CPU time 5.64 seconds
Started Jun 22 04:54:56 PM PDT 24
Finished Jun 22 04:55:03 PM PDT 24
Peak memory 237260 kb
Host smart-d6ae4352-a54a-45a6-afb6-7973e8fc5132
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1368830009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1368830009
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2367852317
Short name T733
Test name
Test status
Simulation time 8655186 ps
CPU time 1.51 seconds
Started Jun 22 04:54:51 PM PDT 24
Finished Jun 22 04:54:54 PM PDT 24
Peak memory 237360 kb
Host smart-a19a5fbc-30db-4eda-bec7-1ec83def7ded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2367852317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2367852317
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2997380483
Short name T789
Test name
Test status
Simulation time 167184879 ps
CPU time 22.89 seconds
Started Jun 22 04:54:52 PM PDT 24
Finished Jun 22 04:55:18 PM PDT 24
Peak memory 248972 kb
Host smart-09bdeca7-8951-4fc1-812c-53ca046b6e5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2997380483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2997380483
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1315299502
Short name T152
Test name
Test status
Simulation time 4699837253 ps
CPU time 325.1 seconds
Started Jun 22 04:54:55 PM PDT 24
Finished Jun 22 05:00:22 PM PDT 24
Peak memory 265684 kb
Host smart-fc70be82-2a91-48e6-8014-99ab95a8da48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1315299502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1315299502
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2217160016
Short name T154
Test name
Test status
Simulation time 8309782767 ps
CPU time 327 seconds
Started Jun 22 04:54:51 PM PDT 24
Finished Jun 22 05:00:21 PM PDT 24
Peak memory 268544 kb
Host smart-a88a80c3-9689-4861-9247-0ed8ad5500a9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217160016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.2217160016
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1718163396
Short name T720
Test name
Test status
Simulation time 58043249 ps
CPU time 5.29 seconds
Started Jun 22 04:54:53 PM PDT 24
Finished Jun 22 04:55:01 PM PDT 24
Peak memory 249036 kb
Host smart-24aad6af-b331-4b2c-9278-5e64ea458bc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1718163396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1718163396
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3047033936
Short name T784
Test name
Test status
Simulation time 2436004178 ps
CPU time 8.58 seconds
Started Jun 22 04:55:07 PM PDT 24
Finished Jun 22 04:55:16 PM PDT 24
Peak memory 238444 kb
Host smart-745c8f4a-1e1d-44c5-b37e-16ef4a562f6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047033936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3047033936
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1532851794
Short name T800
Test name
Test status
Simulation time 33922001 ps
CPU time 5.15 seconds
Started Jun 22 04:54:54 PM PDT 24
Finished Jun 22 04:55:01 PM PDT 24
Peak memory 236336 kb
Host smart-5f538b49-3283-4f71-837f-92bc8ff70005
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1532851794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1532851794
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.4286596586
Short name T357
Test name
Test status
Simulation time 10509503 ps
CPU time 1.34 seconds
Started Jun 22 04:54:59 PM PDT 24
Finished Jun 22 04:55:01 PM PDT 24
Peak memory 237360 kb
Host smart-85d34332-daf0-4edf-9635-31599b1aa7b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4286596586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.4286596586
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.4212944917
Short name T807
Test name
Test status
Simulation time 658087650 ps
CPU time 21.08 seconds
Started Jun 22 04:54:52 PM PDT 24
Finished Jun 22 04:55:15 PM PDT 24
Peak memory 248864 kb
Host smart-e86282f0-da49-42e7-aefd-4b6b4846e5eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4212944917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.4212944917
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.550412474
Short name T144
Test name
Test status
Simulation time 17447017488 ps
CPU time 587.24 seconds
Started Jun 22 04:54:55 PM PDT 24
Finished Jun 22 05:04:44 PM PDT 24
Peak memory 265644 kb
Host smart-af3fe7c9-ca16-4df6-9754-144bcc0d6fdc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550412474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.550412474
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1822728522
Short name T743
Test name
Test status
Simulation time 1329310125 ps
CPU time 14.65 seconds
Started Jun 22 04:54:49 PM PDT 24
Finished Jun 22 04:55:05 PM PDT 24
Peak memory 249028 kb
Host smart-4de561b9-d6c0-419d-be6e-342963793a6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1822728522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1822728522
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2243468040
Short name T729
Test name
Test status
Simulation time 242814125 ps
CPU time 9.1 seconds
Started Jun 22 04:54:56 PM PDT 24
Finished Jun 22 04:55:06 PM PDT 24
Peak memory 248936 kb
Host smart-91f8a49f-a4e1-4606-b4da-5727878ca00e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243468040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2243468040
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1790368327
Short name T808
Test name
Test status
Simulation time 420037891 ps
CPU time 5.67 seconds
Started Jun 22 04:54:56 PM PDT 24
Finished Jun 22 04:55:03 PM PDT 24
Peak memory 240648 kb
Host smart-c4930207-ae6e-46a2-a3be-d32356858d79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1790368327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1790368327
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1402084071
Short name T727
Test name
Test status
Simulation time 10455788 ps
CPU time 1.23 seconds
Started Jun 22 04:54:52 PM PDT 24
Finished Jun 22 04:54:55 PM PDT 24
Peak memory 237240 kb
Host smart-fd9b9c26-88a1-46ac-a274-9e0ab999cf6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1402084071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1402084071
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2613650296
Short name T751
Test name
Test status
Simulation time 176840853 ps
CPU time 20.24 seconds
Started Jun 22 04:54:50 PM PDT 24
Finished Jun 22 04:55:12 PM PDT 24
Peak memory 248984 kb
Host smart-2618b6d1-b619-4c79-b6c4-d8c5bba211ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2613650296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2613650296
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1229327757
Short name T156
Test name
Test status
Simulation time 6819883192 ps
CPU time 191.08 seconds
Started Jun 22 04:54:52 PM PDT 24
Finished Jun 22 04:58:05 PM PDT 24
Peak memory 265588 kb
Host smart-0ff7c11a-0c0f-49ad-aee0-5d3fc2b9dec6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1229327757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1229327757
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3752387658
Short name T146
Test name
Test status
Simulation time 2225653945 ps
CPU time 281.48 seconds
Started Jun 22 04:54:56 PM PDT 24
Finished Jun 22 04:59:39 PM PDT 24
Peak memory 265736 kb
Host smart-ec10db2a-037e-424d-8a29-2c7f7a1ddd4b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752387658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3752387658
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3699580935
Short name T775
Test name
Test status
Simulation time 87650659 ps
CPU time 6.75 seconds
Started Jun 22 04:54:50 PM PDT 24
Finished Jun 22 04:54:58 PM PDT 24
Peak memory 251476 kb
Host smart-eb7b281d-afc6-459f-9817-a2fca5ed7ac4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3699580935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3699580935
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1357032142
Short name T725
Test name
Test status
Simulation time 198709003 ps
CPU time 10.28 seconds
Started Jun 22 04:55:00 PM PDT 24
Finished Jun 22 04:55:12 PM PDT 24
Peak memory 251076 kb
Host smart-78122e04-948e-4876-acf9-444a1b23c9e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357032142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1357032142
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.510767000
Short name T799
Test name
Test status
Simulation time 285522649 ps
CPU time 5.28 seconds
Started Jun 22 04:54:55 PM PDT 24
Finished Jun 22 04:55:02 PM PDT 24
Peak memory 240024 kb
Host smart-bde66496-3008-4589-99d9-827492883a28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=510767000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.510767000
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2322123790
Short name T749
Test name
Test status
Simulation time 9378778 ps
CPU time 1.36 seconds
Started Jun 22 04:55:01 PM PDT 24
Finished Jun 22 04:55:03 PM PDT 24
Peak memory 235372 kb
Host smart-764afae6-5a33-41d0-80dd-c3c87a791c20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2322123790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2322123790
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2437462368
Short name T757
Test name
Test status
Simulation time 1389410377 ps
CPU time 44.51 seconds
Started Jun 22 04:54:52 PM PDT 24
Finished Jun 22 04:55:39 PM PDT 24
Peak memory 245444 kb
Host smart-7ce12680-707b-4f1a-ba8e-90fe034eb444
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2437462368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2437462368
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1758126173
Short name T170
Test name
Test status
Simulation time 7818688777 ps
CPU time 147.85 seconds
Started Jun 22 04:54:55 PM PDT 24
Finished Jun 22 04:57:24 PM PDT 24
Peak memory 265684 kb
Host smart-768e3d79-fe8f-4215-9667-e27551c96b82
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1758126173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1758126173
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3591186496
Short name T171
Test name
Test status
Simulation time 6919989226 ps
CPU time 637.07 seconds
Started Jun 22 04:54:53 PM PDT 24
Finished Jun 22 05:05:32 PM PDT 24
Peak memory 265512 kb
Host smart-742e7e35-8590-42da-8e75-dc2013c57b33
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591186496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3591186496
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1325839379
Short name T785
Test name
Test status
Simulation time 894386005 ps
CPU time 14.09 seconds
Started Jun 22 04:54:54 PM PDT 24
Finished Jun 22 04:55:10 PM PDT 24
Peak memory 248668 kb
Host smart-dd4f04a4-0dde-4053-ae5e-fe7ea8ba04e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1325839379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1325839379
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3139678521
Short name T817
Test name
Test status
Simulation time 290932942 ps
CPU time 12.78 seconds
Started Jun 22 04:55:01 PM PDT 24
Finished Jun 22 04:55:15 PM PDT 24
Peak memory 252088 kb
Host smart-cf756ddc-d90f-4635-aa01-80b40a32e104
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139678521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3139678521
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2101788917
Short name T205
Test name
Test status
Simulation time 67904107 ps
CPU time 3.56 seconds
Started Jun 22 04:54:54 PM PDT 24
Finished Jun 22 04:54:59 PM PDT 24
Peak memory 239604 kb
Host smart-0297a5e7-cbee-4d73-b7f8-b8d6ed1bbc13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2101788917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2101788917
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3136262413
Short name T805
Test name
Test status
Simulation time 10297598 ps
CPU time 1.27 seconds
Started Jun 22 04:54:55 PM PDT 24
Finished Jun 22 04:54:58 PM PDT 24
Peak memory 237280 kb
Host smart-5304a645-5b6a-4fe1-be6d-26505d43e656
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3136262413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3136262413
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.147173850
Short name T204
Test name
Test status
Simulation time 654926881 ps
CPU time 42.31 seconds
Started Jun 22 04:55:01 PM PDT 24
Finished Jun 22 04:55:44 PM PDT 24
Peak memory 245572 kb
Host smart-059ac199-1c87-44a5-a45c-35f6fa514b2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=147173850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outs
tanding.147173850
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3786586125
Short name T163
Test name
Test status
Simulation time 18770930749 ps
CPU time 321.25 seconds
Started Jun 22 04:54:54 PM PDT 24
Finished Jun 22 05:00:17 PM PDT 24
Peak memory 273092 kb
Host smart-0feb63bf-0a12-49af-a0b3-2383ce523335
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3786586125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3786586125
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3624521682
Short name T181
Test name
Test status
Simulation time 51479911421 ps
CPU time 1025.6 seconds
Started Jun 22 04:55:01 PM PDT 24
Finished Jun 22 05:12:08 PM PDT 24
Peak memory 265632 kb
Host smart-2b76fd45-3a8c-418c-b46f-e2ffcef566c6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624521682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3624521682
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3325002166
Short name T723
Test name
Test status
Simulation time 423917283 ps
CPU time 24.41 seconds
Started Jun 22 04:54:54 PM PDT 24
Finished Jun 22 04:55:20 PM PDT 24
Peak memory 249004 kb
Host smart-c577df01-75e2-4d13-a321-24c2a597dd00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3325002166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3325002166
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.4107707298
Short name T820
Test name
Test status
Simulation time 177163194 ps
CPU time 22.56 seconds
Started Jun 22 04:54:52 PM PDT 24
Finished Jun 22 04:55:17 PM PDT 24
Peak memory 237412 kb
Host smart-f73b790a-d156-479c-9c27-614851247759
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4107707298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.4107707298
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1897230318
Short name T571
Test name
Test status
Simulation time 5220097018 ps
CPU time 499.33 seconds
Started Jun 22 05:01:49 PM PDT 24
Finished Jun 22 05:10:10 PM PDT 24
Peak memory 265536 kb
Host smart-819ed291-e4f7-421c-9681-0164b81bec8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897230318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1897230318
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3702239260
Short name T408
Test name
Test status
Simulation time 166742313 ps
CPU time 9.53 seconds
Started Jun 22 05:01:40 PM PDT 24
Finished Jun 22 05:01:50 PM PDT 24
Peak memory 249108 kb
Host smart-b276b531-2ae0-4028-a278-7ca099429298
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3702239260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3702239260
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2813443049
Short name T372
Test name
Test status
Simulation time 6797849722 ps
CPU time 218.14 seconds
Started Jun 22 05:01:25 PM PDT 24
Finished Jun 22 05:05:04 PM PDT 24
Peak memory 257344 kb
Host smart-d36b1fb2-36b5-4501-ad9a-b03d89a6f1db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28134
43049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2813443049
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1120735761
Short name T64
Test name
Test status
Simulation time 1826885745 ps
CPU time 50.5 seconds
Started Jun 22 05:01:38 PM PDT 24
Finished Jun 22 05:02:29 PM PDT 24
Peak memory 255456 kb
Host smart-bcb89e63-63f2-40cb-811c-5e9673c41dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11207
35761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1120735761
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1883430973
Short name T608
Test name
Test status
Simulation time 16638849905 ps
CPU time 1220.24 seconds
Started Jun 22 05:01:41 PM PDT 24
Finished Jun 22 05:22:03 PM PDT 24
Peak memory 289500 kb
Host smart-3a837023-6055-4883-89bb-d3ef279c32cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883430973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1883430973
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3628020037
Short name T509
Test name
Test status
Simulation time 224964839847 ps
CPU time 3172.5 seconds
Started Jun 22 05:01:41 PM PDT 24
Finished Jun 22 05:54:34 PM PDT 24
Peak memory 290120 kb
Host smart-85a6de62-9cdd-4779-abac-6a8288868266
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628020037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3628020037
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2591811263
Short name T269
Test name
Test status
Simulation time 1516145075 ps
CPU time 13.39 seconds
Started Jun 22 05:01:32 PM PDT 24
Finished Jun 22 05:01:46 PM PDT 24
Peak memory 254296 kb
Host smart-4260cb1f-a9d2-42ba-81a2-a7943e02c9b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25918
11263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2591811263
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3509850007
Short name T612
Test name
Test status
Simulation time 132595518 ps
CPU time 13.24 seconds
Started Jun 22 05:01:34 PM PDT 24
Finished Jun 22 05:01:49 PM PDT 24
Peak memory 249268 kb
Host smart-519a7444-40d6-4c3a-ad4b-3d73054e454f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35098
50007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3509850007
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1520721796
Short name T12
Test name
Test status
Simulation time 355349544 ps
CPU time 11.56 seconds
Started Jun 22 05:01:46 PM PDT 24
Finished Jun 22 05:01:58 PM PDT 24
Peak memory 270496 kb
Host smart-fa4fa468-e514-4841-80f5-297f6ab2f0e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1520721796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1520721796
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1501660188
Short name T88
Test name
Test status
Simulation time 1164785771 ps
CPU time 19.49 seconds
Started Jun 22 05:01:43 PM PDT 24
Finished Jun 22 05:02:03 PM PDT 24
Peak memory 248004 kb
Host smart-517b6fec-b2c6-43c9-a533-02d147713d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15016
60188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1501660188
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.4143303823
Short name T535
Test name
Test status
Simulation time 92728330 ps
CPU time 5.87 seconds
Started Jun 22 05:01:43 PM PDT 24
Finished Jun 22 05:01:50 PM PDT 24
Peak memory 249096 kb
Host smart-92841da9-8d0a-4ab4-8f39-54ac8b4b8ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41433
03823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.4143303823
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.598029711
Short name T293
Test name
Test status
Simulation time 98369767133 ps
CPU time 2808.19 seconds
Started Jun 22 05:01:56 PM PDT 24
Finished Jun 22 05:48:45 PM PDT 24
Peak memory 305272 kb
Host smart-22871488-6d59-4e90-a457-114f40118938
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598029711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.598029711
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1602700247
Short name T39
Test name
Test status
Simulation time 119837364 ps
CPU time 3.31 seconds
Started Jun 22 05:01:42 PM PDT 24
Finished Jun 22 05:01:46 PM PDT 24
Peak memory 249264 kb
Host smart-422608b7-f5c5-4bf2-b238-752df986f6e7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1602700247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1602700247
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3911783834
Short name T528
Test name
Test status
Simulation time 322503972491 ps
CPU time 1573.62 seconds
Started Jun 22 05:01:48 PM PDT 24
Finished Jun 22 05:28:03 PM PDT 24
Peak memory 273572 kb
Host smart-6e627652-8c97-4894-87d0-d42c5155f305
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911783834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3911783834
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1645784334
Short name T378
Test name
Test status
Simulation time 276648331 ps
CPU time 8.17 seconds
Started Jun 22 05:01:37 PM PDT 24
Finished Jun 22 05:01:46 PM PDT 24
Peak memory 240836 kb
Host smart-47187dee-245d-4dfb-8417-003b3a148696
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1645784334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1645784334
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1013274217
Short name T458
Test name
Test status
Simulation time 5405230059 ps
CPU time 118.25 seconds
Started Jun 22 05:01:55 PM PDT 24
Finished Jun 22 05:03:54 PM PDT 24
Peak memory 257280 kb
Host smart-cf29a0fa-8749-44ff-b7a5-e1d415431135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10132
74217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1013274217
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1235729203
Short name T80
Test name
Test status
Simulation time 2468419905 ps
CPU time 41.04 seconds
Started Jun 22 05:01:37 PM PDT 24
Finished Jun 22 05:02:19 PM PDT 24
Peak memory 256256 kb
Host smart-45a549ed-8901-4dbb-b16c-62b072889639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12357
29203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1235729203
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2304314430
Short name T692
Test name
Test status
Simulation time 231558543152 ps
CPU time 3048.31 seconds
Started Jun 22 05:02:44 PM PDT 24
Finished Jun 22 05:53:33 PM PDT 24
Peak memory 281952 kb
Host smart-1ed31912-6f01-425a-99ba-1912bc4babc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304314430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2304314430
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.4186003403
Short name T563
Test name
Test status
Simulation time 22297129841 ps
CPU time 1137.32 seconds
Started Jun 22 05:01:51 PM PDT 24
Finished Jun 22 05:20:49 PM PDT 24
Peak memory 288632 kb
Host smart-f9d85570-bdeb-46ca-a285-62a441275539
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186003403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.4186003403
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1099716359
Short name T320
Test name
Test status
Simulation time 2823929891 ps
CPU time 115.55 seconds
Started Jun 22 05:01:37 PM PDT 24
Finished Jun 22 05:03:33 PM PDT 24
Peak memory 248812 kb
Host smart-7295c9da-6dec-4690-8dce-d76011c3e442
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099716359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1099716359
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.410186863
Short name T63
Test name
Test status
Simulation time 5479222539 ps
CPU time 34.92 seconds
Started Jun 22 05:01:49 PM PDT 24
Finished Jun 22 05:02:25 PM PDT 24
Peak memory 249072 kb
Host smart-d0972128-c8d0-4e72-abb4-fab5bc5c981a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41018
6863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.410186863
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2918959778
Short name T418
Test name
Test status
Simulation time 372121873 ps
CPU time 19.12 seconds
Started Jun 22 05:01:48 PM PDT 24
Finished Jun 22 05:02:08 PM PDT 24
Peak memory 248936 kb
Host smart-5fb8ce53-2d83-4f7a-87a8-0ed3093ca003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29189
59778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2918959778
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2816480017
Short name T25
Test name
Test status
Simulation time 329516447 ps
CPU time 17.06 seconds
Started Jun 22 05:01:40 PM PDT 24
Finished Jun 22 05:01:58 PM PDT 24
Peak memory 277928 kb
Host smart-ad600672-1a43-4919-a73b-0c251e02d5b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2816480017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2816480017
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3629727444
Short name T266
Test name
Test status
Simulation time 68652196 ps
CPU time 5.81 seconds
Started Jun 22 05:01:44 PM PDT 24
Finished Jun 22 05:01:50 PM PDT 24
Peak memory 247880 kb
Host smart-46c184bc-ff01-427b-820e-c311bf0795fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36297
27444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3629727444
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3614997930
Short name T487
Test name
Test status
Simulation time 5073479428 ps
CPU time 18.88 seconds
Started Jun 22 05:01:38 PM PDT 24
Finished Jun 22 05:01:58 PM PDT 24
Peak memory 257336 kb
Host smart-401f7368-dca6-41e8-ab38-0e45072bbc0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36149
97930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3614997930
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1758696407
Short name T567
Test name
Test status
Simulation time 13391310038 ps
CPU time 1046.56 seconds
Started Jun 22 05:02:01 PM PDT 24
Finished Jun 22 05:19:28 PM PDT 24
Peak memory 283040 kb
Host smart-7376552d-3620-4770-a5f6-3862a2f50a68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758696407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1758696407
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1831023901
Short name T569
Test name
Test status
Simulation time 398086809 ps
CPU time 19.78 seconds
Started Jun 22 05:02:11 PM PDT 24
Finished Jun 22 05:02:31 PM PDT 24
Peak memory 249112 kb
Host smart-f5214798-b5dc-482b-bc74-b7e71ef11914
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1831023901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1831023901
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.827953996
Short name T453
Test name
Test status
Simulation time 22461741861 ps
CPU time 101.54 seconds
Started Jun 22 05:01:58 PM PDT 24
Finished Jun 22 05:03:41 PM PDT 24
Peak memory 257288 kb
Host smart-72c8bd7e-c8e7-4d8d-a73b-e75c2228496a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82795
3996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.827953996
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1703633524
Short name T8
Test name
Test status
Simulation time 1267298396 ps
CPU time 28.12 seconds
Started Jun 22 05:01:57 PM PDT 24
Finished Jun 22 05:02:27 PM PDT 24
Peak memory 256200 kb
Host smart-89231aed-eedf-4275-b214-c32fae751bb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17036
33524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1703633524
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.671678439
Short name T344
Test name
Test status
Simulation time 44856314269 ps
CPU time 1038.3 seconds
Started Jun 22 05:02:07 PM PDT 24
Finished Jun 22 05:19:26 PM PDT 24
Peak memory 273872 kb
Host smart-986df6de-6208-40af-827c-e2c20090eda3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671678439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.671678439
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2590827744
Short name T440
Test name
Test status
Simulation time 72710400031 ps
CPU time 1442.1 seconds
Started Jun 22 05:01:59 PM PDT 24
Finished Jun 22 05:26:02 PM PDT 24
Peak memory 289284 kb
Host smart-de03e4ff-b44f-493a-8f84-771e6e34731d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590827744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2590827744
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1501987931
Short name T517
Test name
Test status
Simulation time 2184099115 ps
CPU time 89.85 seconds
Started Jun 22 05:01:54 PM PDT 24
Finished Jun 22 05:03:24 PM PDT 24
Peak memory 248568 kb
Host smart-80f266eb-8d84-41bd-841e-8a9b80becaba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501987931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1501987931
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.4162116111
Short name T381
Test name
Test status
Simulation time 1703036091 ps
CPU time 24.52 seconds
Started Jun 22 05:02:02 PM PDT 24
Finished Jun 22 05:02:27 PM PDT 24
Peak memory 249004 kb
Host smart-23952aca-f0e5-4c66-88fe-901b299f2e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41621
16111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.4162116111
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2081909264
Short name T609
Test name
Test status
Simulation time 307345925 ps
CPU time 9.33 seconds
Started Jun 22 05:01:57 PM PDT 24
Finished Jun 22 05:02:07 PM PDT 24
Peak memory 247912 kb
Host smart-496ca64a-1cc4-470c-8cbd-9676319a6920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20819
09264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2081909264
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2531007417
Short name T621
Test name
Test status
Simulation time 789252865 ps
CPU time 29.68 seconds
Started Jun 22 05:02:05 PM PDT 24
Finished Jun 22 05:02:35 PM PDT 24
Peak memory 256912 kb
Host smart-16d6d223-c250-4019-b705-9c543383dec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25310
07417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2531007417
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3392070072
Short name T374
Test name
Test status
Simulation time 260861529 ps
CPU time 21.16 seconds
Started Jun 22 05:02:11 PM PDT 24
Finished Jun 22 05:02:33 PM PDT 24
Peak memory 248992 kb
Host smart-a5d78535-2646-4869-9695-90aa83a332eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33920
70072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3392070072
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1684004249
Short name T494
Test name
Test status
Simulation time 42222331825 ps
CPU time 2685.39 seconds
Started Jun 22 05:01:54 PM PDT 24
Finished Jun 22 05:46:40 PM PDT 24
Peak memory 299208 kb
Host smart-51656530-7863-45bd-bd5f-69e7b128f93b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684004249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1684004249
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.128330532
Short name T674
Test name
Test status
Simulation time 41730484673 ps
CPU time 2421.47 seconds
Started Jun 22 05:02:00 PM PDT 24
Finished Jun 22 05:42:22 PM PDT 24
Peak memory 289488 kb
Host smart-6523e39b-e9f9-41cd-9895-9c5d4c117d10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128330532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.128330532
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.986335047
Short name T389
Test name
Test status
Simulation time 2127067734 ps
CPU time 8.47 seconds
Started Jun 22 05:02:07 PM PDT 24
Finished Jun 22 05:02:16 PM PDT 24
Peak memory 249004 kb
Host smart-08b479c2-d44f-4656-9b9d-0a0a2938b6ee
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=986335047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.986335047
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.4093177863
Short name T42
Test name
Test status
Simulation time 33442334936 ps
CPU time 151.04 seconds
Started Jun 22 05:01:59 PM PDT 24
Finished Jun 22 05:04:31 PM PDT 24
Peak memory 257144 kb
Host smart-a988109c-fa35-42eb-a79d-79681e626025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40931
77863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.4093177863
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.252232726
Short name T441
Test name
Test status
Simulation time 122121079 ps
CPU time 4.14 seconds
Started Jun 22 05:02:13 PM PDT 24
Finished Jun 22 05:02:19 PM PDT 24
Peak memory 240844 kb
Host smart-2b6fdabf-d432-4bf7-83fa-643253e69e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25223
2726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.252232726
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.193408371
Short name T400
Test name
Test status
Simulation time 19415641657 ps
CPU time 1212.13 seconds
Started Jun 22 05:01:58 PM PDT 24
Finished Jun 22 05:22:11 PM PDT 24
Peak memory 273324 kb
Host smart-8b7ae047-7366-4196-aaa8-377346cfb20c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193408371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.193408371
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.682111775
Short name T268
Test name
Test status
Simulation time 5071989051 ps
CPU time 196.88 seconds
Started Jun 22 05:01:59 PM PDT 24
Finished Jun 22 05:05:17 PM PDT 24
Peak memory 248828 kb
Host smart-f16649e1-8567-4992-b2e0-db0c7311b5a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682111775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.682111775
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3682557946
Short name T662
Test name
Test status
Simulation time 235929117 ps
CPU time 15.47 seconds
Started Jun 22 05:01:50 PM PDT 24
Finished Jun 22 05:02:07 PM PDT 24
Peak memory 249108 kb
Host smart-e2ef02d9-e711-4eb4-9bf6-889d62348cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36825
57946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3682557946
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2744841474
Short name T45
Test name
Test status
Simulation time 4407905267 ps
CPU time 70.33 seconds
Started Jun 22 05:02:17 PM PDT 24
Finished Jun 22 05:03:29 PM PDT 24
Peak memory 256052 kb
Host smart-c4e16802-a272-4e9a-a8a5-f9a1a8abd26a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27448
41474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2744841474
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.4106038185
Short name T686
Test name
Test status
Simulation time 356830319 ps
CPU time 21.9 seconds
Started Jun 22 05:02:10 PM PDT 24
Finished Jun 22 05:02:32 PM PDT 24
Peak memory 256464 kb
Host smart-f7b34e29-cc66-4a5a-8ffd-da54e6e5ccd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41060
38185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.4106038185
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1868062735
Short name T60
Test name
Test status
Simulation time 414193630 ps
CPU time 4 seconds
Started Jun 22 05:01:55 PM PDT 24
Finished Jun 22 05:01:59 PM PDT 24
Peak memory 240880 kb
Host smart-f4d5312a-a453-4c49-8ccd-46c3e0f34680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18680
62735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1868062735
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.33807785
Short name T255
Test name
Test status
Simulation time 3299904843 ps
CPU time 57.4 seconds
Started Jun 22 05:01:56 PM PDT 24
Finished Jun 22 05:02:55 PM PDT 24
Peak memory 256700 kb
Host smart-7b23a822-d4ae-4980-98d0-1762a0756b97
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33807785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_hand
ler_stress_all.33807785
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3355636168
Short name T227
Test name
Test status
Simulation time 110363043 ps
CPU time 3.12 seconds
Started Jun 22 05:01:58 PM PDT 24
Finished Jun 22 05:02:02 PM PDT 24
Peak memory 249204 kb
Host smart-3f34c9c0-2b54-433c-8c95-e4414d611288
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3355636168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3355636168
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1889349479
Short name T450
Test name
Test status
Simulation time 6141652433 ps
CPU time 782.54 seconds
Started Jun 22 05:01:56 PM PDT 24
Finished Jun 22 05:15:00 PM PDT 24
Peak memory 273092 kb
Host smart-5c88c05c-2172-4bf5-bf2b-5bf57771ed41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889349479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1889349479
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3592161543
Short name T5
Test name
Test status
Simulation time 2863362614 ps
CPU time 30.24 seconds
Started Jun 22 05:02:00 PM PDT 24
Finished Jun 22 05:02:31 PM PDT 24
Peak memory 249184 kb
Host smart-a3d5f98b-c77b-4056-8bcf-33efdcae3d06
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3592161543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3592161543
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.934357938
Short name T37
Test name
Test status
Simulation time 7737679159 ps
CPU time 67.01 seconds
Started Jun 22 05:02:11 PM PDT 24
Finished Jun 22 05:03:19 PM PDT 24
Peak memory 257164 kb
Host smart-ffc0a3a2-c149-4f6c-a966-6b4f1c72f3a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93435
7938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.934357938
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1246109135
Short name T482
Test name
Test status
Simulation time 302379987 ps
CPU time 4.65 seconds
Started Jun 22 05:02:14 PM PDT 24
Finished Jun 22 05:02:20 PM PDT 24
Peak memory 240812 kb
Host smart-e7212e6c-8dd0-4e2b-809a-50b589f20cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12461
09135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1246109135
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3890316760
Short name T243
Test name
Test status
Simulation time 13586949401 ps
CPU time 1405.86 seconds
Started Jun 22 05:02:01 PM PDT 24
Finished Jun 22 05:25:27 PM PDT 24
Peak memory 288540 kb
Host smart-70a7a35b-3f56-4135-93b8-8317238c55ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890316760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3890316760
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3054910030
Short name T294
Test name
Test status
Simulation time 10585354491 ps
CPU time 1087.01 seconds
Started Jun 22 05:02:06 PM PDT 24
Finished Jun 22 05:20:14 PM PDT 24
Peak memory 284572 kb
Host smart-5022fc0a-9e5b-4d48-b7f0-1f3e9cec426c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054910030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3054910030
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3458504612
Short name T443
Test name
Test status
Simulation time 1773945018 ps
CPU time 23.44 seconds
Started Jun 22 05:01:57 PM PDT 24
Finished Jun 22 05:02:21 PM PDT 24
Peak memory 256768 kb
Host smart-ff57333e-511e-4ee2-b16f-e44913fdd6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34585
04612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3458504612
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1054385376
Short name T465
Test name
Test status
Simulation time 2021244551 ps
CPU time 60.06 seconds
Started Jun 22 05:02:11 PM PDT 24
Finished Jun 22 05:03:12 PM PDT 24
Peak memory 256052 kb
Host smart-d3dc536e-d06c-4ee0-8961-2d4cea095b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10543
85376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1054385376
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.385823870
Short name T370
Test name
Test status
Simulation time 2325787874 ps
CPU time 63.48 seconds
Started Jun 22 05:01:57 PM PDT 24
Finished Jun 22 05:03:02 PM PDT 24
Peak memory 257076 kb
Host smart-4d8dd919-36bd-44c1-beb3-be8c66ad8e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38582
3870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.385823870
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1571115188
Short name T551
Test name
Test status
Simulation time 627486935 ps
CPU time 14.98 seconds
Started Jun 22 05:01:56 PM PDT 24
Finished Jun 22 05:02:12 PM PDT 24
Peak memory 256284 kb
Host smart-f7c9fc4c-e034-454c-8f94-f91b777c3328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15711
15188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1571115188
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2840886495
Short name T220
Test name
Test status
Simulation time 81824976705 ps
CPU time 2554.54 seconds
Started Jun 22 05:02:13 PM PDT 24
Finished Jun 22 05:44:49 PM PDT 24
Peak memory 289844 kb
Host smart-487248b1-2f21-44f3-83e2-c6e042ab2f23
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840886495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2840886495
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.887453560
Short name T123
Test name
Test status
Simulation time 13257726168 ps
CPU time 1581.22 seconds
Started Jun 22 05:01:56 PM PDT 24
Finished Jun 22 05:28:18 PM PDT 24
Peak memory 290296 kb
Host smart-5bf90fe7-5004-49a7-8e95-cc8bfd805854
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887453560 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.887453560
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3572048008
Short name T231
Test name
Test status
Simulation time 15845965 ps
CPU time 2.61 seconds
Started Jun 22 05:02:14 PM PDT 24
Finished Jun 22 05:02:18 PM PDT 24
Peak memory 249244 kb
Host smart-f9756736-c7d0-40f9-b1da-ba8ec5294fe0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3572048008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3572048008
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2799387119
Short name T714
Test name
Test status
Simulation time 478696115 ps
CPU time 22 seconds
Started Jun 22 05:02:10 PM PDT 24
Finished Jun 22 05:02:33 PM PDT 24
Peak memory 249108 kb
Host smart-77a575e2-4855-49b1-b1ca-a6de5b2db71e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2799387119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2799387119
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3457188489
Short name T539
Test name
Test status
Simulation time 974543189 ps
CPU time 95.84 seconds
Started Jun 22 05:02:11 PM PDT 24
Finished Jun 22 05:03:47 PM PDT 24
Peak memory 257296 kb
Host smart-00d98683-b056-414f-8431-e4e4477ee865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34571
88489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3457188489
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2009606885
Short name T14
Test name
Test status
Simulation time 302065454 ps
CPU time 18.31 seconds
Started Jun 22 05:02:00 PM PDT 24
Finished Jun 22 05:02:19 PM PDT 24
Peak memory 249120 kb
Host smart-a27ab537-d5ab-441b-9008-6f897d2f6eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20096
06885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2009606885
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.540800751
Short name T340
Test name
Test status
Simulation time 70336761792 ps
CPU time 1405.15 seconds
Started Jun 22 05:02:17 PM PDT 24
Finished Jun 22 05:25:44 PM PDT 24
Peak memory 281988 kb
Host smart-35a42ace-8545-4a1a-ab8e-4453c088dd4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540800751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.540800751
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.39070587
Short name T428
Test name
Test status
Simulation time 23234400762 ps
CPU time 1061.86 seconds
Started Jun 22 05:02:03 PM PDT 24
Finished Jun 22 05:19:45 PM PDT 24
Peak memory 289192 kb
Host smart-33e64d30-06b8-4bbc-84b3-e89b24e139ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39070587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.39070587
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.932580621
Short name T326
Test name
Test status
Simulation time 15880119072 ps
CPU time 149.61 seconds
Started Jun 22 05:02:14 PM PDT 24
Finished Jun 22 05:04:45 PM PDT 24
Peak memory 248692 kb
Host smart-8d86f371-687f-4062-ad95-ee12423ca2bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932580621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.932580621
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1931379054
Short name T19
Test name
Test status
Simulation time 809746612 ps
CPU time 32.11 seconds
Started Jun 22 05:02:07 PM PDT 24
Finished Jun 22 05:02:40 PM PDT 24
Peak memory 256504 kb
Host smart-9eb1ded2-6e3b-49ac-b3e7-8c6d8f810c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19313
79054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1931379054
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.4008312099
Short name T275
Test name
Test status
Simulation time 499566689 ps
CPU time 29.99 seconds
Started Jun 22 05:01:58 PM PDT 24
Finished Jun 22 05:02:29 PM PDT 24
Peak memory 248272 kb
Host smart-fe4c60db-2caf-4a3e-862f-1371782fce29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40083
12099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.4008312099
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3509575490
Short name T404
Test name
Test status
Simulation time 673869056 ps
CPU time 39.58 seconds
Started Jun 22 05:02:03 PM PDT 24
Finished Jun 22 05:02:44 PM PDT 24
Peak memory 249056 kb
Host smart-c5794d0d-e542-4421-bbc3-4deca282924f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35095
75490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3509575490
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.1459722829
Short name T427
Test name
Test status
Simulation time 4962025412 ps
CPU time 82.63 seconds
Started Jun 22 05:02:14 PM PDT 24
Finished Jun 22 05:03:38 PM PDT 24
Peak memory 257316 kb
Host smart-6d069001-be68-4bcf-af3f-8c0c8fdf5d80
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459722829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.1459722829
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.2285982121
Short name T496
Test name
Test status
Simulation time 67827257687 ps
CPU time 1506.67 seconds
Started Jun 22 05:02:18 PM PDT 24
Finished Jun 22 05:27:26 PM PDT 24
Peak memory 282032 kb
Host smart-73a22c6a-0c7a-489d-82ed-5d84729e1011
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285982121 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2285982121
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1202418914
Short name T230
Test name
Test status
Simulation time 54442821 ps
CPU time 2.56 seconds
Started Jun 22 05:02:12 PM PDT 24
Finished Jun 22 05:02:15 PM PDT 24
Peak memory 249172 kb
Host smart-b84618d0-0288-476e-8aeb-350b0cf388ab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1202418914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1202418914
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3655029004
Short name T485
Test name
Test status
Simulation time 263735647236 ps
CPU time 1456.23 seconds
Started Jun 22 05:02:05 PM PDT 24
Finished Jun 22 05:26:22 PM PDT 24
Peak memory 289600 kb
Host smart-49c5b895-d59a-480a-968b-385a38eb9628
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655029004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3655029004
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2322898654
Short name T552
Test name
Test status
Simulation time 342633948 ps
CPU time 9.35 seconds
Started Jun 22 05:02:11 PM PDT 24
Finished Jun 22 05:02:21 PM PDT 24
Peak memory 249008 kb
Host smart-63769daa-fcd2-4372-b1df-9038ac4b30cf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2322898654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2322898654
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2456296375
Short name T7
Test name
Test status
Simulation time 3910160094 ps
CPU time 136.65 seconds
Started Jun 22 05:02:12 PM PDT 24
Finished Jun 22 05:04:29 PM PDT 24
Peak memory 251492 kb
Host smart-7d975b80-1977-4248-abcf-32916465ce8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24562
96375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2456296375
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.477798934
Short name T505
Test name
Test status
Simulation time 226117880 ps
CPU time 12.16 seconds
Started Jun 22 05:02:00 PM PDT 24
Finished Jun 22 05:02:13 PM PDT 24
Peak memory 249040 kb
Host smart-d7253d2b-0316-4d66-b89b-fbfe8207bb10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47779
8934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.477798934
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2831138728
Short name T656
Test name
Test status
Simulation time 20237227240 ps
CPU time 843.85 seconds
Started Jun 22 05:02:11 PM PDT 24
Finished Jun 22 05:16:16 PM PDT 24
Peak memory 272880 kb
Host smart-2e38d284-9015-4e66-910e-5635dcb114ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831138728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2831138728
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3058779494
Short name T279
Test name
Test status
Simulation time 13872314599 ps
CPU time 1329.47 seconds
Started Jun 22 05:02:10 PM PDT 24
Finished Jun 22 05:24:20 PM PDT 24
Peak memory 289552 kb
Host smart-94d48adc-59f1-4d08-a804-fa17b900bf9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058779494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3058779494
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.4133360854
Short name T304
Test name
Test status
Simulation time 32001694744 ps
CPU time 210.17 seconds
Started Jun 22 05:02:08 PM PDT 24
Finished Jun 22 05:05:39 PM PDT 24
Peak memory 248644 kb
Host smart-5d91f20e-fb2c-4ff1-a909-6ffa48c63f1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133360854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.4133360854
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1976766504
Short name T31
Test name
Test status
Simulation time 334725329 ps
CPU time 22.42 seconds
Started Jun 22 05:01:58 PM PDT 24
Finished Jun 22 05:02:21 PM PDT 24
Peak memory 257240 kb
Host smart-e7ca0d71-1e97-44e9-ad04-0366f8f5d5eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19767
66504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1976766504
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2678071897
Short name T559
Test name
Test status
Simulation time 4826897243 ps
CPU time 58.57 seconds
Started Jun 22 05:02:02 PM PDT 24
Finished Jun 22 05:03:02 PM PDT 24
Peak memory 249160 kb
Host smart-43aa2973-957c-4022-ab94-0a175789b4ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26780
71897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2678071897
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3308918533
Short name T86
Test name
Test status
Simulation time 980697659 ps
CPU time 26.92 seconds
Started Jun 22 05:02:08 PM PDT 24
Finished Jun 22 05:02:35 PM PDT 24
Peak memory 249036 kb
Host smart-321be360-8c94-4dfd-96e4-5d9c1f66452d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33089
18533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3308918533
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.4153060084
Short name T107
Test name
Test status
Simulation time 472961557 ps
CPU time 24.79 seconds
Started Jun 22 05:01:59 PM PDT 24
Finished Jun 22 05:02:25 PM PDT 24
Peak memory 256276 kb
Host smart-1c8b9b8a-09ba-464e-a275-079787d32e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41530
60084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.4153060084
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.989163516
Short name T623
Test name
Test status
Simulation time 38453541913 ps
CPU time 1590.04 seconds
Started Jun 22 05:02:03 PM PDT 24
Finished Jun 22 05:28:34 PM PDT 24
Peak memory 289832 kb
Host smart-b6802155-70d8-425f-bbd3-cd2ceb1613d4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989163516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.989163516
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.1618339255
Short name T273
Test name
Test status
Simulation time 47565313326 ps
CPU time 5374.77 seconds
Started Jun 22 05:02:08 PM PDT 24
Finished Jun 22 06:31:44 PM PDT 24
Peak memory 353356 kb
Host smart-44ffe63f-6338-469d-b8a2-ecc7e4bf3ecb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618339255 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.1618339255
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3290588443
Short name T667
Test name
Test status
Simulation time 36067062598 ps
CPU time 835.43 seconds
Started Jun 22 05:02:05 PM PDT 24
Finished Jun 22 05:16:01 PM PDT 24
Peak memory 265608 kb
Host smart-6587c85c-0111-4363-986b-3aac83fb385b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290588443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3290588443
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2499632585
Short name T467
Test name
Test status
Simulation time 372360915 ps
CPU time 10.76 seconds
Started Jun 22 05:02:10 PM PDT 24
Finished Jun 22 05:02:22 PM PDT 24
Peak memory 240912 kb
Host smart-95373b52-d348-4dc3-8691-6bba590b6717
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2499632585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2499632585
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1502770340
Short name T426
Test name
Test status
Simulation time 1677668911 ps
CPU time 30.2 seconds
Started Jun 22 05:02:15 PM PDT 24
Finished Jun 22 05:02:47 PM PDT 24
Peak memory 249048 kb
Host smart-4055af80-28a9-4147-a629-8107a21ef22e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15027
70340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1502770340
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2470019683
Short name T139
Test name
Test status
Simulation time 64741104 ps
CPU time 7.89 seconds
Started Jun 22 05:01:59 PM PDT 24
Finished Jun 22 05:02:07 PM PDT 24
Peak memory 249100 kb
Host smart-d725c09e-6080-4cd0-a425-8287001e90ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24700
19683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2470019683
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.803295945
Short name T333
Test name
Test status
Simulation time 46339500787 ps
CPU time 1361.26 seconds
Started Jun 22 05:02:08 PM PDT 24
Finished Jun 22 05:24:50 PM PDT 24
Peak memory 266460 kb
Host smart-a0b2b75d-db46-4e9f-998f-6bb2f5b82dfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803295945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.803295945
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3560185521
Short name T316
Test name
Test status
Simulation time 10686385688 ps
CPU time 169.76 seconds
Started Jun 22 05:01:59 PM PDT 24
Finished Jun 22 05:04:50 PM PDT 24
Peak memory 248276 kb
Host smart-c7979637-e527-4bd2-897c-12c52da4d110
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560185521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3560185521
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.941953729
Short name T606
Test name
Test status
Simulation time 3586359572 ps
CPU time 39.02 seconds
Started Jun 22 05:02:04 PM PDT 24
Finished Jun 22 05:02:43 PM PDT 24
Peak memory 249088 kb
Host smart-aa720b95-0eb7-462b-a6ab-9494b6ff6120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94195
3729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.941953729
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2540740669
Short name T133
Test name
Test status
Simulation time 247584789 ps
CPU time 23.39 seconds
Started Jun 22 05:02:12 PM PDT 24
Finished Jun 22 05:02:36 PM PDT 24
Peak memory 256052 kb
Host smart-4b616b48-4660-4399-98b9-cc5a32a80301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25407
40669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2540740669
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.400390668
Short name T504
Test name
Test status
Simulation time 508241819 ps
CPU time 16.98 seconds
Started Jun 22 05:02:17 PM PDT 24
Finished Jun 22 05:02:35 PM PDT 24
Peak memory 247876 kb
Host smart-b9622bfb-7170-43bd-96c8-b5dd160a457f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40039
0668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.400390668
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2851821248
Short name T526
Test name
Test status
Simulation time 953084275 ps
CPU time 14.13 seconds
Started Jun 22 05:02:12 PM PDT 24
Finished Jun 22 05:02:27 PM PDT 24
Peak memory 257212 kb
Host smart-14d3b71e-b775-4ac7-8f4a-5d5398d1827b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28518
21248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2851821248
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.4003284135
Short name T695
Test name
Test status
Simulation time 2493031783 ps
CPU time 142.01 seconds
Started Jun 22 05:02:04 PM PDT 24
Finished Jun 22 05:04:26 PM PDT 24
Peak memory 257360 kb
Host smart-d0d19dfb-04bb-448f-8f8a-0e332f99b95c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003284135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.4003284135
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2547046479
Short name T224
Test name
Test status
Simulation time 20253661 ps
CPU time 2.32 seconds
Started Jun 22 05:02:18 PM PDT 24
Finished Jun 22 05:02:21 PM PDT 24
Peak memory 249260 kb
Host smart-0601c012-816b-4579-88bb-bd2a02a1a929
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2547046479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2547046479
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1648237872
Short name T660
Test name
Test status
Simulation time 36006287572 ps
CPU time 2282.91 seconds
Started Jun 22 05:02:12 PM PDT 24
Finished Jun 22 05:40:16 PM PDT 24
Peak memory 289200 kb
Host smart-ee9e955a-49e7-43b4-9f94-b9ab6cd4b680
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648237872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1648237872
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1566765718
Short name T65
Test name
Test status
Simulation time 815115699 ps
CPU time 19.26 seconds
Started Jun 22 05:02:17 PM PDT 24
Finished Jun 22 05:02:38 PM PDT 24
Peak memory 249104 kb
Host smart-eb78f81d-ab87-4c20-b0d5-86369f7ff267
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1566765718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1566765718
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.545395241
Short name T401
Test name
Test status
Simulation time 693425008 ps
CPU time 16.58 seconds
Started Jun 22 05:02:13 PM PDT 24
Finished Jun 22 05:02:31 PM PDT 24
Peak memory 256544 kb
Host smart-c1b5a245-96c5-4ea8-8475-952adc3811a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54539
5241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.545395241
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1320881274
Short name T472
Test name
Test status
Simulation time 333613233 ps
CPU time 18.88 seconds
Started Jun 22 05:02:13 PM PDT 24
Finished Jun 22 05:02:33 PM PDT 24
Peak memory 249076 kb
Host smart-63fad261-2521-4cfb-a7c5-017fd52fa845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13208
81274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1320881274
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.388720871
Short name T29
Test name
Test status
Simulation time 47634447225 ps
CPU time 2643.72 seconds
Started Jun 22 05:02:14 PM PDT 24
Finished Jun 22 05:46:19 PM PDT 24
Peak memory 289456 kb
Host smart-c5aabd2f-cec5-4c58-a248-c12f08db3d6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388720871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.388720871
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2746269897
Short name T659
Test name
Test status
Simulation time 17142916638 ps
CPU time 1074.79 seconds
Started Jun 22 05:02:16 PM PDT 24
Finished Jun 22 05:20:12 PM PDT 24
Peak memory 273252 kb
Host smart-9705d096-ac06-4763-b1cb-f255d7f69ff3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746269897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2746269897
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1718117938
Short name T645
Test name
Test status
Simulation time 14029926954 ps
CPU time 401.26 seconds
Started Jun 22 05:02:13 PM PDT 24
Finished Jun 22 05:08:55 PM PDT 24
Peak memory 248568 kb
Host smart-36eee671-9964-4117-b369-2b391729345f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718117938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1718117938
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2352644546
Short name T445
Test name
Test status
Simulation time 642537291 ps
CPU time 16.62 seconds
Started Jun 22 05:02:00 PM PDT 24
Finished Jun 22 05:02:18 PM PDT 24
Peak memory 249112 kb
Host smart-35366b92-2eac-46c0-a5b7-b5fa5e9405d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23526
44546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2352644546
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3858293510
Short name T636
Test name
Test status
Simulation time 1816214784 ps
CPU time 27.98 seconds
Started Jun 22 05:02:16 PM PDT 24
Finished Jun 22 05:02:45 PM PDT 24
Peak memory 249008 kb
Host smart-1715545e-e72b-408d-94b5-34e965feeeeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38582
93510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3858293510
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3398577588
Short name T506
Test name
Test status
Simulation time 3321134542 ps
CPU time 53.03 seconds
Started Jun 22 05:02:12 PM PDT 24
Finished Jun 22 05:03:06 PM PDT 24
Peak memory 256116 kb
Host smart-4ccd6cb8-b16d-4dba-8fd2-136094b5a12b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33985
77588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3398577588
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.185222398
Short name T481
Test name
Test status
Simulation time 8099222500 ps
CPU time 59.73 seconds
Started Jun 22 05:02:13 PM PDT 24
Finished Jun 22 05:03:14 PM PDT 24
Peak memory 249076 kb
Host smart-c7def8eb-ea2f-4b4c-b817-3b0aa3f74ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18522
2398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.185222398
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3289276202
Short name T703
Test name
Test status
Simulation time 163238500682 ps
CPU time 1909.39 seconds
Started Jun 22 05:02:16 PM PDT 24
Finished Jun 22 05:34:06 PM PDT 24
Peak memory 284744 kb
Host smart-ab06bdb4-a694-4874-9e8c-3a2819111ca8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289276202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3289276202
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.2847302549
Short name T33
Test name
Test status
Simulation time 41103690995 ps
CPU time 2546.87 seconds
Started Jun 22 05:02:13 PM PDT 24
Finished Jun 22 05:44:42 PM PDT 24
Peak memory 306012 kb
Host smart-e65ddd07-eced-4bd4-91ab-a819864fc503
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847302549 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.2847302549
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3763019010
Short name T91
Test name
Test status
Simulation time 15101224 ps
CPU time 2.57 seconds
Started Jun 22 05:02:14 PM PDT 24
Finished Jun 22 05:02:17 PM PDT 24
Peak memory 249236 kb
Host smart-837ab2b2-8c9f-44b9-98f0-8e9b6463d0ec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3763019010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3763019010
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2780643411
Short name T461
Test name
Test status
Simulation time 30813054863 ps
CPU time 1814.73 seconds
Started Jun 22 05:02:17 PM PDT 24
Finished Jun 22 05:32:34 PM PDT 24
Peak memory 284328 kb
Host smart-8b74f72c-fe04-4699-9825-7dfc65cc5bba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780643411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2780643411
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1507851224
Short name T549
Test name
Test status
Simulation time 492984720 ps
CPU time 13.01 seconds
Started Jun 22 05:02:18 PM PDT 24
Finished Jun 22 05:02:32 PM PDT 24
Peak memory 248980 kb
Host smart-bedef72f-9f75-4c45-b344-a89cbd5a4b7c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1507851224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1507851224
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.3858489515
Short name T671
Test name
Test status
Simulation time 10008730796 ps
CPU time 130.8 seconds
Started Jun 22 05:02:14 PM PDT 24
Finished Jun 22 05:04:26 PM PDT 24
Peak memory 257300 kb
Host smart-16be0f54-e1f4-4239-bb5b-7a72236459c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38584
89515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3858489515
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3591873527
Short name T470
Test name
Test status
Simulation time 4272442137 ps
CPU time 60.37 seconds
Started Jun 22 05:02:06 PM PDT 24
Finished Jun 22 05:03:06 PM PDT 24
Peak memory 249188 kb
Host smart-77c2fe5f-e7a3-4a0c-a72e-b8f6713b7ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35918
73527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3591873527
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1240940384
Short name T350
Test name
Test status
Simulation time 47626758437 ps
CPU time 2333.38 seconds
Started Jun 22 05:02:18 PM PDT 24
Finished Jun 22 05:41:13 PM PDT 24
Peak memory 281848 kb
Host smart-c5d98699-b1a0-4b9a-958b-39838e801335
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240940384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1240940384
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3376426983
Short name T329
Test name
Test status
Simulation time 43067663232 ps
CPU time 918.8 seconds
Started Jun 22 05:02:14 PM PDT 24
Finished Jun 22 05:17:34 PM PDT 24
Peak memory 273364 kb
Host smart-9716eb7a-fda3-4f31-8c1d-228d1be5e6b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376426983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3376426983
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3323588401
Short name T654
Test name
Test status
Simulation time 1477871292 ps
CPU time 15.05 seconds
Started Jun 22 05:02:17 PM PDT 24
Finished Jun 22 05:02:33 PM PDT 24
Peak memory 249084 kb
Host smart-b203dd68-b725-43d1-a457-03995e9cf270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33235
88401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3323588401
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.1864976295
Short name T383
Test name
Test status
Simulation time 932335659 ps
CPU time 24.84 seconds
Started Jun 22 05:02:14 PM PDT 24
Finished Jun 22 05:02:40 PM PDT 24
Peak memory 255580 kb
Host smart-4a833a75-2eaf-47d1-9a40-939ecdc0aa4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18649
76295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.1864976295
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.374223659
Short name T267
Test name
Test status
Simulation time 1987288126 ps
CPU time 34.2 seconds
Started Jun 22 05:02:22 PM PDT 24
Finished Jun 22 05:02:57 PM PDT 24
Peak memory 255912 kb
Host smart-81c45e5b-f401-41f3-b195-98a354ab4c25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37422
3659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.374223659
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3962993888
Short name T515
Test name
Test status
Simulation time 229180898 ps
CPU time 17.64 seconds
Started Jun 22 05:02:19 PM PDT 24
Finished Jun 22 05:02:37 PM PDT 24
Peak memory 249064 kb
Host smart-bb48199b-0a63-4d79-b741-2fb72beb1ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39629
93888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3962993888
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.3818054825
Short name T454
Test name
Test status
Simulation time 36735728200 ps
CPU time 2374.59 seconds
Started Jun 22 05:02:11 PM PDT 24
Finished Jun 22 05:41:47 PM PDT 24
Peak memory 289284 kb
Host smart-16e94754-bb6a-4446-b182-8d7887ab7355
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818054825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.3818054825
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.935518880
Short name T235
Test name
Test status
Simulation time 16816299 ps
CPU time 2.71 seconds
Started Jun 22 05:02:17 PM PDT 24
Finished Jun 22 05:02:21 PM PDT 24
Peak memory 249212 kb
Host smart-0615d109-2917-4286-b88d-37fab9772b4e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=935518880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.935518880
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1647381499
Short name T508
Test name
Test status
Simulation time 350326091730 ps
CPU time 3181.36 seconds
Started Jun 22 05:02:12 PM PDT 24
Finished Jun 22 05:55:15 PM PDT 24
Peak memory 289432 kb
Host smart-31f2b18b-271a-4afd-b3d0-cf19c7d35e02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647381499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1647381499
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2078434787
Short name T90
Test name
Test status
Simulation time 844289983 ps
CPU time 12.33 seconds
Started Jun 22 05:02:19 PM PDT 24
Finished Jun 22 05:02:32 PM PDT 24
Peak memory 249028 kb
Host smart-afbf5d27-f91e-46f5-add3-2a5b26bbada5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2078434787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2078434787
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3048802862
Short name T688
Test name
Test status
Simulation time 2858199409 ps
CPU time 153.54 seconds
Started Jun 22 05:02:14 PM PDT 24
Finished Jun 22 05:04:49 PM PDT 24
Peak memory 257212 kb
Host smart-9e367252-d328-4abe-9c6d-487d09a1039a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30488
02862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3048802862
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.361272554
Short name T555
Test name
Test status
Simulation time 2093659765 ps
CPU time 27.17 seconds
Started Jun 22 05:02:20 PM PDT 24
Finished Jun 22 05:02:48 PM PDT 24
Peak memory 255288 kb
Host smart-a56581bf-58ff-4313-8f37-5c692dc54990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36127
2554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.361272554
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.906446710
Short name T343
Test name
Test status
Simulation time 19131218651 ps
CPU time 1517.35 seconds
Started Jun 22 05:02:15 PM PDT 24
Finished Jun 22 05:27:34 PM PDT 24
Peak memory 281984 kb
Host smart-1de723b3-f1df-4629-9cdb-9a8088ddbe5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906446710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.906446710
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3189619516
Short name T622
Test name
Test status
Simulation time 16455693589 ps
CPU time 1040.99 seconds
Started Jun 22 05:02:08 PM PDT 24
Finished Jun 22 05:19:30 PM PDT 24
Peak memory 282868 kb
Host smart-98ffde80-92f6-4787-8727-c1bb1ffd6a5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189619516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3189619516
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.3573114537
Short name T317
Test name
Test status
Simulation time 11987193957 ps
CPU time 259.02 seconds
Started Jun 22 05:02:15 PM PDT 24
Finished Jun 22 05:06:35 PM PDT 24
Peak memory 247784 kb
Host smart-91601f0c-c6df-40f2-94dd-5e093db71d6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573114537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3573114537
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.142388962
Short name T444
Test name
Test status
Simulation time 554609645 ps
CPU time 21.18 seconds
Started Jun 22 05:02:14 PM PDT 24
Finished Jun 22 05:02:36 PM PDT 24
Peak memory 255824 kb
Host smart-237da395-fdd9-4ce5-bce6-26fafb828500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14238
8962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.142388962
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2341797835
Short name T285
Test name
Test status
Simulation time 1093371662 ps
CPU time 27.68 seconds
Started Jun 22 05:02:21 PM PDT 24
Finished Jun 22 05:02:50 PM PDT 24
Peak memory 249008 kb
Host smart-8fd8cd38-c3b6-4c4c-8e47-81dbbc7184d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23417
97835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2341797835
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2893905432
Short name T560
Test name
Test status
Simulation time 617549963 ps
CPU time 16.19 seconds
Started Jun 22 05:02:15 PM PDT 24
Finished Jun 22 05:02:33 PM PDT 24
Peak memory 249164 kb
Host smart-71225750-5245-4cc6-bc41-665539e8d579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28939
05432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2893905432
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3180032103
Short name T647
Test name
Test status
Simulation time 583676636 ps
CPU time 17.12 seconds
Started Jun 22 05:02:13 PM PDT 24
Finished Jun 22 05:02:31 PM PDT 24
Peak memory 249020 kb
Host smart-6c949459-7841-49c2-b656-900bb7a7f568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31800
32103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3180032103
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2891581372
Short name T136
Test name
Test status
Simulation time 145812007 ps
CPU time 3.22 seconds
Started Jun 22 05:02:20 PM PDT 24
Finished Jun 22 05:02:25 PM PDT 24
Peak memory 249264 kb
Host smart-3cbeb0d1-2e74-4715-9e49-0b23222237c3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2891581372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2891581372
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.762757277
Short name T238
Test name
Test status
Simulation time 23475038560 ps
CPU time 1251.36 seconds
Started Jun 22 05:02:20 PM PDT 24
Finished Jun 22 05:23:12 PM PDT 24
Peak memory 272904 kb
Host smart-7f782d1f-61ca-48d1-8426-39e87f24152f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762757277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.762757277
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3654861348
Short name T388
Test name
Test status
Simulation time 1784278496 ps
CPU time 42.66 seconds
Started Jun 22 05:02:20 PM PDT 24
Finished Jun 22 05:03:04 PM PDT 24
Peak memory 249072 kb
Host smart-29d80dd3-d814-40df-9fd8-c8f301dd99d7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3654861348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3654861348
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.778964577
Short name T289
Test name
Test status
Simulation time 1595948443 ps
CPU time 125.35 seconds
Started Jun 22 05:02:16 PM PDT 24
Finished Jun 22 05:04:23 PM PDT 24
Peak memory 257260 kb
Host smart-1db51077-67df-4d13-8803-9147bcc1dec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77896
4577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.778964577
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1606112835
Short name T430
Test name
Test status
Simulation time 129335311 ps
CPU time 9.73 seconds
Started Jun 22 05:03:10 PM PDT 24
Finished Jun 22 05:03:20 PM PDT 24
Peak memory 249332 kb
Host smart-ee127a6d-3f3e-4de9-bccc-91a84028e80b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16061
12835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1606112835
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.434399742
Short name T676
Test name
Test status
Simulation time 111702491117 ps
CPU time 1641.44 seconds
Started Jun 22 05:02:12 PM PDT 24
Finished Jun 22 05:29:34 PM PDT 24
Peak memory 265580 kb
Host smart-23423f63-3c6e-4423-94a9-e89d9357a600
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434399742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.434399742
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.575674714
Short name T624
Test name
Test status
Simulation time 51727566259 ps
CPU time 2961.56 seconds
Started Jun 22 05:02:19 PM PDT 24
Finished Jun 22 05:51:42 PM PDT 24
Peak memory 290068 kb
Host smart-61d11fdb-eec6-4701-ae6d-a13d8a413f5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575674714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.575674714
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.81756448
Short name T118
Test name
Test status
Simulation time 3224121570 ps
CPU time 132.1 seconds
Started Jun 22 05:02:17 PM PDT 24
Finished Jun 22 05:04:31 PM PDT 24
Peak memory 247544 kb
Host smart-c622ef58-cd2a-424d-bf14-605fc853baef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81756448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.81756448
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2476772209
Short name T394
Test name
Test status
Simulation time 2959388941 ps
CPU time 48.78 seconds
Started Jun 22 05:02:12 PM PDT 24
Finished Jun 22 05:03:02 PM PDT 24
Peak memory 249184 kb
Host smart-15844f5b-bb10-4e2b-80b0-a9cc8246a4c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24767
72209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2476772209
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.181891438
Short name T594
Test name
Test status
Simulation time 1046300100 ps
CPU time 59.79 seconds
Started Jun 22 05:02:14 PM PDT 24
Finished Jun 22 05:03:15 PM PDT 24
Peak memory 256756 kb
Host smart-dbcfb73d-db88-4c69-9dff-ba0c04d201d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18189
1438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.181891438
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1546443388
Short name T670
Test name
Test status
Simulation time 3561509874 ps
CPU time 46.67 seconds
Started Jun 22 05:02:13 PM PDT 24
Finished Jun 22 05:03:00 PM PDT 24
Peak memory 255944 kb
Host smart-a5606d2f-8c83-452e-897f-2474327c3a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15464
43388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1546443388
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1653086876
Short name T589
Test name
Test status
Simulation time 183561866 ps
CPU time 12.55 seconds
Started Jun 22 05:02:16 PM PDT 24
Finished Jun 22 05:02:29 PM PDT 24
Peak memory 249004 kb
Host smart-531efd34-bcd9-4002-8c2b-9919deef484a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16530
86876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1653086876
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2912142956
Short name T221
Test name
Test status
Simulation time 14508610 ps
CPU time 2.42 seconds
Started Jun 22 05:01:39 PM PDT 24
Finished Jun 22 05:01:42 PM PDT 24
Peak memory 249264 kb
Host smart-13860428-6ffd-4b6f-9410-ddb236363acd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2912142956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2912142956
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.654506975
Short name T52
Test name
Test status
Simulation time 12751164665 ps
CPU time 634.58 seconds
Started Jun 22 05:01:43 PM PDT 24
Finished Jun 22 05:12:18 PM PDT 24
Peak memory 272848 kb
Host smart-4156c1b8-37f4-4457-8c32-e6a2b76e854b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654506975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.654506975
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2795213686
Short name T700
Test name
Test status
Simulation time 5663585082 ps
CPU time 60.81 seconds
Started Jun 22 05:01:37 PM PDT 24
Finished Jun 22 05:02:38 PM PDT 24
Peak memory 249176 kb
Host smart-fc70a9ca-2e61-4cbc-b09e-baf2df417506
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2795213686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2795213686
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.92582314
Short name T510
Test name
Test status
Simulation time 5208242975 ps
CPU time 75.12 seconds
Started Jun 22 05:01:47 PM PDT 24
Finished Jun 22 05:03:03 PM PDT 24
Peak memory 257336 kb
Host smart-6b0bcefb-1f61-43a9-b4ab-0ec303afca8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92582
314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.92582314
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.816008180
Short name T550
Test name
Test status
Simulation time 279073151 ps
CPU time 24.29 seconds
Started Jun 22 05:01:38 PM PDT 24
Finished Jun 22 05:02:04 PM PDT 24
Peak memory 249116 kb
Host smart-3da66dad-0c6c-4074-9029-0de270894ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81600
8180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.816008180
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3103607178
Short name T349
Test name
Test status
Simulation time 109155624622 ps
CPU time 1744.31 seconds
Started Jun 22 05:01:34 PM PDT 24
Finished Jun 22 05:30:40 PM PDT 24
Peak memory 273652 kb
Host smart-ac63db46-6c3d-41d7-a442-03bcb61e25e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103607178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3103607178
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1347000080
Short name T598
Test name
Test status
Simulation time 140287653742 ps
CPU time 2311.3 seconds
Started Jun 22 05:01:40 PM PDT 24
Finished Jun 22 05:40:12 PM PDT 24
Peak memory 289152 kb
Host smart-9193d025-7e8e-4e8e-ab1d-23e49a17d355
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347000080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1347000080
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1069832987
Short name T314
Test name
Test status
Simulation time 69970116055 ps
CPU time 358.52 seconds
Started Jun 22 05:01:49 PM PDT 24
Finished Jun 22 05:07:48 PM PDT 24
Peak memory 248560 kb
Host smart-3ccd95af-7de1-44fd-bd7a-cc966ca67df6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069832987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1069832987
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.279561114
Short name T618
Test name
Test status
Simulation time 254015152 ps
CPU time 8.71 seconds
Started Jun 22 05:01:53 PM PDT 24
Finished Jun 22 05:02:02 PM PDT 24
Peak memory 254164 kb
Host smart-a0a4a0ad-7fea-4670-90e8-f1b679d82767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27956
1114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.279561114
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3295302439
Short name T451
Test name
Test status
Simulation time 898238004 ps
CPU time 51.83 seconds
Started Jun 22 05:01:46 PM PDT 24
Finished Jun 22 05:02:39 PM PDT 24
Peak memory 248196 kb
Host smart-2ecd2d62-d4cb-4783-96da-6f7abc5c1afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32953
02439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3295302439
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3910677443
Short name T26
Test name
Test status
Simulation time 1263083234 ps
CPU time 19.63 seconds
Started Jun 22 05:01:52 PM PDT 24
Finished Jun 22 05:02:12 PM PDT 24
Peak memory 266556 kb
Host smart-39796c4d-5a5d-4bfe-be82-dbb926cc135d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3910677443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3910677443
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2078784116
Short name T70
Test name
Test status
Simulation time 135567188 ps
CPU time 8.93 seconds
Started Jun 22 05:01:36 PM PDT 24
Finished Jun 22 05:01:46 PM PDT 24
Peak memory 252416 kb
Host smart-b844dbf7-d2a2-48b8-a930-1e5a96ba1d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20787
84116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2078784116
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2559153725
Short name T77
Test name
Test status
Simulation time 3861956697 ps
CPU time 49.01 seconds
Started Jun 22 05:01:40 PM PDT 24
Finished Jun 22 05:02:30 PM PDT 24
Peak memory 249128 kb
Host smart-5e44cb63-4d1c-4e52-8493-80a368b16915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25591
53725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2559153725
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1060639354
Short name T271
Test name
Test status
Simulation time 421509809678 ps
CPU time 1833.95 seconds
Started Jun 22 05:01:43 PM PDT 24
Finished Jun 22 05:32:18 PM PDT 24
Peak memory 281936 kb
Host smart-e19de990-3034-4c96-acf6-fde06bb0fb5a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060639354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1060639354
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2946080963
Short name T280
Test name
Test status
Simulation time 37932383091 ps
CPU time 2457.7 seconds
Started Jun 22 05:02:23 PM PDT 24
Finished Jun 22 05:43:22 PM PDT 24
Peak memory 289560 kb
Host smart-98be9219-5fb4-4a03-9a3b-f281884d208b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946080963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2946080963
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.227345917
Short name T420
Test name
Test status
Simulation time 2241214973 ps
CPU time 43.45 seconds
Started Jun 22 05:02:24 PM PDT 24
Finished Jun 22 05:03:08 PM PDT 24
Peak memory 257352 kb
Host smart-d87f7cfb-7505-4685-b461-70ae7b352074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22734
5917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.227345917
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.4170328593
Short name T79
Test name
Test status
Simulation time 5136885811 ps
CPU time 37.88 seconds
Started Jun 22 05:02:20 PM PDT 24
Finished Jun 22 05:02:59 PM PDT 24
Peak memory 256164 kb
Host smart-1569c581-65d8-4818-9062-c65f2e970733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41703
28593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.4170328593
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2255662388
Short name T705
Test name
Test status
Simulation time 58049228940 ps
CPU time 3226.84 seconds
Started Jun 22 05:02:15 PM PDT 24
Finished Jun 22 05:56:03 PM PDT 24
Peak memory 289096 kb
Host smart-8c64cea9-bb49-4809-84a1-eb75febb791a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255662388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2255662388
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2015412766
Short name T310
Test name
Test status
Simulation time 38441047762 ps
CPU time 302.77 seconds
Started Jun 22 05:02:16 PM PDT 24
Finished Jun 22 05:07:20 PM PDT 24
Peak memory 248632 kb
Host smart-eac9b61e-5475-4c9c-a4f8-73dea0e28d65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015412766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2015412766
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1535658222
Short name T245
Test name
Test status
Simulation time 522256739 ps
CPU time 29.42 seconds
Started Jun 22 05:02:17 PM PDT 24
Finished Jun 22 05:02:48 PM PDT 24
Peak memory 249188 kb
Host smart-93fa9b82-f3c7-47ff-8e87-d0af38a6a70b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15356
58222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1535658222
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2377141877
Short name T646
Test name
Test status
Simulation time 857137291 ps
CPU time 27.55 seconds
Started Jun 22 05:02:17 PM PDT 24
Finished Jun 22 05:02:46 PM PDT 24
Peak memory 256440 kb
Host smart-70f2e256-9272-4de8-a305-9edbb7a174f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23771
41877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2377141877
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.2979203987
Short name T392
Test name
Test status
Simulation time 62365207 ps
CPU time 7.47 seconds
Started Jun 22 05:02:17 PM PDT 24
Finished Jun 22 05:02:25 PM PDT 24
Peak memory 249032 kb
Host smart-8954f9f1-1eb8-409a-a419-16cb6250f123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29792
03987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2979203987
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3471974430
Short name T391
Test name
Test status
Simulation time 398629710 ps
CPU time 33.98 seconds
Started Jun 22 05:02:22 PM PDT 24
Finished Jun 22 05:02:57 PM PDT 24
Peak memory 256328 kb
Host smart-fb7cba99-51ef-4290-ba8a-c4cf7d949dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34719
74430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3471974430
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2810534419
Short name T387
Test name
Test status
Simulation time 33860999227 ps
CPU time 2899.57 seconds
Started Jun 22 05:02:16 PM PDT 24
Finished Jun 22 05:50:37 PM PDT 24
Peak memory 290016 kb
Host smart-e75020fc-6dab-4532-9640-fc94e36cda34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810534419 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2810534419
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2710442402
Short name T484
Test name
Test status
Simulation time 102961332455 ps
CPU time 1970.23 seconds
Started Jun 22 05:02:22 PM PDT 24
Finished Jun 22 05:35:12 PM PDT 24
Peak memory 289464 kb
Host smart-dfbb8160-69c0-4c84-b13a-7aab1762a812
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710442402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2710442402
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.1756477088
Short name T537
Test name
Test status
Simulation time 1515911279 ps
CPU time 87.76 seconds
Started Jun 22 05:02:20 PM PDT 24
Finished Jun 22 05:03:49 PM PDT 24
Peak memory 257280 kb
Host smart-38674109-70d5-4362-8968-4b99b70c42e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17564
77088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1756477088
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.1952231814
Short name T82
Test name
Test status
Simulation time 619542825 ps
CPU time 21.19 seconds
Started Jun 22 05:02:20 PM PDT 24
Finished Jun 22 05:02:43 PM PDT 24
Peak memory 255316 kb
Host smart-24eb748f-63d9-4048-8b1e-6c0571c3453a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19522
31814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1952231814
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3917262239
Short name T672
Test name
Test status
Simulation time 117048502435 ps
CPU time 1938.25 seconds
Started Jun 22 05:02:16 PM PDT 24
Finished Jun 22 05:34:36 PM PDT 24
Peak memory 281944 kb
Host smart-3d1a8936-6350-454e-a7b2-06aba8f4bdf6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917262239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3917262239
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.2339718727
Short name T411
Test name
Test status
Simulation time 18414359320 ps
CPU time 1110.71 seconds
Started Jun 22 05:02:26 PM PDT 24
Finished Jun 22 05:20:57 PM PDT 24
Peak memory 273216 kb
Host smart-93f690d2-82b9-489e-a9ad-78590c900c19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339718727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2339718727
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2795863600
Short name T367
Test name
Test status
Simulation time 1010816006 ps
CPU time 25.38 seconds
Started Jun 22 05:02:24 PM PDT 24
Finished Jun 22 05:02:50 PM PDT 24
Peak memory 249104 kb
Host smart-98a73403-8746-4502-aa54-2c6d902fc273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27958
63600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2795863600
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.4024934985
Short name T116
Test name
Test status
Simulation time 397499591 ps
CPU time 20.53 seconds
Started Jun 22 05:02:24 PM PDT 24
Finished Jun 22 05:02:45 PM PDT 24
Peak memory 248356 kb
Host smart-8a7e214f-0610-484d-a3ca-94f9ffa043aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40249
34985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.4024934985
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3433258652
Short name T254
Test name
Test status
Simulation time 301921436 ps
CPU time 21.41 seconds
Started Jun 22 05:02:19 PM PDT 24
Finished Jun 22 05:02:41 PM PDT 24
Peak memory 255388 kb
Host smart-f1a69299-11bd-462d-abb2-420585cfa4ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34332
58652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3433258652
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1249263225
Short name T501
Test name
Test status
Simulation time 3536874150 ps
CPU time 60.51 seconds
Started Jun 22 05:02:21 PM PDT 24
Finished Jun 22 05:03:23 PM PDT 24
Peak memory 257244 kb
Host smart-a383fc06-0f95-4a2c-af62-717defe4cae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12492
63225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1249263225
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3317719833
Short name T104
Test name
Test status
Simulation time 44717447409 ps
CPU time 691.59 seconds
Started Jun 22 05:02:18 PM PDT 24
Finished Jun 22 05:13:51 PM PDT 24
Peak memory 265528 kb
Host smart-50d7560a-edb1-4f5e-812b-cb0157011d72
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317719833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3317719833
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1499546617
Short name T20
Test name
Test status
Simulation time 39321870264 ps
CPU time 2428.35 seconds
Started Jun 22 05:02:22 PM PDT 24
Finished Jun 22 05:42:51 PM PDT 24
Peak memory 306504 kb
Host smart-306ed258-ded2-433d-8fca-37add39fa639
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499546617 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1499546617
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.785261561
Short name T523
Test name
Test status
Simulation time 46692570920 ps
CPU time 2512.67 seconds
Started Jun 22 05:02:24 PM PDT 24
Finished Jun 22 05:44:17 PM PDT 24
Peak memory 288716 kb
Host smart-763aafab-fb57-4588-ac6e-1d2bb7fedba4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785261561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.785261561
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1414591937
Short name T286
Test name
Test status
Simulation time 7380698293 ps
CPU time 201.87 seconds
Started Jun 22 05:02:20 PM PDT 24
Finished Jun 22 05:05:43 PM PDT 24
Peak memory 257276 kb
Host smart-8d247a0e-d60a-4d99-b9e6-4100c82910af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14145
91937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1414591937
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3820306643
Short name T81
Test name
Test status
Simulation time 12096293129 ps
CPU time 36.77 seconds
Started Jun 22 05:02:18 PM PDT 24
Finished Jun 22 05:02:56 PM PDT 24
Peak memory 249352 kb
Host smart-39478e40-9ab6-47d1-b5e4-7f90964c79ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38203
06643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3820306643
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3991644172
Short name T332
Test name
Test status
Simulation time 166922522494 ps
CPU time 2444.25 seconds
Started Jun 22 05:02:21 PM PDT 24
Finished Jun 22 05:43:06 PM PDT 24
Peak memory 283872 kb
Host smart-ae35d108-fbf9-466d-9b43-d7a40265b46e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991644172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3991644172
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.947885657
Short name T561
Test name
Test status
Simulation time 90083729399 ps
CPU time 2561.82 seconds
Started Jun 22 05:02:18 PM PDT 24
Finished Jun 22 05:45:01 PM PDT 24
Peak memory 289328 kb
Host smart-6d38053c-6a9a-4c83-bb54-1a47885511c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947885657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.947885657
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3182151948
Short name T298
Test name
Test status
Simulation time 10810776919 ps
CPU time 414.5 seconds
Started Jun 22 05:02:16 PM PDT 24
Finished Jun 22 05:09:12 PM PDT 24
Peak memory 255624 kb
Host smart-74da2ae9-3846-440a-9539-f237a74b59fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182151948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3182151948
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3615582817
Short name T246
Test name
Test status
Simulation time 241808847 ps
CPU time 24.12 seconds
Started Jun 22 05:02:22 PM PDT 24
Finished Jun 22 05:02:47 PM PDT 24
Peak memory 249040 kb
Host smart-7f4960b2-fe08-4ab6-bf76-6a09050ea250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36155
82817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3615582817
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.4187449856
Short name T698
Test name
Test status
Simulation time 25530975 ps
CPU time 3.26 seconds
Started Jun 22 05:02:18 PM PDT 24
Finished Jun 22 05:02:23 PM PDT 24
Peak memory 239708 kb
Host smart-f464f849-6482-4ed8-81f5-ad0b44ec0483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41874
49856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.4187449856
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3307832890
Short name T409
Test name
Test status
Simulation time 590161677 ps
CPU time 17.62 seconds
Started Jun 22 05:02:28 PM PDT 24
Finished Jun 22 05:02:46 PM PDT 24
Peak memory 247984 kb
Host smart-753577e4-b40c-4c52-9f1e-42f2d2353541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33078
32890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3307832890
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1380148088
Short name T419
Test name
Test status
Simulation time 48616048 ps
CPU time 6.39 seconds
Started Jun 22 05:02:21 PM PDT 24
Finished Jun 22 05:02:28 PM PDT 24
Peak memory 249092 kb
Host smart-c5dbf522-84ae-4a08-968e-3f20cd85bc52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13801
48088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1380148088
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.2908700965
Short name T78
Test name
Test status
Simulation time 7973396155 ps
CPU time 126.11 seconds
Started Jun 22 05:02:18 PM PDT 24
Finished Jun 22 05:04:26 PM PDT 24
Peak memory 257300 kb
Host smart-8311ba77-c2a3-44bb-bd16-f85f4e64c74f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908700965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.2908700965
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3129361360
Short name T386
Test name
Test status
Simulation time 9943493214 ps
CPU time 1206.64 seconds
Started Jun 22 05:02:26 PM PDT 24
Finished Jun 22 05:22:34 PM PDT 24
Peak memory 286980 kb
Host smart-a240b940-661b-4a69-bbc0-0e96bd13a8db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129361360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3129361360
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1636018956
Short name T590
Test name
Test status
Simulation time 1468070033 ps
CPU time 109.86 seconds
Started Jun 22 05:02:24 PM PDT 24
Finished Jun 22 05:04:14 PM PDT 24
Peak memory 257224 kb
Host smart-9b6c1cab-fbf6-4f9f-a084-c1604d61a56b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16360
18956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1636018956
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.626151175
Short name T553
Test name
Test status
Simulation time 130791978 ps
CPU time 3.93 seconds
Started Jun 22 05:02:29 PM PDT 24
Finished Jun 22 05:02:34 PM PDT 24
Peak memory 239816 kb
Host smart-05f2a933-1ea9-41aa-88ba-444012a526d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62615
1175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.626151175
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.396984731
Short name T650
Test name
Test status
Simulation time 105790881258 ps
CPU time 1545.01 seconds
Started Jun 22 05:02:20 PM PDT 24
Finished Jun 22 05:28:06 PM PDT 24
Peak memory 271908 kb
Host smart-46ca6163-fecd-4313-b419-98aae774718d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396984731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.396984731
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2098958047
Short name T540
Test name
Test status
Simulation time 8616929306 ps
CPU time 85.71 seconds
Started Jun 22 05:02:28 PM PDT 24
Finished Jun 22 05:03:54 PM PDT 24
Peak memory 248628 kb
Host smart-8bdd54b8-dd66-4ba8-bf12-302edd72a0f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098958047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2098958047
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3616961561
Short name T92
Test name
Test status
Simulation time 1725099279 ps
CPU time 53.95 seconds
Started Jun 22 05:02:22 PM PDT 24
Finished Jun 22 05:03:17 PM PDT 24
Peak memory 256448 kb
Host smart-26bef905-1c13-4332-a19e-0c5bdc0779e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36169
61561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3616961561
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3865164558
Short name T685
Test name
Test status
Simulation time 11570064024 ps
CPU time 73.44 seconds
Started Jun 22 05:02:19 PM PDT 24
Finished Jun 22 05:03:34 PM PDT 24
Peak memory 255980 kb
Host smart-95d576ed-33ab-4d8a-9c09-2081fde8a70e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38651
64558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3865164558
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1706729583
Short name T122
Test name
Test status
Simulation time 2184994183 ps
CPU time 59.29 seconds
Started Jun 22 05:02:34 PM PDT 24
Finished Jun 22 05:03:34 PM PDT 24
Peak memory 248384 kb
Host smart-a606b56d-76a7-4c27-8966-a6d8ee0ad521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17067
29583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1706729583
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.760235638
Short name T405
Test name
Test status
Simulation time 815548545 ps
CPU time 14.59 seconds
Started Jun 22 05:02:22 PM PDT 24
Finished Jun 22 05:02:38 PM PDT 24
Peak memory 249092 kb
Host smart-2b164c5e-0587-4513-9d92-d767827c6c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76023
5638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.760235638
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.2344391039
Short name T249
Test name
Test status
Simulation time 73184252459 ps
CPU time 2188.38 seconds
Started Jun 22 05:02:25 PM PDT 24
Finished Jun 22 05:38:54 PM PDT 24
Peak memory 290296 kb
Host smart-623f34ad-3afc-4105-b7eb-548ed1086194
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344391039 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.2344391039
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2160455548
Short name T278
Test name
Test status
Simulation time 45480054200 ps
CPU time 1929.74 seconds
Started Jun 22 05:02:31 PM PDT 24
Finished Jun 22 05:34:42 PM PDT 24
Peak memory 272948 kb
Host smart-62dac607-233b-4540-bb97-3ef912bf1c81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160455548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2160455548
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1312049745
Short name T578
Test name
Test status
Simulation time 6264577213 ps
CPU time 140.22 seconds
Started Jun 22 05:02:20 PM PDT 24
Finished Jun 22 05:04:42 PM PDT 24
Peak memory 257284 kb
Host smart-4872dd53-52e4-4192-8c71-d6df08944ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13120
49745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1312049745
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1269247786
Short name T513
Test name
Test status
Simulation time 110190738 ps
CPU time 4.84 seconds
Started Jun 22 05:02:23 PM PDT 24
Finished Jun 22 05:02:29 PM PDT 24
Peak memory 239812 kb
Host smart-40daba7e-24fd-447f-88a4-abfe36d7cab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12692
47786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1269247786
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3137067654
Short name T395
Test name
Test status
Simulation time 115828035748 ps
CPU time 1976.61 seconds
Started Jun 22 05:02:34 PM PDT 24
Finished Jun 22 05:35:31 PM PDT 24
Peak memory 284612 kb
Host smart-3b56062b-cedc-403b-af69-0c220cfa9d2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137067654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3137067654
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3660899014
Short name T327
Test name
Test status
Simulation time 31906772286 ps
CPU time 343.28 seconds
Started Jun 22 05:02:29 PM PDT 24
Finished Jun 22 05:08:13 PM PDT 24
Peak memory 247512 kb
Host smart-08984e0a-5a73-4c0a-8b94-ade01484c579
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660899014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3660899014
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1838520904
Short name T44
Test name
Test status
Simulation time 3844708216 ps
CPU time 56.93 seconds
Started Jun 22 05:02:27 PM PDT 24
Finished Jun 22 05:03:24 PM PDT 24
Peak memory 249144 kb
Host smart-ebecc226-7302-4b75-8926-5713e6d965e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18385
20904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1838520904
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2886368407
Short name T459
Test name
Test status
Simulation time 2162491280 ps
CPU time 55.63 seconds
Started Jun 22 05:02:32 PM PDT 24
Finished Jun 22 05:03:28 PM PDT 24
Peak memory 249264 kb
Host smart-1789562e-9006-48ed-b2d7-65b34df2a707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28863
68407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2886368407
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1254584248
Short name T54
Test name
Test status
Simulation time 179157246 ps
CPU time 13.51 seconds
Started Jun 22 05:02:22 PM PDT 24
Finished Jun 22 05:02:36 PM PDT 24
Peak memory 248004 kb
Host smart-1d0ecb22-986f-4c2f-93f8-7c56639cbf63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12545
84248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1254584248
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3760959537
Short name T475
Test name
Test status
Simulation time 509958498 ps
CPU time 16.93 seconds
Started Jun 22 05:02:32 PM PDT 24
Finished Jun 22 05:02:50 PM PDT 24
Peak memory 256332 kb
Host smart-af0c06cc-9a55-489a-bf59-94b41e9f5af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37609
59537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3760959537
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1133184823
Short name T633
Test name
Test status
Simulation time 18512603583 ps
CPU time 1515.85 seconds
Started Jun 22 05:02:29 PM PDT 24
Finished Jun 22 05:27:45 PM PDT 24
Peak memory 289912 kb
Host smart-6635ffcd-f480-4842-a930-26561841edf5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133184823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1133184823
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2262461179
Short name T610
Test name
Test status
Simulation time 45150953517 ps
CPU time 986.67 seconds
Started Jun 22 05:02:29 PM PDT 24
Finished Jun 22 05:18:56 PM PDT 24
Peak memory 273068 kb
Host smart-0e6acc0a-92f9-4175-8c18-455b9a73d184
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262461179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2262461179
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1001694962
Short name T417
Test name
Test status
Simulation time 9893393362 ps
CPU time 270.29 seconds
Started Jun 22 05:02:29 PM PDT 24
Finished Jun 22 05:07:00 PM PDT 24
Peak memory 251396 kb
Host smart-2d98abb3-6e08-4784-8ac2-81d81c2d9c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10016
94962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1001694962
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.145855858
Short name T85
Test name
Test status
Simulation time 806409115 ps
CPU time 34.21 seconds
Started Jun 22 05:02:26 PM PDT 24
Finished Jun 22 05:03:01 PM PDT 24
Peak memory 247796 kb
Host smart-2eaf331a-23fe-4a52-88a0-e3feb5f40d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14585
5858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.145855858
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1610778543
Short name T364
Test name
Test status
Simulation time 76173832891 ps
CPU time 1112.46 seconds
Started Jun 22 05:02:27 PM PDT 24
Finished Jun 22 05:21:01 PM PDT 24
Peak memory 272416 kb
Host smart-68094d1a-671b-4551-b90e-ee96e9de4442
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610778543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1610778543
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2344452011
Short name T488
Test name
Test status
Simulation time 60706815603 ps
CPU time 1219.56 seconds
Started Jun 22 05:02:25 PM PDT 24
Finished Jun 22 05:22:45 PM PDT 24
Peak memory 283020 kb
Host smart-a0b7c0ee-4a81-42d3-818f-d230a7d29db3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344452011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2344452011
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3729296041
Short name T393
Test name
Test status
Simulation time 502688096 ps
CPU time 14.52 seconds
Started Jun 22 05:02:20 PM PDT 24
Finished Jun 22 05:02:36 PM PDT 24
Peak memory 249040 kb
Host smart-362b4497-a63b-4a18-b9b8-2e5abba5c0b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37292
96041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3729296041
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2354642222
Short name T456
Test name
Test status
Simulation time 1715612418 ps
CPU time 29.06 seconds
Started Jun 22 05:02:24 PM PDT 24
Finished Jun 22 05:02:53 PM PDT 24
Peak memory 256092 kb
Host smart-12d1fac3-f72c-4805-beb0-134f224245bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23546
42222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2354642222
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1040592050
Short name T462
Test name
Test status
Simulation time 154076915 ps
CPU time 2.8 seconds
Started Jun 22 05:02:22 PM PDT 24
Finished Jun 22 05:02:26 PM PDT 24
Peak memory 240788 kb
Host smart-5000cbca-7b3a-4013-b2f1-46ee24a71ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10405
92050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1040592050
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3795130090
Short name T644
Test name
Test status
Simulation time 1427192854 ps
CPU time 45.92 seconds
Started Jun 22 05:02:29 PM PDT 24
Finished Jun 22 05:03:16 PM PDT 24
Peak memory 257244 kb
Host smart-6f814532-65df-4e5a-b1d0-0b125e83935e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37951
30090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3795130090
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.889411490
Short name T518
Test name
Test status
Simulation time 74575868528 ps
CPU time 1581 seconds
Started Jun 22 05:02:23 PM PDT 24
Finished Jun 22 05:28:45 PM PDT 24
Peak memory 290024 kb
Host smart-25bb06b1-6450-41f3-8835-7f8332d0bf73
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889411490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.889411490
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3322360326
Short name T248
Test name
Test status
Simulation time 284598951878 ps
CPU time 4677.14 seconds
Started Jun 22 05:02:28 PM PDT 24
Finished Jun 22 06:20:26 PM PDT 24
Peak memory 306536 kb
Host smart-ebe7ba97-adef-4511-bb7f-dad5015f4f85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322360326 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3322360326
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3193055745
Short name T16
Test name
Test status
Simulation time 51950980186 ps
CPU time 1308.69 seconds
Started Jun 22 05:02:30 PM PDT 24
Finished Jun 22 05:24:20 PM PDT 24
Peak memory 285496 kb
Host smart-1a6f06ac-2a6d-470e-9d3f-14fa3238fb23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193055745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3193055745
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3123195895
Short name T424
Test name
Test status
Simulation time 2038537568 ps
CPU time 154.24 seconds
Started Jun 22 05:02:31 PM PDT 24
Finished Jun 22 05:05:07 PM PDT 24
Peak memory 257152 kb
Host smart-ecffdd86-16b5-43d5-8c0f-602553cbbb58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31231
95895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3123195895
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.328488034
Short name T519
Test name
Test status
Simulation time 401075848 ps
CPU time 39.93 seconds
Started Jun 22 05:02:30 PM PDT 24
Finished Jun 22 05:03:10 PM PDT 24
Peak memory 255956 kb
Host smart-0a829949-fbcd-4ef8-8273-b8a03e89da26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32848
8034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.328488034
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.930991375
Short name T72
Test name
Test status
Simulation time 24737110849 ps
CPU time 1079.19 seconds
Started Jun 22 05:02:30 PM PDT 24
Finished Jun 22 05:20:30 PM PDT 24
Peak memory 290012 kb
Host smart-14d429cf-9bf1-49f6-8a2f-b852b88218de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930991375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.930991375
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2321212810
Short name T476
Test name
Test status
Simulation time 65903175711 ps
CPU time 349.59 seconds
Started Jun 22 05:02:29 PM PDT 24
Finished Jun 22 05:08:19 PM PDT 24
Peak memory 248276 kb
Host smart-f6d729e4-b4ab-43c0-a3fb-90d45aee7ffe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321212810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2321212810
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3627141153
Short name T568
Test name
Test status
Simulation time 775461295 ps
CPU time 28.85 seconds
Started Jun 22 05:02:34 PM PDT 24
Finished Jun 22 05:03:04 PM PDT 24
Peak memory 256604 kb
Host smart-69524480-6ba5-458e-b0b5-1d871b43779c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36271
41153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3627141153
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2269130225
Short name T577
Test name
Test status
Simulation time 612088697 ps
CPU time 5.39 seconds
Started Jun 22 05:02:29 PM PDT 24
Finished Jun 22 05:02:35 PM PDT 24
Peak memory 247748 kb
Host smart-214a776b-af37-4662-885f-46c580ef5fff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22691
30225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2269130225
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3052384080
Short name T415
Test name
Test status
Simulation time 95661790 ps
CPU time 4.71 seconds
Started Jun 22 05:02:30 PM PDT 24
Finished Jun 22 05:02:35 PM PDT 24
Peak memory 239776 kb
Host smart-22038faa-8280-43c9-8a06-c05c4a167e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30523
84080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3052384080
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1619663586
Short name T406
Test name
Test status
Simulation time 220713461 ps
CPU time 8.1 seconds
Started Jun 22 05:02:26 PM PDT 24
Finished Jun 22 05:02:35 PM PDT 24
Peak memory 251408 kb
Host smart-fdf14efb-84a1-4bc7-9e68-792c56d3a6fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16196
63586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1619663586
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.837565477
Short name T23
Test name
Test status
Simulation time 9871982100 ps
CPU time 788.32 seconds
Started Jun 22 05:02:30 PM PDT 24
Finished Jun 22 05:15:40 PM PDT 24
Peak memory 281944 kb
Host smart-e14fdd40-2757-45cf-8b15-74eca0b69276
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837565477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.837565477
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.1813919191
Short name T265
Test name
Test status
Simulation time 63644078057 ps
CPU time 1726.33 seconds
Started Jun 22 05:02:32 PM PDT 24
Finished Jun 22 05:31:20 PM PDT 24
Peak memory 305420 kb
Host smart-f3ba9cf5-0df0-4cee-9585-05559f79c3c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813919191 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.1813919191
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.477560748
Short name T277
Test name
Test status
Simulation time 45833471607 ps
CPU time 2726.66 seconds
Started Jun 22 05:02:30 PM PDT 24
Finished Jun 22 05:47:58 PM PDT 24
Peak memory 288212 kb
Host smart-ad0955fa-881c-4632-b6f2-9159a8ad6dfb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477560748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.477560748
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.4060384565
Short name T422
Test name
Test status
Simulation time 21162207997 ps
CPU time 87.32 seconds
Started Jun 22 05:02:34 PM PDT 24
Finished Jun 22 05:04:01 PM PDT 24
Peak memory 250164 kb
Host smart-91357c7c-5665-4cec-b59e-882df6acda5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40603
84565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.4060384565
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1125693618
Short name T562
Test name
Test status
Simulation time 2013729826 ps
CPU time 30.79 seconds
Started Jun 22 05:02:34 PM PDT 24
Finished Jun 22 05:03:06 PM PDT 24
Peak memory 256304 kb
Host smart-82c6de58-a35a-43bb-b8da-703b254b8a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11256
93618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1125693618
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3494474642
Short name T447
Test name
Test status
Simulation time 19695573280 ps
CPU time 1120.22 seconds
Started Jun 22 05:02:30 PM PDT 24
Finished Jun 22 05:21:12 PM PDT 24
Peak memory 265552 kb
Host smart-0358111e-2746-42dc-a45a-4677b5b2b4a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494474642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3494474642
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.368699449
Short name T641
Test name
Test status
Simulation time 64795922898 ps
CPU time 453.52 seconds
Started Jun 22 05:02:30 PM PDT 24
Finished Jun 22 05:10:05 PM PDT 24
Peak memory 248360 kb
Host smart-e526b802-2dd4-4adb-beaf-bef0ba7f5864
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368699449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.368699449
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.253968231
Short name T602
Test name
Test status
Simulation time 2446799768 ps
CPU time 33.93 seconds
Started Jun 22 05:02:28 PM PDT 24
Finished Jun 22 05:03:03 PM PDT 24
Peak memory 249228 kb
Host smart-c6b72042-f338-4f8a-a211-6b1ed62cb1c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25396
8231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.253968231
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3221203069
Short name T114
Test name
Test status
Simulation time 226332301 ps
CPU time 5.2 seconds
Started Jun 22 05:02:31 PM PDT 24
Finished Jun 22 05:02:38 PM PDT 24
Peak memory 239576 kb
Host smart-3adafb33-26bf-4b61-8677-b01b7dda9656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32212
03069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3221203069
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1264979273
Short name T260
Test name
Test status
Simulation time 854239260 ps
CPU time 30.9 seconds
Started Jun 22 05:02:34 PM PDT 24
Finished Jun 22 05:03:05 PM PDT 24
Peak memory 247992 kb
Host smart-780c7084-eb27-49e1-ad0d-84b5ce0f0946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12649
79273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1264979273
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1858344580
Short name T448
Test name
Test status
Simulation time 3121060233 ps
CPU time 52.94 seconds
Started Jun 22 05:02:32 PM PDT 24
Finished Jun 22 05:03:26 PM PDT 24
Peak memory 256652 kb
Host smart-b794b6ac-0063-409e-b32a-79dc59bcc542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18583
44580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1858344580
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2387072842
Short name T115
Test name
Test status
Simulation time 71255617893 ps
CPU time 3335.37 seconds
Started Jun 22 05:02:31 PM PDT 24
Finished Jun 22 05:58:08 PM PDT 24
Peak memory 298388 kb
Host smart-bdd01bc2-c029-43c8-8538-79e2b58a1a02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387072842 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2387072842
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1194806877
Short name T684
Test name
Test status
Simulation time 18174534026 ps
CPU time 527.15 seconds
Started Jun 22 05:02:32 PM PDT 24
Finished Jun 22 05:11:20 PM PDT 24
Peak memory 272680 kb
Host smart-7d4be34f-87c7-47c8-944b-b77441996b73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194806877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1194806877
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2219969049
Short name T59
Test name
Test status
Simulation time 423624198 ps
CPU time 19.85 seconds
Started Jun 22 05:02:30 PM PDT 24
Finished Jun 22 05:02:51 PM PDT 24
Peak memory 256560 kb
Host smart-cfdaab52-4cb5-49a5-938e-8aec08f0e8e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22199
69049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2219969049
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2560623505
Short name T423
Test name
Test status
Simulation time 620606140 ps
CPU time 19.4 seconds
Started Jun 22 05:02:34 PM PDT 24
Finished Jun 22 05:02:54 PM PDT 24
Peak memory 249392 kb
Host smart-5c4a2cf8-55a6-4f79-b895-b55d8d939c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25606
23505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2560623505
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3904135556
Short name T337
Test name
Test status
Simulation time 34408352528 ps
CPU time 671.26 seconds
Started Jun 22 05:02:34 PM PDT 24
Finished Jun 22 05:13:46 PM PDT 24
Peak memory 271980 kb
Host smart-8fda330f-2330-4cc9-b9a5-c2f1e6ac87d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904135556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3904135556
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.334320639
Short name T244
Test name
Test status
Simulation time 212278187839 ps
CPU time 3282.31 seconds
Started Jun 22 05:02:31 PM PDT 24
Finished Jun 22 05:57:15 PM PDT 24
Peak memory 289784 kb
Host smart-f7f252f8-4db6-430f-b827-f7f266f94ee3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334320639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.334320639
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2251361574
Short name T442
Test name
Test status
Simulation time 493677586 ps
CPU time 10.04 seconds
Started Jun 22 05:02:32 PM PDT 24
Finished Jun 22 05:02:43 PM PDT 24
Peak memory 256284 kb
Host smart-39a83032-931d-4bba-b0bd-297d31bbc36d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22513
61574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2251361574
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3031756596
Short name T468
Test name
Test status
Simulation time 1037359579 ps
CPU time 19.8 seconds
Started Jun 22 05:02:34 PM PDT 24
Finished Jun 22 05:02:54 PM PDT 24
Peak memory 256028 kb
Host smart-e73b9221-62c1-4d2f-8114-a03f7c3cc3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30317
56596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3031756596
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.4163055945
Short name T140
Test name
Test status
Simulation time 18514514253 ps
CPU time 71.32 seconds
Started Jun 22 05:02:31 PM PDT 24
Finished Jun 22 05:03:44 PM PDT 24
Peak memory 249420 kb
Host smart-8b19835c-dc94-44f0-9bb8-a8e4b0b58dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41630
55945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.4163055945
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3161530557
Short name T547
Test name
Test status
Simulation time 1377496502 ps
CPU time 19.72 seconds
Started Jun 22 05:02:30 PM PDT 24
Finished Jun 22 05:02:51 PM PDT 24
Peak memory 249088 kb
Host smart-5d4bc4a1-b28d-4779-b2b7-f5a4939eaa28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31615
30557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3161530557
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3218509393
Short name T258
Test name
Test status
Simulation time 129034658906 ps
CPU time 1946.47 seconds
Started Jun 22 05:02:30 PM PDT 24
Finished Jun 22 05:34:58 PM PDT 24
Peak memory 289316 kb
Host smart-cb44da2d-8f73-4d2a-9fc0-d44a78054e22
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218509393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3218509393
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2846170393
Short name T696
Test name
Test status
Simulation time 431109738966 ps
CPU time 2137.73 seconds
Started Jun 22 05:02:39 PM PDT 24
Finished Jun 22 05:38:17 PM PDT 24
Peak memory 286712 kb
Host smart-f6df25fc-3ee4-4c69-8fb5-eb67fe34d05f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846170393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2846170393
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.36642885
Short name T531
Test name
Test status
Simulation time 2441927784 ps
CPU time 40.74 seconds
Started Jun 22 05:02:35 PM PDT 24
Finished Jun 22 05:03:17 PM PDT 24
Peak memory 257276 kb
Host smart-215dcc2c-b6e6-4782-b848-25542b637771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36642
885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.36642885
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.325395638
Short name T649
Test name
Test status
Simulation time 374103173 ps
CPU time 32.47 seconds
Started Jun 22 05:02:45 PM PDT 24
Finished Jun 22 05:03:18 PM PDT 24
Peak memory 256328 kb
Host smart-93bc86f4-2f6c-4980-8ea2-1d8bd54b71f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32539
5638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.325395638
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2084685730
Short name T536
Test name
Test status
Simulation time 50411663318 ps
CPU time 1021.76 seconds
Started Jun 22 05:02:35 PM PDT 24
Finished Jun 22 05:19:38 PM PDT 24
Peak memory 273024 kb
Host smart-9bd66c38-e92e-43e5-a20e-b52e8af20f5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084685730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2084685730
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2522645307
Short name T658
Test name
Test status
Simulation time 50578622525 ps
CPU time 1033.88 seconds
Started Jun 22 05:02:39 PM PDT 24
Finished Jun 22 05:19:53 PM PDT 24
Peak memory 272788 kb
Host smart-8cc0e72a-417f-42f0-bf55-47085b28606b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522645307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2522645307
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2154698095
Short name T143
Test name
Test status
Simulation time 15650802867 ps
CPU time 315.39 seconds
Started Jun 22 05:02:38 PM PDT 24
Finished Jun 22 05:07:53 PM PDT 24
Peak memory 247564 kb
Host smart-ab87be6f-80e0-4931-8bd7-51bc8a46303d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154698095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2154698095
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2288276570
Short name T683
Test name
Test status
Simulation time 116458467 ps
CPU time 9.44 seconds
Started Jun 22 05:02:36 PM PDT 24
Finished Jun 22 05:02:46 PM PDT 24
Peak memory 251584 kb
Host smart-d1510dcc-ce95-41a4-8dfb-0efa75f6c256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22882
76570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2288276570
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2960826955
Short name T669
Test name
Test status
Simulation time 520156890 ps
CPU time 9.07 seconds
Started Jun 22 05:02:38 PM PDT 24
Finished Jun 22 05:02:48 PM PDT 24
Peak memory 253688 kb
Host smart-a0702c9d-e1ae-48f8-9cb4-80072d0de2cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29608
26955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2960826955
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3911722169
Short name T500
Test name
Test status
Simulation time 167374896 ps
CPU time 17.97 seconds
Started Jun 22 05:02:38 PM PDT 24
Finished Jun 22 05:02:57 PM PDT 24
Peak memory 255908 kb
Host smart-0ac0e4fe-88c2-4d6c-84b9-4213b83ae144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39117
22169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3911722169
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1945796116
Short name T377
Test name
Test status
Simulation time 291575999 ps
CPU time 9.82 seconds
Started Jun 22 05:02:31 PM PDT 24
Finished Jun 22 05:02:42 PM PDT 24
Peak memory 248964 kb
Host smart-dd185f34-f7b9-4e91-8a88-6b825302cd1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19457
96116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1945796116
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.115368147
Short name T689
Test name
Test status
Simulation time 5720764940 ps
CPU time 87.68 seconds
Started Jun 22 05:02:35 PM PDT 24
Finished Jun 22 05:04:03 PM PDT 24
Peak memory 257064 kb
Host smart-0919c1d4-93bb-4203-8d27-f8da75ab57f4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115368147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.115368147
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2336420042
Short name T225
Test name
Test status
Simulation time 43580055 ps
CPU time 2.32 seconds
Started Jun 22 05:01:42 PM PDT 24
Finished Jun 22 05:01:45 PM PDT 24
Peak memory 249264 kb
Host smart-9a2b4edf-74b8-437c-b629-d1eee56a4802
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2336420042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2336420042
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.307586059
Short name T43
Test name
Test status
Simulation time 12625234176 ps
CPU time 680.15 seconds
Started Jun 22 05:01:53 PM PDT 24
Finished Jun 22 05:13:14 PM PDT 24
Peak memory 266588 kb
Host smart-6c83275a-8c4f-4d6a-95bf-72c36ebbbd8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307586059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.307586059
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2148493679
Short name T407
Test name
Test status
Simulation time 364287245 ps
CPU time 17.97 seconds
Started Jun 22 05:01:49 PM PDT 24
Finished Jun 22 05:02:08 PM PDT 24
Peak memory 249060 kb
Host smart-3d24f73c-00f0-4cb5-922b-823afcfaf30c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2148493679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2148493679
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.814208788
Short name T429
Test name
Test status
Simulation time 566380174 ps
CPU time 12.38 seconds
Started Jun 22 05:01:51 PM PDT 24
Finished Jun 22 05:02:04 PM PDT 24
Peak memory 249172 kb
Host smart-903f7094-2d81-4722-bfa1-609547804535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81420
8788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.814208788
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3496715729
Short name T76
Test name
Test status
Simulation time 317651379 ps
CPU time 29.23 seconds
Started Jun 22 05:01:41 PM PDT 24
Finished Jun 22 05:02:11 PM PDT 24
Peak memory 256232 kb
Host smart-4af47f41-da29-4369-9c01-2d3bedc55e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34967
15729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3496715729
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1805224291
Short name T628
Test name
Test status
Simulation time 97196286291 ps
CPU time 2379.6 seconds
Started Jun 22 05:01:47 PM PDT 24
Finished Jun 22 05:41:28 PM PDT 24
Peak memory 287696 kb
Host smart-9fc5f9ae-9765-43d6-afff-727fdef12d02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805224291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1805224291
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3138101533
Short name T284
Test name
Test status
Simulation time 8118046183 ps
CPU time 325.69 seconds
Started Jun 22 05:01:55 PM PDT 24
Finished Jun 22 05:07:22 PM PDT 24
Peak memory 248860 kb
Host smart-bdaacaaf-cdaf-4fd6-bd93-4a7698e15095
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138101533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3138101533
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1669637888
Short name T565
Test name
Test status
Simulation time 3194994920 ps
CPU time 49.31 seconds
Started Jun 22 05:01:48 PM PDT 24
Finished Jun 22 05:02:38 PM PDT 24
Peak memory 249028 kb
Host smart-f04f8347-6be2-4714-b6bf-36cf7498c38b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16696
37888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1669637888
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1071915544
Short name T512
Test name
Test status
Simulation time 158607746 ps
CPU time 15.14 seconds
Started Jun 22 05:01:48 PM PDT 24
Finished Jun 22 05:02:04 PM PDT 24
Peak memory 255368 kb
Host smart-c2d59bf1-c4a2-42ce-91f2-29732ac87133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10719
15544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1071915544
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1390505707
Short name T13
Test name
Test status
Simulation time 877179454 ps
CPU time 11.13 seconds
Started Jun 22 05:01:42 PM PDT 24
Finished Jun 22 05:01:54 PM PDT 24
Peak memory 269168 kb
Host smart-921bf2ab-01f7-45eb-bd6b-3a13b9b21dec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1390505707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1390505707
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.127262517
Short name T239
Test name
Test status
Simulation time 4917470686 ps
CPU time 76.15 seconds
Started Jun 22 05:01:52 PM PDT 24
Finished Jun 22 05:03:09 PM PDT 24
Peak memory 256096 kb
Host smart-9fdd795f-ba16-42d2-aab4-c28662cc89a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12726
2517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.127262517
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1778539281
Short name T421
Test name
Test status
Simulation time 3754514715 ps
CPU time 60.45 seconds
Started Jun 22 05:01:35 PM PDT 24
Finished Jun 22 05:02:36 PM PDT 24
Peak memory 257120 kb
Host smart-b455acf2-340e-4a41-a6a1-220e468c49d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17785
39281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1778539281
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2462671161
Short name T520
Test name
Test status
Simulation time 14154811228 ps
CPU time 446.67 seconds
Started Jun 22 05:01:47 PM PDT 24
Finished Jun 22 05:09:14 PM PDT 24
Peak memory 257260 kb
Host smart-20fe4465-132f-4a8d-90ba-e70303a3b578
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462671161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2462671161
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3643839919
Short name T385
Test name
Test status
Simulation time 39163120233 ps
CPU time 918.96 seconds
Started Jun 22 05:02:35 PM PDT 24
Finished Jun 22 05:17:55 PM PDT 24
Peak memory 273044 kb
Host smart-8b9e7366-2df1-4c51-8e0f-ba2ca153ef5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643839919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3643839919
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1759409708
Short name T449
Test name
Test status
Simulation time 2347964325 ps
CPU time 48.41 seconds
Started Jun 22 05:02:36 PM PDT 24
Finished Jun 22 05:03:25 PM PDT 24
Peak memory 257272 kb
Host smart-44668395-3eb3-43eb-a314-0979fd4d59ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17594
09708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1759409708
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3182761376
Short name T375
Test name
Test status
Simulation time 494000059 ps
CPU time 16 seconds
Started Jun 22 05:02:35 PM PDT 24
Finished Jun 22 05:02:51 PM PDT 24
Peak memory 253596 kb
Host smart-fee13df6-26bf-4c8e-a3e3-7dc21d940ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31827
61376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3182761376
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.4066895014
Short name T716
Test name
Test status
Simulation time 83858664971 ps
CPU time 1335.41 seconds
Started Jun 22 05:02:37 PM PDT 24
Finished Jun 22 05:24:53 PM PDT 24
Peak memory 273664 kb
Host smart-815264bf-e852-485e-956d-30f9826d2ee9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066895014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.4066895014
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3661945528
Short name T611
Test name
Test status
Simulation time 37863551909 ps
CPU time 2391.77 seconds
Started Jun 22 05:02:35 PM PDT 24
Finished Jun 22 05:42:28 PM PDT 24
Peak memory 289640 kb
Host smart-63f90760-c77f-47d9-90da-e25602203045
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661945528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3661945528
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.4232105610
Short name T323
Test name
Test status
Simulation time 59131408645 ps
CPU time 600.04 seconds
Started Jun 22 05:02:38 PM PDT 24
Finished Jun 22 05:12:38 PM PDT 24
Peak memory 248272 kb
Host smart-5993d37e-c96c-4264-a0b3-4a8a9b5f6310
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232105610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.4232105610
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2192335582
Short name T585
Test name
Test status
Simulation time 413835679 ps
CPU time 15.47 seconds
Started Jun 22 05:02:36 PM PDT 24
Finished Jun 22 05:02:52 PM PDT 24
Peak memory 254428 kb
Host smart-fdc91eb5-e222-4811-847f-16b27ba8ee6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21923
35582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2192335582
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3381246385
Short name T522
Test name
Test status
Simulation time 688529112 ps
CPU time 13.41 seconds
Started Jun 22 05:02:39 PM PDT 24
Finished Jun 22 05:02:52 PM PDT 24
Peak memory 247884 kb
Host smart-5e68ae32-0176-4d4c-a66b-002897c0679e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33812
46385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3381246385
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.2901250424
Short name T483
Test name
Test status
Simulation time 214769553 ps
CPU time 14.88 seconds
Started Jun 22 05:02:39 PM PDT 24
Finished Jun 22 05:02:54 PM PDT 24
Peak memory 255592 kb
Host smart-b3d1986f-35e7-4c42-a658-83dd197fec01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29012
50424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2901250424
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3665510694
Short name T614
Test name
Test status
Simulation time 2751589390 ps
CPU time 36.59 seconds
Started Jun 22 05:02:36 PM PDT 24
Finished Jun 22 05:03:13 PM PDT 24
Peak memory 257264 kb
Host smart-8cfd3eeb-fd84-4d7d-985f-8c0faf111a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36655
10694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3665510694
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.355130184
Short name T690
Test name
Test status
Simulation time 344162148659 ps
CPU time 1434.49 seconds
Started Jun 22 05:02:35 PM PDT 24
Finished Jun 22 05:26:31 PM PDT 24
Peak memory 289584 kb
Host smart-80b60f1f-885c-40b8-8e49-62845814c17e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355130184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.355130184
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3542972001
Short name T111
Test name
Test status
Simulation time 202982006692 ps
CPU time 1734.4 seconds
Started Jun 22 05:02:42 PM PDT 24
Finished Jun 22 05:31:37 PM PDT 24
Peak memory 273092 kb
Host smart-4088b7c1-ef75-415a-b614-27608aa70495
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542972001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3542972001
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.179408240
Short name T538
Test name
Test status
Simulation time 2215355462 ps
CPU time 134.01 seconds
Started Jun 22 05:02:44 PM PDT 24
Finished Jun 22 05:04:58 PM PDT 24
Peak memory 249292 kb
Host smart-b6638fbf-8b9a-46f6-97be-73391e07591c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17940
8240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.179408240
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2611267335
Short name T75
Test name
Test status
Simulation time 1735340502 ps
CPU time 52.16 seconds
Started Jun 22 05:02:44 PM PDT 24
Finished Jun 22 05:03:36 PM PDT 24
Peak memory 257216 kb
Host smart-0daf31ae-d059-4c6e-bec2-4ce7a1542e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26112
67335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2611267335
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.2071755931
Short name T21
Test name
Test status
Simulation time 369241355963 ps
CPU time 2681.27 seconds
Started Jun 22 05:02:44 PM PDT 24
Finished Jun 22 05:47:26 PM PDT 24
Peak memory 290136 kb
Host smart-86893f45-5436-4ec1-8f99-7dbf87f9729c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071755931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2071755931
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.372646870
Short name T524
Test name
Test status
Simulation time 28208838707 ps
CPU time 1627.3 seconds
Started Jun 22 05:02:49 PM PDT 24
Finished Jun 22 05:29:56 PM PDT 24
Peak memory 273456 kb
Host smart-3083e26e-f5b3-4c86-bc75-ecaae9b68d55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372646870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.372646870
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1953508007
Short name T319
Test name
Test status
Simulation time 4189895052 ps
CPU time 163.35 seconds
Started Jun 22 05:02:44 PM PDT 24
Finished Jun 22 05:05:28 PM PDT 24
Peak memory 248628 kb
Host smart-6b000f34-09aa-4da3-b5f6-f1729b8addcd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953508007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1953508007
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.780841682
Short name T436
Test name
Test status
Simulation time 3386657026 ps
CPU time 51.24 seconds
Started Jun 22 05:02:47 PM PDT 24
Finished Jun 22 05:03:39 PM PDT 24
Peak memory 257348 kb
Host smart-a1cb367a-15c3-443b-80bc-7d600ea6fd1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78084
1682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.780841682
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1114488466
Short name T15
Test name
Test status
Simulation time 933083798 ps
CPU time 42.52 seconds
Started Jun 22 05:02:44 PM PDT 24
Finished Jun 22 05:03:27 PM PDT 24
Peak memory 249936 kb
Host smart-784478e9-875e-4db6-ad86-e336b8c02756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11144
88466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1114488466
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.691444479
Short name T541
Test name
Test status
Simulation time 695302416 ps
CPU time 43.51 seconds
Started Jun 22 05:02:45 PM PDT 24
Finished Jun 22 05:03:29 PM PDT 24
Peak memory 257256 kb
Host smart-5ef29bb3-4115-4952-b0f3-0c1dc36a7917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69144
4479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.691444479
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1368982051
Short name T262
Test name
Test status
Simulation time 9063291652 ps
CPU time 141.72 seconds
Started Jun 22 05:02:43 PM PDT 24
Finished Jun 22 05:05:05 PM PDT 24
Peak memory 257360 kb
Host smart-55cf45fd-cdc4-4491-b7c2-4719a093e3b9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368982051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1368982051
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1776346479
Short name T601
Test name
Test status
Simulation time 9582540244 ps
CPU time 1125.56 seconds
Started Jun 22 05:02:52 PM PDT 24
Finished Jun 22 05:21:38 PM PDT 24
Peak memory 286312 kb
Host smart-9a685cd0-6bf2-47ff-9ea8-4902c0ea49a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776346479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1776346479
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1067604840
Short name T288
Test name
Test status
Simulation time 11225471023 ps
CPU time 205.08 seconds
Started Jun 22 05:02:43 PM PDT 24
Finished Jun 22 05:06:08 PM PDT 24
Peak memory 257288 kb
Host smart-f0945cd5-00eb-46f8-b4b5-899890d98c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10676
04840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1067604840
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.4213419858
Short name T574
Test name
Test status
Simulation time 483256931 ps
CPU time 13.13 seconds
Started Jun 22 05:02:43 PM PDT 24
Finished Jun 22 05:02:57 PM PDT 24
Peak memory 254996 kb
Host smart-58f57403-c467-4064-ba98-8e78d65054d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42134
19858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.4213419858
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2582244023
Short name T308
Test name
Test status
Simulation time 101162833791 ps
CPU time 1612.6 seconds
Started Jun 22 05:02:52 PM PDT 24
Finished Jun 22 05:29:45 PM PDT 24
Peak memory 273868 kb
Host smart-8310a856-1fec-4217-8cd2-9c17b10f68a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582244023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2582244023
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2302385429
Short name T588
Test name
Test status
Simulation time 29799141492 ps
CPU time 739.06 seconds
Started Jun 22 05:02:52 PM PDT 24
Finished Jun 22 05:15:12 PM PDT 24
Peak memory 273548 kb
Host smart-260bb635-dbbc-4035-91cb-d989266ae4b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302385429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2302385429
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.998675896
Short name T134
Test name
Test status
Simulation time 356124923 ps
CPU time 10.14 seconds
Started Jun 22 05:02:42 PM PDT 24
Finished Jun 22 05:02:53 PM PDT 24
Peak memory 255360 kb
Host smart-3af61c49-10a6-4144-b088-546b452ff62f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99867
5896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.998675896
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.93411696
Short name T57
Test name
Test status
Simulation time 461666399 ps
CPU time 10.81 seconds
Started Jun 22 05:02:48 PM PDT 24
Finished Jun 22 05:02:59 PM PDT 24
Peak memory 249064 kb
Host smart-3241278e-574d-4b64-8edf-336c6f82a8fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93411
696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.93411696
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1436331180
Short name T566
Test name
Test status
Simulation time 1271453490 ps
CPU time 41.1 seconds
Started Jun 22 05:02:50 PM PDT 24
Finished Jun 22 05:03:31 PM PDT 24
Peak memory 257132 kb
Host smart-1e02aaf2-b82d-4c1c-b79a-922fefd5b189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14363
31180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1436331180
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1973523993
Short name T706
Test name
Test status
Simulation time 809156513 ps
CPU time 53.36 seconds
Started Jun 22 05:02:44 PM PDT 24
Finished Jun 22 05:03:38 PM PDT 24
Peak memory 257068 kb
Host smart-055ba1f0-e8dc-4e09-a5a4-26d983f7c8a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19735
23993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1973523993
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.434302392
Short name T384
Test name
Test status
Simulation time 72138152765 ps
CPU time 1989.7 seconds
Started Jun 22 05:02:53 PM PDT 24
Finished Jun 22 05:36:03 PM PDT 24
Peak memory 272920 kb
Host smart-8535ed92-995b-4e13-8bf0-cf138d7d98da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434302392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.434302392
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2073911696
Short name T290
Test name
Test status
Simulation time 2528310926 ps
CPU time 137.84 seconds
Started Jun 22 05:02:52 PM PDT 24
Finished Jun 22 05:05:10 PM PDT 24
Peak memory 257312 kb
Host smart-782b4c95-5f74-43ba-b6a8-c64b14a3c03c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20739
11696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2073911696
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2581293250
Short name T681
Test name
Test status
Simulation time 158615816 ps
CPU time 7.65 seconds
Started Jun 22 05:02:51 PM PDT 24
Finished Jun 22 05:02:59 PM PDT 24
Peak memory 249108 kb
Host smart-cbc38513-e680-429c-a99b-9b29605c8629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25812
93250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2581293250
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3172289859
Short name T694
Test name
Test status
Simulation time 166025066025 ps
CPU time 2507.58 seconds
Started Jun 22 05:02:51 PM PDT 24
Finished Jun 22 05:44:40 PM PDT 24
Peak memory 289452 kb
Host smart-e42a9bb6-13d4-497e-8227-d497afabf5e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172289859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3172289859
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.4102898783
Short name T715
Test name
Test status
Simulation time 20829963886 ps
CPU time 1374.49 seconds
Started Jun 22 05:02:52 PM PDT 24
Finished Jun 22 05:25:47 PM PDT 24
Peak memory 273756 kb
Host smart-7b752b25-dbad-4253-888e-77128cc65cc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102898783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.4102898783
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3190217218
Short name T640
Test name
Test status
Simulation time 16497613803 ps
CPU time 665.37 seconds
Started Jun 22 05:02:52 PM PDT 24
Finished Jun 22 05:13:58 PM PDT 24
Peak memory 248640 kb
Host smart-99d85663-c7e6-4353-bc60-36ed31268c9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190217218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3190217218
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.683680337
Short name T287
Test name
Test status
Simulation time 425491623 ps
CPU time 40.51 seconds
Started Jun 22 05:02:50 PM PDT 24
Finished Jun 22 05:03:31 PM PDT 24
Peak memory 249012 kb
Host smart-86bb8044-10b2-483f-9862-623b3c4a2e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68368
0337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.683680337
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2000629049
Short name T119
Test name
Test status
Simulation time 8842753216 ps
CPU time 54.62 seconds
Started Jun 22 05:02:52 PM PDT 24
Finished Jun 22 05:03:48 PM PDT 24
Peak memory 256196 kb
Host smart-ea8c9bd2-0d45-4ccc-a415-ed747cc03a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20006
29049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2000629049
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1759733890
Short name T67
Test name
Test status
Simulation time 499215642 ps
CPU time 31.2 seconds
Started Jun 22 05:02:53 PM PDT 24
Finished Jun 22 05:03:24 PM PDT 24
Peak memory 249036 kb
Host smart-4fd1c063-825d-4de8-b908-30847083fe66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17597
33890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1759733890
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.4096865769
Short name T452
Test name
Test status
Simulation time 820451352 ps
CPU time 20.02 seconds
Started Jun 22 05:02:53 PM PDT 24
Finished Jun 22 05:03:13 PM PDT 24
Peak memory 249020 kb
Host smart-49360e83-9d6b-40ac-a0e2-0e2d44bcd080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40968
65769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.4096865769
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2378781306
Short name T17
Test name
Test status
Simulation time 17158311377 ps
CPU time 561.2 seconds
Started Jun 22 05:02:53 PM PDT 24
Finished Jun 22 05:12:15 PM PDT 24
Peak memory 257356 kb
Host smart-e8dcbe85-6386-4407-8374-36ec8178d149
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378781306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2378781306
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.2348418623
Short name T250
Test name
Test status
Simulation time 20270613141 ps
CPU time 1234.63 seconds
Started Jun 22 05:02:53 PM PDT 24
Finished Jun 22 05:23:28 PM PDT 24
Peak memory 273736 kb
Host smart-ef2f107f-5b71-4416-b108-83734820d158
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348418623 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.2348418623
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2669873878
Short name T127
Test name
Test status
Simulation time 24287880124 ps
CPU time 1329.57 seconds
Started Jun 22 05:03:00 PM PDT 24
Finished Jun 22 05:25:10 PM PDT 24
Peak memory 273700 kb
Host smart-94d7c881-d5a6-4b35-8e68-3adfbe399c80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669873878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2669873878
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1991995995
Short name T431
Test name
Test status
Simulation time 11002246626 ps
CPU time 177.49 seconds
Started Jun 22 05:03:02 PM PDT 24
Finished Jun 22 05:06:00 PM PDT 24
Peak memory 251344 kb
Host smart-9f91c4dd-2502-4039-a2a6-868c8c04dfe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19919
95995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1991995995
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.4001344974
Short name T434
Test name
Test status
Simulation time 407471108 ps
CPU time 30.56 seconds
Started Jun 22 05:03:03 PM PDT 24
Finished Jun 22 05:03:34 PM PDT 24
Peak memory 249212 kb
Host smart-54c4020c-9cbb-42a2-b732-33f63a1744ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40013
44974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.4001344974
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.356686942
Short name T334
Test name
Test status
Simulation time 19382912937 ps
CPU time 855.97 seconds
Started Jun 22 05:03:02 PM PDT 24
Finished Jun 22 05:17:19 PM PDT 24
Peak memory 267528 kb
Host smart-a6c39f35-ddc4-4bc7-b6cb-7afd4f38e692
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356686942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.356686942
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1767341260
Short name T398
Test name
Test status
Simulation time 24512918059 ps
CPU time 1473.68 seconds
Started Jun 22 05:03:02 PM PDT 24
Finished Jun 22 05:27:36 PM PDT 24
Peak memory 265552 kb
Host smart-8a3aa2e6-1ffe-423e-b24a-6eb132f0b1f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767341260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1767341260
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2933870366
Short name T303
Test name
Test status
Simulation time 66964673543 ps
CPU time 220.59 seconds
Started Jun 22 05:03:01 PM PDT 24
Finished Jun 22 05:06:42 PM PDT 24
Peak memory 248600 kb
Host smart-21636281-53af-47a4-a83a-ea7faf71ad5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933870366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2933870366
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3354853715
Short name T371
Test name
Test status
Simulation time 2067601886 ps
CPU time 35.65 seconds
Started Jun 22 05:02:51 PM PDT 24
Finished Jun 22 05:03:27 PM PDT 24
Peak memory 249160 kb
Host smart-c2c41115-6a74-4946-8ccc-820207b3d5fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33548
53715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3354853715
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3802890489
Short name T713
Test name
Test status
Simulation time 409500455 ps
CPU time 40.99 seconds
Started Jun 22 05:02:51 PM PDT 24
Finished Jun 22 05:03:32 PM PDT 24
Peak memory 255560 kb
Host smart-227faa99-e13c-455a-961e-09c4ac0c7e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38028
90489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3802890489
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3067252933
Short name T497
Test name
Test status
Simulation time 388861260 ps
CPU time 23.81 seconds
Started Jun 22 05:03:03 PM PDT 24
Finished Jun 22 05:03:27 PM PDT 24
Peak memory 249104 kb
Host smart-47de81bd-f6cb-4acb-8a18-ec56edb4251d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30672
52933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3067252933
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3604111887
Short name T390
Test name
Test status
Simulation time 517559586 ps
CPU time 35.39 seconds
Started Jun 22 05:02:52 PM PDT 24
Finished Jun 22 05:03:28 PM PDT 24
Peak memory 256196 kb
Host smart-a576de1c-2cab-40d9-a189-3df6eabad89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36041
11887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3604111887
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2532134592
Short name T477
Test name
Test status
Simulation time 25600296097 ps
CPU time 607.53 seconds
Started Jun 22 05:03:03 PM PDT 24
Finished Jun 22 05:13:11 PM PDT 24
Peak memory 272908 kb
Host smart-697de91d-4b55-461b-82e4-0d97057a3cfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532134592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2532134592
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3952864978
Short name T35
Test name
Test status
Simulation time 411113789 ps
CPU time 21.15 seconds
Started Jun 22 05:03:01 PM PDT 24
Finished Jun 22 05:03:23 PM PDT 24
Peak memory 256968 kb
Host smart-c39a3ecb-93eb-4622-a3e4-712d0e865585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39528
64978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3952864978
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2735652128
Short name T480
Test name
Test status
Simulation time 89233005 ps
CPU time 10.59 seconds
Started Jun 22 05:03:03 PM PDT 24
Finished Jun 22 05:03:14 PM PDT 24
Peak memory 249120 kb
Host smart-6b553944-7441-453a-99e1-8fbef8691b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27356
52128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2735652128
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1516894354
Short name T276
Test name
Test status
Simulation time 113000813041 ps
CPU time 1419.47 seconds
Started Jun 22 05:03:02 PM PDT 24
Finished Jun 22 05:26:42 PM PDT 24
Peak memory 273140 kb
Host smart-a74132ef-83f5-404b-b470-d0f910aabfc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516894354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1516894354
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.651609798
Short name T110
Test name
Test status
Simulation time 6312148102 ps
CPU time 133.34 seconds
Started Jun 22 05:03:03 PM PDT 24
Finished Jun 22 05:05:17 PM PDT 24
Peak memory 247736 kb
Host smart-c89cc893-c6be-4119-8bed-6ab745f206a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651609798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.651609798
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.2264116600
Short name T625
Test name
Test status
Simulation time 3556194886 ps
CPU time 49.96 seconds
Started Jun 22 05:03:02 PM PDT 24
Finished Jun 22 05:03:52 PM PDT 24
Peak memory 249172 kb
Host smart-4a081583-7aaf-4425-aba9-24d08288bbe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22641
16600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2264116600
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.3026285366
Short name T241
Test name
Test status
Simulation time 197130181 ps
CPU time 20.19 seconds
Started Jun 22 05:03:02 PM PDT 24
Finished Jun 22 05:03:22 PM PDT 24
Peak memory 256088 kb
Host smart-d8a27a7c-122a-4691-8724-f6098b6feb37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30262
85366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3026285366
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.4123798848
Short name T399
Test name
Test status
Simulation time 169685849 ps
CPU time 18.09 seconds
Started Jun 22 05:03:01 PM PDT 24
Finished Jun 22 05:03:20 PM PDT 24
Peak memory 247860 kb
Host smart-e7e8da21-c0da-484a-9308-5aa5c909cd2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41237
98848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.4123798848
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1497220916
Short name T626
Test name
Test status
Simulation time 822927700 ps
CPU time 55.18 seconds
Started Jun 22 05:03:02 PM PDT 24
Finished Jun 22 05:03:58 PM PDT 24
Peak memory 256860 kb
Host smart-68590799-acea-44ac-b63d-a05e5b33176c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14972
20916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1497220916
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.4030820714
Short name T128
Test name
Test status
Simulation time 46547855141 ps
CPU time 2510.24 seconds
Started Jun 22 05:03:00 PM PDT 24
Finished Jun 22 05:44:51 PM PDT 24
Peak memory 289744 kb
Host smart-ff2b94c5-09f3-4974-81eb-97419beedd4a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030820714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.4030820714
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3433964858
Short name T135
Test name
Test status
Simulation time 19420125861 ps
CPU time 366.43 seconds
Started Jun 22 05:03:04 PM PDT 24
Finished Jun 22 05:09:11 PM PDT 24
Peak memory 266696 kb
Host smart-6b3b01cc-664e-4fb6-bdb4-f4f8b8caae63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433964858 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3433964858
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1578920396
Short name T99
Test name
Test status
Simulation time 55202094563 ps
CPU time 3131.19 seconds
Started Jun 22 05:03:09 PM PDT 24
Finished Jun 22 05:55:21 PM PDT 24
Peak memory 289664 kb
Host smart-7c0dc52f-efd6-4c69-a6a0-00fa76ce646b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578920396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1578920396
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.812325564
Short name T402
Test name
Test status
Simulation time 60450811 ps
CPU time 7.05 seconds
Started Jun 22 05:03:11 PM PDT 24
Finished Jun 22 05:03:18 PM PDT 24
Peak memory 253204 kb
Host smart-c854832c-d569-41d5-9b11-5799b014f145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81232
5564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.812325564
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3982483014
Short name T708
Test name
Test status
Simulation time 52449455794 ps
CPU time 2931.25 seconds
Started Jun 22 05:03:09 PM PDT 24
Finished Jun 22 05:52:01 PM PDT 24
Peak memory 281948 kb
Host smart-3e52cc8c-5c39-40e9-8243-b8859fbbcd90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982483014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3982483014
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.4192891316
Short name T592
Test name
Test status
Simulation time 34713256581 ps
CPU time 2063.24 seconds
Started Jun 22 05:03:08 PM PDT 24
Finished Jun 22 05:37:32 PM PDT 24
Peak memory 287808 kb
Host smart-98fe3d13-c891-4819-9567-61bb3e975fdc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192891316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.4192891316
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1316532982
Short name T296
Test name
Test status
Simulation time 13551998031 ps
CPU time 515.64 seconds
Started Jun 22 05:03:09 PM PDT 24
Finished Jun 22 05:11:45 PM PDT 24
Peak memory 256612 kb
Host smart-28206479-ed24-488c-aa3a-2050ab01ba7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316532982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1316532982
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2843260065
Short name T240
Test name
Test status
Simulation time 140152115 ps
CPU time 13.92 seconds
Started Jun 22 05:03:01 PM PDT 24
Finished Jun 22 05:03:15 PM PDT 24
Peak memory 256524 kb
Host smart-3ec9142c-7e0f-4b9b-b6a5-b2741ce5e917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28432
60065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2843260065
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.237184821
Short name T619
Test name
Test status
Simulation time 667738902 ps
CPU time 9.62 seconds
Started Jun 22 05:03:08 PM PDT 24
Finished Jun 22 05:03:18 PM PDT 24
Peak memory 252988 kb
Host smart-f20c78b6-3470-44ec-bcaa-d51517bca743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23718
4821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.237184821
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2878822341
Short name T593
Test name
Test status
Simulation time 199993806 ps
CPU time 26.35 seconds
Started Jun 22 05:03:11 PM PDT 24
Finished Jun 22 05:03:38 PM PDT 24
Peak memory 249008 kb
Host smart-7bd0505e-b180-48b0-9ae7-6d4c8268d208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28788
22341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2878822341
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.397578014
Short name T581
Test name
Test status
Simulation time 381954290 ps
CPU time 37.92 seconds
Started Jun 22 05:03:01 PM PDT 24
Finished Jun 22 05:03:39 PM PDT 24
Peak memory 256316 kb
Host smart-92eecb92-31c7-4638-ab3c-30da1258becc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39757
8014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.397578014
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1606296511
Short name T120
Test name
Test status
Simulation time 785190634892 ps
CPU time 2877.4 seconds
Started Jun 22 05:03:08 PM PDT 24
Finished Jun 22 05:51:06 PM PDT 24
Peak memory 290308 kb
Host smart-e2b28548-4391-417e-8d85-514ee0cc6713
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606296511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1606296511
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2426973651
Short name T530
Test name
Test status
Simulation time 150296329055 ps
CPU time 2270.63 seconds
Started Jun 22 05:03:11 PM PDT 24
Finished Jun 22 05:41:02 PM PDT 24
Peak memory 289564 kb
Host smart-dac6c42d-4520-4fce-9045-042ef969afa6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426973651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2426973651
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3147275670
Short name T396
Test name
Test status
Simulation time 8305053203 ps
CPU time 128.82 seconds
Started Jun 22 05:03:10 PM PDT 24
Finished Jun 22 05:05:19 PM PDT 24
Peak memory 249228 kb
Host smart-5d464d84-7d7e-497f-ba96-5f08f7aaf294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31472
75670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3147275670
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3534848841
Short name T643
Test name
Test status
Simulation time 7422700454 ps
CPU time 51.45 seconds
Started Jun 22 05:03:08 PM PDT 24
Finished Jun 22 05:04:00 PM PDT 24
Peak memory 249172 kb
Host smart-0fa416b2-57f3-42de-b09e-8aa6b7e2ed74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35348
48841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3534848841
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2195850646
Short name T324
Test name
Test status
Simulation time 40544630300 ps
CPU time 2600.72 seconds
Started Jun 22 05:03:10 PM PDT 24
Finished Jun 22 05:46:32 PM PDT 24
Peak memory 289704 kb
Host smart-7cfa52c5-55df-4f1d-8b0f-3a079b9e0978
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195850646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2195850646
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2711308472
Short name T495
Test name
Test status
Simulation time 51314365847 ps
CPU time 806.69 seconds
Started Jun 22 05:03:10 PM PDT 24
Finished Jun 22 05:16:37 PM PDT 24
Peak memory 267548 kb
Host smart-56d9fd87-0cc2-4f0d-b841-30003715e234
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711308472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2711308472
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.4168354716
Short name T328
Test name
Test status
Simulation time 31388502973 ps
CPU time 311.6 seconds
Started Jun 22 05:03:08 PM PDT 24
Finished Jun 22 05:08:20 PM PDT 24
Peak memory 248824 kb
Host smart-6851ffc1-22ba-4143-891d-7bec0f0cff33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168354716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.4168354716
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2943427640
Short name T410
Test name
Test status
Simulation time 552831418 ps
CPU time 32.14 seconds
Started Jun 22 05:03:09 PM PDT 24
Finished Jun 22 05:03:41 PM PDT 24
Peak memory 249164 kb
Host smart-85fe2d07-2d83-458e-a2b3-599c8ee19d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29434
27640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2943427640
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3795247416
Short name T529
Test name
Test status
Simulation time 3212475703 ps
CPU time 36.94 seconds
Started Jun 22 05:03:09 PM PDT 24
Finished Jun 22 05:03:47 PM PDT 24
Peak memory 256080 kb
Host smart-d8bbe0af-172d-41c2-9926-c566bb6e1444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37952
47416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3795247416
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2382125510
Short name T9
Test name
Test status
Simulation time 2896941808 ps
CPU time 35.43 seconds
Started Jun 22 05:03:08 PM PDT 24
Finished Jun 22 05:03:44 PM PDT 24
Peak memory 257040 kb
Host smart-6e48c7a9-e56f-4b7e-83cc-e176f3bac5ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23821
25510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2382125510
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2448404355
Short name T576
Test name
Test status
Simulation time 63393793 ps
CPU time 4.64 seconds
Started Jun 22 05:03:08 PM PDT 24
Finished Jun 22 05:03:13 PM PDT 24
Peak memory 257240 kb
Host smart-33f9719b-e3ae-45c3-8b68-ace7b4fa8cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24484
04355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2448404355
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.1022889711
Short name T101
Test name
Test status
Simulation time 78856351352 ps
CPU time 2347.65 seconds
Started Jun 22 05:03:10 PM PDT 24
Finished Jun 22 05:42:19 PM PDT 24
Peak memory 306124 kb
Host smart-ad9d60ec-df5c-4b1e-bc86-2bbbfec3902a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022889711 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.1022889711
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3005684000
Short name T108
Test name
Test status
Simulation time 10114194900 ps
CPU time 1143.56 seconds
Started Jun 22 05:03:09 PM PDT 24
Finished Jun 22 05:22:14 PM PDT 24
Peak memory 289296 kb
Host smart-508c1b30-3b2f-4e54-9e14-60aa39d72585
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005684000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3005684000
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2674457958
Short name T534
Test name
Test status
Simulation time 2977877837 ps
CPU time 129.21 seconds
Started Jun 22 05:03:09 PM PDT 24
Finished Jun 22 05:05:18 PM PDT 24
Peak memory 250104 kb
Host smart-63d9cd59-15dc-45b4-8d3f-2570255a172f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26744
57958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2674457958
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2106525307
Short name T437
Test name
Test status
Simulation time 217087824 ps
CPU time 23.8 seconds
Started Jun 22 05:03:10 PM PDT 24
Finished Jun 22 05:03:35 PM PDT 24
Peak memory 255504 kb
Host smart-91a109b4-0164-4b6d-96ad-8c088e8081f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21065
25307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2106525307
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.196528767
Short name T125
Test name
Test status
Simulation time 24685056922 ps
CPU time 915.93 seconds
Started Jun 22 05:03:08 PM PDT 24
Finished Jun 22 05:18:25 PM PDT 24
Peak memory 273032 kb
Host smart-684ac6dc-7c06-41a2-b2ec-d20d9e0132b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196528767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.196528767
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3080125135
Short name T2
Test name
Test status
Simulation time 120155629162 ps
CPU time 2044.19 seconds
Started Jun 22 05:03:10 PM PDT 24
Finished Jun 22 05:37:15 PM PDT 24
Peak memory 289812 kb
Host smart-c5daba65-e8a2-471a-adb7-d55548b91c93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080125135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3080125135
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3702977380
Short name T302
Test name
Test status
Simulation time 39465543680 ps
CPU time 396.26 seconds
Started Jun 22 05:03:09 PM PDT 24
Finished Jun 22 05:09:46 PM PDT 24
Peak memory 248556 kb
Host smart-26b07faa-b440-44f6-b938-01e17d6deac4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702977380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3702977380
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3547091545
Short name T455
Test name
Test status
Simulation time 599668586 ps
CPU time 8.17 seconds
Started Jun 22 05:03:08 PM PDT 24
Finished Jun 22 05:03:17 PM PDT 24
Peak memory 249108 kb
Host smart-eabce776-7ca3-479d-a37c-aa06a25ce3ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35470
91545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3547091545
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1530498460
Short name T46
Test name
Test status
Simulation time 1317091646 ps
CPU time 25.58 seconds
Started Jun 22 05:03:10 PM PDT 24
Finished Jun 22 05:03:37 PM PDT 24
Peak memory 256488 kb
Host smart-25cf396c-a6b4-48fc-8100-e4c1737ba7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15304
98460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1530498460
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1593711570
Short name T403
Test name
Test status
Simulation time 39449758 ps
CPU time 5.34 seconds
Started Jun 22 05:03:08 PM PDT 24
Finished Jun 22 05:03:14 PM PDT 24
Peak memory 247908 kb
Host smart-83d3b470-fbd6-4c47-bce2-a5d1ebf4e503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15937
11570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1593711570
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1164252452
Short name T58
Test name
Test status
Simulation time 2011279312 ps
CPU time 57.98 seconds
Started Jun 22 05:03:08 PM PDT 24
Finished Jun 22 05:04:07 PM PDT 24
Peak memory 248996 kb
Host smart-c5705daa-08dc-4485-95ce-80f04c363c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11642
52452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1164252452
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.874882059
Short name T138
Test name
Test status
Simulation time 2681730634 ps
CPU time 148.32 seconds
Started Jun 22 05:03:16 PM PDT 24
Finished Jun 22 05:05:44 PM PDT 24
Peak memory 257488 kb
Host smart-fc7bb9e9-b45b-42c4-854e-734a0354defe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874882059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.874882059
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2168753630
Short name T259
Test name
Test status
Simulation time 77341484073 ps
CPU time 6379 seconds
Started Jun 22 05:03:16 PM PDT 24
Finished Jun 22 06:49:36 PM PDT 24
Peak memory 338692 kb
Host smart-46c2738b-5837-4bfc-a3ed-e2d044616bf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168753630 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2168753630
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1639861884
Short name T642
Test name
Test status
Simulation time 508214752133 ps
CPU time 3287.98 seconds
Started Jun 22 05:03:19 PM PDT 24
Finished Jun 22 05:58:08 PM PDT 24
Peak memory 289552 kb
Host smart-b8d60a50-e5c7-4dd4-8fca-93a9f26f15df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639861884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1639861884
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3684798201
Short name T691
Test name
Test status
Simulation time 4323598838 ps
CPU time 87.62 seconds
Started Jun 22 05:03:17 PM PDT 24
Finished Jun 22 05:04:46 PM PDT 24
Peak memory 257288 kb
Host smart-b33a8e62-7c80-4249-8fd8-d9a35bdac1be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36847
98201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3684798201
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1322843953
Short name T439
Test name
Test status
Simulation time 588963630 ps
CPU time 19.71 seconds
Started Jun 22 05:03:17 PM PDT 24
Finished Jun 22 05:03:38 PM PDT 24
Peak memory 256700 kb
Host smart-3c3f7af2-e193-45f0-b175-f5e1fa5a91e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13228
43953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1322843953
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3194481670
Short name T342
Test name
Test status
Simulation time 365045884862 ps
CPU time 1031.74 seconds
Started Jun 22 05:03:17 PM PDT 24
Finished Jun 22 05:20:29 PM PDT 24
Peak memory 265664 kb
Host smart-19421758-f98f-46c4-8ed0-43398121e987
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194481670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3194481670
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1704350675
Short name T533
Test name
Test status
Simulation time 14878254791 ps
CPU time 1355.48 seconds
Started Jun 22 05:03:19 PM PDT 24
Finished Jun 22 05:25:55 PM PDT 24
Peak memory 289184 kb
Host smart-70de4b4b-a5a6-4f0b-9ccc-c363cd2dc2a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704350675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1704350675
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2434816489
Short name T466
Test name
Test status
Simulation time 18698662255 ps
CPU time 178.22 seconds
Started Jun 22 05:03:17 PM PDT 24
Finished Jun 22 05:06:16 PM PDT 24
Peak memory 247672 kb
Host smart-3ba95dab-51a1-433a-a4df-dc2983ea5787
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434816489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2434816489
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.434756550
Short name T613
Test name
Test status
Simulation time 1989726379 ps
CPU time 52.21 seconds
Started Jun 22 05:03:16 PM PDT 24
Finished Jun 22 05:04:09 PM PDT 24
Peak memory 248960 kb
Host smart-985d0c49-47a9-41b2-af7a-dbcee671cc67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43475
6550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.434756550
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1298103283
Short name T22
Test name
Test status
Simulation time 657132608 ps
CPU time 46.66 seconds
Started Jun 22 05:03:20 PM PDT 24
Finished Jun 22 05:04:07 PM PDT 24
Peak memory 256076 kb
Host smart-5f0c367c-84c2-4d37-9f8d-e15649c55beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12981
03283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1298103283
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3792373471
Short name T66
Test name
Test status
Simulation time 62317268 ps
CPU time 2.83 seconds
Started Jun 22 05:03:17 PM PDT 24
Finished Jun 22 05:03:21 PM PDT 24
Peak memory 239804 kb
Host smart-a80b12c2-75e4-471c-8244-0c624d456db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37923
73471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3792373471
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2683869022
Short name T616
Test name
Test status
Simulation time 1545117764 ps
CPU time 50.42 seconds
Started Jun 22 05:03:18 PM PDT 24
Finished Jun 22 05:04:09 PM PDT 24
Peak memory 249092 kb
Host smart-56db0bec-6ab9-49d4-93aa-d79aab69a3d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26838
69022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2683869022
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.3695405676
Short name T87
Test name
Test status
Simulation time 174500762709 ps
CPU time 2867.55 seconds
Started Jun 22 05:03:18 PM PDT 24
Finished Jun 22 05:51:06 PM PDT 24
Peak memory 289656 kb
Host smart-41349822-948b-48a3-b29e-e0761c1adeab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695405676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.3695405676
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.880223666
Short name T223
Test name
Test status
Simulation time 133606339 ps
CPU time 3.28 seconds
Started Jun 22 05:01:48 PM PDT 24
Finished Jun 22 05:01:52 PM PDT 24
Peak memory 249216 kb
Host smart-2cf98041-7e9f-43da-b616-7b659e56ca2f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=880223666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.880223666
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1970189873
Short name T663
Test name
Test status
Simulation time 69799809586 ps
CPU time 2522.57 seconds
Started Jun 22 05:01:45 PM PDT 24
Finished Jun 22 05:43:49 PM PDT 24
Peak memory 289048 kb
Host smart-afac823a-c73f-4466-990c-8c2d458dd6bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970189873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1970189873
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1867966646
Short name T474
Test name
Test status
Simulation time 2208420670 ps
CPU time 22.85 seconds
Started Jun 22 05:01:41 PM PDT 24
Finished Jun 22 05:02:05 PM PDT 24
Peak memory 249316 kb
Host smart-7e374880-bb1c-4bd2-88af-387a99f7cfb2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1867966646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1867966646
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3561129743
Short name T514
Test name
Test status
Simulation time 712901440 ps
CPU time 61.87 seconds
Started Jun 22 05:01:47 PM PDT 24
Finished Jun 22 05:02:50 PM PDT 24
Peak memory 249080 kb
Host smart-7d4a78df-5bd6-427c-b48a-913ad16ae7e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35611
29743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3561129743
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.415295591
Short name T438
Test name
Test status
Simulation time 63077765 ps
CPU time 5.53 seconds
Started Jun 22 05:01:46 PM PDT 24
Finished Jun 22 05:01:53 PM PDT 24
Peak memory 251148 kb
Host smart-c7a0efab-ea0a-4102-ae8b-8f44c28acb95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41529
5591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.415295591
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3735623061
Short name T346
Test name
Test status
Simulation time 20557809225 ps
CPU time 935.17 seconds
Started Jun 22 05:01:40 PM PDT 24
Finished Jun 22 05:17:16 PM PDT 24
Peak memory 273736 kb
Host smart-35ca449d-65ff-41df-a427-4261acd03a36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735623061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3735623061
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3456815654
Short name T638
Test name
Test status
Simulation time 34054198071 ps
CPU time 1739.13 seconds
Started Jun 22 05:01:50 PM PDT 24
Finished Jun 22 05:30:50 PM PDT 24
Peak memory 281436 kb
Host smart-2ae50a72-5170-4f8c-8fea-2ce3f92cc6cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456815654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3456815654
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.4187891810
Short name T573
Test name
Test status
Simulation time 4921247990 ps
CPU time 175.65 seconds
Started Jun 22 05:01:45 PM PDT 24
Finished Jun 22 05:04:41 PM PDT 24
Peak memory 248804 kb
Host smart-f1c684df-0b55-4c4a-8f54-4028b0872848
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187891810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.4187891810
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.48098858
Short name T557
Test name
Test status
Simulation time 706298449 ps
CPU time 40.66 seconds
Started Jun 22 05:01:50 PM PDT 24
Finished Jun 22 05:02:32 PM PDT 24
Peak memory 249076 kb
Host smart-5c674794-b6c7-4eb7-9d95-49d57a93ba1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48098
858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.48098858
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2213825378
Short name T380
Test name
Test status
Simulation time 4209208130 ps
CPU time 40.89 seconds
Started Jun 22 05:01:42 PM PDT 24
Finished Jun 22 05:02:24 PM PDT 24
Peak memory 256032 kb
Host smart-3616b8cd-4425-40b9-81e9-eac2961e05de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22138
25378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2213825378
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1201727633
Short name T527
Test name
Test status
Simulation time 259486777 ps
CPU time 28.78 seconds
Started Jun 22 05:01:43 PM PDT 24
Finished Jun 22 05:02:13 PM PDT 24
Peak memory 256084 kb
Host smart-680b6032-d29c-443f-b9b2-479c9aea6be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12017
27633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1201727633
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3038450550
Short name T207
Test name
Test status
Simulation time 124982605 ps
CPU time 14.28 seconds
Started Jun 22 05:01:44 PM PDT 24
Finished Jun 22 05:01:59 PM PDT 24
Peak memory 249092 kb
Host smart-d76c7330-a1a8-402a-b102-94ac351b2266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30384
50550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3038450550
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1697376618
Short name T102
Test name
Test status
Simulation time 60709224925 ps
CPU time 1704.26 seconds
Started Jun 22 05:01:48 PM PDT 24
Finished Jun 22 05:30:13 PM PDT 24
Peak memory 273508 kb
Host smart-00d546b0-8c78-4f60-abb1-771982703e85
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697376618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1697376618
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3321960662
Short name T503
Test name
Test status
Simulation time 177111215780 ps
CPU time 2625.76 seconds
Started Jun 22 05:03:18 PM PDT 24
Finished Jun 22 05:47:05 PM PDT 24
Peak memory 283312 kb
Host smart-9e620c65-9a62-4e4f-b552-a8568d727132
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321960662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3321960662
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3277103774
Short name T507
Test name
Test status
Simulation time 10624474960 ps
CPU time 128.76 seconds
Started Jun 22 05:03:15 PM PDT 24
Finished Jun 22 05:05:24 PM PDT 24
Peak memory 257300 kb
Host smart-263169b0-cebf-4f0b-8e35-d1061143c527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32771
03774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3277103774
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1329671724
Short name T657
Test name
Test status
Simulation time 1749627682 ps
CPU time 23.19 seconds
Started Jun 22 05:03:18 PM PDT 24
Finished Jun 22 05:03:42 PM PDT 24
Peak memory 249448 kb
Host smart-36336c21-6a60-49c2-b3ae-c3dea3bf9320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13296
71724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1329671724
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1472227291
Short name T331
Test name
Test status
Simulation time 246012093245 ps
CPU time 2394.74 seconds
Started Jun 22 05:03:16 PM PDT 24
Finished Jun 22 05:43:12 PM PDT 24
Peak memory 273788 kb
Host smart-22cbd221-c402-478c-91d1-6dc4346fca88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472227291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1472227291
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2066529655
Short name T570
Test name
Test status
Simulation time 243705598286 ps
CPU time 2954.33 seconds
Started Jun 22 05:03:23 PM PDT 24
Finished Jun 22 05:52:38 PM PDT 24
Peak memory 289304 kb
Host smart-db223b96-bd19-4ea3-b155-c45f6298794e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066529655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2066529655
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.239368764
Short name T318
Test name
Test status
Simulation time 10362358882 ps
CPU time 302.21 seconds
Started Jun 22 05:03:17 PM PDT 24
Finished Jun 22 05:08:20 PM PDT 24
Peak memory 248680 kb
Host smart-bc871451-a53c-4440-a7fb-fc3b495c57ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239368764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.239368764
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.2013770837
Short name T369
Test name
Test status
Simulation time 195820239 ps
CPU time 13.6 seconds
Started Jun 22 05:03:19 PM PDT 24
Finished Jun 22 05:03:33 PM PDT 24
Peak memory 249080 kb
Host smart-8b94369c-2e4b-49bd-8b5f-222cd586e09d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20137
70837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2013770837
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1817619963
Short name T564
Test name
Test status
Simulation time 6554988624 ps
CPU time 28.1 seconds
Started Jun 22 05:03:19 PM PDT 24
Finished Jun 22 05:03:48 PM PDT 24
Peak memory 256172 kb
Host smart-530de73e-3795-486e-8194-bb97a6c18fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18176
19963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1817619963
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.165810736
Short name T545
Test name
Test status
Simulation time 76629421 ps
CPU time 10.76 seconds
Started Jun 22 05:03:19 PM PDT 24
Finished Jun 22 05:03:30 PM PDT 24
Peak memory 247880 kb
Host smart-d3e1c7be-e1c5-4db0-8b05-6544c149714f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16581
0736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.165810736
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3645877039
Short name T554
Test name
Test status
Simulation time 371854668 ps
CPU time 32.09 seconds
Started Jun 22 05:03:17 PM PDT 24
Finished Jun 22 05:03:50 PM PDT 24
Peak memory 248992 kb
Host smart-637e5e00-4d42-43dc-9ab0-7102d1087aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36458
77039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3645877039
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.87237928
Short name T61
Test name
Test status
Simulation time 929755303 ps
CPU time 94.92 seconds
Started Jun 22 05:03:16 PM PDT 24
Finished Jun 22 05:04:51 PM PDT 24
Peak memory 256448 kb
Host smart-6283b470-2cfe-41a4-a119-c3de8f237190
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87237928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_hand
ler_stress_all.87237928
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.464064841
Short name T543
Test name
Test status
Simulation time 336168755837 ps
CPU time 7039.23 seconds
Started Jun 22 05:03:18 PM PDT 24
Finished Jun 22 07:00:38 PM PDT 24
Peak memory 322812 kb
Host smart-b49c0174-2755-41a0-a28a-dcbf839b6456
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464064841 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.464064841
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2426011254
Short name T103
Test name
Test status
Simulation time 37009688579 ps
CPU time 637.8 seconds
Started Jun 22 05:03:25 PM PDT 24
Finished Jun 22 05:14:04 PM PDT 24
Peak memory 265448 kb
Host smart-63c1b46b-8157-4a62-af7f-0bee64497437
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426011254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2426011254
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.69789615
Short name T632
Test name
Test status
Simulation time 3231559286 ps
CPU time 165.91 seconds
Started Jun 22 05:03:16 PM PDT 24
Finished Jun 22 05:06:03 PM PDT 24
Peak memory 257356 kb
Host smart-cf5dde79-b58f-40f4-b5b9-b3bb391032b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69789
615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.69789615
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3944810589
Short name T631
Test name
Test status
Simulation time 517143712 ps
CPU time 43.29 seconds
Started Jun 22 05:03:16 PM PDT 24
Finished Jun 22 05:04:00 PM PDT 24
Peak memory 249012 kb
Host smart-e52b355c-4a84-4fa5-ad11-d05cf9c8e3c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39448
10589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3944810589
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3307525200
Short name T351
Test name
Test status
Simulation time 48435423738 ps
CPU time 2931.56 seconds
Started Jun 22 05:03:26 PM PDT 24
Finished Jun 22 05:52:18 PM PDT 24
Peak memory 281680 kb
Host smart-e280f899-1464-4022-a3c8-dbce919ab4b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307525200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3307525200
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.348614504
Short name T4
Test name
Test status
Simulation time 37292632958 ps
CPU time 864.52 seconds
Started Jun 22 05:03:24 PM PDT 24
Finished Jun 22 05:17:49 PM PDT 24
Peak memory 273280 kb
Host smart-0e621a41-220a-4720-b3be-ebadf5d761fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348614504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.348614504
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3369448107
Short name T299
Test name
Test status
Simulation time 21914722542 ps
CPU time 232.75 seconds
Started Jun 22 05:03:26 PM PDT 24
Finished Jun 22 05:07:19 PM PDT 24
Peak memory 248384 kb
Host smart-1768b5cf-903d-43fe-909d-9c1aa5b14813
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369448107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3369448107
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1969183070
Short name T652
Test name
Test status
Simulation time 236307690 ps
CPU time 5.69 seconds
Started Jun 22 05:03:17 PM PDT 24
Finished Jun 22 05:03:24 PM PDT 24
Peak memory 240840 kb
Host smart-f5bd4775-b5fe-4bac-8a6e-af7c51e607bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19691
83070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1969183070
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3250196494
Short name T272
Test name
Test status
Simulation time 13392577829 ps
CPU time 54.5 seconds
Started Jun 22 05:03:17 PM PDT 24
Finished Jun 22 05:04:13 PM PDT 24
Peak memory 257292 kb
Host smart-3f4d8d9b-d555-499c-a53c-e621b821e167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32501
96494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3250196494
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.2526124978
Short name T1
Test name
Test status
Simulation time 250081255 ps
CPU time 14.92 seconds
Started Jun 22 05:03:24 PM PDT 24
Finished Jun 22 05:03:40 PM PDT 24
Peak memory 247832 kb
Host smart-77cbe941-5fb1-463c-8316-d427a2d8098d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25261
24978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2526124978
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3338832047
Short name T366
Test name
Test status
Simulation time 2837530185 ps
CPU time 15.42 seconds
Started Jun 22 05:03:16 PM PDT 24
Finished Jun 22 05:03:32 PM PDT 24
Peak memory 256560 kb
Host smart-91782974-b014-4dc8-baba-4e301fe2d8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33388
32047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3338832047
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.619183875
Short name T24
Test name
Test status
Simulation time 106806257683 ps
CPU time 2970.36 seconds
Started Jun 22 05:03:26 PM PDT 24
Finished Jun 22 05:52:57 PM PDT 24
Peak memory 289420 kb
Host smart-06f07f98-ef17-4026-8ece-b0ee79835fac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619183875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.619183875
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.3467931968
Short name T130
Test name
Test status
Simulation time 187412430167 ps
CPU time 2967.8 seconds
Started Jun 22 05:03:28 PM PDT 24
Finished Jun 22 05:52:56 PM PDT 24
Peak memory 305640 kb
Host smart-86841950-f95a-46b6-be20-999e76cd75f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467931968 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.3467931968
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1104831723
Short name T457
Test name
Test status
Simulation time 144597296694 ps
CPU time 1995.2 seconds
Started Jun 22 05:03:24 PM PDT 24
Finished Jun 22 05:36:40 PM PDT 24
Peak memory 283812 kb
Host smart-0442fa7b-1a36-4725-853a-21c85538024b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104831723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1104831723
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.113903498
Short name T30
Test name
Test status
Simulation time 5507779731 ps
CPU time 35.56 seconds
Started Jun 22 05:03:26 PM PDT 24
Finished Jun 22 05:04:02 PM PDT 24
Peak memory 256980 kb
Host smart-2a6a43a2-5bc9-4c8c-819a-c2133cd1d7fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11390
3498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.113903498
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2400250508
Short name T142
Test name
Test status
Simulation time 491178563 ps
CPU time 34.63 seconds
Started Jun 22 05:03:25 PM PDT 24
Finished Jun 22 05:04:00 PM PDT 24
Peak memory 249216 kb
Host smart-169248bc-a20c-4b46-8f68-2913b1bc2e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24002
50508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2400250508
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3520545115
Short name T435
Test name
Test status
Simulation time 26443767481 ps
CPU time 1728.67 seconds
Started Jun 22 05:03:25 PM PDT 24
Finished Jun 22 05:32:14 PM PDT 24
Peak memory 273412 kb
Host smart-b16eae8b-2ced-4b4d-a151-fe168d98b855
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520545115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3520545115
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.199052976
Short name T291
Test name
Test status
Simulation time 58390381148 ps
CPU time 538.98 seconds
Started Jun 22 05:03:28 PM PDT 24
Finished Jun 22 05:12:27 PM PDT 24
Peak memory 248704 kb
Host smart-64af40dd-3a48-44a9-89ec-75231fdb629e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199052976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.199052976
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1673924768
Short name T661
Test name
Test status
Simulation time 2121553934 ps
CPU time 17.67 seconds
Started Jun 22 05:03:25 PM PDT 24
Finished Jun 22 05:03:43 PM PDT 24
Peak memory 256476 kb
Host smart-8b57746d-92e2-42bd-8fee-534e2eff22f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16739
24768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1673924768
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.469222696
Short name T604
Test name
Test status
Simulation time 376502216 ps
CPU time 13 seconds
Started Jun 22 05:03:28 PM PDT 24
Finished Jun 22 05:03:41 PM PDT 24
Peak memory 253536 kb
Host smart-2b543e86-0650-4919-a88d-51350ea5acb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46922
2696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.469222696
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1390586656
Short name T34
Test name
Test status
Simulation time 226654016 ps
CPU time 16.82 seconds
Started Jun 22 05:03:25 PM PDT 24
Finished Jun 22 05:03:43 PM PDT 24
Peak memory 247908 kb
Host smart-a50bb5eb-a423-4c27-bc1c-88c124fdb634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13905
86656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1390586656
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3563834152
Short name T106
Test name
Test status
Simulation time 1154631906 ps
CPU time 40.08 seconds
Started Jun 22 05:03:25 PM PDT 24
Finished Jun 22 05:04:05 PM PDT 24
Peak memory 249080 kb
Host smart-764da005-9125-4fa1-841d-1364dd05721d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35638
34152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3563834152
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.92273381
Short name T73
Test name
Test status
Simulation time 768047155 ps
CPU time 43.96 seconds
Started Jun 22 05:03:26 PM PDT 24
Finished Jun 22 05:04:10 PM PDT 24
Peak memory 256012 kb
Host smart-5d31d1a7-d43b-4b3b-902c-44983a6df9dc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92273381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_hand
ler_stress_all.92273381
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2815467597
Short name T97
Test name
Test status
Simulation time 53565704063 ps
CPU time 1532.13 seconds
Started Jun 22 05:03:23 PM PDT 24
Finished Jun 22 05:28:56 PM PDT 24
Peak memory 272924 kb
Host smart-01fa9724-ce3e-4a7e-bdbc-8a714c8ea7d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815467597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2815467597
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.767446784
Short name T460
Test name
Test status
Simulation time 2020859938 ps
CPU time 54.35 seconds
Started Jun 22 05:03:26 PM PDT 24
Finished Jun 22 05:04:21 PM PDT 24
Peak memory 249220 kb
Host smart-8226ea3d-9dfc-4634-a171-22e1e9181e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76744
6784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.767446784
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3934813000
Short name T704
Test name
Test status
Simulation time 1004044369 ps
CPU time 56.11 seconds
Started Jun 22 05:03:25 PM PDT 24
Finished Jun 22 05:04:22 PM PDT 24
Peak memory 257112 kb
Host smart-5d9820c5-00e2-4899-bccf-8bdef351912b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39348
13000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3934813000
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1704072117
Short name T348
Test name
Test status
Simulation time 109740420991 ps
CPU time 863.23 seconds
Started Jun 22 05:03:35 PM PDT 24
Finished Jun 22 05:17:59 PM PDT 24
Peak memory 273596 kb
Host smart-f33c615b-0a02-494d-92b9-7b18be6adf7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704072117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1704072117
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2631775645
Short name T96
Test name
Test status
Simulation time 535632456090 ps
CPU time 2131.57 seconds
Started Jun 22 05:03:30 PM PDT 24
Finished Jun 22 05:39:02 PM PDT 24
Peak memory 281988 kb
Host smart-f6c1b9ea-6f63-446d-bdd6-5160ff689ade
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631775645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2631775645
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.81336562
Short name T639
Test name
Test status
Simulation time 32034129248 ps
CPU time 334.6 seconds
Started Jun 22 05:03:24 PM PDT 24
Finished Jun 22 05:08:59 PM PDT 24
Peak memory 248476 kb
Host smart-87ca338d-3f8e-4070-88c2-671d0109cb3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81336562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.81336562
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.1069101881
Short name T655
Test name
Test status
Simulation time 270937990 ps
CPU time 17.5 seconds
Started Jun 22 05:03:25 PM PDT 24
Finished Jun 22 05:03:43 PM PDT 24
Peak memory 255168 kb
Host smart-a1605414-8a45-4c21-b677-811b1467adf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10691
01881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1069101881
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.75130888
Short name T544
Test name
Test status
Simulation time 556042591 ps
CPU time 34.24 seconds
Started Jun 22 05:03:25 PM PDT 24
Finished Jun 22 05:04:00 PM PDT 24
Peak memory 249100 kb
Host smart-1cc3b65e-9968-4f13-a763-b55af3077fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75130
888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.75130888
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2071261022
Short name T583
Test name
Test status
Simulation time 226007214 ps
CPU time 6.41 seconds
Started Jun 22 05:03:23 PM PDT 24
Finished Jun 22 05:03:30 PM PDT 24
Peak memory 253472 kb
Host smart-c752a92e-d898-419b-81ba-2832fa9c379a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20712
61022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2071261022
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3506196844
Short name T587
Test name
Test status
Simulation time 3656352597 ps
CPU time 31.29 seconds
Started Jun 22 05:03:23 PM PDT 24
Finished Jun 22 05:03:55 PM PDT 24
Peak memory 249156 kb
Host smart-bb9fb8a6-67c2-43a5-9387-ad0c2a35cfc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35061
96844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3506196844
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.3270930536
Short name T446
Test name
Test status
Simulation time 4896883679 ps
CPU time 325.7 seconds
Started Jun 22 05:03:32 PM PDT 24
Finished Jun 22 05:08:58 PM PDT 24
Peak memory 265596 kb
Host smart-fb1c3ddd-3619-45ca-b9c7-f97b96ae6dc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270930536 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.3270930536
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.190944963
Short name T368
Test name
Test status
Simulation time 578241618536 ps
CPU time 3265.13 seconds
Started Jun 22 05:03:31 PM PDT 24
Finished Jun 22 05:57:57 PM PDT 24
Peak memory 289628 kb
Host smart-c5f12cf6-2ea0-4ac4-9f1e-d68693087fb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190944963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.190944963
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1843492947
Short name T365
Test name
Test status
Simulation time 1259815691 ps
CPU time 46.69 seconds
Started Jun 22 05:03:31 PM PDT 24
Finished Jun 22 05:04:18 PM PDT 24
Peak memory 257168 kb
Host smart-4ca48699-3d84-4bbf-94be-3fd407685d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18434
92947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1843492947
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3827913544
Short name T635
Test name
Test status
Simulation time 296716822 ps
CPU time 24.02 seconds
Started Jun 22 05:03:31 PM PDT 24
Finished Jun 22 05:03:56 PM PDT 24
Peak memory 249012 kb
Host smart-8d048a2c-c410-4d47-8c3b-10c4c3a0f1e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38279
13544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3827913544
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.757344908
Short name T682
Test name
Test status
Simulation time 45213399457 ps
CPU time 1138.29 seconds
Started Jun 22 05:03:34 PM PDT 24
Finished Jun 22 05:22:33 PM PDT 24
Peak memory 273316 kb
Host smart-a561d412-e7c5-4bca-af9a-0c342f83d544
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757344908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.757344908
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1826206069
Short name T98
Test name
Test status
Simulation time 56545847871 ps
CPU time 1319.91 seconds
Started Jun 22 05:03:32 PM PDT 24
Finished Jun 22 05:25:32 PM PDT 24
Peak memory 281924 kb
Host smart-e84c14ec-a3d2-4f64-a3ec-f5f6861d14ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826206069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1826206069
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.621394368
Short name T315
Test name
Test status
Simulation time 10176513888 ps
CPU time 403.19 seconds
Started Jun 22 05:03:34 PM PDT 24
Finished Jun 22 05:10:17 PM PDT 24
Peak memory 256916 kb
Host smart-a4af4e10-4fe1-428b-86d5-4fb3e203af8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621394368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.621394368
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.919960588
Short name T376
Test name
Test status
Simulation time 270072543 ps
CPU time 23.46 seconds
Started Jun 22 05:03:31 PM PDT 24
Finished Jun 22 05:03:55 PM PDT 24
Peak memory 249380 kb
Host smart-445c84f0-1b79-4a19-ad89-c88ccab98a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91996
0588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.919960588
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.4149252950
Short name T532
Test name
Test status
Simulation time 1176799378 ps
CPU time 35.68 seconds
Started Jun 22 05:03:30 PM PDT 24
Finished Jun 22 05:04:06 PM PDT 24
Peak memory 249036 kb
Host smart-997a2e45-e27f-492b-9317-e4e9c68bd952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41492
52950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.4149252950
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.4255804808
Short name T47
Test name
Test status
Simulation time 598986292 ps
CPU time 44.61 seconds
Started Jun 22 05:03:35 PM PDT 24
Finished Jun 22 05:04:20 PM PDT 24
Peak memory 256272 kb
Host smart-797840b1-c628-4d0a-b0d3-65cceb81e621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42558
04808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.4255804808
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1916437654
Short name T433
Test name
Test status
Simulation time 1620967030 ps
CPU time 50.55 seconds
Started Jun 22 05:03:30 PM PDT 24
Finished Jun 22 05:04:21 PM PDT 24
Peak memory 257276 kb
Host smart-7aec7385-fc11-415f-9be0-8d2e1b0307dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19164
37654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1916437654
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.710636216
Short name T584
Test name
Test status
Simulation time 9122686306 ps
CPU time 263.14 seconds
Started Jun 22 05:03:31 PM PDT 24
Finished Jun 22 05:07:55 PM PDT 24
Peak memory 257348 kb
Host smart-1755ccf6-76f7-4241-8513-08cda8490b9c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710636216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.710636216
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.358255909
Short name T648
Test name
Test status
Simulation time 119960026388 ps
CPU time 2367.73 seconds
Started Jun 22 05:03:39 PM PDT 24
Finished Jun 22 05:43:07 PM PDT 24
Peak memory 288784 kb
Host smart-0d6bc27b-2390-4d2f-98a0-b45c67c5805c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358255909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.358255909
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1479086962
Short name T62
Test name
Test status
Simulation time 1805316927 ps
CPU time 106.94 seconds
Started Jun 22 05:03:33 PM PDT 24
Finished Jun 22 05:05:21 PM PDT 24
Peak memory 257232 kb
Host smart-48cfab18-be6d-4600-bf3e-1a3658eef049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14790
86962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1479086962
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1792896815
Short name T546
Test name
Test status
Simulation time 1094333418 ps
CPU time 36.08 seconds
Started Jun 22 05:03:30 PM PDT 24
Finished Jun 22 05:04:06 PM PDT 24
Peak memory 255484 kb
Host smart-bda83d2a-6890-4220-b4a2-e0d5b6007346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17928
96815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1792896815
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.228802887
Short name T710
Test name
Test status
Simulation time 41970676943 ps
CPU time 1280.75 seconds
Started Jun 22 05:03:40 PM PDT 24
Finished Jun 22 05:25:02 PM PDT 24
Peak memory 265556 kb
Host smart-74efd801-fdd5-4346-8f3d-01b5d6b382fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228802887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.228802887
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3711449037
Short name T412
Test name
Test status
Simulation time 27256481283 ps
CPU time 1313.92 seconds
Started Jun 22 05:03:38 PM PDT 24
Finished Jun 22 05:25:33 PM PDT 24
Peak memory 289904 kb
Host smart-048f2cd3-b564-4356-ba1d-cc329e24e05b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711449037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3711449037
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1174300099
Short name T322
Test name
Test status
Simulation time 8649475987 ps
CPU time 328.59 seconds
Started Jun 22 05:03:40 PM PDT 24
Finished Jun 22 05:09:10 PM PDT 24
Peak memory 256560 kb
Host smart-1db3e68f-3d00-409e-a38c-bbd5869c69f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174300099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1174300099
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3345432128
Short name T599
Test name
Test status
Simulation time 1585330593 ps
CPU time 34.18 seconds
Started Jun 22 05:03:31 PM PDT 24
Finished Jun 22 05:04:06 PM PDT 24
Peak memory 249112 kb
Host smart-9abf87d5-4ecf-451c-98f7-e3278df0de7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33454
32128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3345432128
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.677681379
Short name T242
Test name
Test status
Simulation time 3452547394 ps
CPU time 34.85 seconds
Started Jun 22 05:03:33 PM PDT 24
Finished Jun 22 05:04:08 PM PDT 24
Peak memory 249176 kb
Host smart-ea114e5c-3807-4a69-b052-cc3a7a4c2363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67768
1379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.677681379
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2448529825
Short name T707
Test name
Test status
Simulation time 855544024 ps
CPU time 52.35 seconds
Started Jun 22 05:03:38 PM PDT 24
Finished Jun 22 05:04:31 PM PDT 24
Peak memory 248308 kb
Host smart-aabbc7ee-2bec-447a-bb7e-f6bfee266da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24485
29825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2448529825
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2668065399
Short name T620
Test name
Test status
Simulation time 157236693 ps
CPU time 4.43 seconds
Started Jun 22 05:03:32 PM PDT 24
Finished Jun 22 05:03:37 PM PDT 24
Peak memory 240904 kb
Host smart-294f4456-d43a-429d-b148-c413fca514fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26680
65399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2668065399
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3247764495
Short name T687
Test name
Test status
Simulation time 210324126932 ps
CPU time 2723.6 seconds
Started Jun 22 05:03:38 PM PDT 24
Finished Jun 22 05:49:03 PM PDT 24
Peak memory 287640 kb
Host smart-9364cd07-17b5-4c6b-93cc-7814bf0de09d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247764495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3247764495
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3820762823
Short name T607
Test name
Test status
Simulation time 39709072960 ps
CPU time 962.15 seconds
Started Jun 22 05:03:40 PM PDT 24
Finished Jun 22 05:19:43 PM PDT 24
Peak memory 273068 kb
Host smart-a187df1f-075c-4030-9c98-101d68f17669
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820762823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3820762823
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.4076416153
Short name T493
Test name
Test status
Simulation time 1846438687 ps
CPU time 176.82 seconds
Started Jun 22 05:03:39 PM PDT 24
Finished Jun 22 05:06:37 PM PDT 24
Peak memory 257260 kb
Host smart-b0ab188d-eb79-42df-8bb8-40dc63afbad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40764
16153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.4076416153
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1390881310
Short name T124
Test name
Test status
Simulation time 1303378058 ps
CPU time 15.82 seconds
Started Jun 22 05:03:38 PM PDT 24
Finished Jun 22 05:03:55 PM PDT 24
Peak memory 249064 kb
Host smart-5e02e054-3d8d-4b26-b420-fef053a0410e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13908
81310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1390881310
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3077416565
Short name T339
Test name
Test status
Simulation time 20975892593 ps
CPU time 1283.69 seconds
Started Jun 22 05:03:39 PM PDT 24
Finished Jun 22 05:25:03 PM PDT 24
Peak memory 273688 kb
Host smart-3da602cd-42f5-4f57-8616-58166c2df78e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077416565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3077416565
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3666544444
Short name T586
Test name
Test status
Simulation time 53026297926 ps
CPU time 1152.71 seconds
Started Jun 22 05:03:40 PM PDT 24
Finished Jun 22 05:22:54 PM PDT 24
Peak memory 285288 kb
Host smart-49add60f-30aa-4a18-be4d-75bc52de6f94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666544444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3666544444
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.176515908
Short name T653
Test name
Test status
Simulation time 16319589671 ps
CPU time 384.67 seconds
Started Jun 22 05:03:40 PM PDT 24
Finished Jun 22 05:10:05 PM PDT 24
Peak memory 255032 kb
Host smart-19038a81-a0ca-4a3c-8544-64e084674aee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176515908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.176515908
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2851125180
Short name T693
Test name
Test status
Simulation time 331861896 ps
CPU time 7.08 seconds
Started Jun 22 05:03:37 PM PDT 24
Finished Jun 22 05:03:45 PM PDT 24
Peak memory 251224 kb
Host smart-ff48ea75-5a9a-4c5b-aed4-372ae3187413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28511
25180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2851125180
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.4031886070
Short name T32
Test name
Test status
Simulation time 113729630 ps
CPU time 7.83 seconds
Started Jun 22 05:03:39 PM PDT 24
Finished Jun 22 05:03:48 PM PDT 24
Peak memory 247752 kb
Host smart-3ce045d0-bafc-4992-805f-c617b3532611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40318
86070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.4031886070
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1467576129
Short name T697
Test name
Test status
Simulation time 251254207 ps
CPU time 23.96 seconds
Started Jun 22 05:03:37 PM PDT 24
Finished Jun 22 05:04:02 PM PDT 24
Peak memory 249036 kb
Host smart-228ec954-5efd-462c-9fb9-b8e237fc7311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14675
76129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1467576129
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3735904097
Short name T511
Test name
Test status
Simulation time 1958322099 ps
CPU time 29.2 seconds
Started Jun 22 05:03:40 PM PDT 24
Finished Jun 22 05:04:09 PM PDT 24
Peak memory 257240 kb
Host smart-a1b084ae-87c5-4fe2-9bac-cbe6a4bcf1f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37359
04097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3735904097
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1961267482
Short name T582
Test name
Test status
Simulation time 42387258720 ps
CPU time 1442.6 seconds
Started Jun 22 05:03:40 PM PDT 24
Finished Jun 22 05:27:43 PM PDT 24
Peak memory 273732 kb
Host smart-ed087c99-cdc8-4230-8097-5af247de2ecd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961267482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1961267482
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1176825493
Short name T498
Test name
Test status
Simulation time 13612902068 ps
CPU time 1322.3 seconds
Started Jun 22 05:03:45 PM PDT 24
Finished Jun 22 05:25:48 PM PDT 24
Peak memory 289168 kb
Host smart-57a58c8b-fcdb-48eb-8d84-dd76b7ea2d5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176825493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1176825493
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.4094450754
Short name T463
Test name
Test status
Simulation time 4232281687 ps
CPU time 256.92 seconds
Started Jun 22 05:03:46 PM PDT 24
Finished Jun 22 05:08:03 PM PDT 24
Peak memory 251552 kb
Host smart-ef4749c8-68d6-4665-9f85-83315f9b76ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40944
50754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.4094450754
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1041299930
Short name T629
Test name
Test status
Simulation time 343305093 ps
CPU time 9.07 seconds
Started Jun 22 05:03:45 PM PDT 24
Finished Jun 22 05:03:54 PM PDT 24
Peak memory 249088 kb
Host smart-dbf12814-61af-4ba5-93f0-2e4b4d12b35f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10412
99930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1041299930
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2392782838
Short name T627
Test name
Test status
Simulation time 38902278703 ps
CPU time 1481.35 seconds
Started Jun 22 05:03:48 PM PDT 24
Finished Jun 22 05:28:30 PM PDT 24
Peak memory 288336 kb
Host smart-34b5ed37-5f44-4b72-a8fb-9d2a44e3da96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392782838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2392782838
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3692536456
Short name T274
Test name
Test status
Simulation time 43890264889 ps
CPU time 2505.41 seconds
Started Jun 22 05:03:46 PM PDT 24
Finished Jun 22 05:45:33 PM PDT 24
Peak memory 281576 kb
Host smart-57b6d462-9414-4cbd-9805-b3eaeb2c7b5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692536456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3692536456
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3101297202
Short name T702
Test name
Test status
Simulation time 24190097715 ps
CPU time 256.25 seconds
Started Jun 22 05:03:45 PM PDT 24
Finished Jun 22 05:08:02 PM PDT 24
Peak memory 248444 kb
Host smart-73c2985c-551c-42c3-8088-90a98ef4bd35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101297202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3101297202
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.432796082
Short name T3
Test name
Test status
Simulation time 596576993 ps
CPU time 13.4 seconds
Started Jun 22 05:03:46 PM PDT 24
Finished Jun 22 05:04:00 PM PDT 24
Peak memory 249196 kb
Host smart-3489201a-0139-4b42-85fb-e0692494df51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43279
6082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.432796082
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1723779366
Short name T664
Test name
Test status
Simulation time 292208487 ps
CPU time 32.87 seconds
Started Jun 22 05:03:47 PM PDT 24
Finished Jun 22 05:04:21 PM PDT 24
Peak memory 255980 kb
Host smart-94db87e7-aa39-49f6-9962-0386df46bdd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17237
79366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1723779366
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2125656031
Short name T701
Test name
Test status
Simulation time 684878742 ps
CPU time 23.08 seconds
Started Jun 22 05:03:47 PM PDT 24
Finished Jun 22 05:04:11 PM PDT 24
Peak memory 249324 kb
Host smart-f689f33f-5838-49b1-9aa7-89799dae07c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21256
56031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2125656031
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.848400393
Short name T617
Test name
Test status
Simulation time 493123450 ps
CPU time 8.8 seconds
Started Jun 22 05:03:46 PM PDT 24
Finished Jun 22 05:03:56 PM PDT 24
Peak memory 252728 kb
Host smart-d99e911b-47a1-4686-b38d-d4a0b1b6b1ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84840
0393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.848400393
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.4011665024
Short name T717
Test name
Test status
Simulation time 127302992406 ps
CPU time 6394.27 seconds
Started Jun 22 05:03:53 PM PDT 24
Finished Jun 22 06:50:29 PM PDT 24
Peak memory 355844 kb
Host smart-f28f950e-6f05-4455-b60f-8d705137a8e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011665024 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.4011665024
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3310075970
Short name T591
Test name
Test status
Simulation time 13503101765 ps
CPU time 1489.03 seconds
Started Jun 22 05:03:53 PM PDT 24
Finished Jun 22 05:28:43 PM PDT 24
Peak memory 288676 kb
Host smart-26466def-8861-4b78-ba6f-d741c914dc81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310075970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3310075970
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2199908087
Short name T112
Test name
Test status
Simulation time 1068121368 ps
CPU time 59.97 seconds
Started Jun 22 05:03:57 PM PDT 24
Finished Jun 22 05:04:58 PM PDT 24
Peak memory 257264 kb
Host smart-d471ff16-617c-4a29-b985-62d279f137ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21999
08087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2199908087
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.4091457448
Short name T548
Test name
Test status
Simulation time 28800271 ps
CPU time 4.38 seconds
Started Jun 22 05:03:54 PM PDT 24
Finished Jun 22 05:03:59 PM PDT 24
Peak memory 250300 kb
Host smart-ea25b4e6-0cda-4c79-ab94-2d5073284a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40914
57448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.4091457448
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3773914926
Short name T345
Test name
Test status
Simulation time 357689185580 ps
CPU time 2225.56 seconds
Started Jun 22 05:03:55 PM PDT 24
Finished Jun 22 05:41:01 PM PDT 24
Peak memory 281948 kb
Host smart-9f662aef-f134-4917-9250-4caca994165c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773914926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3773914926
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.4248046853
Short name T673
Test name
Test status
Simulation time 100374240318 ps
CPU time 1573.99 seconds
Started Jun 22 05:03:55 PM PDT 24
Finished Jun 22 05:30:09 PM PDT 24
Peak memory 273660 kb
Host smart-305a7150-7d9b-42e2-8c92-40d4b310bee7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248046853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.4248046853
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.4137253020
Short name T605
Test name
Test status
Simulation time 1499068390 ps
CPU time 42.39 seconds
Started Jun 22 05:03:53 PM PDT 24
Finished Jun 22 05:04:36 PM PDT 24
Peak memory 255688 kb
Host smart-1573a212-e821-416d-9375-bca6bc4a3e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41372
53020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.4137253020
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2988663051
Short name T478
Test name
Test status
Simulation time 3440601048 ps
CPU time 47.72 seconds
Started Jun 22 05:03:57 PM PDT 24
Finished Jun 22 05:04:46 PM PDT 24
Peak memory 256000 kb
Host smart-6844496d-2bb3-48d9-94c7-8b8e4efac679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29886
63051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2988663051
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2950492419
Short name T490
Test name
Test status
Simulation time 805194835 ps
CPU time 45.18 seconds
Started Jun 22 05:03:56 PM PDT 24
Finished Jun 22 05:04:42 PM PDT 24
Peak memory 255256 kb
Host smart-f12951ee-4e05-4aaf-95a5-b154425dbdc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29504
92419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2950492419
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2552402031
Short name T630
Test name
Test status
Simulation time 1022611870 ps
CPU time 67.57 seconds
Started Jun 22 05:03:57 PM PDT 24
Finished Jun 22 05:05:06 PM PDT 24
Peak memory 256648 kb
Host smart-22ecaac2-a3ff-43f6-8bbd-20c83aef8353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25524
02031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2552402031
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1196539080
Short name T257
Test name
Test status
Simulation time 55927575985 ps
CPU time 3100.22 seconds
Started Jun 22 05:03:57 PM PDT 24
Finished Jun 22 05:55:38 PM PDT 24
Peak memory 306260 kb
Host smart-c91dcd13-4971-4938-8c05-b0260fd4d947
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196539080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1196539080
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.4080626056
Short name T71
Test name
Test status
Simulation time 12608451060 ps
CPU time 1134.86 seconds
Started Jun 22 05:04:01 PM PDT 24
Finished Jun 22 05:22:57 PM PDT 24
Peak memory 281476 kb
Host smart-082a268c-4013-43d6-8cca-9e59f8671af6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080626056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.4080626056
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.289460030
Short name T675
Test name
Test status
Simulation time 13892252684 ps
CPU time 168.17 seconds
Started Jun 22 05:04:03 PM PDT 24
Finished Jun 22 05:06:51 PM PDT 24
Peak memory 257284 kb
Host smart-794b7c07-da44-47a6-941b-32928d93a718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28946
0030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.289460030
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3246864736
Short name T525
Test name
Test status
Simulation time 2206112847 ps
CPU time 37.48 seconds
Started Jun 22 05:03:53 PM PDT 24
Finished Jun 22 05:04:31 PM PDT 24
Peak memory 249188 kb
Host smart-d4391c55-378d-426f-90da-064f3634d571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32468
64736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3246864736
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.106013027
Short name T335
Test name
Test status
Simulation time 9694529693 ps
CPU time 787.16 seconds
Started Jun 22 05:04:01 PM PDT 24
Finished Jun 22 05:17:09 PM PDT 24
Peak memory 273736 kb
Host smart-6074f935-d235-4316-bbf9-b7010c177fe2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106013027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.106013027
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.977207590
Short name T575
Test name
Test status
Simulation time 77973212525 ps
CPU time 1462.77 seconds
Started Jun 22 05:04:02 PM PDT 24
Finished Jun 22 05:28:26 PM PDT 24
Peak memory 289548 kb
Host smart-df3c7a9d-677a-4ed8-b86e-df3815ff4334
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977207590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.977207590
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3347984405
Short name T311
Test name
Test status
Simulation time 3967280082 ps
CPU time 163.3 seconds
Started Jun 22 05:03:59 PM PDT 24
Finished Jun 22 05:06:43 PM PDT 24
Peak memory 249100 kb
Host smart-f571edb7-cb7a-4088-b550-0ca04c922959
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347984405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3347984405
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1216209675
Short name T51
Test name
Test status
Simulation time 300696733 ps
CPU time 32.5 seconds
Started Jun 22 05:03:54 PM PDT 24
Finished Jun 22 05:04:27 PM PDT 24
Peak memory 256452 kb
Host smart-c1a72d83-f014-4713-bb4b-f47a384a28b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12162
09675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1216209675
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3806601387
Short name T479
Test name
Test status
Simulation time 1986269320 ps
CPU time 40.65 seconds
Started Jun 22 05:03:54 PM PDT 24
Finished Jun 22 05:04:36 PM PDT 24
Peak memory 255900 kb
Host smart-3d23ddb3-c7aa-432d-b8f2-66e363c96b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38066
01387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3806601387
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1757115891
Short name T579
Test name
Test status
Simulation time 1702111547 ps
CPU time 26.64 seconds
Started Jun 22 05:04:03 PM PDT 24
Finished Jun 22 05:04:30 PM PDT 24
Peak memory 256152 kb
Host smart-54f8b619-dd8e-4963-82fb-38044b86fac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17571
15891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1757115891
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.2589410301
Short name T382
Test name
Test status
Simulation time 1310015520 ps
CPU time 61.14 seconds
Started Jun 22 05:03:54 PM PDT 24
Finished Jun 22 05:04:56 PM PDT 24
Peak memory 257172 kb
Host smart-4e8bceb9-cdc3-4fb1-abf4-b865da948bde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25894
10301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2589410301
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.559296136
Short name T263
Test name
Test status
Simulation time 144024604702 ps
CPU time 2653.89 seconds
Started Jun 22 05:04:01 PM PDT 24
Finished Jun 22 05:48:16 PM PDT 24
Peak memory 289652 kb
Host smart-8d58312e-6080-4ed5-89be-e8ac13fd8020
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559296136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.559296136
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.203480811
Short name T48
Test name
Test status
Simulation time 424214487383 ps
CPU time 5942.83 seconds
Started Jun 22 05:04:04 PM PDT 24
Finished Jun 22 06:43:08 PM PDT 24
Peak memory 322052 kb
Host smart-5fea3395-3655-46f9-b779-2302ef368a47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203480811 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.203480811
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2074387537
Short name T222
Test name
Test status
Simulation time 53068749 ps
CPU time 3.94 seconds
Started Jun 22 05:01:46 PM PDT 24
Finished Jun 22 05:01:51 PM PDT 24
Peak memory 249280 kb
Host smart-d0d86141-725b-4e3d-8ded-2d7090be6e18
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2074387537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2074387537
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.4129616507
Short name T464
Test name
Test status
Simulation time 774573138 ps
CPU time 32.75 seconds
Started Jun 22 05:01:42 PM PDT 24
Finished Jun 22 05:02:16 PM PDT 24
Peak memory 249112 kb
Host smart-e34ba164-4842-4a0d-8240-89bc7fb74929
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4129616507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.4129616507
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1852224401
Short name T397
Test name
Test status
Simulation time 4008306566 ps
CPU time 231.54 seconds
Started Jun 22 05:01:52 PM PDT 24
Finished Jun 22 05:05:44 PM PDT 24
Peak memory 251360 kb
Host smart-306960e5-5f2e-4de4-8d4d-130b62613812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18522
24401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1852224401
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2209988827
Short name T542
Test name
Test status
Simulation time 272320091 ps
CPU time 29.73 seconds
Started Jun 22 05:01:41 PM PDT 24
Finished Jun 22 05:02:12 PM PDT 24
Peak memory 256340 kb
Host smart-6de8a87e-ad71-4e6f-8d92-6432a1702525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22099
88827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2209988827
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2668844112
Short name T469
Test name
Test status
Simulation time 71469845725 ps
CPU time 2331.37 seconds
Started Jun 22 05:01:52 PM PDT 24
Finished Jun 22 05:40:44 PM PDT 24
Peak memory 289320 kb
Host smart-1f999742-74c4-45ff-b1fb-b1afe5a8b5d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668844112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2668844112
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3376353277
Short name T325
Test name
Test status
Simulation time 50976961097 ps
CPU time 461.13 seconds
Started Jun 22 05:01:48 PM PDT 24
Finished Jun 22 05:09:31 PM PDT 24
Peak memory 248732 kb
Host smart-c0a22e95-20f1-460f-98d3-adffc723e7ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376353277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3376353277
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1656029183
Short name T678
Test name
Test status
Simulation time 4460835609 ps
CPU time 34.3 seconds
Started Jun 22 05:01:41 PM PDT 24
Finished Jun 22 05:02:17 PM PDT 24
Peak memory 249268 kb
Host smart-30279384-5613-4916-8ab7-0d73eb671e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16560
29183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1656029183
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1586729866
Short name T141
Test name
Test status
Simulation time 1971649816 ps
CPU time 11.63 seconds
Started Jun 22 05:01:45 PM PDT 24
Finished Jun 22 05:01:57 PM PDT 24
Peak memory 253328 kb
Host smart-a6c076c0-839c-4b5b-9372-39b82711b924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15867
29866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1586729866
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3109534996
Short name T471
Test name
Test status
Simulation time 584264792 ps
CPU time 31.57 seconds
Started Jun 22 05:01:50 PM PDT 24
Finished Jun 22 05:02:23 PM PDT 24
Peak memory 255956 kb
Host smart-532b8dc1-0b18-406a-982d-f5006ab074a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31095
34996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3109534996
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3737555482
Short name T379
Test name
Test status
Simulation time 188647647 ps
CPU time 15.2 seconds
Started Jun 22 05:01:45 PM PDT 24
Finished Jun 22 05:02:01 PM PDT 24
Peak memory 249072 kb
Host smart-b3753557-c36d-4373-b163-d49199e06013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37375
55482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3737555482
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1388115934
Short name T595
Test name
Test status
Simulation time 10754700783 ps
CPU time 55.51 seconds
Started Jun 22 05:01:50 PM PDT 24
Finished Jun 22 05:02:46 PM PDT 24
Peak memory 257252 kb
Host smart-4d86e70c-d4cc-4ba3-bb69-02c5bb1c4eca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388115934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1388115934
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.4009034097
Short name T491
Test name
Test status
Simulation time 73682910995 ps
CPU time 1375.11 seconds
Started Jun 22 05:01:43 PM PDT 24
Finished Jun 22 05:24:39 PM PDT 24
Peak memory 288796 kb
Host smart-4abdb67a-2c38-40c7-b702-92cbef31e973
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009034097 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.4009034097
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3864267438
Short name T226
Test name
Test status
Simulation time 24937111 ps
CPU time 2.36 seconds
Started Jun 22 05:01:53 PM PDT 24
Finished Jun 22 05:01:56 PM PDT 24
Peak memory 249240 kb
Host smart-8dc6def3-a957-41c9-85fd-b3df6942362b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3864267438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3864267438
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3035113754
Short name T432
Test name
Test status
Simulation time 120444356714 ps
CPU time 2072.91 seconds
Started Jun 22 05:01:50 PM PDT 24
Finished Jun 22 05:36:24 PM PDT 24
Peak memory 289256 kb
Host smart-d12a95a1-ce73-4cdd-a4f9-8b47d4ce321f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035113754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3035113754
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1206203801
Short name T677
Test name
Test status
Simulation time 190643149 ps
CPU time 10.23 seconds
Started Jun 22 05:01:55 PM PDT 24
Finished Jun 22 05:02:06 PM PDT 24
Peak memory 249092 kb
Host smart-38500df8-6acd-4fd9-97d9-a355f1b7497c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1206203801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1206203801
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1270890612
Short name T521
Test name
Test status
Simulation time 9398530493 ps
CPU time 139.5 seconds
Started Jun 22 05:01:47 PM PDT 24
Finished Jun 22 05:04:07 PM PDT 24
Peak memory 257332 kb
Host smart-d603090b-a98e-43c2-a24c-1634709c18a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12708
90612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1270890612
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2035826165
Short name T596
Test name
Test status
Simulation time 121795550 ps
CPU time 8 seconds
Started Jun 22 05:01:42 PM PDT 24
Finished Jun 22 05:01:51 PM PDT 24
Peak memory 252664 kb
Host smart-8ea29956-6024-4ebb-8db6-2cfdc068f58c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20358
26165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2035826165
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2054701628
Short name T341
Test name
Test status
Simulation time 159421356153 ps
CPU time 2237.77 seconds
Started Jun 22 05:01:52 PM PDT 24
Finished Jun 22 05:39:10 PM PDT 24
Peak memory 288996 kb
Host smart-f8823ff8-c800-4264-9afa-586cc82cc1fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054701628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2054701628
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3737618388
Short name T572
Test name
Test status
Simulation time 10239073926 ps
CPU time 939.5 seconds
Started Jun 22 05:01:56 PM PDT 24
Finished Jun 22 05:17:36 PM PDT 24
Peak memory 273372 kb
Host smart-07f022e5-c177-47d7-83db-5c81a2b69644
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737618388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3737618388
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2805532590
Short name T712
Test name
Test status
Simulation time 30281880277 ps
CPU time 356.75 seconds
Started Jun 22 05:02:07 PM PDT 24
Finished Jun 22 05:08:05 PM PDT 24
Peak memory 247576 kb
Host smart-7312e537-acc2-4a98-a10e-1f5af6902120
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805532590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2805532590
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1036254231
Short name T502
Test name
Test status
Simulation time 770764741 ps
CPU time 32 seconds
Started Jun 22 05:01:56 PM PDT 24
Finished Jun 22 05:02:29 PM PDT 24
Peak memory 256576 kb
Host smart-c7f6363e-9e6a-4d37-a963-2e4dfca7d763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10362
54231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1036254231
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2568649351
Short name T558
Test name
Test status
Simulation time 89143132 ps
CPU time 11.36 seconds
Started Jun 22 05:01:37 PM PDT 24
Finished Jun 22 05:01:50 PM PDT 24
Peak memory 249216 kb
Host smart-4ed5ac68-acd6-4188-b8e2-b2d8b2e45572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25686
49351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2568649351
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2984031665
Short name T413
Test name
Test status
Simulation time 813349766 ps
CPU time 43.34 seconds
Started Jun 22 05:01:49 PM PDT 24
Finished Jun 22 05:02:33 PM PDT 24
Peak memory 256428 kb
Host smart-c4c674aa-ad0d-4273-8ce1-4528d4ce748e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29840
31665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2984031665
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.4100736798
Short name T137
Test name
Test status
Simulation time 603956989 ps
CPU time 33.69 seconds
Started Jun 22 05:01:46 PM PDT 24
Finished Jun 22 05:02:20 PM PDT 24
Peak memory 249108 kb
Host smart-12abd003-9cee-4e6b-b236-8e93caba989d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41007
36798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.4100736798
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1047189668
Short name T665
Test name
Test status
Simulation time 29884380816 ps
CPU time 802.39 seconds
Started Jun 22 05:01:49 PM PDT 24
Finished Jun 22 05:15:13 PM PDT 24
Peak memory 265456 kb
Host smart-08fb929e-9ab2-454f-a810-6e3592824ec5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047189668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1047189668
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.988125529
Short name T132
Test name
Test status
Simulation time 66919904942 ps
CPU time 2863.73 seconds
Started Jun 22 05:01:49 PM PDT 24
Finished Jun 22 05:49:34 PM PDT 24
Peak memory 289040 kb
Host smart-2c912037-b7a0-432a-817d-dc2679bd5b8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988125529 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.988125529
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.4165454663
Short name T233
Test name
Test status
Simulation time 112395246 ps
CPU time 3.23 seconds
Started Jun 22 05:01:54 PM PDT 24
Finished Jun 22 05:01:58 PM PDT 24
Peak memory 249200 kb
Host smart-7d22bd7d-2899-4228-a963-a43fe28104ee
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4165454663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.4165454663
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1330864216
Short name T615
Test name
Test status
Simulation time 39124023653 ps
CPU time 943.62 seconds
Started Jun 22 05:01:57 PM PDT 24
Finished Jun 22 05:17:41 PM PDT 24
Peak memory 273580 kb
Host smart-f0ca949e-68e8-4801-90bb-e074862f4bb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330864216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1330864216
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1928493813
Short name T711
Test name
Test status
Simulation time 3503648513 ps
CPU time 42.33 seconds
Started Jun 22 05:02:04 PM PDT 24
Finished Jun 22 05:02:47 PM PDT 24
Peak memory 249232 kb
Host smart-1b9db7f5-7b91-4a65-bd46-2f008dc561c3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1928493813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1928493813
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2579397360
Short name T208
Test name
Test status
Simulation time 3973394986 ps
CPU time 212.8 seconds
Started Jun 22 05:01:58 PM PDT 24
Finished Jun 22 05:05:32 PM PDT 24
Peak memory 257352 kb
Host smart-28cdc2fc-cb69-438e-a095-eb9174ff63b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25793
97360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2579397360
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.4245486725
Short name T499
Test name
Test status
Simulation time 139479582 ps
CPU time 13.21 seconds
Started Jun 22 05:01:54 PM PDT 24
Finished Jun 22 05:02:08 PM PDT 24
Peak memory 249108 kb
Host smart-17aa0d97-dca6-4c07-83a2-0cc2a9c00255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42454
86725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.4245486725
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3819268799
Short name T28
Test name
Test status
Simulation time 106263664823 ps
CPU time 757.29 seconds
Started Jun 22 05:01:55 PM PDT 24
Finished Jun 22 05:14:33 PM PDT 24
Peak memory 265556 kb
Host smart-82789b43-5ea0-4b8b-bb79-558f6f80d3dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819268799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3819268799
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.545612477
Short name T473
Test name
Test status
Simulation time 8915456128 ps
CPU time 642.97 seconds
Started Jun 22 05:02:01 PM PDT 24
Finished Jun 22 05:12:45 PM PDT 24
Peak memory 265504 kb
Host smart-5a261e36-a429-43aa-897d-7f5f0f5ab355
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545612477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.545612477
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1717900244
Short name T313
Test name
Test status
Simulation time 10820805499 ps
CPU time 437.65 seconds
Started Jun 22 05:01:49 PM PDT 24
Finished Jun 22 05:09:08 PM PDT 24
Peak memory 248708 kb
Host smart-7765bb87-974a-4ea3-aa8d-2f7ec521f599
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717900244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1717900244
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.883748970
Short name T516
Test name
Test status
Simulation time 31795704 ps
CPU time 2.91 seconds
Started Jun 22 05:01:56 PM PDT 24
Finished Jun 22 05:01:59 PM PDT 24
Peak memory 240788 kb
Host smart-f83db09c-e91b-4290-94af-8a9a2f137d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88374
8970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.883748970
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1612305096
Short name T489
Test name
Test status
Simulation time 129893867 ps
CPU time 9.89 seconds
Started Jun 22 05:01:52 PM PDT 24
Finished Jun 22 05:02:07 PM PDT 24
Peak memory 254492 kb
Host smart-9a30da6f-9846-4031-973c-95443b5e402b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16123
05096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1612305096
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.139776363
Short name T414
Test name
Test status
Simulation time 324063202 ps
CPU time 16.17 seconds
Started Jun 22 05:01:53 PM PDT 24
Finished Jun 22 05:02:10 PM PDT 24
Peak memory 257264 kb
Host smart-1580ed58-108c-4e08-9f92-4585e4d10d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13977
6363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.139776363
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1112811743
Short name T680
Test name
Test status
Simulation time 59316544262 ps
CPU time 3490.65 seconds
Started Jun 22 05:01:54 PM PDT 24
Finished Jun 22 06:00:06 PM PDT 24
Peak memory 289952 kb
Host smart-6612f063-3fff-472c-b52b-fd7aca4e6e40
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112811743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1112811743
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.280294666
Short name T232
Test name
Test status
Simulation time 17111638 ps
CPU time 2.85 seconds
Started Jun 22 05:01:59 PM PDT 24
Finished Jun 22 05:02:03 PM PDT 24
Peak memory 249284 kb
Host smart-cad164c3-7a9d-4355-a61d-684cb92bfa30
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=280294666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.280294666
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3733664732
Short name T55
Test name
Test status
Simulation time 14722834337 ps
CPU time 1078.3 seconds
Started Jun 22 05:02:02 PM PDT 24
Finished Jun 22 05:20:01 PM PDT 24
Peak memory 273624 kb
Host smart-d1b97105-b22d-4168-bb76-878d44c9a4c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733664732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3733664732
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.202245313
Short name T634
Test name
Test status
Simulation time 411239894 ps
CPU time 15.67 seconds
Started Jun 22 05:01:59 PM PDT 24
Finished Jun 22 05:02:16 PM PDT 24
Peak memory 249104 kb
Host smart-efa408d2-3ce7-4fd2-b70c-8880c55fce76
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=202245313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.202245313
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2097439512
Short name T209
Test name
Test status
Simulation time 41448532897 ps
CPU time 279.2 seconds
Started Jun 22 05:01:55 PM PDT 24
Finished Jun 22 05:06:34 PM PDT 24
Peak memory 251260 kb
Host smart-95531139-67d6-44b1-a601-333a3fe95b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20974
39512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2097439512
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.4018612968
Short name T416
Test name
Test status
Simulation time 548112675 ps
CPU time 28.92 seconds
Started Jun 22 05:01:54 PM PDT 24
Finished Jun 22 05:02:23 PM PDT 24
Peak memory 249172 kb
Host smart-f304f3d6-9d83-4cb5-9b07-ac0c7d710e4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40186
12968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.4018612968
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.4121038447
Short name T338
Test name
Test status
Simulation time 35355126358 ps
CPU time 1396.39 seconds
Started Jun 22 05:02:05 PM PDT 24
Finished Jun 22 05:25:22 PM PDT 24
Peak memory 288952 kb
Host smart-2eb00894-4419-4c3e-b629-fc9daf8969ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121038447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.4121038447
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1094811846
Short name T373
Test name
Test status
Simulation time 100242875082 ps
CPU time 2883.98 seconds
Started Jun 22 05:01:52 PM PDT 24
Finished Jun 22 05:49:57 PM PDT 24
Peak memory 290140 kb
Host smart-a5daa01a-b84d-495b-81e7-0a2c3d30dd26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094811846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1094811846
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3377619263
Short name T306
Test name
Test status
Simulation time 4820093260 ps
CPU time 201.11 seconds
Started Jun 22 05:01:57 PM PDT 24
Finished Jun 22 05:05:19 PM PDT 24
Peak memory 248724 kb
Host smart-725b4b8c-3d3a-4a30-a4c7-04e5862a9c96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377619263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3377619263
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.4220814034
Short name T597
Test name
Test status
Simulation time 1249823275 ps
CPU time 48.94 seconds
Started Jun 22 05:02:00 PM PDT 24
Finished Jun 22 05:02:50 PM PDT 24
Peak memory 256284 kb
Host smart-ab20b428-7d5c-4f9f-814a-42686b0cfb50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42208
14034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.4220814034
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.507447244
Short name T637
Test name
Test status
Simulation time 998814896 ps
CPU time 42.81 seconds
Started Jun 22 05:01:48 PM PDT 24
Finished Jun 22 05:02:32 PM PDT 24
Peak memory 249148 kb
Host smart-5287d67a-debd-4695-b840-a86dfda1912b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50744
7244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.507447244
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3992416021
Short name T40
Test name
Test status
Simulation time 1369364992 ps
CPU time 34.91 seconds
Started Jun 22 05:01:55 PM PDT 24
Finished Jun 22 05:02:31 PM PDT 24
Peak memory 248172 kb
Host smart-990c3d4e-406e-4151-8043-8491c86c72ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39924
16021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3992416021
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3907256581
Short name T556
Test name
Test status
Simulation time 202904971 ps
CPU time 17.25 seconds
Started Jun 22 05:01:55 PM PDT 24
Finished Jun 22 05:02:13 PM PDT 24
Peak memory 248876 kb
Host smart-9254d10f-8c1b-4edc-91b7-0497b4557aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39072
56581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3907256581
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.489282076
Short name T486
Test name
Test status
Simulation time 86353156706 ps
CPU time 2188.18 seconds
Started Jun 22 05:01:58 PM PDT 24
Finished Jun 22 05:38:27 PM PDT 24
Peak memory 285004 kb
Host smart-c18ee58e-c0af-4cf0-a01d-3fdd4f887378
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489282076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.489282076
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.1852399245
Short name T264
Test name
Test status
Simulation time 99950220885 ps
CPU time 2114.43 seconds
Started Jun 22 05:01:56 PM PDT 24
Finished Jun 22 05:37:12 PM PDT 24
Peak memory 288044 kb
Host smart-ce22168d-3227-447b-8400-a4c8bbadc0c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852399245 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.1852399245
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1331018084
Short name T229
Test name
Test status
Simulation time 24121333 ps
CPU time 2.26 seconds
Started Jun 22 05:02:10 PM PDT 24
Finished Jun 22 05:02:13 PM PDT 24
Peak memory 249136 kb
Host smart-9d2aab2c-7909-4111-b6aa-eecfeef23958
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1331018084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1331018084
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.406811963
Short name T666
Test name
Test status
Simulation time 206185465786 ps
CPU time 1166.49 seconds
Started Jun 22 05:02:01 PM PDT 24
Finished Jun 22 05:21:29 PM PDT 24
Peak memory 289824 kb
Host smart-fd8ed2a2-57b1-4634-9808-52f576a8f6fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406811963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.406811963
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2957023960
Short name T668
Test name
Test status
Simulation time 159100773 ps
CPU time 8.89 seconds
Started Jun 22 05:02:16 PM PDT 24
Finished Jun 22 05:02:26 PM PDT 24
Peak memory 249004 kb
Host smart-19400ed9-8ce1-4540-ba5c-8d18ee85e9f3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2957023960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2957023960
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.200501080
Short name T36
Test name
Test status
Simulation time 8653319131 ps
CPU time 230.51 seconds
Started Jun 22 05:02:01 PM PDT 24
Finished Jun 22 05:05:52 PM PDT 24
Peak memory 251416 kb
Host smart-8b42c818-a829-4c36-a417-096dbcd57755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20050
1080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.200501080
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3631708039
Short name T709
Test name
Test status
Simulation time 885483434 ps
CPU time 17.16 seconds
Started Jun 22 05:01:52 PM PDT 24
Finished Jun 22 05:02:09 PM PDT 24
Peak memory 254440 kb
Host smart-bb87ae5a-41d1-4240-bfd2-5529daf15494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36317
08039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3631708039
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.383648385
Short name T492
Test name
Test status
Simulation time 31196544413 ps
CPU time 961.99 seconds
Started Jun 22 05:02:15 PM PDT 24
Finished Jun 22 05:18:19 PM PDT 24
Peak memory 288992 kb
Host smart-70e88159-3fe5-49e3-ab90-94b588c2fb05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383648385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.383648385
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3245702462
Short name T600
Test name
Test status
Simulation time 52898869592 ps
CPU time 380.6 seconds
Started Jun 22 05:02:09 PM PDT 24
Finished Jun 22 05:08:30 PM PDT 24
Peak memory 248372 kb
Host smart-af560b88-3c1a-41da-b004-aeb6a3f5c7a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245702462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3245702462
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1613314859
Short name T580
Test name
Test status
Simulation time 219059836 ps
CPU time 23.73 seconds
Started Jun 22 05:02:03 PM PDT 24
Finished Jun 22 05:02:27 PM PDT 24
Peak memory 249036 kb
Host smart-a8539f98-0411-4144-b77c-cd45217061f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16133
14859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1613314859
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.537957827
Short name T121
Test name
Test status
Simulation time 462980394 ps
CPU time 36.75 seconds
Started Jun 22 05:02:01 PM PDT 24
Finished Jun 22 05:02:39 PM PDT 24
Peak memory 247984 kb
Host smart-1adb116a-d929-405f-acaa-d14b1401acee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53795
7827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.537957827
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3825614970
Short name T699
Test name
Test status
Simulation time 3560821926 ps
CPU time 50.06 seconds
Started Jun 22 05:02:02 PM PDT 24
Finished Jun 22 05:02:52 PM PDT 24
Peak memory 256152 kb
Host smart-36caa68b-2124-4c58-bde5-2252ef2ac70f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38256
14970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3825614970
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2478723161
Short name T425
Test name
Test status
Simulation time 28115791 ps
CPU time 4.51 seconds
Started Jun 22 05:01:59 PM PDT 24
Finished Jun 22 05:02:04 PM PDT 24
Peak memory 240896 kb
Host smart-bfe66d4d-b297-4191-90ef-268d447093ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24787
23161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2478723161
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1213815911
Short name T603
Test name
Test status
Simulation time 7379036573 ps
CPU time 164.78 seconds
Started Jun 22 05:01:59 PM PDT 24
Finished Jun 22 05:04:45 PM PDT 24
Peak memory 257360 kb
Host smart-28b06bdb-9f98-4cfa-9b86-ba886d023e30
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213815911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1213815911
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.3075396261
Short name T56
Test name
Test status
Simulation time 104304274232 ps
CPU time 2621.84 seconds
Started Jun 22 05:02:00 PM PDT 24
Finished Jun 22 05:45:43 PM PDT 24
Peak memory 322260 kb
Host smart-6570d801-5e8f-4446-a5ef-419285046b53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075396261 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.3075396261
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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