Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	119057	1			T3	9		T19	2		T14	1
class_i[0x1]	39755	1			T1	5		T14	6		T64	4
class_i[0x2]	49965	1			T1	2		T19	4		T24	16
class_i[0x3]	62795	1			T1	8		T3	5		T24	1213

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	68944	1			T1	8		T3	5		T19	1
alert[0x1]	69262	1			T1	1		T3	2		T19	4
alert[0x2]	65019	1			T1	3		T19	1		T14	2
alert[0x3]	68347	1			T1	3		T3	7		T24	390

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

271309

1

T1

15

T3

9

T19

6

esc_ping_fail

263

1

T3

5

T8

8

T9

9

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	68868	1			T1	8		T3	3		T19	1
esc_integrity_fail	alert[0x1]	69199	1			T1	1		T3	1		T19	4
esc_integrity_fail	alert[0x2]	64960	1			T1	3		T19	1		T14	2
esc_integrity_fail	alert[0x3]	68282	1			T1	3		T3	5		T24	390
esc_ping_fail	alert[0x0]	76	1			T3	2		T8	2		T9	3
esc_ping_fail	alert[0x1]	63	1			T3	1		T8	2		T9	2
esc_ping_fail	alert[0x2]	59	1			T8	2		T9	3		T261	1
esc_ping_fail	alert[0x3]	65	1			T3	2		T8	2		T9	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	118992	1			T3	9		T19	2		T14	1
esc_integrity_fail	class_i[0x1]	39684	1			T1	5		T14	6		T64	4
esc_integrity_fail	class_i[0x2]	49899	1			T1	2		T19	4		T24	16
esc_integrity_fail	class_i[0x3]	62734	1			T1	8		T24	1213		T26	5
esc_ping_fail	class_i[0x0]	65	1			T295	2		T261	1		T302	7
esc_ping_fail	class_i[0x1]	71	1			T8	1		T300	6		T229	4
esc_ping_fail	class_i[0x2]	66	1			T8	6		T9	9		T261	3
esc_ping_fail	class_i[0x3]	61	1			T3	5		T8	1		T62	1