Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	693566296	0	0	629
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	693566296	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	693566296	693394925	0	0
tb.dut.CheckAccuCntDw	0	0	629	629	0	0
tb.dut.CheckEscCntDw	0	0	629	629	0	0
tb.dut.CheckNAlerts	0	0	629	629	0	0
tb.dut.CheckNClasses	0	0	629	629	0	0
tb.dut.CheckNEscSev	0	0	629	629	0	0
tb.dut.CrashdumpKnownO_A	0	0	693566296	693394925	0	0
tb.dut.EdnKnownO_A	0	0	693566296	693394925	0	0
tb.dut.EscPKnownO_A	0	0	693566296	693394925	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	693566296	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	693566296	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	693566296	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	693566296	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	693566296	80	0	0
tb.dut.IrqAKnownO_A	0	0	693566296	693394925	0	0
tb.dut.IrqBKnownO_A	0	0	693566296	693394925	0	0
tb.dut.IrqCKnownO_A	0	0	693566296	693394925	0	0
tb.dut.IrqDKnownO_A	0	0	693566296	693394925	0	0
tb.dut.TlAReadyKnownO_A	0	0	693566296	693394925	0	0
tb.dut.TlDValidKnownO_A	0	0	693566296	693394925	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	719473250	3785339	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	719473250	15767	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	719473250	15802	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	719473250	15771	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	719473250	15824	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	719473250	16436	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	719473250	16426	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	719473250	16503	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	719473250	15878	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	719473250	16392	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	719473250	16991	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	719473250	16777	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	719473250	15994	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	719473250	15751	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	719473250	16052	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	719473250	15734	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	719473250	15884	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	719473250	16239	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	719473250	16093	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	719473250	15890	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	719473250	15817	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	719473250	16053	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	719473250	16309	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	719473250	16008	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	719473250	15952	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	719473250	15715	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	719473250	15921	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	719473250	15660	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	719473250	16349	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	719473250	16131	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	719473250	16778	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	719473250	15867	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	719473250	15835	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	719473250	16361	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	719473250	15853	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	719473250	16047	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	719473250	16413	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	719473250	16589	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	719473250	15714	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	719473250	16155	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	719473250	16177	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	719473250	16408	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	719473250	16309	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	719473250	15953	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	719473250	16189	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	719473250	15951	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	719473250	16020	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	719473250	15966	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	719473250	16173	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	719473250	16663	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	719473250	16622	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	719473250	16346	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	719473250	16538	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	719473250	15867	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	719473250	16452	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	719473250	16148	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	719473250	16396	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	719473250	16112	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	719473250	15807	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	719473250	16343	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	719473250	15783	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	719473250	15970	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	719473250	16162	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	719473250	16065	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	719473250	16266	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	719473250	15648	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	719473250	15963	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	719473250	16026	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	719473250	15874	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	719473250	16749	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	719473250	29388	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	719473250	16041	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	719473250	16238	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	719473250	16851	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	719473250	16098	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	719473250	16805	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	719473250	16062	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	719473250	15774	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	719473250	16188	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	693566296	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	693566296	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	693566296	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	693566296	4326	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	693566296	224191	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	693566296	340965123	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	693566296	271	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	693566296	858	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	693566296	42	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	693566296	415	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	693400511	228547725	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	693566296	955	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	693566296	928	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	693566296	908	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	693566296	892	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	693566296	771	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	693566296	86205	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	693566296	656	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	693566296	72	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	693566296	1495	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	693566296	1255	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	693399168	693329590	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	629	629	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	693566296	693394925	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	693566296	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	693566296	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	693566296	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	693566296	3296	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	693566296	209280	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	693566296	320612427	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	693566296	342	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	693566296	529	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	693566296	22	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	693566296	216	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	693400511	256161919	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	693566296	609	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	693566296	592	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	693566296	578	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	693566296	566	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	693566296	1407	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	693566296	170502	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	693566296	1318	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	693566296	65	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	693566296	1505	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	693566296	1265	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	693399168	693329590	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	629	629	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	693566296	693394925	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	693566296	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	693566296	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	693566296	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	693566296	2345	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	693566296	213285	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	693566296	358557815	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	693566296	270	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	693566296	544	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	693566296	23	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	693566296	238	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	693400511	275284040	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	693566296	597	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	693566296	580	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	693566296	560	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	693566296	549	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	693566296	1311	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	693566296	134690	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	693566296	1236	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	693566296	49	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	693566296	1426	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	693566296	1186	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	693399168	693329590	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	629	629	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	693566296	693394925	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	693566296	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	693566296	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	693566296	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	693566296	3613	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	693566296	209259	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	693566296	373323997	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	693566296	335	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	693566296	515	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	693566296	23	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	693566296	216	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	693400511	294124193	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	693566296	595	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	693566296	584	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	693566296	570	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	693566296	560	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	693566296	1098	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	693566296	125749	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	693566296	1008	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	693566296	65	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	693566296	1500	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	693566296	1260	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	693399168	693329590	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	629	629	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	693566296	693394925	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	719473250	145401576	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	719473250	718801860	0	0
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