Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	3	41	93.18

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	3	41	93.18	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	184	1			T1	2		T6	1		T26	2
index[0x1]	169	1			T6	2		T19	1		T24	1
index[0x2]	168	1			T1	2		T23	1		T33	2
index[0x3]	172	1			T5	2		T23	2		T24	7

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	204	1			T1	3		T19	1		T23	1
lens_less_than_1000[1]	152	1			T5	2		T6	1		T23	1
lens_less_than_1000[2]	107	1			T6	1		T33	2		T16	1
lens_less_than_1000[3]	86	1			T33	1		T26	4		T65	2
lens_less_than_1000[4]	45	1			T28	1		T77	2		T92	1
lens_less_than_1000[5]	39	1			T79	1		T36	1		T56	2
lens_less_than_1000[6]	30	1			T1	1		T117	1		T79	2
lens_less_than_1000[7]	19	1			T6	1		T80	1		T36	1
lens_less_than_1000[8]	6	1			T23	1		T246	1		T216	1
lens_less_than_1000[9]	1	1			T33	1		-	-		-	-
len_2	4	1			T247	1		T248	1		T249	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	3	41	93.18	3

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0] , index[0x1]]	[lens_less_than_1000[9]]	--	--	2
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	52	1			T1	1		T64	1		T250	1
index[0x0]	lens_less_than_1000[1]	40	1			T182	1		T65	2		T114	1
index[0x0]	lens_less_than_1000[2]	37	1			T26	1		T251	1		T79	1
index[0x0]	lens_less_than_1000[3]	13	1			T26	1		T38	1		T252	1
index[0x0]	lens_less_than_1000[4]	19	1			T28	1		T77	2		T38	1
index[0x0]	lens_less_than_1000[5]	11	1			T79	1		T88	1		T253	1
index[0x0]	lens_less_than_1000[6]	8	1			T1	1		T85	1		T254	1
index[0x0]	lens_less_than_1000[7]	2	1			T6	1		T36	1		-	-
index[0x0]	lens_less_than_1000[8]	1	1			T216	1		-	-		-	-
index[0x0]	len_2	1	1			T247	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	49	1			T19	1		T24	1		T64	1
index[0x1]	lens_less_than_1000[1]	36	1			T6	1		T66	1		T79	1
index[0x1]	lens_less_than_1000[2]	28	1			T6	1		T33	1		T79	2
index[0x1]	lens_less_than_1000[3]	22	1			T33	1		T26	1		T28	1
index[0x1]	lens_less_than_1000[4]	5	1			T92	1		T101	1		T247	1
index[0x1]	lens_less_than_1000[5]	13	1			T37	1		T38	3		T255	1
index[0x1]	lens_less_than_1000[6]	10	1			T117	1		T79	2		T256	1
index[0x1]	lens_less_than_1000[7]	4	1			T257	1		T225	1		T258	1
index[0x1]	lens_less_than_1000[8]	1	1			T259	1		-	-		-	-
index[0x1]	len_2	1	1			T248	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	46	1			T1	2		T79	1		T39	1
index[0x2]	lens_less_than_1000[1]	28	1			T23	1		T26	1		T260	1
index[0x2]	lens_less_than_1000[2]	25	1			T33	1		T74	1		T261	1
index[0x2]	lens_less_than_1000[3]	34	1			T66	1		T77	8		T94	1
index[0x2]	lens_less_than_1000[4]	8	1			T36	1		T101	1		T50	1
index[0x2]	lens_less_than_1000[5]	9	1			T36	1		T38	1		T262	1
index[0x2]	lens_less_than_1000[6]	7	1			T57	1		T44	1		T88	1
index[0x2]	lens_less_than_1000[7]	7	1			T230	1		T248	1		T263	3
index[0x2]	lens_less_than_1000[8]	2	1			T246	1		T225	1		-	-
index[0x2]	lens_less_than_1000[9]	1	1			T33	1		-	-		-	-
index[0x2]	len_2	1	1			T264	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	57	1			T23	1		T24	6		T34	2
index[0x3]	lens_less_than_1000[1]	48	1			T5	2		T24	1		T27	5
index[0x3]	lens_less_than_1000[2]	17	1			T16	1		T46	1		T104	1
index[0x3]	lens_less_than_1000[3]	17	1			T26	2		T65	2		T39	1
index[0x3]	lens_less_than_1000[4]	13	1			T119	1		T44	1		T233	1
index[0x3]	lens_less_than_1000[5]	6	1			T56	2		T88	1		T265	1
index[0x3]	lens_less_than_1000[6]	5	1			T36	1		T38	1		T257	1
index[0x3]	lens_less_than_1000[7]	6	1			T80	1		T252	1		T89	1
index[0x3]	lens_less_than_1000[8]	2	1			T23	1		T222	1		-	-
index[0x3]	len_2	1	1			T249	1		-	-		-	-