Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	72	1			T19	2		T23	4		T70	1
class_index[0x1]	65	1			T19	2		T64	1		T36	1
class_index[0x2]	49	1			T1	1		T77	1		T60	1
class_index[0x3]	65	1			T19	1		T34	1		T103	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	98	1			T19	1		T23	1		T79	1
intr_timeout_cnt[1]	67	1			T19	1		T37	2		T39	1
intr_timeout_cnt[2]	26	1			T23	3		T34	1		T64	1
intr_timeout_cnt[3]	14	1			T37	1		T88	2		T122	1
intr_timeout_cnt[4]	10	1			T41	1		T85	1		T266	1
intr_timeout_cnt[5]	7	1			T38	1		T122	1		T247	1
intr_timeout_cnt[6]	10	1			T1	1		T19	1		T36	1
intr_timeout_cnt[7]	10	1			T19	2		T85	1		T101	1
intr_timeout_cnt[8]	5	1			T103	1		T100	1		T247	1
intr_timeout_cnt[9]	4	1			T122	1		T222	1		T267	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x2]]	[intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	2

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	30	1			T19	1		T23	1		T77	1
class_index[0x0]	intr_timeout_cnt[1]	20	1			T19	1		T37	1		T87	1
class_index[0x0]	intr_timeout_cnt[2]	8	1			T23	3		T70	1		T102	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T268	1		T186	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	4	1			T41	1		T269	1		T270	2
class_index[0x0]	intr_timeout_cnt[5]	2	1			T38	1		T271	1		-	-
class_index[0x0]	intr_timeout_cnt[6]	1	1			T272	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	2	1			T273	1		T274	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	2	1			T100	1		T275	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T238	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	22	1			T60	1		T88	1		T95	1
class_index[0x1]	intr_timeout_cnt[1]	16	1			T37	1		T83	1		T90	1
class_index[0x1]	intr_timeout_cnt[2]	7	1			T64	1		T36	1		T38	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T88	1		T276	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	3	1			T85	1		T269	1		T277	1
class_index[0x1]	intr_timeout_cnt[5]	2	1			T122	1		T247	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	7	1			T19	1		T247	1		T258	1
class_index[0x1]	intr_timeout_cnt[7]	3	1			T19	1		T122	1		T259	1
class_index[0x1]	intr_timeout_cnt[8]	2	1			T247	1		T278	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T267	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	13	1			T77	1		T60	1		T37	1
class_index[0x2]	intr_timeout_cnt[1]	14	1			T39	1		T88	1		T101	1
class_index[0x2]	intr_timeout_cnt[2]	7	1			T101	1		T279	1		T280	3
class_index[0x2]	intr_timeout_cnt[3]	7	1			T88	1		T122	1		T257	1
class_index[0x2]	intr_timeout_cnt[4]	2	1			T266	1		T281	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	2	1			T282	1		T275	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	1	1			T1	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	3	1			T101	1		T274	2		-	-
class_index[0x3]	intr_timeout_cnt[0]	33	1			T79	1		T36	1		T61	3
class_index[0x3]	intr_timeout_cnt[1]	17	1			T119	1		T41	1		T84	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T34	1		T283	1		T89	2
class_index[0x3]	intr_timeout_cnt[3]	3	1			T37	1		T238	1		T284	1
class_index[0x3]	intr_timeout_cnt[4]	1	1			T285	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	1	1			T286	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	1	1			T36	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T19	1		T85	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T103	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	2	1			T122	1		T222	1		-	-