Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	362205	1			T1	250		T2	11		T3	31
all_values[1]	362205	1			T1	250		T2	11		T3	31
all_values[2]	362205	1			T1	250		T2	11		T3	31
all_values[3]	362205	1			T1	250		T2	11		T3	31

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

721528

1

T1

477

T2

15

T18

100

auto[1]

727292

1

T1

523

T2

29

T3

124

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

858785

1

T1

498

T2

42

T3

104

auto[1]

590035

1

T1

502

T2

2

T3

20

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	102013	1			T1	57		T18	12		T4	370
all_values[0]	auto[0]	auto[1]	78461	1			T1	58		T18	11		T4	363
all_values[0]	auto[1]	auto[0]	103268	1			T1	64		T2	9		T3	16
all_values[0]	auto[1]	auto[1]	78463	1			T1	71		T2	2		T3	15
all_values[1]	auto[0]	auto[0]	107874	1			T1	56		T2	9		T18	11
all_values[1]	auto[0]	auto[1]	72560	1			T1	60		T18	11		T4	378
all_values[1]	auto[1]	auto[0]	109164	1			T1	67		T2	2		T3	31
all_values[1]	auto[1]	auto[1]	72607	1			T1	67		T18	8		T4	360
all_values[2]	auto[0]	auto[0]	109106	1			T1	63		T2	4		T18	15
all_values[2]	auto[0]	auto[1]	71378	1			T1	63		T18	14		T4	379
all_values[2]	auto[1]	auto[0]	110332	1			T1	58		T2	7		T3	31
all_values[2]	auto[1]	auto[1]	71389	1			T1	66		T18	5		T4	357
all_values[3]	auto[0]	auto[0]	107722	1			T1	66		T2	2		T18	13
all_values[3]	auto[0]	auto[1]	72414	1			T1	54		T18	13		T4	367
all_values[3]	auto[1]	auto[0]	109306	1			T1	67		T2	9		T3	26
all_values[3]	auto[1]	auto[1]	72763	1			T1	63		T3	5		T18	5