Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	362205	1			T1	250		T2	11		T3	31
all_pins[1]	362205	1			T1	250		T2	11		T3	31
all_pins[2]	362205	1			T1	250		T2	11		T3	31
all_pins[3]	362205	1			T1	250		T2	11		T3	31

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1153598	1			T1	733		T2	42		T3	104
values[0x1]	295222	1			T1	267		T2	2		T3	20
transitions[0x0=>0x1]	196995	1			T1	162		T2	2		T3	19
transitions[0x1=>0x0]	197265	1			T1	163		T2	2		T3	20

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	283742	1			T1	179		T2	9		T3	16
all_pins[0]	values[0x1]	78463	1			T1	71		T2	2		T3	15
all_pins[0]	transitions[0x0=>0x1]	77778	1			T1	66		T2	2		T3	14
all_pins[0]	transitions[0x1=>0x0]	72348	1			T1	59		T3	5		T18	5
all_pins[1]	values[0x0]	289598	1			T1	183		T2	11		T3	31
all_pins[1]	values[0x1]	72607	1			T1	67		T18	8		T4	360
all_pins[1]	transitions[0x0=>0x1]	39656	1			T1	35		T18	6		T4	183
all_pins[1]	transitions[0x1=>0x0]	45512	1			T1	39		T2	2		T3	15
all_pins[2]	values[0x0]	290816	1			T1	184		T2	11		T3	31
all_pins[2]	values[0x1]	71389	1			T1	66		T18	5		T4	357
all_pins[2]	transitions[0x0=>0x1]	39223	1			T1	32		T18	4		T4	181
all_pins[2]	transitions[0x1=>0x0]	40441	1			T1	33		T18	7		T4	184
all_pins[3]	values[0x0]	289442	1			T1	187		T2	11		T3	26
all_pins[3]	values[0x1]	72763	1			T1	63		T3	5		T18	5
all_pins[3]	transitions[0x0=>0x1]	40338	1			T1	29		T3	5		T18	2
all_pins[3]	transitions[0x1=>0x0]	38964	1			T1	32		T18	2		T4	179