Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287	1			T161	4		T163	7		T234	7
all_values[1]	287	1			T161	4		T163	7		T234	7
all_values[2]	287	1			T161	4		T163	7		T234	7
all_values[3]	287	1			T161	4		T163	7		T234	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

599

1

T161

14

T163

18

T234

18

auto[1]

549

1

T161

2

T163

10

T234

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

405

1

T161

11

T163

11

T234

15

auto[1]

743

1

T161

5

T163

17

T234

13

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

634

1

T161

12

T163

16

T234

21

auto[1]

514

1

T161

4

T163

12

T234

7

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

48

1

T161

2

T163

1

T234

2

all_values[0]

auto[0]

auto[0]

auto[1]

34

1

T234

3

T235

1

T347

3

all_values[0]

auto[0]

auto[1]

auto[0]

38

1

T161

1

T163

1

T348

1

all_values[0]

auto[0]

auto[1]

auto[1]

26

1

T163

2

T347

1

T348

1

all_values[0]

auto[1]

auto[0]

auto[1]

79

1

T161

1

T163

2

T234

2

all_values[0]

auto[1]

auto[1]

auto[1]

62

1

T163

1

T235

1

T347

2

all_values[1]

auto[0]

auto[0]

auto[0]

45

1

T161

2

T163

2

T234

1

all_values[1]

auto[0]

auto[0]

auto[1]

38

1

T163

1

T235

1

T349

1

all_values[1]

auto[0]

auto[1]

auto[0]

49

1

T161

1

T234

1

T347

1

all_values[1]

auto[0]

auto[1]

auto[1]

32

1

T234

2

T235

2

T348

1

all_values[1]

auto[1]

auto[0]

auto[1]

60

1

T161

1

T163

3

T234

2

all_values[1]

auto[1]

auto[1]

auto[1]

63

1

T163

1

T234

1

T235

1

all_values[2]

auto[0]

auto[0]

auto[0]

55

1

T161

3

T163

2

T234

2

all_values[2]

auto[0]

auto[0]

auto[1]

22

1

T163

1

T234

1

T347

1

all_values[2]

auto[0]

auto[1]

auto[0]

59

1

T234

2

T347

1

T348

1

all_values[2]

auto[0]

auto[1]

auto[1]

24

1

T348

1

T350

1

T351

1

all_values[2]

auto[1]

auto[0]

auto[1]

68

1

T161

1

T163

2

T234

2

all_values[2]

auto[1]

auto[1]

auto[1]

59

1

T163

2

T235

1

T347

5

all_values[3]

auto[0]

auto[0]

auto[0]

59

1

T161

2

T163

2

T234

3

all_values[3]

auto[0]

auto[0]

auto[1]

25

1

T161

1

T163

1

T348

2

all_values[3]

auto[0]

auto[1]

auto[0]

52

1

T163

3

T234

4

T235

1

all_values[3]

auto[0]

auto[1]

auto[1]

28

1

T348

3

T352

1

T350

1

all_values[3]

auto[1]

auto[0]

auto[1]

66

1

T161

1

T163

1

T235

1

all_values[3]

auto[1]

auto[1]

auto[1]

57

1

T235

1

T347

1

T348

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal