Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	99487	1			T4	1029		T5	1037		T6	437
accum_cnt_1000	253508	1			T1	122		T4	886		T5	947
accum_cnt_100	31151	1			T1	81		T4	43		T5	56
accum_cnt_50	69380	1			T1	140		T18	13		T4	40
accum_cnt_10	191679	1			T1	101		T2	1		T3	18
accum_cnt_0	373787	1			T1	144		T2	27		T3	66

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	267250	1			T1	147		T2	7		T3	21
class_index[0x1]	267250	1			T1	147		T2	7		T3	21
class_index[0x2]	267250	1			T1	147		T2	7		T3	21
class_index[0x3]	267250	1			T1	147		T2	7		T3	21

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	23397	1			T4	492		T5	457		T6	437
class_index[0x0]	accum_cnt_1000	63981	1			T4	414		T5	439		T6	465
class_index[0x0]	accum_cnt_100	8597	1			T4	19		T5	22		T6	24
class_index[0x0]	accum_cnt_50	22776	1			T1	17		T4	20		T5	18
class_index[0x0]	accum_cnt_10	50979	1			T1	26		T2	1		T3	11
class_index[0x0]	accum_cnt_0	84007	1			T1	104		T2	6		T3	10
class_index[0x1]	accum_cnt_2000	31242	1			T4	537		T13	558		T26	395
class_index[0x1]	accum_cnt_1000	70157	1			T1	53		T4	472		T19	64
class_index[0x1]	accum_cnt_100	8244	1			T1	21		T4	24		T19	43
class_index[0x1]	accum_cnt_50	15127	1			T1	38		T4	20		T19	61
class_index[0x1]	accum_cnt_10	44580	1			T1	24		T4	4		T5	3
class_index[0x1]	accum_cnt_0	88394	1			T1	11		T2	7		T3	21
class_index[0x2]	accum_cnt_2000	23002	1			T5	580		T23	217		T26	496
class_index[0x2]	accum_cnt_1000	61532	1			T1	54		T5	508		T23	175
class_index[0x2]	accum_cnt_100	6395	1			T1	20		T5	34		T23	11
class_index[0x2]	accum_cnt_50	14336	1			T1	30		T18	13		T5	26
class_index[0x2]	accum_cnt_10	49705	1			T1	17		T18	4		T5	12
class_index[0x2]	accum_cnt_0	99296	1			T1	26		T2	7		T3	21
class_index[0x3]	accum_cnt_2000	21846	1			T13	604		T14	194		T23	82
class_index[0x3]	accum_cnt_1000	57838	1			T1	15		T19	53		T13	539
class_index[0x3]	accum_cnt_100	7915	1			T1	40		T19	12		T13	30
class_index[0x3]	accum_cnt_50	17141	1			T1	55		T19	23		T13	26
class_index[0x3]	accum_cnt_10	46415	1			T1	34		T3	7		T18	19
class_index[0x3]	accum_cnt_0	102090	1			T1	3		T2	7		T3	14