Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	7547	1			T64	17		T261	1		T293	1
alert[0x1]	8223	1			T3	1		T23	1367		T28	37
alert[0x2]	5842	1			T14	21		T16	17		T64	13
alert[0x3]	4280	1			T23	590		T16	36		T34	1
alert[0x4]	12094	1			T14	1367		T72	1		T65	2
alert[0x5]	4270	1			T16	5		T8	1		T77	1
alert[0x6]	4714	1			T79	10		T39	51		T42	128
alert[0x7]	4717	1			T3	1		T14	2323		T23	1
alert[0x8]	4431	1			T23	99		T16	2		T9	1
alert[0x9]	5139	1			T1	1		T16	4		T72	1
alert[0xa]	4725	1			T23	63		T16	2		T34	9
alert[0xb]	3476	1			T14	47		T34	144		T79	142
alert[0xc]	4288	1			T16	27		T79	72		T38	162
alert[0xd]	4378	1			T3	1		T8	1		T79	56
alert[0xe]	7071	1			T19	24		T16	180		T34	122
alert[0xf]	5824	1			T16	1		T34	50		T9	1
alert[0x10]	6161	1			T1	4		T64	98		T72	26
alert[0x11]	5664	1			T14	236		T28	359		T79	2189
alert[0x12]	5923	1			T28	35		T294	2		T92	9
alert[0x13]	4166	1			T14	240		T34	78		T79	201
alert[0x14]	5244	1			T1	19		T65	1		T28	66
alert[0x15]	14847	1			T23	155		T294	1		T36	8
alert[0x16]	4818	1			T14	1041		T79	40		T295	1
alert[0x17]	3856	1			T3	2		T64	123		T28	488
alert[0x18]	12444	1			T28	180		T9	2		T75	5
alert[0x19]	9913	1			T14	27		T16	13		T64	26
alert[0x1a]	5419	1			T24	5		T261	1		T38	344
alert[0x1b]	8233	1			T14	18		T7	1		T8	1
alert[0x1c]	13788	1			T14	21		T16	25		T28	351
alert[0x1d]	9091	1			T34	15		T8	1		T79	46
alert[0x1e]	3585	1			T23	30		T16	2		T64	86
alert[0x1f]	2601	1			T14	485		T7	1		T34	2
alert[0x20]	2877	1			T16	10		T79	51		T294	26
alert[0x21]	10033	1			T14	510		T16	311		T64	235
alert[0x22]	4050	1			T295	1		T36	6		T57	1
alert[0x23]	4727	1			T23	42		T64	244		T121	3
alert[0x24]	4025	1			T3	1		T14	39		T16	8
alert[0x25]	5401	1			T1	1		T16	6		T65	1
alert[0x26]	7796	1			T28	72		T9	2		T261	1
alert[0x27]	4520	1			T14	315		T34	41		T64	957
alert[0x28]	879	1			T1	3		T16	2		T65	13
alert[0x29]	12282	1			T14	36		T34	14		T8	1
alert[0x2a]	3903	1			T14	1		T65	53		T28	69
alert[0x2b]	5163	1			T65	4		T28	185		T75	1
alert[0x2c]	4051	1			T14	105		T250	2		T28	108
alert[0x2d]	5213	1			T23	462		T64	30		T9	1
alert[0x2e]	5672	1			T16	3		T62	1		T296	7
alert[0x2f]	3799	1			T14	76		T24	2		T16	5
alert[0x30]	4025	1			T1	5		T3	2		T14	127
alert[0x31]	4717	1			T3	1		T23	344		T34	184
alert[0x32]	3841	1			T28	163		T9	1		T38	29
alert[0x33]	5088	1			T23	2864		T16	19		T64	343
alert[0x34]	4629	1			T64	13		T28	1564		T9	1
alert[0x35]	6055	1			T23	82		T16	22		T64	171
alert[0x36]	1095	1			T1	1		T3	1		T16	22
alert[0x37]	7274	1			T1	1		T23	1		T36	8
alert[0x38]	1858	1			T34	22		T64	16		T28	10
alert[0x39]	3705	1			T1	1		T23	196		T16	28
alert[0x3a]	2188	1			T65	7		T9	1		T121	1
alert[0x3b]	5791	1			T16	9		T64	240		T39	45
alert[0x3c]	5323	1			T24	1		T16	3		T34	232
alert[0x3d]	3970	1			T23	5		T16	1		T64	23
alert[0x3e]	4445	1			T34	17		T64	87		T38	137
alert[0x3f]	6999	1			T16	110		T65	11		T28	24
alert[0x40]	4579	1			T14	91		T16	1		T9	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	71962	1			T1	9		T3	10		T23	39
class_i[0x1]	62695	1			T1	9		T34	1		T64	3074
class_i[0x2]	116935	1			T19	24		T23	6262		T16	918
class_i[0x3]	115153	1			T1	18		T14	7126		T24	6

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

366104

1

T1

36

T19

24

T14

7126

alert_ping_fail

641

1

T3

10

T7

2

T8

7

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	7538	1			T64	17		T293	1		T41	230
alert_integrity_fail	alert[0x1]	8217	1			T23	1367		T28	37		T75	1
alert_integrity_fail	alert[0x2]	5837	1			T14	21		T16	17		T64	13
alert_integrity_fail	alert[0x3]	4271	1			T23	590		T16	36		T34	1
alert_integrity_fail	alert[0x4]	12086	1			T14	1367		T72	1		T65	2
alert_integrity_fail	alert[0x5]	4259	1			T16	5		T77	1		T42	331
alert_integrity_fail	alert[0x6]	4707	1			T79	10		T39	51		T42	128
alert_integrity_fail	alert[0x7]	4703	1			T14	2323		T23	1		T16	44
alert_integrity_fail	alert[0x8]	4411	1			T23	99		T16	2		T294	2
alert_integrity_fail	alert[0x9]	5130	1			T1	1		T16	4		T72	1
alert_integrity_fail	alert[0xa]	4712	1			T23	63		T16	2		T34	9
alert_integrity_fail	alert[0xb]	3471	1			T14	47		T34	144		T79	142
alert_integrity_fail	alert[0xc]	4277	1			T16	27		T79	72		T38	162
alert_integrity_fail	alert[0xd]	4365	1			T79	56		T38	2		T39	1
alert_integrity_fail	alert[0xe]	7064	1			T19	24		T16	180		T34	122
alert_integrity_fail	alert[0xf]	5811	1			T16	1		T34	50		T79	100
alert_integrity_fail	alert[0x10]	6154	1			T1	4		T64	98		T72	26
alert_integrity_fail	alert[0x11]	5655	1			T14	236		T28	359		T79	2189
alert_integrity_fail	alert[0x12]	5913	1			T28	35		T294	2		T92	9
alert_integrity_fail	alert[0x13]	4154	1			T14	240		T34	78		T79	201
alert_integrity_fail	alert[0x14]	5232	1			T1	19		T65	1		T28	66
alert_integrity_fail	alert[0x15]	14836	1			T23	155		T294	1		T36	8
alert_integrity_fail	alert[0x16]	4807	1			T14	1041		T79	40		T119	2
alert_integrity_fail	alert[0x17]	3843	1			T64	123		T28	488		T79	493
alert_integrity_fail	alert[0x18]	12433	1			T28	180		T75	5		T58	9
alert_integrity_fail	alert[0x19]	9907	1			T14	27		T16	13		T64	26
alert_integrity_fail	alert[0x1a]	5413	1			T24	5		T38	344		T39	16
alert_integrity_fail	alert[0x1b]	8219	1			T14	18		T28	1152		T56	1
alert_integrity_fail	alert[0x1c]	13777	1			T14	21		T16	25		T28	351
alert_integrity_fail	alert[0x1d]	9075	1			T34	15		T79	46		T36	9
alert_integrity_fail	alert[0x1e]	3580	1			T23	30		T16	2		T64	86
alert_integrity_fail	alert[0x1f]	2585	1			T14	485		T34	2		T28	90
alert_integrity_fail	alert[0x20]	2866	1			T16	10		T79	51		T294	26
alert_integrity_fail	alert[0x21]	10021	1			T14	510		T16	311		T64	235
alert_integrity_fail	alert[0x22]	4041	1			T36	6		T42	73		T45	3
alert_integrity_fail	alert[0x23]	4717	1			T23	42		T64	244		T121	3
alert_integrity_fail	alert[0x24]	4019	1			T14	39		T16	8		T64	126
alert_integrity_fail	alert[0x25]	5394	1			T1	1		T16	6		T65	1
alert_integrity_fail	alert[0x26]	7788	1			T28	72		T56	1		T41	488
alert_integrity_fail	alert[0x27]	4506	1			T14	315		T34	41		T64	957
alert_integrity_fail	alert[0x28]	863	1			T1	3		T16	2		T65	13
alert_integrity_fail	alert[0x29]	12273	1			T14	36		T34	14		T75	3
alert_integrity_fail	alert[0x2a]	3897	1			T14	1		T65	53		T28	69
alert_integrity_fail	alert[0x2b]	5156	1			T65	4		T28	185		T75	1
alert_integrity_fail	alert[0x2c]	4035	1			T14	105		T28	108		T77	1
alert_integrity_fail	alert[0x2d]	5200	1			T23	462		T64	30		T79	21
alert_integrity_fail	alert[0x2e]	5657	1			T16	3		T296	7		T297	1
alert_integrity_fail	alert[0x2f]	3789	1			T14	76		T24	2		T16	5
alert_integrity_fail	alert[0x30]	4005	1			T1	5		T14	127		T28	309
alert_integrity_fail	alert[0x31]	4709	1			T23	344		T34	184		T64	179
alert_integrity_fail	alert[0x32]	3830	1			T28	163		T38	29		T41	553
alert_integrity_fail	alert[0x33]	5081	1			T23	2864		T16	19		T64	343
alert_integrity_fail	alert[0x34]	4615	1			T64	13		T28	1564		T79	40
alert_integrity_fail	alert[0x35]	6041	1			T23	82		T16	22		T64	171
alert_integrity_fail	alert[0x36]	1083	1			T1	1		T16	22		T34	5
alert_integrity_fail	alert[0x37]	7272	1			T1	1		T23	1		T36	8
alert_integrity_fail	alert[0x38]	1851	1			T34	22		T64	16		T28	10
alert_integrity_fail	alert[0x39]	3695	1			T1	1		T23	196		T16	28
alert_integrity_fail	alert[0x3a]	2182	1			T65	7		T121	1		T56	6
alert_integrity_fail	alert[0x3b]	5783	1			T16	9		T64	240		T39	45
alert_integrity_fail	alert[0x3c]	5317	1			T24	1		T16	3		T34	232
alert_integrity_fail	alert[0x3d]	3966	1			T23	5		T16	1		T64	23
alert_integrity_fail	alert[0x3e]	4439	1			T34	17		T64	87		T38	137
alert_integrity_fail	alert[0x3f]	6996	1			T16	110		T65	11		T28	24
alert_integrity_fail	alert[0x40]	4575	1			T14	91		T16	1		T36	1
alert_ping_fail	alert[0x0]	9	1			T261	1		T233	1		T298	1
alert_ping_fail	alert[0x1]	6	1			T3	1		T295	1		T62	1
alert_ping_fail	alert[0x2]	5	1			T9	1		T299	1		T298	1
alert_ping_fail	alert[0x3]	9	1			T62	1		T300	1		T233	1
alert_ping_fail	alert[0x4]	8	1			T9	1		T62	1		T301	1
alert_ping_fail	alert[0x5]	11	1			T8	1		T302	1		T96	1
alert_ping_fail	alert[0x6]	7	1			T303	2		T304	1		T223	1
alert_ping_fail	alert[0x7]	14	1			T3	1		T8	1		T305	1
alert_ping_fail	alert[0x8]	20	1			T9	1		T261	1		T57	1
alert_ping_fail	alert[0x9]	9	1			T62	1		T305	1		T229	1
alert_ping_fail	alert[0xa]	13	1			T295	1		T301	1		T226	2
alert_ping_fail	alert[0xb]	5	1			T302	1		T306	1		T226	1
alert_ping_fail	alert[0xc]	11	1			T302	3		T299	2		T233	1
alert_ping_fail	alert[0xd]	13	1			T3	1		T8	1		T62	1
alert_ping_fail	alert[0xe]	7	1			T299	1		T305	1		T233	1
alert_ping_fail	alert[0xf]	13	1			T9	1		T62	1		T96	1
alert_ping_fail	alert[0x10]	7	1			T261	1		T306	1		T307	1
alert_ping_fail	alert[0x11]	9	1			T302	1		T300	1		T298	1
alert_ping_fail	alert[0x12]	10	1			T62	1		T302	1		T308	2
alert_ping_fail	alert[0x13]	12	1			T309	1		T226	1		T310	1
alert_ping_fail	alert[0x14]	12	1			T295	1		T298	1		T301	1
alert_ping_fail	alert[0x15]	11	1			T57	1		T96	1		T299	1
alert_ping_fail	alert[0x16]	11	1			T295	1		T96	1		T300	1
alert_ping_fail	alert[0x17]	13	1			T3	2		T302	1		T298	1
alert_ping_fail	alert[0x18]	11	1			T9	2		T295	1		T299	2
alert_ping_fail	alert[0x19]	6	1			T9	1		T302	1		T299	1
alert_ping_fail	alert[0x1a]	6	1			T261	1		T298	1		T311	1
alert_ping_fail	alert[0x1b]	14	1			T7	1		T8	1		T302	1
alert_ping_fail	alert[0x1c]	11	1			T261	1		T57	1		T292	1
alert_ping_fail	alert[0x1d]	16	1			T8	1		T300	1		T233	1
alert_ping_fail	alert[0x1e]	5	1			T312	1		T313	1		T314	1
alert_ping_fail	alert[0x1f]	16	1			T7	1		T9	1		T96	1
alert_ping_fail	alert[0x20]	11	1			T62	1		T302	1		T96	1
alert_ping_fail	alert[0x21]	12	1			T62	1		T306	1		T233	1
alert_ping_fail	alert[0x22]	9	1			T295	1		T57	1		T229	1
alert_ping_fail	alert[0x23]	10	1			T62	2		T306	1		T229	1
alert_ping_fail	alert[0x24]	6	1			T3	1		T315	1		T314	1
alert_ping_fail	alert[0x25]	7	1			T9	1		T305	1		T226	1
alert_ping_fail	alert[0x26]	8	1			T9	2		T261	1		T62	1
alert_ping_fail	alert[0x27]	14	1			T9	1		T261	1		T62	1
alert_ping_fail	alert[0x28]	16	1			T9	1		T62	1		T302	1
alert_ping_fail	alert[0x29]	9	1			T8	1		T9	1		T299	1
alert_ping_fail	alert[0x2a]	6	1			T62	1		T299	1		T308	1
alert_ping_fail	alert[0x2b]	7	1			T261	1		T316	1		T317	1
alert_ping_fail	alert[0x2c]	16	1			T250	2		T62	1		T300	1
alert_ping_fail	alert[0x2d]	13	1			T9	1		T299	1		T298	1
alert_ping_fail	alert[0x2e]	15	1			T62	1		T229	2		T308	1
alert_ping_fail	alert[0x2f]	10	1			T68	1		T57	1		T298	1
alert_ping_fail	alert[0x30]	20	1			T3	2		T96	1		T305	1
alert_ping_fail	alert[0x31]	8	1			T3	1		T8	1		T62	1
alert_ping_fail	alert[0x32]	11	1			T9	1		T302	1		T305	1
alert_ping_fail	alert[0x33]	7	1			T261	1		T302	1		T299	1
alert_ping_fail	alert[0x34]	14	1			T9	1		T62	1		T302	1
alert_ping_fail	alert[0x35]	14	1			T62	1		T302	1		T305	1
alert_ping_fail	alert[0x36]	12	1			T3	1		T305	3		T229	1
alert_ping_fail	alert[0x37]	2	1			T312	1		T318	1		-	-
alert_ping_fail	alert[0x38]	7	1			T302	1		T305	1		T298	1
alert_ping_fail	alert[0x39]	10	1			T9	1		T302	1		T305	1
alert_ping_fail	alert[0x3a]	6	1			T9	1		T233	1		T319	1
alert_ping_fail	alert[0x3b]	8	1			T310	1		T320	1		T311	1
alert_ping_fail	alert[0x3c]	6	1			T261	1		T226	1		T312	1
alert_ping_fail	alert[0x3d]	4	1			T96	1		T299	1		T321	1
alert_ping_fail	alert[0x3e]	6	1			T300	1		T316	1		T322	1
alert_ping_fail	alert[0x3f]	3	1			T316	1		T320	1		T312	1
alert_ping_fail	alert[0x40]	4	1			T9	1		T62	1		T306	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	71790	1			T1	9		T23	39		T24	2
alert_integrity_fail	class_i[0x1]	62530	1			T1	9		T34	1		T64	3074
alert_integrity_fail	class_i[0x2]	116768	1			T19	24		T23	6262		T16	918
alert_integrity_fail	class_i[0x3]	115016	1			T1	18		T14	7126		T24	6
alert_ping_fail	class_i[0x0]	172	1			T3	10		T250	2		T9	1
alert_ping_fail	class_i[0x1]	165	1			T68	1		T9	2		T295	5
alert_ping_fail	class_i[0x2]	167	1			T9	14		T57	5		T62	18
alert_ping_fail	class_i[0x3]	137	1			T7	2		T8	7		T9	3