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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.69 100.00 100.00 100.00 99.38 99.60


Total test records in report: 834
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T775 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.761021537 Jun 23 06:30:08 PM PDT 24 Jun 23 06:30:22 PM PDT 24 323187833 ps
T776 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2083773188 Jun 23 06:29:31 PM PDT 24 Jun 23 06:29:50 PM PDT 24 287755435 ps
T777 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3316618542 Jun 23 06:29:48 PM PDT 24 Jun 23 06:29:58 PM PDT 24 152140497 ps
T146 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1427844211 Jun 23 06:29:38 PM PDT 24 Jun 23 06:38:00 PM PDT 24 6776917194 ps
T778 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3193414112 Jun 23 06:30:00 PM PDT 24 Jun 23 06:30:14 PM PDT 24 874168851 ps
T779 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3563764575 Jun 23 06:29:57 PM PDT 24 Jun 23 06:30:08 PM PDT 24 140376005 ps
T165 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1918747448 Jun 23 06:29:22 PM PDT 24 Jun 23 06:29:27 PM PDT 24 63887704 ps
T780 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.4170428644 Jun 23 06:29:59 PM PDT 24 Jun 23 06:30:38 PM PDT 24 609601971 ps
T781 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2656188820 Jun 23 06:30:12 PM PDT 24 Jun 23 06:30:14 PM PDT 24 25506731 ps
T168 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3715450038 Jun 23 06:29:52 PM PDT 24 Jun 23 06:31:35 PM PDT 24 4294033588 ps
T782 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2509045970 Jun 23 06:29:53 PM PDT 24 Jun 23 06:30:04 PM PDT 24 166106687 ps
T783 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3794604162 Jun 23 06:30:22 PM PDT 24 Jun 23 06:30:24 PM PDT 24 48655374 ps
T784 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3604732377 Jun 23 06:29:56 PM PDT 24 Jun 23 06:30:09 PM PDT 24 192612549 ps
T785 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1284242802 Jun 23 06:30:20 PM PDT 24 Jun 23 06:30:22 PM PDT 24 11942973 ps
T142 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3156339558 Jun 23 06:29:56 PM PDT 24 Jun 23 06:36:41 PM PDT 24 22999396098 ps
T786 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3383800585 Jun 23 06:29:06 PM PDT 24 Jun 23 06:30:45 PM PDT 24 3270565661 ps
T787 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3078449850 Jun 23 06:30:02 PM PDT 24 Jun 23 06:30:08 PM PDT 24 150553788 ps
T788 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3385043834 Jun 23 06:30:01 PM PDT 24 Jun 23 06:30:13 PM PDT 24 1882701812 ps
T789 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2065026093 Jun 23 06:30:08 PM PDT 24 Jun 23 06:30:14 PM PDT 24 45443275 ps
T790 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3152789773 Jun 23 06:29:32 PM PDT 24 Jun 23 06:29:33 PM PDT 24 7709504 ps
T791 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2350833253 Jun 23 06:30:21 PM PDT 24 Jun 23 06:30:23 PM PDT 24 9706628 ps
T140 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3851540830 Jun 23 06:30:11 PM PDT 24 Jun 23 06:40:56 PM PDT 24 6473499608 ps
T143 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.219972551 Jun 23 06:29:37 PM PDT 24 Jun 23 06:48:54 PM PDT 24 65812570908 ps
T792 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.253934671 Jun 23 06:29:38 PM PDT 24 Jun 23 06:30:03 PM PDT 24 1089766550 ps
T156 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1929811847 Jun 23 06:29:31 PM PDT 24 Jun 23 06:31:02 PM PDT 24 3143187426 ps
T793 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.77703993 Jun 23 06:30:17 PM PDT 24 Jun 23 06:30:19 PM PDT 24 10042436 ps
T167 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1596281246 Jun 23 06:29:59 PM PDT 24 Jun 23 06:30:03 PM PDT 24 111237865 ps
T794 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.105821805 Jun 23 06:29:49 PM PDT 24 Jun 23 06:29:53 PM PDT 24 198131246 ps
T180 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3812498024 Jun 23 06:29:30 PM PDT 24 Jun 23 06:29:49 PM PDT 24 155384276 ps
T795 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2405588564 Jun 23 06:30:07 PM PDT 24 Jun 23 06:30:31 PM PDT 24 1514335399 ps
T151 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.4197251443 Jun 23 06:29:36 PM PDT 24 Jun 23 06:34:31 PM PDT 24 17942717575 ps
T796 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3324653731 Jun 23 06:29:36 PM PDT 24 Jun 23 06:29:42 PM PDT 24 1023274653 ps
T797 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1063098161 Jun 23 06:29:16 PM PDT 24 Jun 23 06:29:18 PM PDT 24 7704338 ps
T798 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.4205798611 Jun 23 06:29:12 PM PDT 24 Jun 23 06:29:23 PM PDT 24 539752405 ps
T173 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1547601786 Jun 23 06:29:32 PM PDT 24 Jun 23 06:30:13 PM PDT 24 606578085 ps
T799 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2714741301 Jun 23 06:29:38 PM PDT 24 Jun 23 06:29:40 PM PDT 24 46027191 ps
T152 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.986118613 Jun 23 06:30:09 PM PDT 24 Jun 23 06:32:49 PM PDT 24 8480320436 ps
T800 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.316725560 Jun 23 06:29:23 PM PDT 24 Jun 23 06:29:29 PM PDT 24 231529648 ps
T801 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1639293968 Jun 23 06:29:09 PM PDT 24 Jun 23 06:29:20 PM PDT 24 582035991 ps
T153 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1793858337 Jun 23 06:30:02 PM PDT 24 Jun 23 06:35:41 PM PDT 24 2304756708 ps
T802 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.907688646 Jun 23 06:29:27 PM PDT 24 Jun 23 06:29:36 PM PDT 24 113884427 ps
T803 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3964641585 Jun 23 06:29:32 PM PDT 24 Jun 23 06:29:37 PM PDT 24 111632467 ps
T804 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3179977214 Jun 23 06:29:22 PM PDT 24 Jun 23 06:29:24 PM PDT 24 18485020 ps
T805 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2734060750 Jun 23 06:29:08 PM PDT 24 Jun 23 06:29:14 PM PDT 24 115985270 ps
T806 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.664588749 Jun 23 06:30:08 PM PDT 24 Jun 23 06:30:29 PM PDT 24 327339323 ps
T171 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2493812592 Jun 23 06:29:57 PM PDT 24 Jun 23 06:31:22 PM PDT 24 4847021699 ps
T807 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3539304863 Jun 23 06:29:47 PM PDT 24 Jun 23 06:29:57 PM PDT 24 103090546 ps
T808 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2747604942 Jun 23 06:30:17 PM PDT 24 Jun 23 06:30:20 PM PDT 24 7492427 ps
T809 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1962793565 Jun 23 06:30:13 PM PDT 24 Jun 23 06:30:17 PM PDT 24 20010002 ps
T810 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.467745031 Jun 23 06:30:12 PM PDT 24 Jun 23 06:30:14 PM PDT 24 15173634 ps
T811 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2870913283 Jun 23 06:30:22 PM PDT 24 Jun 23 06:30:24 PM PDT 24 7562620 ps
T166 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2200566191 Jun 23 06:30:01 PM PDT 24 Jun 23 06:30:04 PM PDT 24 121190082 ps
T812 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1006712959 Jun 23 06:29:46 PM PDT 24 Jun 23 06:30:16 PM PDT 24 696372178 ps
T813 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3990313820 Jun 23 06:29:32 PM PDT 24 Jun 23 06:29:39 PM PDT 24 54830637 ps
T814 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1102594513 Jun 23 06:30:01 PM PDT 24 Jun 23 06:30:03 PM PDT 24 75176318 ps
T815 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1207529917 Jun 23 06:29:12 PM PDT 24 Jun 23 06:29:23 PM PDT 24 247771043 ps
T164 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.868938433 Jun 23 06:29:08 PM PDT 24 Jun 23 06:29:12 PM PDT 24 122001659 ps
T816 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1971086395 Jun 23 06:29:19 PM PDT 24 Jun 23 06:38:04 PM PDT 24 24862114583 ps
T817 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2314574077 Jun 23 06:30:03 PM PDT 24 Jun 23 06:30:05 PM PDT 24 30437725 ps
T818 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1848999885 Jun 23 06:29:51 PM PDT 24 Jun 23 06:30:03 PM PDT 24 171888367 ps
T819 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.126744709 Jun 23 06:30:16 PM PDT 24 Jun 23 06:30:18 PM PDT 24 9194706 ps
T362 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1237395792 Jun 23 06:29:23 PM PDT 24 Jun 23 06:35:11 PM PDT 24 3098318255 ps
T820 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3406329688 Jun 23 06:29:15 PM PDT 24 Jun 23 06:31:15 PM PDT 24 7181016881 ps
T821 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1336746263 Jun 23 06:29:52 PM PDT 24 Jun 23 06:30:20 PM PDT 24 330102199 ps
T822 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1382073681 Jun 23 06:29:03 PM PDT 24 Jun 23 06:32:10 PM PDT 24 3350259103 ps
T170 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.4201011766 Jun 23 06:29:46 PM PDT 24 Jun 23 06:30:30 PM PDT 24 2308405409 ps
T823 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2148057794 Jun 23 06:29:12 PM PDT 24 Jun 23 06:29:17 PM PDT 24 56618529 ps
T824 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2131116023 Jun 23 06:29:47 PM PDT 24 Jun 23 06:29:53 PM PDT 24 63096545 ps
T181 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2369333932 Jun 23 06:29:27 PM PDT 24 Jun 23 06:29:32 PM PDT 24 420144213 ps
T825 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1021452946 Jun 23 06:29:37 PM PDT 24 Jun 23 06:29:43 PM PDT 24 475574493 ps
T826 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3444251799 Jun 23 06:29:23 PM PDT 24 Jun 23 06:29:29 PM PDT 24 130986005 ps
T827 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1818758377 Jun 23 06:29:27 PM PDT 24 Jun 23 06:29:34 PM PDT 24 50616888 ps
T154 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2121067927 Jun 23 06:29:16 PM PDT 24 Jun 23 06:35:19 PM PDT 24 20128580453 ps
T828 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1780518271 Jun 23 06:30:08 PM PDT 24 Jun 23 06:30:16 PM PDT 24 186940738 ps
T157 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.736304669 Jun 23 06:29:53 PM PDT 24 Jun 23 06:35:41 PM PDT 24 78315086876 ps
T829 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3193413550 Jun 23 06:29:26 PM PDT 24 Jun 23 06:29:27 PM PDT 24 9273744 ps
T830 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1213510249 Jun 23 06:30:02 PM PDT 24 Jun 23 06:30:04 PM PDT 24 8543690 ps
T361 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.588761295 Jun 23 06:30:03 PM PDT 24 Jun 23 06:36:09 PM PDT 24 8772531466 ps
T155 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3508536438 Jun 23 06:29:52 PM PDT 24 Jun 23 06:38:14 PM PDT 24 12331369883 ps
T174 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1415394654 Jun 23 06:29:14 PM PDT 24 Jun 23 06:29:23 PM PDT 24 157390739 ps
T831 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.483235845 Jun 23 06:29:54 PM PDT 24 Jun 23 06:30:01 PM PDT 24 290467931 ps
T832 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1793264207 Jun 23 06:29:12 PM PDT 24 Jun 23 06:29:49 PM PDT 24 599528594 ps
T833 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.155932962 Jun 23 06:29:56 PM PDT 24 Jun 23 06:32:47 PM PDT 24 2409940103 ps
T834 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.4230292050 Jun 23 06:29:57 PM PDT 24 Jun 23 06:29:58 PM PDT 24 12638560 ps

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.1213458495
Short name T19
Test name
Test status
Simulation time 247228545836 ps
CPU time 1618.3 seconds
Started Jun 23 06:44:06 PM PDT 24
Finished Jun 23 07:11:05 PM PDT 24
Peak memory 281968 kb
Host smart-8aaa975b-5011-4fbd-8837-4bd744969895
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213458495 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.1213458495
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3920018774
Short name T10
Test name
Test status
Simulation time 470470320 ps
CPU time 26.52 seconds
Started Jun 23 06:41:14 PM PDT 24
Finished Jun 23 06:41:41 PM PDT 24
Peak memory 277732 kb
Host smart-e8fcd15b-7fab-45c2-b1d7-22e27c4af2d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3920018774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3920018774
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.454615615
Short name T15
Test name
Test status
Simulation time 794434167 ps
CPU time 18.64 seconds
Started Jun 23 06:41:17 PM PDT 24
Finished Jun 23 06:41:36 PM PDT 24
Peak memory 249056 kb
Host smart-6af43265-da98-41bf-bddb-016cf9018a4a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=454615615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.454615615
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2434803412
Short name T123
Test name
Test status
Simulation time 15771230757 ps
CPU time 1016.13 seconds
Started Jun 23 06:29:56 PM PDT 24
Finished Jun 23 06:46:52 PM PDT 24
Peak memory 265704 kb
Host smart-751af02e-7daf-421b-afd2-dae5dd3f134d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434803412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2434803412
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.3093440151
Short name T64
Test name
Test status
Simulation time 53350647448 ps
CPU time 2104.98 seconds
Started Jun 23 06:43:26 PM PDT 24
Finished Jun 23 07:18:31 PM PDT 24
Peak memory 306312 kb
Host smart-f1798a9a-3f18-4bc4-bd17-f880499038ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093440151 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.3093440151
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.2717076025
Short name T51
Test name
Test status
Simulation time 178283718147 ps
CPU time 8444.71 seconds
Started Jun 23 06:42:45 PM PDT 24
Finished Jun 23 09:03:32 PM PDT 24
Peak memory 354616 kb
Host smart-9a728cd7-466c-469f-b6c4-5ee0e65e92d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717076025 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.2717076025
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.2144671411
Short name T50
Test name
Test status
Simulation time 69390190640 ps
CPU time 6799.45 seconds
Started Jun 23 06:41:18 PM PDT 24
Finished Jun 23 08:34:39 PM PDT 24
Peak memory 372032 kb
Host smart-f789b844-cd99-4d74-90f9-d7a8ea2f47c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144671411 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.2144671411
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1863434140
Short name T137
Test name
Test status
Simulation time 17235903141 ps
CPU time 385.39 seconds
Started Jun 23 06:29:57 PM PDT 24
Finished Jun 23 06:36:23 PM PDT 24
Peak memory 265812 kb
Host smart-8bb88546-e316-47c8-ae44-540e502bf627
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1863434140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1863434140
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2550416044
Short name T65
Test name
Test status
Simulation time 51148948832 ps
CPU time 1471.67 seconds
Started Jun 23 06:42:27 PM PDT 24
Finished Jun 23 07:06:59 PM PDT 24
Peak memory 287424 kb
Host smart-59040b90-4e4b-4eb2-a674-8c52d47f7f5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550416044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2550416044
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1256886862
Short name T250
Test name
Test status
Simulation time 53959137904 ps
CPU time 3262.62 seconds
Started Jun 23 06:42:24 PM PDT 24
Finished Jun 23 07:36:47 PM PDT 24
Peak memory 289420 kb
Host smart-bf24046d-bab4-4050-9ee5-d95eeabe3be9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256886862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1256886862
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2627573992
Short name T125
Test name
Test status
Simulation time 66507335361 ps
CPU time 1322.62 seconds
Started Jun 23 06:29:49 PM PDT 24
Finished Jun 23 06:51:52 PM PDT 24
Peak memory 265644 kb
Host smart-442ea287-7491-4369-805b-bc7a83604766
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627573992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2627573992
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.145977803
Short name T24
Test name
Test status
Simulation time 129382497743 ps
CPU time 5720.19 seconds
Started Jun 23 06:43:01 PM PDT 24
Finished Jun 23 08:18:23 PM PDT 24
Peak memory 299488 kb
Host smart-d9e52f82-9be6-49a7-965d-e939655b3d1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145977803 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.145977803
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.32562801
Short name T134
Test name
Test status
Simulation time 19173599982 ps
CPU time 357.35 seconds
Started Jun 23 06:29:33 PM PDT 24
Finished Jun 23 06:35:30 PM PDT 24
Peak memory 265676 kb
Host smart-c2e70b16-2891-4f09-bcf8-789f27a2a43e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=32562801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors
.32562801
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2823014057
Short name T175
Test name
Test status
Simulation time 1237609107 ps
CPU time 83.76 seconds
Started Jun 23 06:29:47 PM PDT 24
Finished Jun 23 06:31:11 PM PDT 24
Peak memory 240140 kb
Host smart-8ead085a-b1ae-4dfa-a397-15c5be0fa771
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2823014057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2823014057
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.4058365211
Short name T62
Test name
Test status
Simulation time 161728063303 ps
CPU time 702.5 seconds
Started Jun 23 06:42:26 PM PDT 24
Finished Jun 23 06:54:09 PM PDT 24
Peak memory 248424 kb
Host smart-e53da30e-d076-42a8-ba63-228737f74a3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058365211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.4058365211
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.2250751033
Short name T79
Test name
Test status
Simulation time 68637662175 ps
CPU time 6352.68 seconds
Started Jun 23 06:42:21 PM PDT 24
Finished Jun 23 08:28:14 PM PDT 24
Peak memory 371832 kb
Host smart-27adeee7-d66a-423e-9c53-bbc562e0c154
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250751033 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.2250751033
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2160434262
Short name T348
Test name
Test status
Simulation time 10261000 ps
CPU time 1.56 seconds
Started Jun 23 06:30:19 PM PDT 24
Finished Jun 23 06:30:21 PM PDT 24
Peak memory 237552 kb
Host smart-5fd8b1e8-7570-4e25-9116-162514654515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2160434262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2160434262
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2096891082
Short name T292
Test name
Test status
Simulation time 66936477760 ps
CPU time 1573.21 seconds
Started Jun 23 06:41:30 PM PDT 24
Finished Jun 23 07:07:44 PM PDT 24
Peak memory 289716 kb
Host smart-7ee6a3cf-7a3a-4bba-943a-0e8e7ad4d674
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096891082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2096891082
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2721343976
Short name T128
Test name
Test status
Simulation time 20435914760 ps
CPU time 345.46 seconds
Started Jun 23 06:29:23 PM PDT 24
Finished Jun 23 06:35:09 PM PDT 24
Peak memory 265668 kb
Host smart-731198f7-0c79-4c1d-9e04-440adde7a1ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2721343976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2721343976
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3549965987
Short name T28
Test name
Test status
Simulation time 26630962184 ps
CPU time 1818 seconds
Started Jun 23 06:43:04 PM PDT 24
Finished Jun 23 07:13:22 PM PDT 24
Peak memory 282348 kb
Host smart-cb162b94-033d-452e-ab5e-f7056b341ecb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549965987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3549965987
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3582657470
Short name T144
Test name
Test status
Simulation time 55188214980 ps
CPU time 1006.29 seconds
Started Jun 23 06:29:33 PM PDT 24
Finished Jun 23 06:46:20 PM PDT 24
Peak memory 271856 kb
Host smart-583b7507-47dd-4ac0-a43a-fb5ff9cdd82b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582657470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3582657470
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.4149364035
Short name T7
Test name
Test status
Simulation time 14886251877 ps
CPU time 698.92 seconds
Started Jun 23 06:43:33 PM PDT 24
Finished Jun 23 06:55:12 PM PDT 24
Peak memory 273628 kb
Host smart-2be61bfc-98a3-44ec-b4b3-b786f0dadcc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149364035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.4149364035
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.1163980882
Short name T342
Test name
Test status
Simulation time 28902269583 ps
CPU time 1904.67 seconds
Started Jun 23 06:42:02 PM PDT 24
Finished Jun 23 07:13:48 PM PDT 24
Peak memory 273780 kb
Host smart-2787f14d-d782-488b-8679-4889c6b540aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163980882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.1163980882
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1617922392
Short name T299
Test name
Test status
Simulation time 45343198214 ps
CPU time 430.41 seconds
Started Jun 23 06:42:36 PM PDT 24
Finished Jun 23 06:49:47 PM PDT 24
Peak memory 248464 kb
Host smart-4a7dcd1d-51af-4970-a69b-07dd36f10b36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617922392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1617922392
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.791002740
Short name T131
Test name
Test status
Simulation time 48649024518 ps
CPU time 1108.07 seconds
Started Jun 23 06:29:03 PM PDT 24
Finished Jun 23 06:47:32 PM PDT 24
Peak memory 265648 kb
Host smart-1af48486-267f-4a27-a2a4-8e76ac9a83b0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791002740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.791002740
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1070953194
Short name T226
Test name
Test status
Simulation time 68197193620 ps
CPU time 694.28 seconds
Started Jun 23 06:44:10 PM PDT 24
Finished Jun 23 06:55:44 PM PDT 24
Peak memory 248508 kb
Host smart-a35e4f47-f9ed-4b1f-95c4-4c89f42dda9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070953194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1070953194
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.861994853
Short name T247
Test name
Test status
Simulation time 160758787357 ps
CPU time 2310.76 seconds
Started Jun 23 06:42:02 PM PDT 24
Finished Jun 23 07:20:33 PM PDT 24
Peak memory 290148 kb
Host smart-41c46839-ef96-4c53-ad74-6ada742abeaf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861994853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.861994853
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.736304669
Short name T157
Test name
Test status
Simulation time 78315086876 ps
CPU time 347.93 seconds
Started Jun 23 06:29:53 PM PDT 24
Finished Jun 23 06:35:41 PM PDT 24
Peak memory 265656 kb
Host smart-2f27ac70-5f91-4e84-b2b0-554d5f8dde80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=736304669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.736304669
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2478317076
Short name T88
Test name
Test status
Simulation time 289364619486 ps
CPU time 6290.32 seconds
Started Jun 23 06:43:54 PM PDT 24
Finished Jun 23 08:28:45 PM PDT 24
Peak memory 346800 kb
Host smart-734e31ee-565e-4885-bd60-03138b68f2ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478317076 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2478317076
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.27353442
Short name T72
Test name
Test status
Simulation time 263214903833 ps
CPU time 1975.28 seconds
Started Jun 23 06:42:07 PM PDT 24
Finished Jun 23 07:15:03 PM PDT 24
Peak memory 273712 kb
Host smart-28f73f41-4378-457b-beb2-1cd29631179a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27353442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.27353442
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.3656681143
Short name T265
Test name
Test status
Simulation time 32869835236 ps
CPU time 1823.45 seconds
Started Jun 23 06:41:05 PM PDT 24
Finished Jun 23 07:11:29 PM PDT 24
Peak memory 268552 kb
Host smart-b3e4b398-4655-4b7c-a34f-9779a70e1a50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656681143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3656681143
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1975026616
Short name T330
Test name
Test status
Simulation time 38828821227 ps
CPU time 1810.11 seconds
Started Jun 23 06:41:53 PM PDT 24
Finished Jun 23 07:12:04 PM PDT 24
Peak memory 289368 kb
Host smart-3a51d633-3bcc-4933-a8f1-77d1a4b2bf53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975026616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1975026616
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.771259939
Short name T302
Test name
Test status
Simulation time 15533758185 ps
CPU time 627.51 seconds
Started Jun 23 06:43:34 PM PDT 24
Finished Jun 23 06:54:01 PM PDT 24
Peak memory 248732 kb
Host smart-8691276a-2cc5-42d9-9777-11e5f264b1c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771259939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.771259939
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2027111692
Short name T23
Test name
Test status
Simulation time 64367142820 ps
CPU time 2249.02 seconds
Started Jun 23 06:42:04 PM PDT 24
Finished Jun 23 07:19:33 PM PDT 24
Peak memory 289436 kb
Host smart-871953e1-0f0b-4d50-bfec-d6475690ab18
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027111692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2027111692
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2115160690
Short name T325
Test name
Test status
Simulation time 38216546812 ps
CPU time 2358.2 seconds
Started Jun 23 06:42:41 PM PDT 24
Finished Jun 23 07:22:00 PM PDT 24
Peak memory 281928 kb
Host smart-c7f42bc2-d3b0-430a-ba25-ba362585f154
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115160690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2115160690
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3179344746
Short name T150
Test name
Test status
Simulation time 37470425726 ps
CPU time 986.76 seconds
Started Jun 23 06:29:49 PM PDT 24
Finished Jun 23 06:46:16 PM PDT 24
Peak memory 272756 kb
Host smart-5fa739ce-9210-4ab3-bcb9-7e56556ff367
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179344746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3179344746
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.4193323229
Short name T235
Test name
Test status
Simulation time 15076720 ps
CPU time 1.55 seconds
Started Jun 23 06:29:37 PM PDT 24
Finished Jun 23 06:29:39 PM PDT 24
Peak memory 236424 kb
Host smart-8ed33ea0-0a1f-443b-8519-2e62cedd93c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4193323229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.4193323229
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3974778487
Short name T312
Test name
Test status
Simulation time 8242579907 ps
CPU time 332.08 seconds
Started Jun 23 06:42:19 PM PDT 24
Finished Jun 23 06:47:51 PM PDT 24
Peak memory 256484 kb
Host smart-173ca1db-5b11-4743-a893-b0c845a28956
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974778487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3974778487
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.434740582
Short name T38
Test name
Test status
Simulation time 65146160582 ps
CPU time 6390.07 seconds
Started Jun 23 06:41:23 PM PDT 24
Finished Jun 23 08:27:54 PM PDT 24
Peak memory 338300 kb
Host smart-02d50899-b977-42a1-98a5-ab6741fc1695
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434740582 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.434740582
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1809546871
Short name T356
Test name
Test status
Simulation time 43971508641 ps
CPU time 399.48 seconds
Started Jun 23 06:29:17 PM PDT 24
Finished Jun 23 06:35:57 PM PDT 24
Peak memory 237356 kb
Host smart-94654793-7c63-4aeb-b058-4709ce2ae9c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1809546871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1809546871
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3262187931
Short name T647
Test name
Test status
Simulation time 10567562913 ps
CPU time 364.55 seconds
Started Jun 23 06:42:01 PM PDT 24
Finished Jun 23 06:48:06 PM PDT 24
Peak memory 248428 kb
Host smart-40f0407d-5089-4e77-b949-e2240065fe21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262187931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3262187931
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.2229425664
Short name T238
Test name
Test status
Simulation time 56622148813 ps
CPU time 3434.4 seconds
Started Jun 23 06:42:34 PM PDT 24
Finished Jun 23 07:39:50 PM PDT 24
Peak memory 289564 kb
Host smart-1050410f-9507-4523-90ac-a59af8c1312e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229425664 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.2229425664
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.4051969034
Short name T323
Test name
Test status
Simulation time 35285119754 ps
CPU time 1901.29 seconds
Started Jun 23 06:41:59 PM PDT 24
Finished Jun 23 07:13:41 PM PDT 24
Peak memory 281864 kb
Host smart-290aca68-9c27-4b9e-8193-bfd2c9131c34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051969034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.4051969034
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.989487820
Short name T33
Test name
Test status
Simulation time 718641169 ps
CPU time 15.22 seconds
Started Jun 23 06:43:31 PM PDT 24
Finished Jun 23 06:43:46 PM PDT 24
Peak memory 247928 kb
Host smart-5339e764-3944-45e4-ba5a-a30383a5c758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98948
7820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.989487820
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2938531659
Short name T85
Test name
Test status
Simulation time 176567855 ps
CPU time 20.74 seconds
Started Jun 23 06:43:47 PM PDT 24
Finished Jun 23 06:44:08 PM PDT 24
Peak memory 255196 kb
Host smart-793f50df-2d73-4941-9f37-9d8f99e6cc77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29385
31659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2938531659
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.3010214221
Short name T274
Test name
Test status
Simulation time 497950090 ps
CPU time 39.92 seconds
Started Jun 23 06:42:08 PM PDT 24
Finished Jun 23 06:42:48 PM PDT 24
Peak memory 256940 kb
Host smart-826f0c4f-f220-4d79-aa36-fbe6f3f24933
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010214221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.3010214221
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.219972551
Short name T143
Test name
Test status
Simulation time 65812570908 ps
CPU time 1156.21 seconds
Started Jun 23 06:29:37 PM PDT 24
Finished Jun 23 06:48:54 PM PDT 24
Peak memory 265644 kb
Host smart-86c231e9-5d71-4b2a-b3c1-615b64b76086
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219972551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.219972551
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.868938433
Short name T164
Test name
Test status
Simulation time 122001659 ps
CPU time 4.46 seconds
Started Jun 23 06:29:08 PM PDT 24
Finished Jun 23 06:29:12 PM PDT 24
Peak memory 237248 kb
Host smart-4167e87e-31a3-4644-ac2e-922e89193dea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=868938433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.868938433
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.2923648535
Short name T34
Test name
Test status
Simulation time 427946638636 ps
CPU time 8729.79 seconds
Started Jun 23 06:43:24 PM PDT 24
Finished Jun 23 09:08:55 PM PDT 24
Peak memory 403976 kb
Host smart-9180bf79-1ea3-4d22-909b-6995447cf9b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923648535 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.2923648535
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2376962707
Short name T211
Test name
Test status
Simulation time 35399801 ps
CPU time 3.23 seconds
Started Jun 23 06:41:08 PM PDT 24
Finished Jun 23 06:41:12 PM PDT 24
Peak memory 249236 kb
Host smart-69e174fb-3e8e-4185-9d2e-ae062fbddc80
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2376962707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2376962707
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1095634324
Short name T197
Test name
Test status
Simulation time 17677367 ps
CPU time 2.44 seconds
Started Jun 23 06:41:11 PM PDT 24
Finished Jun 23 06:41:14 PM PDT 24
Peak memory 249260 kb
Host smart-811b525e-16f3-4af0-9935-ca2dcc1e13d9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1095634324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1095634324
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.920523425
Short name T210
Test name
Test status
Simulation time 35930836 ps
CPU time 3.33 seconds
Started Jun 23 06:41:45 PM PDT 24
Finished Jun 23 06:41:48 PM PDT 24
Peak memory 249288 kb
Host smart-6fa1f610-7580-4d52-b1ad-5d302dda1fac
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=920523425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.920523425
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.579396548
Short name T208
Test name
Test status
Simulation time 34300650 ps
CPU time 3.05 seconds
Started Jun 23 06:42:02 PM PDT 24
Finished Jun 23 06:42:05 PM PDT 24
Peak memory 249212 kb
Host smart-02ee08ca-3769-471e-b1bd-848739ae5347
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=579396548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.579396548
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.1491070238
Short name T36
Test name
Test status
Simulation time 30814512918 ps
CPU time 2703.43 seconds
Started Jun 23 06:41:44 PM PDT 24
Finished Jun 23 07:26:48 PM PDT 24
Peak memory 290192 kb
Host smart-005e3296-e976-4023-a6f8-b27eb39403cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491070238 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.1491070238
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2848258657
Short name T328
Test name
Test status
Simulation time 57554664510 ps
CPU time 1178.12 seconds
Started Jun 23 06:41:13 PM PDT 24
Finished Jun 23 07:00:51 PM PDT 24
Peak memory 282060 kb
Host smart-04330c34-5cf4-4549-90e1-9aaa3050dc0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848258657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2848258657
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2972779512
Short name T225
Test name
Test status
Simulation time 52049387384 ps
CPU time 2759.16 seconds
Started Jun 23 06:42:17 PM PDT 24
Finished Jun 23 07:28:16 PM PDT 24
Peak memory 289336 kb
Host smart-d8b71d8b-d8fc-401d-bb0e-70d38bd6225d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972779512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2972779512
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3250275709
Short name T640
Test name
Test status
Simulation time 27492043960 ps
CPU time 263.94 seconds
Started Jun 23 06:42:25 PM PDT 24
Finished Jun 23 06:46:49 PM PDT 24
Peak memory 248296 kb
Host smart-e7e7412b-48dd-4fc5-b480-c69abe067f43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250275709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3250275709
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.315186323
Short name T275
Test name
Test status
Simulation time 37246088110 ps
CPU time 2081 seconds
Started Jun 23 06:42:25 PM PDT 24
Finished Jun 23 07:17:07 PM PDT 24
Peak memory 283592 kb
Host smart-c2df646e-a9f2-4715-9f53-c8d5d59892b9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315186323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.315186323
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3106046235
Short name T340
Test name
Test status
Simulation time 30137047711 ps
CPU time 1895.98 seconds
Started Jun 23 06:42:30 PM PDT 24
Finished Jun 23 07:14:07 PM PDT 24
Peak memory 273292 kb
Host smart-85a3f7a8-c880-4a19-9139-759ea881e070
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106046235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3106046235
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2682711432
Short name T259
Test name
Test status
Simulation time 562830173 ps
CPU time 12.49 seconds
Started Jun 23 06:42:54 PM PDT 24
Finished Jun 23 06:43:07 PM PDT 24
Peak memory 256164 kb
Host smart-e82c00f6-b37c-43ca-ae3f-1258f560d0a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26827
11432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2682711432
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2567641049
Short name T481
Test name
Test status
Simulation time 17212746715 ps
CPU time 561.44 seconds
Started Jun 23 06:41:39 PM PDT 24
Finished Jun 23 06:51:01 PM PDT 24
Peak memory 248464 kb
Host smart-325c84b9-642d-417b-9b85-b89431c3ec12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567641049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2567641049
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.4124424989
Short name T122
Test name
Test status
Simulation time 57053579763 ps
CPU time 3205.07 seconds
Started Jun 23 06:42:54 PM PDT 24
Finished Jun 23 07:36:20 PM PDT 24
Peak memory 304648 kb
Host smart-99ed6474-7eae-4d47-a88c-c693adf9e940
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124424989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.4124424989
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1204302514
Short name T192
Test name
Test status
Simulation time 52269692 ps
CPU time 5.12 seconds
Started Jun 23 06:29:48 PM PDT 24
Finished Jun 23 06:29:54 PM PDT 24
Peak memory 241076 kb
Host smart-7ab346d6-1a23-42c7-b2d4-e21a460bcfc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204302514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1204302514
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1153164626
Short name T139
Test name
Test status
Simulation time 140910451318 ps
CPU time 1127.26 seconds
Started Jun 23 06:29:08 PM PDT 24
Finished Jun 23 06:47:56 PM PDT 24
Peak memory 273828 kb
Host smart-abe09609-6464-46a4-a4af-2f3ed3b8afb4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153164626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1153164626
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1145751909
Short name T135
Test name
Test status
Simulation time 4535785428 ps
CPU time 290.37 seconds
Started Jun 23 06:29:12 PM PDT 24
Finished Jun 23 06:34:03 PM PDT 24
Peak memory 265676 kb
Host smart-0d8b760c-36aa-49f9-b8e7-663d44315122
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1145751909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1145751909
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1230992294
Short name T127
Test name
Test status
Simulation time 15330307864 ps
CPU time 276.9 seconds
Started Jun 23 06:29:16 PM PDT 24
Finished Jun 23 06:33:53 PM PDT 24
Peak memory 265692 kb
Host smart-237e417f-9472-4e3a-a67c-af9855fbdf8e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1230992294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1230992294
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3962286142
Short name T132
Test name
Test status
Simulation time 79258559922 ps
CPU time 476.3 seconds
Started Jun 23 06:29:57 PM PDT 24
Finished Jun 23 06:37:53 PM PDT 24
Peak memory 265748 kb
Host smart-5ddae020-3f29-4261-8fec-2e411c2926f9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962286142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3962286142
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3456050092
Short name T270
Test name
Test status
Simulation time 2129693977 ps
CPU time 25.01 seconds
Started Jun 23 06:41:08 PM PDT 24
Finished Jun 23 06:41:33 PM PDT 24
Peak memory 255392 kb
Host smart-08655d36-32c2-4540-9634-ad25ef505956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34560
50092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3456050092
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1748139483
Short name T588
Test name
Test status
Simulation time 46782318541 ps
CPU time 5545.6 seconds
Started Jun 23 06:41:07 PM PDT 24
Finished Jun 23 08:13:34 PM PDT 24
Peak memory 338676 kb
Host smart-eda3a533-c489-44e8-8552-653cf28f9cfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748139483 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1748139483
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3222025374
Short name T272
Test name
Test status
Simulation time 861946521 ps
CPU time 15.73 seconds
Started Jun 23 06:41:41 PM PDT 24
Finished Jun 23 06:41:57 PM PDT 24
Peak memory 249052 kb
Host smart-fcc9e5ce-5e20-4b72-9adf-75570ae1a8f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32220
25374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3222025374
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.4287255695
Short name T332
Test name
Test status
Simulation time 597392434926 ps
CPU time 2875.39 seconds
Started Jun 23 06:41:54 PM PDT 24
Finished Jun 23 07:29:50 PM PDT 24
Peak memory 289316 kb
Host smart-7d21040e-29b9-493a-adf7-28a7009f0888
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287255695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.4287255695
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3951925133
Short name T95
Test name
Test status
Simulation time 91027578708 ps
CPU time 2916.38 seconds
Started Jun 23 06:41:59 PM PDT 24
Finished Jun 23 07:30:36 PM PDT 24
Peak memory 322964 kb
Host smart-14755117-2392-468a-a525-3eadb171cdf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951925133 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3951925133
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2287767132
Short name T186
Test name
Test status
Simulation time 121797900413 ps
CPU time 2861.63 seconds
Started Jun 23 06:42:13 PM PDT 24
Finished Jun 23 07:29:56 PM PDT 24
Peak memory 306452 kb
Host smart-94e8196d-3940-463e-a261-7bf511edb761
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287767132 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2287767132
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1446457158
Short name T103
Test name
Test status
Simulation time 2241864790 ps
CPU time 39.81 seconds
Started Jun 23 06:42:18 PM PDT 24
Finished Jun 23 06:42:59 PM PDT 24
Peak memory 256520 kb
Host smart-549064aa-ae4b-4993-a2f9-ff7772942f1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14464
57158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1446457158
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.694538632
Short name T267
Test name
Test status
Simulation time 2028927134 ps
CPU time 56.47 seconds
Started Jun 23 06:42:25 PM PDT 24
Finished Jun 23 06:43:22 PM PDT 24
Peak memory 256176 kb
Host smart-c97639ef-65e1-49b1-b524-971870a7a230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69453
8632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.694538632
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.907865871
Short name T216
Test name
Test status
Simulation time 25544054154 ps
CPU time 2846.2 seconds
Started Jun 23 06:42:25 PM PDT 24
Finished Jun 23 07:29:52 PM PDT 24
Peak memory 323028 kb
Host smart-cd687103-2272-421f-97bd-c64f4bc2f23c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907865871 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.907865871
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2148861096
Short name T249
Test name
Test status
Simulation time 6695243603 ps
CPU time 172.23 seconds
Started Jun 23 06:42:23 PM PDT 24
Finished Jun 23 06:45:16 PM PDT 24
Peak memory 250148 kb
Host smart-a015cc35-ea79-415c-8dd0-976ca96a9222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21488
61096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2148861096
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2203514789
Short name T1
Test name
Test status
Simulation time 2729776643 ps
CPU time 220.87 seconds
Started Jun 23 06:42:29 PM PDT 24
Finished Jun 23 06:46:10 PM PDT 24
Peak memory 254596 kb
Host smart-cdad7404-9596-4c64-8eea-e94c31b6a57f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203514789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2203514789
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.37203253
Short name T281
Test name
Test status
Simulation time 105436563819 ps
CPU time 1669.89 seconds
Started Jun 23 06:41:16 PM PDT 24
Finished Jun 23 07:09:06 PM PDT 24
Peak memory 281968 kb
Host smart-8d49642c-35df-4925-a686-777d6f91351d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37203253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handl
er_stress_all.37203253
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2583903529
Short name T264
Test name
Test status
Simulation time 182775266266 ps
CPU time 3080.94 seconds
Started Jun 23 06:43:22 PM PDT 24
Finished Jun 23 07:34:44 PM PDT 24
Peak memory 300800 kb
Host smart-19b5a4a2-a0d2-4909-b647-49fe7c4be42c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583903529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2583903529
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1939243604
Short name T285
Test name
Test status
Simulation time 1103999508 ps
CPU time 61.58 seconds
Started Jun 23 06:43:49 PM PDT 24
Finished Jun 23 06:44:51 PM PDT 24
Peak memory 257168 kb
Host smart-4468f5ab-d96d-469b-a38e-d1ca4c660ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19392
43604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1939243604
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.597665133
Short name T248
Test name
Test status
Simulation time 5083081583 ps
CPU time 495.05 seconds
Started Jun 23 06:43:55 PM PDT 24
Finished Jun 23 06:52:10 PM PDT 24
Peak memory 265468 kb
Host smart-a2ba767c-ddbc-477d-ac78-5a68b3d7cae0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597665133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.597665133
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3181802111
Short name T286
Test name
Test status
Simulation time 172747896315 ps
CPU time 2531.06 seconds
Started Jun 23 06:41:32 PM PDT 24
Finished Jun 23 07:23:44 PM PDT 24
Peak memory 289912 kb
Host smart-eb2134e2-f1c3-4f01-a624-a4e5508c1c46
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181802111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3181802111
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1382073681
Short name T822
Test name
Test status
Simulation time 3350259103 ps
CPU time 186.48 seconds
Started Jun 23 06:29:03 PM PDT 24
Finished Jun 23 06:32:10 PM PDT 24
Peak memory 273600 kb
Host smart-3d07f56a-086a-4efc-a938-98d9679d1b17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1382073681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1382073681
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1596281246
Short name T167
Test name
Test status
Simulation time 111237865 ps
CPU time 3.96 seconds
Started Jun 23 06:29:59 PM PDT 24
Finished Jun 23 06:30:03 PM PDT 24
Peak memory 237268 kb
Host smart-1d17cb70-6e13-439e-a9eb-ac67d4608cee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1596281246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1596281246
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1415394654
Short name T174
Test name
Test status
Simulation time 157390739 ps
CPU time 7.91 seconds
Started Jun 23 06:29:14 PM PDT 24
Finished Jun 23 06:29:23 PM PDT 24
Peak memory 238648 kb
Host smart-8ba31efe-d75b-4e62-b29e-a8392fa5dd52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1415394654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1415394654
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.4201011766
Short name T170
Test name
Test status
Simulation time 2308405409 ps
CPU time 43.53 seconds
Started Jun 23 06:29:46 PM PDT 24
Finished Jun 23 06:30:30 PM PDT 24
Peak memory 240284 kb
Host smart-cdbc23b4-3bbc-4b82-8b5e-6e459a82b5b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4201011766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.4201011766
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2493812592
Short name T171
Test name
Test status
Simulation time 4847021699 ps
CPU time 84.25 seconds
Started Jun 23 06:29:57 PM PDT 24
Finished Jun 23 06:31:22 PM PDT 24
Peak memory 240836 kb
Host smart-98cae353-7945-4895-bf34-d7852c82720b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2493812592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2493812592
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.4195562623
Short name T172
Test name
Test status
Simulation time 3497883212 ps
CPU time 41.54 seconds
Started Jun 23 06:30:15 PM PDT 24
Finished Jun 23 06:30:57 PM PDT 24
Peak memory 240844 kb
Host smart-fa73d198-d141-4fdd-8fa0-682dfd8b066e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4195562623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.4195562623
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1547601786
Short name T173
Test name
Test status
Simulation time 606578085 ps
CPU time 40.38 seconds
Started Jun 23 06:29:32 PM PDT 24
Finished Jun 23 06:30:13 PM PDT 24
Peak memory 237460 kb
Host smart-4b87acf8-47d6-44a2-a522-6864209bdc1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1547601786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1547601786
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2113535724
Short name T169
Test name
Test status
Simulation time 35773447 ps
CPU time 2.82 seconds
Started Jun 23 06:29:37 PM PDT 24
Finished Jun 23 06:29:40 PM PDT 24
Peak memory 237104 kb
Host smart-9bb13c32-423f-4166-9653-630f5a00feb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2113535724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2113535724
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2858873093
Short name T130
Test name
Test status
Simulation time 4319291672 ps
CPU time 184.45 seconds
Started Jun 23 06:29:47 PM PDT 24
Finished Jun 23 06:32:52 PM PDT 24
Peak memory 265688 kb
Host smart-a68889b0-3ca3-4072-b80a-9bdeb8db8d1a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2858873093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2858873093
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3715450038
Short name T168
Test name
Test status
Simulation time 4294033588 ps
CPU time 103.23 seconds
Started Jun 23 06:29:52 PM PDT 24
Finished Jun 23 06:31:35 PM PDT 24
Peak memory 249048 kb
Host smart-0885870c-0847-4564-8b4d-97d6a1cb1702
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3715450038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3715450038
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1918747448
Short name T165
Test name
Test status
Simulation time 63887704 ps
CPU time 4.96 seconds
Started Jun 23 06:29:22 PM PDT 24
Finished Jun 23 06:29:27 PM PDT 24
Peak memory 237484 kb
Host smart-ec15acf5-e142-4949-bd20-0016de63053c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1918747448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1918747448
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2200566191
Short name T166
Test name
Test status
Simulation time 121190082 ps
CPU time 3.26 seconds
Started Jun 23 06:30:01 PM PDT 24
Finished Jun 23 06:30:04 PM PDT 24
Peak memory 237268 kb
Host smart-05a0adbd-83ad-4ce6-8b1c-c08b3df338a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2200566191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2200566191
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2318563956
Short name T176
Test name
Test status
Simulation time 144750494 ps
CPU time 2.23 seconds
Started Jun 23 06:29:21 PM PDT 24
Finished Jun 23 06:29:23 PM PDT 24
Peak memory 237308 kb
Host smart-1dfd49c0-000e-44ed-b868-0aa506e71e0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2318563956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2318563956
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2369333932
Short name T181
Test name
Test status
Simulation time 420144213 ps
CPU time 4.12 seconds
Started Jun 23 06:29:27 PM PDT 24
Finished Jun 23 06:29:32 PM PDT 24
Peak memory 237528 kb
Host smart-7749a954-80b1-47d9-bbfc-fe22572d0799
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2369333932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2369333932
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1047170048
Short name T21
Test name
Test status
Simulation time 69470456353 ps
CPU time 2063.31 seconds
Started Jun 23 06:41:21 PM PDT 24
Finished Jun 23 07:15:45 PM PDT 24
Peak memory 287564 kb
Host smart-a0e43226-90b9-4832-962e-ee80d0a99ca8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047170048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1047170048
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.704071396
Short name T727
Test name
Test status
Simulation time 523841561 ps
CPU time 61.23 seconds
Started Jun 23 06:29:07 PM PDT 24
Finished Jun 23 06:30:08 PM PDT 24
Peak memory 237380 kb
Host smart-e77a8eeb-5d64-44a9-9605-a77c3eb45c74
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=704071396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.704071396
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3383800585
Short name T786
Test name
Test status
Simulation time 3270565661 ps
CPU time 98.8 seconds
Started Jun 23 06:29:06 PM PDT 24
Finished Jun 23 06:30:45 PM PDT 24
Peak memory 240780 kb
Host smart-992b6631-d9ff-4681-99d0-0d7dc9d71967
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3383800585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3383800585
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2734060750
Short name T805
Test name
Test status
Simulation time 115985270 ps
CPU time 4.98 seconds
Started Jun 23 06:29:08 PM PDT 24
Finished Jun 23 06:29:14 PM PDT 24
Peak memory 240696 kb
Host smart-8fa9856b-9d09-4dad-91e4-a13724e178d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2734060750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2734060750
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1639293968
Short name T801
Test name
Test status
Simulation time 582035991 ps
CPU time 10.71 seconds
Started Jun 23 06:29:09 PM PDT 24
Finished Jun 23 06:29:20 PM PDT 24
Peak memory 239524 kb
Host smart-cb53ea5e-0e41-42ec-923d-1ec84eded733
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639293968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1639293968
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3320961801
Short name T752
Test name
Test status
Simulation time 71615132 ps
CPU time 4.29 seconds
Started Jun 23 06:29:06 PM PDT 24
Finished Jun 23 06:29:11 PM PDT 24
Peak memory 236348 kb
Host smart-da32b284-77cf-4d52-b484-b66573e868b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3320961801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3320961801
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2754515883
Short name T737
Test name
Test status
Simulation time 8183666 ps
CPU time 1.58 seconds
Started Jun 23 06:29:10 PM PDT 24
Finished Jun 23 06:29:12 PM PDT 24
Peak memory 235596 kb
Host smart-f5552e14-ace6-465f-a76e-f2dc271f2847
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2754515883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2754515883
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.332949593
Short name T757
Test name
Test status
Simulation time 511428106 ps
CPU time 34.29 seconds
Started Jun 23 06:29:07 PM PDT 24
Finished Jun 23 06:29:42 PM PDT 24
Peak memory 244632 kb
Host smart-9562d534-cdd3-4e0c-b43c-bd5abf683761
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=332949593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.332949593
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3263387342
Short name T734
Test name
Test status
Simulation time 445633575 ps
CPU time 7.8 seconds
Started Jun 23 06:29:09 PM PDT 24
Finished Jun 23 06:29:18 PM PDT 24
Peak memory 249036 kb
Host smart-53cbb548-f26f-46ce-bab2-17657244cbe9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3263387342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3263387342
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.4182919041
Short name T728
Test name
Test status
Simulation time 568433299 ps
CPU time 70 seconds
Started Jun 23 06:29:11 PM PDT 24
Finished Jun 23 06:30:21 PM PDT 24
Peak memory 237296 kb
Host smart-edab1b0c-87fb-46a2-9958-189d1f68d67d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4182919041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.4182919041
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3200849233
Short name T177
Test name
Test status
Simulation time 8714624368 ps
CPU time 288.45 seconds
Started Jun 23 06:29:13 PM PDT 24
Finished Jun 23 06:34:02 PM PDT 24
Peak memory 240780 kb
Host smart-ec73f5f0-a1f0-48b3-8250-44ddd28ea072
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3200849233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3200849233
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1207529917
Short name T815
Test name
Test status
Simulation time 247771043 ps
CPU time 9.81 seconds
Started Jun 23 06:29:12 PM PDT 24
Finished Jun 23 06:29:23 PM PDT 24
Peak memory 240900 kb
Host smart-8e21f4d0-45a5-4811-a2ce-28202a281cd0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1207529917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1207529917
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2148057794
Short name T823
Test name
Test status
Simulation time 56618529 ps
CPU time 5.15 seconds
Started Jun 23 06:29:12 PM PDT 24
Finished Jun 23 06:29:17 PM PDT 24
Peak memory 239864 kb
Host smart-81385aa3-0127-44ac-a12e-e6efd3499c67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148057794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.2148057794
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.4197076829
Short name T354
Test name
Test status
Simulation time 122366458 ps
CPU time 5.65 seconds
Started Jun 23 06:29:16 PM PDT 24
Finished Jun 23 06:29:22 PM PDT 24
Peak memory 237288 kb
Host smart-e3409719-e18f-4afc-83b6-c2c2283706cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4197076829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.4197076829
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3907625499
Short name T767
Test name
Test status
Simulation time 10092447 ps
CPU time 1.35 seconds
Started Jun 23 06:29:11 PM PDT 24
Finished Jun 23 06:29:13 PM PDT 24
Peak memory 237332 kb
Host smart-e62719e7-a9fd-43dc-9212-5ea9b1fbf911
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3907625499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3907625499
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1793264207
Short name T832
Test name
Test status
Simulation time 599528594 ps
CPU time 36.48 seconds
Started Jun 23 06:29:12 PM PDT 24
Finished Jun 23 06:29:49 PM PDT 24
Peak memory 248956 kb
Host smart-618fc13f-a2ef-4a49-8290-e129173d3b5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1793264207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1793264207
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3264163238
Short name T738
Test name
Test status
Simulation time 367166312 ps
CPU time 14.02 seconds
Started Jun 23 06:29:12 PM PDT 24
Finished Jun 23 06:29:27 PM PDT 24
Peak memory 248908 kb
Host smart-6f07b623-fbb3-44fd-9941-4067117f3cf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3264163238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3264163238
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.105821805
Short name T794
Test name
Test status
Simulation time 198131246 ps
CPU time 4.65 seconds
Started Jun 23 06:29:49 PM PDT 24
Finished Jun 23 06:29:53 PM PDT 24
Peak memory 237256 kb
Host smart-8bae2a64-aac7-40cb-8c42-7ab587e2b5f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=105821805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.105821805
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.967900940
Short name T761
Test name
Test status
Simulation time 13596396 ps
CPU time 1.39 seconds
Started Jun 23 06:29:47 PM PDT 24
Finished Jun 23 06:29:49 PM PDT 24
Peak memory 235456 kb
Host smart-8cc5bc93-b42c-49e5-b090-4dc700e8be6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=967900940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.967900940
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1006712959
Short name T812
Test name
Test status
Simulation time 696372178 ps
CPU time 29.62 seconds
Started Jun 23 06:29:46 PM PDT 24
Finished Jun 23 06:30:16 PM PDT 24
Peak memory 245560 kb
Host smart-cf8904c1-8de8-443e-9ad6-d3903099ccba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1006712959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1006712959
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3311230752
Short name T124
Test name
Test status
Simulation time 51461983360 ps
CPU time 500.26 seconds
Started Jun 23 06:29:48 PM PDT 24
Finished Jun 23 06:38:08 PM PDT 24
Peak memory 265552 kb
Host smart-3cf3724d-1d22-4094-9f41-32eded54c175
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311230752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3311230752
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3316618542
Short name T777
Test name
Test status
Simulation time 152140497 ps
CPU time 9.57 seconds
Started Jun 23 06:29:48 PM PDT 24
Finished Jun 23 06:29:58 PM PDT 24
Peak memory 247792 kb
Host smart-7ab62837-cae3-4b06-82dd-ae1fcce61875
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3316618542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3316618542
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3539304863
Short name T807
Test name
Test status
Simulation time 103090546 ps
CPU time 9.7 seconds
Started Jun 23 06:29:47 PM PDT 24
Finished Jun 23 06:29:57 PM PDT 24
Peak memory 240312 kb
Host smart-2eac697d-c780-43bb-af68-f11351d7a28d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539304863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3539304863
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.146799653
Short name T745
Test name
Test status
Simulation time 41728522 ps
CPU time 6.05 seconds
Started Jun 23 06:29:46 PM PDT 24
Finished Jun 23 06:29:52 PM PDT 24
Peak memory 237292 kb
Host smart-08ada0b9-39a4-4e06-bff6-8c2b3ef5ba6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=146799653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.146799653
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.380290779
Short name T732
Test name
Test status
Simulation time 9337911 ps
CPU time 1.55 seconds
Started Jun 23 06:29:47 PM PDT 24
Finished Jun 23 06:29:48 PM PDT 24
Peak memory 237264 kb
Host smart-a2c04509-dcd7-460e-aa1d-6d8696298e46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=380290779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.380290779
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1848999885
Short name T818
Test name
Test status
Simulation time 171888367 ps
CPU time 11.76 seconds
Started Jun 23 06:29:51 PM PDT 24
Finished Jun 23 06:30:03 PM PDT 24
Peak memory 245536 kb
Host smart-1b83d789-0164-4aa6-8836-ea34e4fec816
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1848999885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1848999885
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2822455484
Short name T138
Test name
Test status
Simulation time 2858687131 ps
CPU time 85.58 seconds
Started Jun 23 06:29:48 PM PDT 24
Finished Jun 23 06:31:13 PM PDT 24
Peak memory 265680 kb
Host smart-598fcb9c-03c7-4bbc-8a18-32d06b6c2c69
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2822455484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2822455484
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3025479665
Short name T758
Test name
Test status
Simulation time 58030127 ps
CPU time 4.47 seconds
Started Jun 23 06:29:48 PM PDT 24
Finished Jun 23 06:29:53 PM PDT 24
Peak memory 252376 kb
Host smart-14856228-cf49-4eca-9cb9-d4976f69b466
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3025479665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3025479665
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.483235845
Short name T831
Test name
Test status
Simulation time 290467931 ps
CPU time 6.68 seconds
Started Jun 23 06:29:54 PM PDT 24
Finished Jun 23 06:30:01 PM PDT 24
Peak memory 240096 kb
Host smart-e01f23fc-b7bf-4464-bf89-01ca145a90d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483235845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.483235845
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2509045970
Short name T782
Test name
Test status
Simulation time 166106687 ps
CPU time 10.68 seconds
Started Jun 23 06:29:53 PM PDT 24
Finished Jun 23 06:30:04 PM PDT 24
Peak memory 237460 kb
Host smart-7c7bfa63-1a78-4c52-9cce-e73540bc5285
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2509045970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2509045970
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.486919624
Short name T770
Test name
Test status
Simulation time 15085363 ps
CPU time 1.37 seconds
Started Jun 23 06:29:52 PM PDT 24
Finished Jun 23 06:29:54 PM PDT 24
Peak memory 235372 kb
Host smart-25f810fe-df78-4552-beb0-6cd72bfb894c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=486919624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.486919624
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1336746263
Short name T821
Test name
Test status
Simulation time 330102199 ps
CPU time 28.23 seconds
Started Jun 23 06:29:52 PM PDT 24
Finished Jun 23 06:30:20 PM PDT 24
Peak memory 245560 kb
Host smart-22bdbd93-3008-4289-8346-33edf0d5e6bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1336746263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1336746263
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.4138257170
Short name T756
Test name
Test status
Simulation time 332029004 ps
CPU time 12.01 seconds
Started Jun 23 06:29:52 PM PDT 24
Finished Jun 23 06:30:04 PM PDT 24
Peak memory 248208 kb
Host smart-97fb6be0-3ba8-4f03-a939-5566ce2423e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4138257170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.4138257170
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.908460751
Short name T355
Test name
Test status
Simulation time 456431657 ps
CPU time 6.25 seconds
Started Jun 23 06:29:56 PM PDT 24
Finished Jun 23 06:30:03 PM PDT 24
Peak memory 243716 kb
Host smart-7a943abb-68c3-4a61-9baa-83b3ae4b9350
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908460751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.908460751
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1827838073
Short name T748
Test name
Test status
Simulation time 95688523 ps
CPU time 4.98 seconds
Started Jun 23 06:29:59 PM PDT 24
Finished Jun 23 06:30:04 PM PDT 24
Peak memory 236364 kb
Host smart-08671ef9-eb30-4416-98de-120eba52b569
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1827838073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1827838073
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1102594513
Short name T814
Test name
Test status
Simulation time 75176318 ps
CPU time 1.42 seconds
Started Jun 23 06:30:01 PM PDT 24
Finished Jun 23 06:30:03 PM PDT 24
Peak memory 236436 kb
Host smart-7b36d68b-d2de-4f33-8201-637aa1e1dea8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1102594513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1102594513
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.4170428644
Short name T780
Test name
Test status
Simulation time 609601971 ps
CPU time 38.44 seconds
Started Jun 23 06:29:59 PM PDT 24
Finished Jun 23 06:30:38 PM PDT 24
Peak memory 244616 kb
Host smart-ce7bdb64-08ab-46b4-b7c8-84c4981ed8f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4170428644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.4170428644
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3156339558
Short name T142
Test name
Test status
Simulation time 22999396098 ps
CPU time 403.81 seconds
Started Jun 23 06:29:56 PM PDT 24
Finished Jun 23 06:36:41 PM PDT 24
Peak memory 266712 kb
Host smart-9479885b-71c6-4b50-9058-be38d626d21a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3156339558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3156339558
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3508536438
Short name T155
Test name
Test status
Simulation time 12331369883 ps
CPU time 502.09 seconds
Started Jun 23 06:29:52 PM PDT 24
Finished Jun 23 06:38:14 PM PDT 24
Peak memory 265632 kb
Host smart-63e4610d-d3e9-497f-bd4c-883f0f1df3b7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508536438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3508536438
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3193414112
Short name T778
Test name
Test status
Simulation time 874168851 ps
CPU time 13.78 seconds
Started Jun 23 06:30:00 PM PDT 24
Finished Jun 23 06:30:14 PM PDT 24
Peak memory 249000 kb
Host smart-eac98745-9087-4d2f-9ff3-24f689e654e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3193414112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3193414112
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3818630155
Short name T159
Test name
Test status
Simulation time 112164010 ps
CPU time 4.55 seconds
Started Jun 23 06:29:59 PM PDT 24
Finished Jun 23 06:30:04 PM PDT 24
Peak memory 237216 kb
Host smart-c96fe4bb-255b-44fa-860c-f52a6d1cee23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3818630155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3818630155
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3563764575
Short name T779
Test name
Test status
Simulation time 140376005 ps
CPU time 11.13 seconds
Started Jun 23 06:29:57 PM PDT 24
Finished Jun 23 06:30:08 PM PDT 24
Peak memory 240828 kb
Host smart-edb26670-3f9b-47f7-89d2-dcc80add0dbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563764575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3563764575
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1586661316
Short name T747
Test name
Test status
Simulation time 77074671 ps
CPU time 5.05 seconds
Started Jun 23 06:29:57 PM PDT 24
Finished Jun 23 06:30:02 PM PDT 24
Peak memory 239112 kb
Host smart-76080323-425d-4c33-b5af-6ac979f07483
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1586661316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1586661316
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.4230292050
Short name T834
Test name
Test status
Simulation time 12638560 ps
CPU time 1.37 seconds
Started Jun 23 06:29:57 PM PDT 24
Finished Jun 23 06:29:58 PM PDT 24
Peak memory 236432 kb
Host smart-a631ea63-a419-4de7-acc7-17fe428a2576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4230292050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.4230292050
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.441779131
Short name T725
Test name
Test status
Simulation time 175172049 ps
CPU time 19.56 seconds
Started Jun 23 06:30:01 PM PDT 24
Finished Jun 23 06:30:21 PM PDT 24
Peak memory 244628 kb
Host smart-2c49e6f9-593a-4990-9c54-0b21e40e5c99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=441779131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.441779131
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.328239456
Short name T721
Test name
Test status
Simulation time 918798063 ps
CPU time 7.54 seconds
Started Jun 23 06:29:58 PM PDT 24
Finished Jun 23 06:30:05 PM PDT 24
Peak memory 251084 kb
Host smart-c620be79-9ddd-43d0-930f-226dff5627b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=328239456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.328239456
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3078449850
Short name T787
Test name
Test status
Simulation time 150553788 ps
CPU time 6.32 seconds
Started Jun 23 06:30:02 PM PDT 24
Finished Jun 23 06:30:08 PM PDT 24
Peak memory 239964 kb
Host smart-33372e2a-e019-4a1f-9209-5eab14ffffa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078449850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3078449850
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3063625746
Short name T358
Test name
Test status
Simulation time 73400161 ps
CPU time 3.52 seconds
Started Jun 23 06:30:03 PM PDT 24
Finished Jun 23 06:30:07 PM PDT 24
Peak memory 237288 kb
Host smart-a457b7fc-eefd-4033-b832-eec8653eaa21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3063625746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3063625746
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2314574077
Short name T817
Test name
Test status
Simulation time 30437725 ps
CPU time 1.51 seconds
Started Jun 23 06:30:03 PM PDT 24
Finished Jun 23 06:30:05 PM PDT 24
Peak memory 237352 kb
Host smart-4c951480-d605-44df-8b71-5fd322806ee3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2314574077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2314574077
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1149563247
Short name T760
Test name
Test status
Simulation time 477843243 ps
CPU time 26.63 seconds
Started Jun 23 06:30:03 PM PDT 24
Finished Jun 23 06:30:30 PM PDT 24
Peak memory 245572 kb
Host smart-767613e6-84d7-40db-9d14-1780cc6a4130
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1149563247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1149563247
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.155932962
Short name T833
Test name
Test status
Simulation time 2409940103 ps
CPU time 170.66 seconds
Started Jun 23 06:29:56 PM PDT 24
Finished Jun 23 06:32:47 PM PDT 24
Peak memory 265660 kb
Host smart-05ad2492-ccf8-4bc8-953e-0a5c49dfe790
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=155932962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.155932962
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3604732377
Short name T784
Test name
Test status
Simulation time 192612549 ps
CPU time 12.72 seconds
Started Jun 23 06:29:56 PM PDT 24
Finished Jun 23 06:30:09 PM PDT 24
Peak memory 246648 kb
Host smart-3d3d4c6d-9d60-424d-bc30-7d41898b70f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3604732377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3604732377
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3385043834
Short name T788
Test name
Test status
Simulation time 1882701812 ps
CPU time 10.78 seconds
Started Jun 23 06:30:01 PM PDT 24
Finished Jun 23 06:30:13 PM PDT 24
Peak memory 251052 kb
Host smart-43abfe63-b904-455e-8028-7763d6a59829
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385043834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3385043834
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.320825186
Short name T750
Test name
Test status
Simulation time 224959575 ps
CPU time 4.54 seconds
Started Jun 23 06:30:01 PM PDT 24
Finished Jun 23 06:30:05 PM PDT 24
Peak memory 236352 kb
Host smart-65ab8f9b-130d-4094-8fa3-4ea9b67b569a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=320825186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.320825186
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1213510249
Short name T830
Test name
Test status
Simulation time 8543690 ps
CPU time 1.52 seconds
Started Jun 23 06:30:02 PM PDT 24
Finished Jun 23 06:30:04 PM PDT 24
Peak memory 237384 kb
Host smart-3210cab9-8d10-43f9-9ed6-b6f4fc79f576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1213510249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1213510249
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.630915225
Short name T179
Test name
Test status
Simulation time 516651873 ps
CPU time 39.31 seconds
Started Jun 23 06:30:01 PM PDT 24
Finished Jun 23 06:30:40 PM PDT 24
Peak memory 245760 kb
Host smart-6a7eeaad-a4e8-464b-b6a0-7aa208771b4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=630915225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.630915225
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3054156974
Short name T149
Test name
Test status
Simulation time 1861008425 ps
CPU time 117.26 seconds
Started Jun 23 06:30:06 PM PDT 24
Finished Jun 23 06:32:03 PM PDT 24
Peak memory 265604 kb
Host smart-946a5452-5dcc-40b1-85f1-6628a31335cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3054156974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3054156974
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.588761295
Short name T361
Test name
Test status
Simulation time 8772531466 ps
CPU time 364.94 seconds
Started Jun 23 06:30:03 PM PDT 24
Finished Jun 23 06:36:09 PM PDT 24
Peak memory 269860 kb
Host smart-8de7d153-6171-4ca7-ba85-d1a55540449f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588761295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.588761295
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1761162593
Short name T720
Test name
Test status
Simulation time 50353900 ps
CPU time 7.14 seconds
Started Jun 23 06:30:03 PM PDT 24
Finished Jun 23 06:30:10 PM PDT 24
Peak memory 249044 kb
Host smart-118a1fad-8132-4463-a3c6-b8cd48b37482
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1761162593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1761162593
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1780518271
Short name T828
Test name
Test status
Simulation time 186940738 ps
CPU time 7.82 seconds
Started Jun 23 06:30:08 PM PDT 24
Finished Jun 23 06:30:16 PM PDT 24
Peak memory 251404 kb
Host smart-656afd99-9839-4de9-89f3-8edd49d5b57b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780518271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1780518271
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2267732909
Short name T730
Test name
Test status
Simulation time 122178013 ps
CPU time 5.7 seconds
Started Jun 23 06:30:07 PM PDT 24
Finished Jun 23 06:30:13 PM PDT 24
Peak memory 237292 kb
Host smart-4d76342c-e4a3-4345-b675-980221b519f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2267732909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2267732909
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2952370835
Short name T350
Test name
Test status
Simulation time 16056153 ps
CPU time 1.4 seconds
Started Jun 23 06:30:10 PM PDT 24
Finished Jun 23 06:30:11 PM PDT 24
Peak memory 237372 kb
Host smart-b3a37372-9596-45e1-896c-159f88586ef4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2952370835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2952370835
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.761021537
Short name T775
Test name
Test status
Simulation time 323187833 ps
CPU time 13.94 seconds
Started Jun 23 06:30:08 PM PDT 24
Finished Jun 23 06:30:22 PM PDT 24
Peak memory 240768 kb
Host smart-9a0aed36-38cd-4dcd-a591-bab0c646595e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=761021537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.761021537
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.348574766
Short name T126
Test name
Test status
Simulation time 10803291347 ps
CPU time 147.35 seconds
Started Jun 23 06:30:08 PM PDT 24
Finished Jun 23 06:32:36 PM PDT 24
Peak memory 265664 kb
Host smart-a0eb4f98-4c38-434b-9e3e-854551bdc1b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=348574766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.348574766
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1793858337
Short name T153
Test name
Test status
Simulation time 2304756708 ps
CPU time 338.81 seconds
Started Jun 23 06:30:02 PM PDT 24
Finished Jun 23 06:35:41 PM PDT 24
Peak memory 265756 kb
Host smart-270ccc86-4a0f-4031-bc45-54100761455f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793858337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1793858337
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2065026093
Short name T789
Test name
Test status
Simulation time 45443275 ps
CPU time 5.43 seconds
Started Jun 23 06:30:08 PM PDT 24
Finished Jun 23 06:30:14 PM PDT 24
Peak memory 249004 kb
Host smart-6d9ed9c9-1bf3-4999-9572-b9d7368406ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2065026093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2065026093
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2405588564
Short name T795
Test name
Test status
Simulation time 1514335399 ps
CPU time 23.94 seconds
Started Jun 23 06:30:07 PM PDT 24
Finished Jun 23 06:30:31 PM PDT 24
Peak memory 245700 kb
Host smart-0697623d-4729-4d41-896d-19bf49cd6525
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2405588564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2405588564
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.45227216
Short name T771
Test name
Test status
Simulation time 224074528 ps
CPU time 8.82 seconds
Started Jun 23 06:30:07 PM PDT 24
Finished Jun 23 06:30:16 PM PDT 24
Peak memory 240828 kb
Host smart-baae7364-739c-4fc0-bf71-6ee15762916e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45227216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.alert_handler_csr_mem_rw_with_rand_reset.45227216
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.4241974732
Short name T731
Test name
Test status
Simulation time 168797450 ps
CPU time 5.5 seconds
Started Jun 23 06:30:07 PM PDT 24
Finished Jun 23 06:30:13 PM PDT 24
Peak memory 237288 kb
Host smart-700f2fe5-d4d1-4086-9b6b-99ce21c1ae9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4241974732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.4241974732
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3537315366
Short name T723
Test name
Test status
Simulation time 124581709 ps
CPU time 1.38 seconds
Started Jun 23 06:30:08 PM PDT 24
Finished Jun 23 06:30:10 PM PDT 24
Peak memory 235304 kb
Host smart-a5479ec8-0122-4ce5-a065-1667bd0a2815
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3537315366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3537315366
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.664588749
Short name T806
Test name
Test status
Simulation time 327339323 ps
CPU time 19.85 seconds
Started Jun 23 06:30:08 PM PDT 24
Finished Jun 23 06:30:29 PM PDT 24
Peak memory 245568 kb
Host smart-e594a74b-1130-4a37-b9e0-3466dfbfcfdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=664588749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.664588749
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.986118613
Short name T152
Test name
Test status
Simulation time 8480320436 ps
CPU time 159.75 seconds
Started Jun 23 06:30:09 PM PDT 24
Finished Jun 23 06:32:49 PM PDT 24
Peak memory 265688 kb
Host smart-12308542-4530-4fdb-8d25-d8189cab84f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=986118613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_erro
rs.986118613
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1076159084
Short name T129
Test name
Test status
Simulation time 11337037582 ps
CPU time 343.47 seconds
Started Jun 23 06:30:08 PM PDT 24
Finished Jun 23 06:35:52 PM PDT 24
Peak memory 265620 kb
Host smart-fe387301-d83f-4311-8894-e80c9d27c458
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076159084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1076159084
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2085145388
Short name T716
Test name
Test status
Simulation time 131828326 ps
CPU time 9.19 seconds
Started Jun 23 06:30:08 PM PDT 24
Finished Jun 23 06:30:18 PM PDT 24
Peak memory 249980 kb
Host smart-b6850641-acd1-44e0-83ea-d176ccffe619
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2085145388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2085145388
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1144078109
Short name T158
Test name
Test status
Simulation time 58072713 ps
CPU time 3.74 seconds
Started Jun 23 06:30:07 PM PDT 24
Finished Jun 23 06:30:11 PM PDT 24
Peak memory 237148 kb
Host smart-c9dfee2c-d980-4185-a8e0-70d961ca249e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1144078109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1144078109
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2225159177
Short name T749
Test name
Test status
Simulation time 150779811 ps
CPU time 11.01 seconds
Started Jun 23 06:30:11 PM PDT 24
Finished Jun 23 06:30:22 PM PDT 24
Peak memory 243244 kb
Host smart-cb27e277-03e3-4441-9bb5-ea84a6ba54cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225159177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2225159177
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1962793565
Short name T809
Test name
Test status
Simulation time 20010002 ps
CPU time 3.49 seconds
Started Jun 23 06:30:13 PM PDT 24
Finished Jun 23 06:30:17 PM PDT 24
Peak memory 236328 kb
Host smart-470ef250-3ba5-438e-9176-70d71eaaa644
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1962793565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1962793565
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.4026590720
Short name T163
Test name
Test status
Simulation time 8639597 ps
CPU time 1.44 seconds
Started Jun 23 06:30:13 PM PDT 24
Finished Jun 23 06:30:14 PM PDT 24
Peak memory 237384 kb
Host smart-5f15da54-7411-43d0-986d-400544d5487c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4026590720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.4026590720
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3353077337
Short name T189
Test name
Test status
Simulation time 791693403 ps
CPU time 26.4 seconds
Started Jun 23 06:30:14 PM PDT 24
Finished Jun 23 06:30:40 PM PDT 24
Peak memory 245552 kb
Host smart-1a29c109-9982-4793-addc-e3adaa8b57de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3353077337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3353077337
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.379017087
Short name T147
Test name
Test status
Simulation time 1944453017 ps
CPU time 149.72 seconds
Started Jun 23 06:30:13 PM PDT 24
Finished Jun 23 06:32:43 PM PDT 24
Peak memory 257432 kb
Host smart-929e51fc-bb82-45bb-9e37-362f4ea051e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=379017087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.379017087
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3851540830
Short name T140
Test name
Test status
Simulation time 6473499608 ps
CPU time 644.12 seconds
Started Jun 23 06:30:11 PM PDT 24
Finished Jun 23 06:40:56 PM PDT 24
Peak memory 265848 kb
Host smart-79b29494-f709-415a-80fd-f74af41bb192
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851540830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3851540830
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4145793350
Short name T759
Test name
Test status
Simulation time 166182690 ps
CPU time 7.41 seconds
Started Jun 23 06:30:12 PM PDT 24
Finished Jun 23 06:30:20 PM PDT 24
Peak memory 248992 kb
Host smart-78004e4f-2d00-45c4-b204-602a0a6260de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4145793350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.4145793350
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3406329688
Short name T820
Test name
Test status
Simulation time 7181016881 ps
CPU time 119.08 seconds
Started Jun 23 06:29:15 PM PDT 24
Finished Jun 23 06:31:15 PM PDT 24
Peak memory 240784 kb
Host smart-f34fb151-f7a8-4a9c-a7a3-22323d266ccd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3406329688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3406329688
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2152666980
Short name T162
Test name
Test status
Simulation time 42172906 ps
CPU time 3.33 seconds
Started Jun 23 06:29:17 PM PDT 24
Finished Jun 23 06:29:21 PM PDT 24
Peak memory 240692 kb
Host smart-4298fb72-03cd-4549-80ea-ebdeb31a70b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2152666980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2152666980
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.126837069
Short name T191
Test name
Test status
Simulation time 1827208452 ps
CPU time 12.81 seconds
Started Jun 23 06:29:18 PM PDT 24
Finished Jun 23 06:29:31 PM PDT 24
Peak memory 251432 kb
Host smart-e5dda2ba-7a42-49e1-afbe-8cff670366c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126837069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.alert_handler_csr_mem_rw_with_rand_reset.126837069
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.892305919
Short name T772
Test name
Test status
Simulation time 35553540 ps
CPU time 6.94 seconds
Started Jun 23 06:29:16 PM PDT 24
Finished Jun 23 06:29:24 PM PDT 24
Peak memory 237328 kb
Host smart-9693af33-9a10-4354-9b35-67798425c2f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=892305919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.892305919
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1063098161
Short name T797
Test name
Test status
Simulation time 7704338 ps
CPU time 1.49 seconds
Started Jun 23 06:29:16 PM PDT 24
Finished Jun 23 06:29:18 PM PDT 24
Peak memory 237372 kb
Host smart-f54779d8-f4e2-4df4-aa13-56b2612425f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1063098161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1063098161
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3072866181
Short name T729
Test name
Test status
Simulation time 490041040 ps
CPU time 36.43 seconds
Started Jun 23 06:29:20 PM PDT 24
Finished Jun 23 06:29:57 PM PDT 24
Peak memory 244540 kb
Host smart-02ce2eac-9917-41c5-b3b9-6d8ee9abdcb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3072866181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3072866181
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.427531212
Short name T145
Test name
Test status
Simulation time 7103721654 ps
CPU time 479.59 seconds
Started Jun 23 06:29:13 PM PDT 24
Finished Jun 23 06:37:13 PM PDT 24
Peak memory 265664 kb
Host smart-71302468-af30-440d-9c35-0fc905ad161e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427531212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.427531212
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.4205798611
Short name T798
Test name
Test status
Simulation time 539752405 ps
CPU time 10.06 seconds
Started Jun 23 06:29:12 PM PDT 24
Finished Jun 23 06:29:23 PM PDT 24
Peak memory 249008 kb
Host smart-08eceb54-4ba1-49dd-95b4-7b832eb3a16d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4205798611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.4205798611
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1153450834
Short name T160
Test name
Test status
Simulation time 23615136 ps
CPU time 2.53 seconds
Started Jun 23 06:29:18 PM PDT 24
Finished Jun 23 06:29:21 PM PDT 24
Peak memory 237272 kb
Host smart-284a5631-dfb0-45e7-96ca-3be021bb8204
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1153450834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1153450834
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.977774426
Short name T736
Test name
Test status
Simulation time 8959106 ps
CPU time 1.52 seconds
Started Jun 23 06:30:15 PM PDT 24
Finished Jun 23 06:30:17 PM PDT 24
Peak memory 237372 kb
Host smart-6d9f0efa-5662-4da0-b69f-685d9964fbcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=977774426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.977774426
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1695860422
Short name T349
Test name
Test status
Simulation time 25383044 ps
CPU time 1.64 seconds
Started Jun 23 06:30:13 PM PDT 24
Finished Jun 23 06:30:15 PM PDT 24
Peak memory 237336 kb
Host smart-3d9e1b21-30b6-4ce4-b0d3-e50a05724db7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1695860422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1695860422
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2656188820
Short name T781
Test name
Test status
Simulation time 25506731 ps
CPU time 1.38 seconds
Started Jun 23 06:30:12 PM PDT 24
Finished Jun 23 06:30:14 PM PDT 24
Peak memory 237372 kb
Host smart-cc0911b6-364e-4748-9a77-1e4985981ea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2656188820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2656188820
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3386152676
Short name T234
Test name
Test status
Simulation time 9384754 ps
CPU time 1.51 seconds
Started Jun 23 06:30:12 PM PDT 24
Finished Jun 23 06:30:13 PM PDT 24
Peak memory 237372 kb
Host smart-e2184dc9-55ee-490f-a6cc-40546c989a16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3386152676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.3386152676
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.467745031
Short name T810
Test name
Test status
Simulation time 15173634 ps
CPU time 1.3 seconds
Started Jun 23 06:30:12 PM PDT 24
Finished Jun 23 06:30:14 PM PDT 24
Peak memory 237372 kb
Host smart-03e72333-6398-44c3-9bd8-d7eba621c774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=467745031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.467745031
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3334372000
Short name T742
Test name
Test status
Simulation time 11319030 ps
CPU time 1.33 seconds
Started Jun 23 06:30:17 PM PDT 24
Finished Jun 23 06:30:18 PM PDT 24
Peak memory 237372 kb
Host smart-ae36339f-d875-40b5-970b-5afe9dbc4a43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3334372000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3334372000
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3251601520
Short name T161
Test name
Test status
Simulation time 11442454 ps
CPU time 1.51 seconds
Started Jun 23 06:30:18 PM PDT 24
Finished Jun 23 06:30:20 PM PDT 24
Peak memory 237372 kb
Host smart-c2d5fa3e-759c-4611-aacb-faa8fde4e79d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3251601520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3251601520
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1766566568
Short name T743
Test name
Test status
Simulation time 7873691 ps
CPU time 1.36 seconds
Started Jun 23 06:30:18 PM PDT 24
Finished Jun 23 06:30:20 PM PDT 24
Peak memory 237372 kb
Host smart-00b3cdef-939b-43f7-b2b6-171c960fb049
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1766566568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1766566568
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.4044594957
Short name T719
Test name
Test status
Simulation time 7985401 ps
CPU time 1.5 seconds
Started Jun 23 06:30:17 PM PDT 24
Finished Jun 23 06:30:19 PM PDT 24
Peak memory 237360 kb
Host smart-32959443-06af-4068-9f90-b088d037918e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4044594957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.4044594957
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2233837708
Short name T359
Test name
Test status
Simulation time 611740548 ps
CPU time 74.86 seconds
Started Jun 23 06:29:22 PM PDT 24
Finished Jun 23 06:30:37 PM PDT 24
Peak memory 237272 kb
Host smart-46776c07-f9a1-4817-a0e7-3be1ee008178
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2233837708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2233837708
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.661871194
Short name T360
Test name
Test status
Simulation time 30046191658 ps
CPU time 435.05 seconds
Started Jun 23 06:29:21 PM PDT 24
Finished Jun 23 06:36:36 PM PDT 24
Peak memory 240776 kb
Host smart-a33503d1-3523-41d0-a0ce-118b035f5397
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=661871194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.661871194
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3444251799
Short name T826
Test name
Test status
Simulation time 130986005 ps
CPU time 5.51 seconds
Started Jun 23 06:29:23 PM PDT 24
Finished Jun 23 06:29:29 PM PDT 24
Peak memory 240700 kb
Host smart-205309c1-d9dc-4000-b97f-0a362701ac4b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3444251799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3444251799
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1045510093
Short name T240
Test name
Test status
Simulation time 80995693 ps
CPU time 5.96 seconds
Started Jun 23 06:29:21 PM PDT 24
Finished Jun 23 06:29:27 PM PDT 24
Peak memory 239700 kb
Host smart-3a6263c1-3e09-444e-bcc8-9aa09531551a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045510093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1045510093
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.316725560
Short name T800
Test name
Test status
Simulation time 231529648 ps
CPU time 5.6 seconds
Started Jun 23 06:29:23 PM PDT 24
Finished Jun 23 06:29:29 PM PDT 24
Peak memory 237292 kb
Host smart-fe57934d-5b6a-4648-afd8-24c5e2dab117
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=316725560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.316725560
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3179977214
Short name T804
Test name
Test status
Simulation time 18485020 ps
CPU time 1.46 seconds
Started Jun 23 06:29:22 PM PDT 24
Finished Jun 23 06:29:24 PM PDT 24
Peak memory 237356 kb
Host smart-f253313d-e5ee-4289-8a10-def6a1bcc2f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3179977214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3179977214
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2744265279
Short name T178
Test name
Test status
Simulation time 1303745203 ps
CPU time 19.27 seconds
Started Jun 23 06:29:22 PM PDT 24
Finished Jun 23 06:29:42 PM PDT 24
Peak memory 248992 kb
Host smart-284e7d4c-ac24-4eab-bb5a-29649dd88059
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2744265279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2744265279
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2121067927
Short name T154
Test name
Test status
Simulation time 20128580453 ps
CPU time 362.51 seconds
Started Jun 23 06:29:16 PM PDT 24
Finished Jun 23 06:35:19 PM PDT 24
Peak memory 266704 kb
Host smart-3d641926-8f80-48bd-b259-d62482c1c9da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2121067927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2121067927
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1971086395
Short name T816
Test name
Test status
Simulation time 24862114583 ps
CPU time 525.12 seconds
Started Jun 23 06:29:19 PM PDT 24
Finished Jun 23 06:38:04 PM PDT 24
Peak memory 265644 kb
Host smart-b4eef785-146d-494e-963a-8e82ac15d424
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971086395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1971086395
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3076567642
Short name T714
Test name
Test status
Simulation time 50422064 ps
CPU time 4.04 seconds
Started Jun 23 06:29:17 PM PDT 24
Finished Jun 23 06:29:22 PM PDT 24
Peak memory 249044 kb
Host smart-27c19106-9210-4b49-9ccc-242eed470cd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3076567642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3076567642
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2808496545
Short name T765
Test name
Test status
Simulation time 10078578 ps
CPU time 1.26 seconds
Started Jun 23 06:30:16 PM PDT 24
Finished Jun 23 06:30:18 PM PDT 24
Peak memory 237364 kb
Host smart-618271da-813c-44ea-a893-5bf665c67761
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2808496545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2808496545
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1687017139
Short name T718
Test name
Test status
Simulation time 10512404 ps
CPU time 1.34 seconds
Started Jun 23 06:30:16 PM PDT 24
Finished Jun 23 06:30:18 PM PDT 24
Peak memory 235384 kb
Host smart-beaa58fb-243a-4a0f-8503-e621988c5212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1687017139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1687017139
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2747604942
Short name T808
Test name
Test status
Simulation time 7492427 ps
CPU time 1.47 seconds
Started Jun 23 06:30:17 PM PDT 24
Finished Jun 23 06:30:20 PM PDT 24
Peak memory 237372 kb
Host smart-c726834a-917e-4708-9b41-7f66d98596b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2747604942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2747604942
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.526067637
Short name T762
Test name
Test status
Simulation time 25435445 ps
CPU time 1.46 seconds
Started Jun 23 06:30:19 PM PDT 24
Finished Jun 23 06:30:21 PM PDT 24
Peak memory 237376 kb
Host smart-5cae4e50-8d00-4470-afc8-1229d24c11fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=526067637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.526067637
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.77703993
Short name T793
Test name
Test status
Simulation time 10042436 ps
CPU time 1.26 seconds
Started Jun 23 06:30:17 PM PDT 24
Finished Jun 23 06:30:19 PM PDT 24
Peak memory 237344 kb
Host smart-ea8b55dc-b22a-4e26-8290-1cd342093c0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=77703993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.77703993
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3232135531
Short name T351
Test name
Test status
Simulation time 19372080 ps
CPU time 1.44 seconds
Started Jun 23 06:30:20 PM PDT 24
Finished Jun 23 06:30:22 PM PDT 24
Peak memory 237360 kb
Host smart-b5fc017e-c3b5-4108-b536-749552e9b2f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3232135531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3232135531
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.126744709
Short name T819
Test name
Test status
Simulation time 9194706 ps
CPU time 1.53 seconds
Started Jun 23 06:30:16 PM PDT 24
Finished Jun 23 06:30:18 PM PDT 24
Peak memory 237376 kb
Host smart-9fcb976a-e4a7-45a0-ab64-4db7067ecce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=126744709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.126744709
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1284242802
Short name T785
Test name
Test status
Simulation time 11942973 ps
CPU time 1.36 seconds
Started Jun 23 06:30:20 PM PDT 24
Finished Jun 23 06:30:22 PM PDT 24
Peak memory 236628 kb
Host smart-92c6dc5b-e691-4960-8a1c-caeb4937169c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1284242802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1284242802
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.270164891
Short name T740
Test name
Test status
Simulation time 7827008 ps
CPU time 1.32 seconds
Started Jun 23 06:30:16 PM PDT 24
Finished Jun 23 06:30:18 PM PDT 24
Peak memory 237376 kb
Host smart-ec4b6554-d301-49bc-83ab-a7ef32b98d36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=270164891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.270164891
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.292728673
Short name T774
Test name
Test status
Simulation time 23163790 ps
CPU time 1.41 seconds
Started Jun 23 06:30:17 PM PDT 24
Finished Jun 23 06:30:19 PM PDT 24
Peak memory 236312 kb
Host smart-153cc1f7-bb64-49e4-9907-7faef8792c5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=292728673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.292728673
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2568981156
Short name T187
Test name
Test status
Simulation time 1202828797 ps
CPU time 169.78 seconds
Started Jun 23 06:29:26 PM PDT 24
Finished Jun 23 06:32:17 PM PDT 24
Peak memory 240716 kb
Host smart-675fb144-01bd-468c-b18d-a96dbc79181c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2568981156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2568981156
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3903313708
Short name T763
Test name
Test status
Simulation time 3270055673 ps
CPU time 117.05 seconds
Started Jun 23 06:29:26 PM PDT 24
Finished Jun 23 06:31:23 PM PDT 24
Peak memory 237356 kb
Host smart-3a6fd520-4f99-457b-be6a-eede7fcf946e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3903313708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3903313708
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.280171185
Short name T746
Test name
Test status
Simulation time 144463754 ps
CPU time 5.82 seconds
Started Jun 23 06:29:23 PM PDT 24
Finished Jun 23 06:29:29 PM PDT 24
Peak memory 240716 kb
Host smart-6c82affb-73fc-44d0-851d-813ac4b6c085
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=280171185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.280171185
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.907688646
Short name T802
Test name
Test status
Simulation time 113884427 ps
CPU time 8.96 seconds
Started Jun 23 06:29:27 PM PDT 24
Finished Jun 23 06:29:36 PM PDT 24
Peak memory 257024 kb
Host smart-279003dc-1200-45bd-baa7-ab5899d62021
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907688646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.907688646
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3713081180
Short name T722
Test name
Test status
Simulation time 88833356 ps
CPU time 4.91 seconds
Started Jun 23 06:29:25 PM PDT 24
Finished Jun 23 06:29:30 PM PDT 24
Peak memory 237248 kb
Host smart-d13dded6-f14a-4eb2-8e46-f39fd887d3dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3713081180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3713081180
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.258265446
Short name T741
Test name
Test status
Simulation time 19155800 ps
CPU time 1.45 seconds
Started Jun 23 06:29:22 PM PDT 24
Finished Jun 23 06:29:24 PM PDT 24
Peak memory 236396 kb
Host smart-8d087aac-8df2-44f2-b83e-db43ac769e6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=258265446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.258265446
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.471921693
Short name T773
Test name
Test status
Simulation time 2743488542 ps
CPU time 50.78 seconds
Started Jun 23 06:29:27 PM PDT 24
Finished Jun 23 06:30:18 PM PDT 24
Peak memory 245592 kb
Host smart-4e4382fa-bdde-4ee2-9873-4ab2aaf4b742
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=471921693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.471921693
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1237395792
Short name T362
Test name
Test status
Simulation time 3098318255 ps
CPU time 347.34 seconds
Started Jun 23 06:29:23 PM PDT 24
Finished Jun 23 06:35:11 PM PDT 24
Peak memory 265708 kb
Host smart-b03ee05d-9f5e-4390-83be-94d83e389359
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237395792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1237395792
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2445587230
Short name T744
Test name
Test status
Simulation time 90300698 ps
CPU time 6.51 seconds
Started Jun 23 06:29:23 PM PDT 24
Finished Jun 23 06:29:30 PM PDT 24
Peak memory 249044 kb
Host smart-62fd5848-d392-45db-bf4e-65db348690c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2445587230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2445587230
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3333737812
Short name T753
Test name
Test status
Simulation time 19274760 ps
CPU time 1.37 seconds
Started Jun 23 06:30:17 PM PDT 24
Finished Jun 23 06:30:19 PM PDT 24
Peak memory 237372 kb
Host smart-647d3f1d-3bb2-4614-b1f3-4f3b53979f04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3333737812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3333737812
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2009766609
Short name T352
Test name
Test status
Simulation time 31390205 ps
CPU time 1.4 seconds
Started Jun 23 06:30:18 PM PDT 24
Finished Jun 23 06:30:20 PM PDT 24
Peak memory 236416 kb
Host smart-566e4479-d474-4714-8446-c849f197931d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2009766609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2009766609
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.545336533
Short name T724
Test name
Test status
Simulation time 20171408 ps
CPU time 1.56 seconds
Started Jun 23 06:30:36 PM PDT 24
Finished Jun 23 06:30:38 PM PDT 24
Peak memory 236436 kb
Host smart-79071d89-cb5d-47af-83e9-2c797ab58ab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=545336533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.545336533
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1091566366
Short name T347
Test name
Test status
Simulation time 9244297 ps
CPU time 1.5 seconds
Started Jun 23 06:30:22 PM PDT 24
Finished Jun 23 06:30:24 PM PDT 24
Peak memory 237364 kb
Host smart-30b74a8a-593f-4ae1-9dc8-b455f483f6b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1091566366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1091566366
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2144999850
Short name T735
Test name
Test status
Simulation time 27157045 ps
CPU time 1.34 seconds
Started Jun 23 06:30:21 PM PDT 24
Finished Jun 23 06:30:23 PM PDT 24
Peak memory 237376 kb
Host smart-01a4fc61-e778-461a-9a2f-a828766fb7ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2144999850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2144999850
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1987534476
Short name T726
Test name
Test status
Simulation time 11226303 ps
CPU time 1.67 seconds
Started Jun 23 06:30:21 PM PDT 24
Finished Jun 23 06:30:24 PM PDT 24
Peak memory 236424 kb
Host smart-483e031e-68db-4a5f-9ff5-29aac7248cfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1987534476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1987534476
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2870913283
Short name T811
Test name
Test status
Simulation time 7562620 ps
CPU time 1.47 seconds
Started Jun 23 06:30:22 PM PDT 24
Finished Jun 23 06:30:24 PM PDT 24
Peak memory 236444 kb
Host smart-66260ba3-378f-4d32-ad16-502e5553b0d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2870913283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2870913283
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3794604162
Short name T783
Test name
Test status
Simulation time 48655374 ps
CPU time 1.38 seconds
Started Jun 23 06:30:22 PM PDT 24
Finished Jun 23 06:30:24 PM PDT 24
Peak memory 236276 kb
Host smart-de0e2f74-e4e7-4751-a0e6-ad820b35b1b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3794604162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3794604162
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3555939335
Short name T717
Test name
Test status
Simulation time 8947482 ps
CPU time 1.53 seconds
Started Jun 23 06:30:22 PM PDT 24
Finished Jun 23 06:30:24 PM PDT 24
Peak memory 237552 kb
Host smart-cc23640d-1082-47dd-9c03-e3359315a20c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3555939335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3555939335
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2350833253
Short name T791
Test name
Test status
Simulation time 9706628 ps
CPU time 1.51 seconds
Started Jun 23 06:30:21 PM PDT 24
Finished Jun 23 06:30:23 PM PDT 24
Peak memory 236376 kb
Host smart-873d4a6d-3b19-4cdd-80f0-cc4f705c6874
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2350833253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2350833253
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3964641585
Short name T803
Test name
Test status
Simulation time 111632467 ps
CPU time 5.33 seconds
Started Jun 23 06:29:32 PM PDT 24
Finished Jun 23 06:29:37 PM PDT 24
Peak memory 241456 kb
Host smart-301b34f0-229a-4892-b8fc-f4875a404a6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964641585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3964641585
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3388883402
Short name T190
Test name
Test status
Simulation time 117798413 ps
CPU time 5.32 seconds
Started Jun 23 06:29:27 PM PDT 24
Finished Jun 23 06:29:33 PM PDT 24
Peak memory 237288 kb
Host smart-1648910d-f33b-4b66-82cc-c59c6181fdbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3388883402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3388883402
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3193413550
Short name T829
Test name
Test status
Simulation time 9273744 ps
CPU time 1.25 seconds
Started Jun 23 06:29:26 PM PDT 24
Finished Jun 23 06:29:27 PM PDT 24
Peak memory 235396 kb
Host smart-444d24df-fa85-4762-af5e-fe66df4bda30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3193413550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3193413550
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3394718856
Short name T733
Test name
Test status
Simulation time 499483949 ps
CPU time 21.83 seconds
Started Jun 23 06:29:28 PM PDT 24
Finished Jun 23 06:29:50 PM PDT 24
Peak memory 245568 kb
Host smart-c5262f1a-4a8c-417a-b0a4-2ee31a58a4cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3394718856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3394718856
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2094249423
Short name T136
Test name
Test status
Simulation time 3333562367 ps
CPU time 103.53 seconds
Started Jun 23 06:29:26 PM PDT 24
Finished Jun 23 06:31:09 PM PDT 24
Peak memory 257492 kb
Host smart-5526786b-a132-4e13-9150-16a7f4d55df8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2094249423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2094249423
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2894570566
Short name T133
Test name
Test status
Simulation time 2565907344 ps
CPU time 292.16 seconds
Started Jun 23 06:29:28 PM PDT 24
Finished Jun 23 06:34:20 PM PDT 24
Peak memory 265840 kb
Host smart-36c98239-5367-4e2e-8b8b-2f4507845ccd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894570566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.2894570566
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1818758377
Short name T827
Test name
Test status
Simulation time 50616888 ps
CPU time 6.8 seconds
Started Jun 23 06:29:27 PM PDT 24
Finished Jun 23 06:29:34 PM PDT 24
Peak memory 249040 kb
Host smart-20812195-b8b7-4c00-8080-27bdfb3b4750
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1818758377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1818758377
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2561178376
Short name T754
Test name
Test status
Simulation time 649982814 ps
CPU time 10.55 seconds
Started Jun 23 06:29:33 PM PDT 24
Finished Jun 23 06:29:44 PM PDT 24
Peak memory 251072 kb
Host smart-428b0253-953c-4286-9e89-5640cd58087e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561178376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2561178376
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.883363007
Short name T769
Test name
Test status
Simulation time 190177112 ps
CPU time 5.38 seconds
Started Jun 23 06:29:32 PM PDT 24
Finished Jun 23 06:29:38 PM PDT 24
Peak memory 240704 kb
Host smart-f53961d8-ab55-4702-a74d-024af075a6fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=883363007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.883363007
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3152789773
Short name T790
Test name
Test status
Simulation time 7709504 ps
CPU time 1.56 seconds
Started Jun 23 06:29:32 PM PDT 24
Finished Jun 23 06:29:33 PM PDT 24
Peak memory 235388 kb
Host smart-6dad2494-565c-4efd-847b-d072a2ae151d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3152789773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3152789773
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2083773188
Short name T776
Test name
Test status
Simulation time 287755435 ps
CPU time 18.36 seconds
Started Jun 23 06:29:31 PM PDT 24
Finished Jun 23 06:29:50 PM PDT 24
Peak memory 244636 kb
Host smart-8ac86b55-d6de-4ef1-ad06-c83cd8af6d99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2083773188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2083773188
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1929811847
Short name T156
Test name
Test status
Simulation time 3143187426 ps
CPU time 90.16 seconds
Started Jun 23 06:29:31 PM PDT 24
Finished Jun 23 06:31:02 PM PDT 24
Peak memory 257504 kb
Host smart-41d0bd72-22c4-4c0d-a3d4-df635e5e5c75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1929811847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1929811847
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3990313820
Short name T813
Test name
Test status
Simulation time 54830637 ps
CPU time 7.21 seconds
Started Jun 23 06:29:32 PM PDT 24
Finished Jun 23 06:29:39 PM PDT 24
Peak memory 249044 kb
Host smart-e3bb8c4e-2298-41e4-b685-0d9db82bc73e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3990313820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3990313820
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3324653731
Short name T796
Test name
Test status
Simulation time 1023274653 ps
CPU time 5.31 seconds
Started Jun 23 06:29:36 PM PDT 24
Finished Jun 23 06:29:42 PM PDT 24
Peak memory 240828 kb
Host smart-7bc1ebac-2af2-4449-9cf7-655121a2b5c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324653731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3324653731
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1021452946
Short name T825
Test name
Test status
Simulation time 475574493 ps
CPU time 5.6 seconds
Started Jun 23 06:29:37 PM PDT 24
Finished Jun 23 06:29:43 PM PDT 24
Peak memory 237468 kb
Host smart-4e863ac6-be5a-41c0-a63b-023f78d86046
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1021452946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1021452946
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1096022010
Short name T751
Test name
Test status
Simulation time 442078612 ps
CPU time 21.17 seconds
Started Jun 23 06:29:36 PM PDT 24
Finished Jun 23 06:29:58 PM PDT 24
Peak memory 244648 kb
Host smart-d44353c3-d3f4-4cad-93a1-bb0aba030221
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1096022010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1096022010
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.370716854
Short name T141
Test name
Test status
Simulation time 16760541159 ps
CPU time 582.84 seconds
Started Jun 23 06:29:34 PM PDT 24
Finished Jun 23 06:39:17 PM PDT 24
Peak memory 265644 kb
Host smart-e4f04760-de00-4266-be1d-88ba7947c5cc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370716854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.370716854
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3151133541
Short name T766
Test name
Test status
Simulation time 101899500 ps
CPU time 14.53 seconds
Started Jun 23 06:29:32 PM PDT 24
Finished Jun 23 06:29:47 PM PDT 24
Peak memory 248828 kb
Host smart-1e6c41ab-81b3-4aa6-9625-c52a36fdabf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3151133541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3151133541
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3812498024
Short name T180
Test name
Test status
Simulation time 155384276 ps
CPU time 18.38 seconds
Started Jun 23 06:29:30 PM PDT 24
Finished Jun 23 06:29:49 PM PDT 24
Peak memory 237536 kb
Host smart-01ddb8f3-1f0d-468e-b4c3-803008d293c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3812498024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3812498024
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2855486706
Short name T357
Test name
Test status
Simulation time 109714851 ps
CPU time 4.97 seconds
Started Jun 23 06:29:38 PM PDT 24
Finished Jun 23 06:29:44 PM PDT 24
Peak memory 242016 kb
Host smart-3d71be1c-151b-4d13-89c5-61256f3b0595
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855486706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2855486706
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1334020326
Short name T764
Test name
Test status
Simulation time 766818087 ps
CPU time 4.81 seconds
Started Jun 23 06:29:35 PM PDT 24
Finished Jun 23 06:29:40 PM PDT 24
Peak memory 239240 kb
Host smart-1718594f-0a75-4433-a4df-0992b822d918
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1334020326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1334020326
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2714741301
Short name T799
Test name
Test status
Simulation time 46027191 ps
CPU time 1.51 seconds
Started Jun 23 06:29:38 PM PDT 24
Finished Jun 23 06:29:40 PM PDT 24
Peak memory 237228 kb
Host smart-52371ac4-cf42-4048-9ec2-890ae8095b27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2714741301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2714741301
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.253934671
Short name T792
Test name
Test status
Simulation time 1089766550 ps
CPU time 24.69 seconds
Started Jun 23 06:29:38 PM PDT 24
Finished Jun 23 06:30:03 PM PDT 24
Peak memory 245548 kb
Host smart-2f3e2f27-c34d-4721-9870-05b6d90403d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=253934671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.253934671
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.4197251443
Short name T151
Test name
Test status
Simulation time 17942717575 ps
CPU time 294.29 seconds
Started Jun 23 06:29:36 PM PDT 24
Finished Jun 23 06:34:31 PM PDT 24
Peak memory 273604 kb
Host smart-d1fccce4-ce97-4d12-b0ce-47c4da5f0ea0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4197251443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.4197251443
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1371227102
Short name T755
Test name
Test status
Simulation time 253027520 ps
CPU time 4.35 seconds
Started Jun 23 06:29:37 PM PDT 24
Finished Jun 23 06:29:42 PM PDT 24
Peak memory 247740 kb
Host smart-45235679-673a-4518-936e-31e4306564a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1371227102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1371227102
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2131116023
Short name T824
Test name
Test status
Simulation time 63096545 ps
CPU time 5.81 seconds
Started Jun 23 06:29:47 PM PDT 24
Finished Jun 23 06:29:53 PM PDT 24
Peak memory 237400 kb
Host smart-8ac41574-a11d-43a3-b3c6-a28a077aa730
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131116023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2131116023
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.710739492
Short name T739
Test name
Test status
Simulation time 518812400 ps
CPU time 10.79 seconds
Started Jun 23 06:29:42 PM PDT 24
Finished Jun 23 06:29:53 PM PDT 24
Peak memory 237268 kb
Host smart-676bad75-a2b7-46d4-a5a9-8295b9957efd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=710739492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.710739492
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1740620052
Short name T768
Test name
Test status
Simulation time 9691561 ps
CPU time 1.62 seconds
Started Jun 23 06:29:43 PM PDT 24
Finished Jun 23 06:29:45 PM PDT 24
Peak memory 236436 kb
Host smart-4bacf67a-2eed-416d-8555-e6c1597e0dad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1740620052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1740620052
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3800328822
Short name T188
Test name
Test status
Simulation time 514077072 ps
CPU time 19.97 seconds
Started Jun 23 06:29:42 PM PDT 24
Finished Jun 23 06:30:02 PM PDT 24
Peak memory 249024 kb
Host smart-023e6e74-bb0a-4c8e-a5c6-7dc87f78a71f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3800328822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.3800328822
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3478750307
Short name T148
Test name
Test status
Simulation time 2455344864 ps
CPU time 158.66 seconds
Started Jun 23 06:29:37 PM PDT 24
Finished Jun 23 06:32:16 PM PDT 24
Peak memory 257492 kb
Host smart-5d83390e-7eee-4791-a602-6037a6d6a93e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3478750307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3478750307
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1427844211
Short name T146
Test name
Test status
Simulation time 6776917194 ps
CPU time 501.88 seconds
Started Jun 23 06:29:38 PM PDT 24
Finished Jun 23 06:38:00 PM PDT 24
Peak memory 269536 kb
Host smart-3439ead6-2654-438c-b543-3d39f8fd8f68
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427844211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1427844211
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3906882997
Short name T715
Test name
Test status
Simulation time 348924819 ps
CPU time 10.89 seconds
Started Jun 23 06:29:36 PM PDT 24
Finished Jun 23 06:29:48 PM PDT 24
Peak memory 249044 kb
Host smart-08ab1497-5679-4033-ad7a-bc54fb914a18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3906882997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3906882997
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2192625861
Short name T245
Test name
Test status
Simulation time 39720194 ps
CPU time 3.39 seconds
Started Jun 23 06:29:41 PM PDT 24
Finished Jun 23 06:29:44 PM PDT 24
Peak memory 237464 kb
Host smart-bb7a4f94-de9f-4320-948f-4c7c0c13dc95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2192625861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2192625861
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1650407823
Short name T26
Test name
Test status
Simulation time 130429104522 ps
CPU time 2156.19 seconds
Started Jun 23 06:41:07 PM PDT 24
Finished Jun 23 07:17:04 PM PDT 24
Peak memory 285976 kb
Host smart-7ad1823e-e0b9-4368-8106-27626e64678d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650407823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1650407823
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1626544470
Short name T399
Test name
Test status
Simulation time 203887771 ps
CPU time 10.29 seconds
Started Jun 23 06:41:10 PM PDT 24
Finished Jun 23 06:41:21 PM PDT 24
Peak memory 249108 kb
Host smart-8815ac6f-81c6-4e2a-a9de-4a8d93877f9c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1626544470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1626544470
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1017169219
Short name T243
Test name
Test status
Simulation time 3752536701 ps
CPU time 204.39 seconds
Started Jun 23 06:41:07 PM PDT 24
Finished Jun 23 06:44:32 PM PDT 24
Peak memory 257348 kb
Host smart-e121195c-e5fa-4906-b4b5-e3d93e4a5cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10171
69219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1017169219
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2111746027
Short name T672
Test name
Test status
Simulation time 1356126528 ps
CPU time 20.91 seconds
Started Jun 23 06:41:19 PM PDT 24
Finished Jun 23 06:41:41 PM PDT 24
Peak memory 247724 kb
Host smart-c56b9748-4d9a-407a-8305-797c90b6fe0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21117
46027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2111746027
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3649933351
Short name T94
Test name
Test status
Simulation time 35422650864 ps
CPU time 1838.12 seconds
Started Jun 23 06:41:11 PM PDT 24
Finished Jun 23 07:11:50 PM PDT 24
Peak memory 273204 kb
Host smart-1b80bf7f-dd4f-464b-951c-46bef656765c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649933351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3649933351
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1144280010
Short name T622
Test name
Test status
Simulation time 12740212410 ps
CPU time 125.35 seconds
Started Jun 23 06:41:15 PM PDT 24
Finished Jun 23 06:43:21 PM PDT 24
Peak memory 248716 kb
Host smart-493178be-a264-4200-9cd7-83dd7937bf45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144280010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1144280010
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.298821174
Short name T556
Test name
Test status
Simulation time 3185839267 ps
CPU time 49.05 seconds
Started Jun 23 06:41:03 PM PDT 24
Finished Jun 23 06:41:53 PM PDT 24
Peak memory 256692 kb
Host smart-9f766d4d-5dbe-46d9-af75-2bab217acd54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29882
1174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.298821174
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3305269960
Short name T507
Test name
Test status
Simulation time 348615998 ps
CPU time 20.27 seconds
Started Jun 23 06:41:01 PM PDT 24
Finished Jun 23 06:41:22 PM PDT 24
Peak memory 249060 kb
Host smart-7b6d28c5-bf34-4aca-a634-57555d282a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33052
69960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3305269960
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2096344232
Short name T605
Test name
Test status
Simulation time 8808922900 ps
CPU time 64.77 seconds
Started Jun 23 06:41:03 PM PDT 24
Finished Jun 23 06:42:08 PM PDT 24
Peak memory 256144 kb
Host smart-db1f3653-36bb-4d4e-ad6c-0267972d926c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20963
44232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2096344232
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3484319818
Short name T475
Test name
Test status
Simulation time 1346610391 ps
CPU time 75.08 seconds
Started Jun 23 06:41:08 PM PDT 24
Finished Jun 23 06:42:24 PM PDT 24
Peak memory 256976 kb
Host smart-2ec4d452-0280-41be-96b0-516ac86bb7ec
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484319818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3484319818
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3296229112
Short name T462
Test name
Test status
Simulation time 31196900755 ps
CPU time 1914.67 seconds
Started Jun 23 06:41:17 PM PDT 24
Finished Jun 23 07:13:12 PM PDT 24
Peak memory 285528 kb
Host smart-7815b77b-93d7-4912-9d3f-d9014ecf3083
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296229112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3296229112
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2025581314
Short name T466
Test name
Test status
Simulation time 17914341460 ps
CPU time 240.16 seconds
Started Jun 23 06:41:06 PM PDT 24
Finished Jun 23 06:45:07 PM PDT 24
Peak memory 257372 kb
Host smart-77ec537f-d94b-45b3-ac63-57bf9c53278e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20255
81314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2025581314
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1285679675
Short name T519
Test name
Test status
Simulation time 1023364800 ps
CPU time 31.84 seconds
Started Jun 23 06:41:08 PM PDT 24
Finished Jun 23 06:41:40 PM PDT 24
Peak memory 257288 kb
Host smart-c5479847-fce2-4429-9ece-8cfcf56bafea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12856
79675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1285679675
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3125753259
Short name T291
Test name
Test status
Simulation time 397086073457 ps
CPU time 3176.66 seconds
Started Jun 23 06:41:13 PM PDT 24
Finished Jun 23 07:34:11 PM PDT 24
Peak memory 289560 kb
Host smart-5f929231-6fe4-4836-90bd-672e6599caa5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125753259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3125753259
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2964596875
Short name T93
Test name
Test status
Simulation time 211128233108 ps
CPU time 1237.72 seconds
Started Jun 23 06:41:13 PM PDT 24
Finished Jun 23 07:01:51 PM PDT 24
Peak memory 273764 kb
Host smart-92708f40-d66f-43bd-9405-15ff4485f1be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964596875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2964596875
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.4284232096
Short name T320
Test name
Test status
Simulation time 5593397034 ps
CPU time 235.35 seconds
Started Jun 23 06:41:19 PM PDT 24
Finished Jun 23 06:45:16 PM PDT 24
Peak memory 248692 kb
Host smart-bfdade87-da7f-4a4d-868a-4a653cbce4ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284232096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.4284232096
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1260743783
Short name T422
Test name
Test status
Simulation time 153398764 ps
CPU time 3.53 seconds
Started Jun 23 06:41:04 PM PDT 24
Finished Jun 23 06:41:08 PM PDT 24
Peak memory 240932 kb
Host smart-559ac8d4-4cbf-493b-88b4-99ac6c26f927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12607
43783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1260743783
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.4168828915
Short name T184
Test name
Test status
Simulation time 421316585 ps
CPU time 13.68 seconds
Started Jun 23 06:41:07 PM PDT 24
Finished Jun 23 06:41:21 PM PDT 24
Peak memory 254592 kb
Host smart-06308af2-7a48-48b8-a47d-f60f6877b81a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41688
28915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.4168828915
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3074101388
Short name T11
Test name
Test status
Simulation time 306498331 ps
CPU time 12.77 seconds
Started Jun 23 06:41:16 PM PDT 24
Finished Jun 23 06:41:30 PM PDT 24
Peak memory 278176 kb
Host smart-530f59c1-89fe-4455-b142-4c4068ce4828
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3074101388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3074101388
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2725753002
Short name T394
Test name
Test status
Simulation time 275524754 ps
CPU time 18.83 seconds
Started Jun 23 06:41:20 PM PDT 24
Finished Jun 23 06:41:40 PM PDT 24
Peak memory 256896 kb
Host smart-c856b159-85c7-46a7-b03c-d3062d4ed970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27257
53002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2725753002
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.4135790082
Short name T396
Test name
Test status
Simulation time 744494642 ps
CPU time 37.34 seconds
Started Jun 23 06:41:06 PM PDT 24
Finished Jun 23 06:41:43 PM PDT 24
Peak memory 257284 kb
Host smart-3916a7f9-a427-4595-8c1e-be6384f35d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41357
90082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.4135790082
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3863889942
Short name T102
Test name
Test status
Simulation time 228164927478 ps
CPU time 3095.87 seconds
Started Jun 23 06:41:13 PM PDT 24
Finished Jun 23 07:32:49 PM PDT 24
Peak memory 290128 kb
Host smart-4a7c6ac4-9fa0-4f5b-8484-cc7085f21856
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863889942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3863889942
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.1044015580
Short name T207
Test name
Test status
Simulation time 238364119 ps
CPU time 3.77 seconds
Started Jun 23 06:41:44 PM PDT 24
Finished Jun 23 06:41:48 PM PDT 24
Peak memory 249236 kb
Host smart-0af4cbf0-ba66-47ae-9939-0bd2bec95d2c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1044015580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1044015580
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3250925003
Short name T691
Test name
Test status
Simulation time 144349132351 ps
CPU time 2102.56 seconds
Started Jun 23 06:41:44 PM PDT 24
Finished Jun 23 07:16:47 PM PDT 24
Peak memory 287120 kb
Host smart-b4a1d58e-f67e-4bca-98a0-dd7289022e9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250925003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3250925003
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2819814333
Short name T489
Test name
Test status
Simulation time 322746497 ps
CPU time 16.36 seconds
Started Jun 23 06:41:40 PM PDT 24
Finished Jun 23 06:41:57 PM PDT 24
Peak memory 240932 kb
Host smart-0ec3ab60-8ca7-4c6c-b3d8-746b0dfc5365
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2819814333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2819814333
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.170860279
Short name T439
Test name
Test status
Simulation time 1526502522 ps
CPU time 63.48 seconds
Started Jun 23 06:41:41 PM PDT 24
Finished Jun 23 06:42:44 PM PDT 24
Peak memory 256368 kb
Host smart-bb4cee64-7aaf-454d-a373-8b8192c00929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17086
0279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.170860279
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2563013322
Short name T60
Test name
Test status
Simulation time 9376768632 ps
CPU time 44.09 seconds
Started Jun 23 06:41:40 PM PDT 24
Finished Jun 23 06:42:25 PM PDT 24
Peak memory 256652 kb
Host smart-3a0b2d34-1908-4546-8c91-6ee2dcc2ab7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25630
13322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2563013322
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.3975886999
Short name T346
Test name
Test status
Simulation time 11876498321 ps
CPU time 1072.71 seconds
Started Jun 23 06:41:41 PM PDT 24
Finished Jun 23 06:59:34 PM PDT 24
Peak memory 284400 kb
Host smart-0fdd0dac-6c9e-4579-b5bc-bc5f525bd986
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975886999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3975886999
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.532530873
Short name T649
Test name
Test status
Simulation time 485006114713 ps
CPU time 2455.41 seconds
Started Jun 23 06:41:39 PM PDT 24
Finished Jun 23 07:22:35 PM PDT 24
Peak memory 283200 kb
Host smart-b83f5f50-defb-4386-9e21-1662d9338e5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532530873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.532530873
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1053961129
Short name T677
Test name
Test status
Simulation time 1089409642 ps
CPU time 47.85 seconds
Started Jun 23 06:41:40 PM PDT 24
Finished Jun 23 06:42:28 PM PDT 24
Peak memory 248628 kb
Host smart-c596ddc0-de65-45fd-8a42-eb3fb3f43b7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053961129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1053961129
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3052217938
Short name T253
Test name
Test status
Simulation time 121187424 ps
CPU time 12.95 seconds
Started Jun 23 06:41:35 PM PDT 24
Finished Jun 23 06:41:49 PM PDT 24
Peak memory 256260 kb
Host smart-ae2ff4ed-cb8d-4165-b689-f0bcb0ade494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30522
17938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3052217938
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3969957075
Short name T518
Test name
Test status
Simulation time 115593254 ps
CPU time 5.08 seconds
Started Jun 23 06:41:39 PM PDT 24
Finished Jun 23 06:41:45 PM PDT 24
Peak memory 240860 kb
Host smart-c1666418-3b80-43df-af79-045757dd063f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39699
57075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3969957075
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2486932050
Short name T82
Test name
Test status
Simulation time 1855572816 ps
CPU time 19.3 seconds
Started Jun 23 06:41:36 PM PDT 24
Finished Jun 23 06:41:56 PM PDT 24
Peak memory 255452 kb
Host smart-6dd42425-e9b3-438a-bb40-9068f357cffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24869
32050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2486932050
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1282525032
Short name T625
Test name
Test status
Simulation time 13967665172 ps
CPU time 947.81 seconds
Started Jun 23 06:41:39 PM PDT 24
Finished Jun 23 06:57:27 PM PDT 24
Peak memory 286172 kb
Host smart-37b551db-ef0d-4873-b216-4b4b2995a7ca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282525032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1282525032
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.2222380086
Short name T239
Test name
Test status
Simulation time 126007366244 ps
CPU time 2007.48 seconds
Started Jun 23 06:41:39 PM PDT 24
Finished Jun 23 07:15:07 PM PDT 24
Peak memory 284020 kb
Host smart-3f06805b-9d86-488a-916a-0aef892b61ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222380086 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.2222380086
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3292094183
Short name T636
Test name
Test status
Simulation time 117435427200 ps
CPU time 1686.81 seconds
Started Jun 23 06:41:40 PM PDT 24
Finished Jun 23 07:09:47 PM PDT 24
Peak memory 272928 kb
Host smart-fc94eefd-b06f-4998-9dfa-b7a3876b71bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292094183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3292094183
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2180217909
Short name T546
Test name
Test status
Simulation time 659134901 ps
CPU time 17.39 seconds
Started Jun 23 06:41:52 PM PDT 24
Finished Jun 23 06:42:09 PM PDT 24
Peak memory 249048 kb
Host smart-0311dff7-69bd-4260-8b69-41849c9331f7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2180217909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2180217909
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2500741420
Short name T390
Test name
Test status
Simulation time 5887173621 ps
CPU time 126.66 seconds
Started Jun 23 06:41:44 PM PDT 24
Finished Jun 23 06:43:51 PM PDT 24
Peak memory 257348 kb
Host smart-753b5462-558a-42ab-900d-2afabdb88c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25007
41420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2500741420
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2556029690
Short name T627
Test name
Test status
Simulation time 1287728114 ps
CPU time 33.49 seconds
Started Jun 23 06:41:39 PM PDT 24
Finished Jun 23 06:42:13 PM PDT 24
Peak memory 255908 kb
Host smart-430bf271-2d8e-4cd4-95a9-d4da381fe988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25560
29690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2556029690
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2357398174
Short name T336
Test name
Test status
Simulation time 8237622371 ps
CPU time 671.84 seconds
Started Jun 23 06:41:50 PM PDT 24
Finished Jun 23 06:53:03 PM PDT 24
Peak memory 265620 kb
Host smart-edf21f60-b39e-4fb1-91cb-0b5cabd7f912
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357398174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2357398174
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2398510886
Short name T27
Test name
Test status
Simulation time 51547415317 ps
CPU time 1484.61 seconds
Started Jun 23 06:41:44 PM PDT 24
Finished Jun 23 07:06:29 PM PDT 24
Peak memory 265592 kb
Host smart-6f4281a9-cb3a-4366-8921-dc4713fb0c77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398510886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2398510886
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2888188610
Short name T317
Test name
Test status
Simulation time 27759419127 ps
CPU time 220.71 seconds
Started Jun 23 06:41:41 PM PDT 24
Finished Jun 23 06:45:22 PM PDT 24
Peak memory 248820 kb
Host smart-de59eb20-90a1-499c-b6d8-fee29ae53d8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888188610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2888188610
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3861037491
Short name T580
Test name
Test status
Simulation time 538058135 ps
CPU time 34.69 seconds
Started Jun 23 06:41:40 PM PDT 24
Finished Jun 23 06:42:15 PM PDT 24
Peak memory 256368 kb
Host smart-e1179c99-35c7-4df0-9066-aaf933ab150e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38610
37491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3861037491
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2953098806
Short name T49
Test name
Test status
Simulation time 5049206091 ps
CPU time 69.5 seconds
Started Jun 23 06:41:44 PM PDT 24
Finished Jun 23 06:42:54 PM PDT 24
Peak memory 257276 kb
Host smart-ece7e979-cfa6-4f7d-b025-bc80157b8453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29530
98806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2953098806
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2864418430
Short name T603
Test name
Test status
Simulation time 424241080 ps
CPU time 11.66 seconds
Started Jun 23 06:41:44 PM PDT 24
Finished Jun 23 06:41:56 PM PDT 24
Peak memory 249052 kb
Host smart-185586ba-3e7d-40cf-88b0-9332215999e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28644
18430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2864418430
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3119760802
Short name T2
Test name
Test status
Simulation time 290991640 ps
CPU time 17 seconds
Started Jun 23 06:41:41 PM PDT 24
Finished Jun 23 06:41:58 PM PDT 24
Peak memory 249108 kb
Host smart-3968f622-09a3-4423-9b48-5a30ef8d2eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31197
60802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3119760802
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1817402991
Short name T584
Test name
Test status
Simulation time 100440534824 ps
CPU time 3017.7 seconds
Started Jun 23 06:41:43 PM PDT 24
Finished Jun 23 07:32:01 PM PDT 24
Peak memory 289740 kb
Host smart-8a6353ce-0155-44b6-a865-42ae0829fef2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817402991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1817402991
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2954972262
Short name T198
Test name
Test status
Simulation time 33928372 ps
CPU time 3.36 seconds
Started Jun 23 06:41:48 PM PDT 24
Finished Jun 23 06:41:52 PM PDT 24
Peak memory 249288 kb
Host smart-5685d9bd-7fcf-4229-af2d-f3e439e6e424
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2954972262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2954972262
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3653154649
Short name T631
Test name
Test status
Simulation time 37068940957 ps
CPU time 2412.68 seconds
Started Jun 23 06:41:49 PM PDT 24
Finished Jun 23 07:22:02 PM PDT 24
Peak memory 289692 kb
Host smart-a87239a8-1f51-4ac6-8029-4d5cee038607
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653154649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3653154649
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2641491321
Short name T411
Test name
Test status
Simulation time 808006978 ps
CPU time 11.11 seconds
Started Jun 23 06:41:54 PM PDT 24
Finished Jun 23 06:42:06 PM PDT 24
Peak memory 240856 kb
Host smart-25871967-595e-400c-bd5a-1de2dacbb3b8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2641491321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2641491321
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3352996681
Short name T551
Test name
Test status
Simulation time 19926726877 ps
CPU time 290.16 seconds
Started Jun 23 06:41:55 PM PDT 24
Finished Jun 23 06:46:46 PM PDT 24
Peak memory 250584 kb
Host smart-bebb33bf-54b5-4aef-88a3-f89bde11b782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33529
96681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3352996681
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.839996093
Short name T232
Test name
Test status
Simulation time 186499164 ps
CPU time 21.17 seconds
Started Jun 23 06:41:55 PM PDT 24
Finished Jun 23 06:42:17 PM PDT 24
Peak memory 254144 kb
Host smart-b7712270-93ae-431a-8c1b-07303fcfc4d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83999
6093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.839996093
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.4214025355
Short name T369
Test name
Test status
Simulation time 26186330585 ps
CPU time 1707.34 seconds
Started Jun 23 06:41:48 PM PDT 24
Finished Jun 23 07:10:16 PM PDT 24
Peak memory 273404 kb
Host smart-9b797218-3b48-4a51-907f-e7ac72b6dc29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214025355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.4214025355
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3912026315
Short name T307
Test name
Test status
Simulation time 51130778870 ps
CPU time 407.88 seconds
Started Jun 23 06:41:50 PM PDT 24
Finished Jun 23 06:48:38 PM PDT 24
Peak memory 248596 kb
Host smart-aa5f16eb-4051-4d08-94b8-36598a034084
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912026315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3912026315
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.442598812
Short name T602
Test name
Test status
Simulation time 39586948 ps
CPU time 5.9 seconds
Started Jun 23 06:41:44 PM PDT 24
Finished Jun 23 06:41:50 PM PDT 24
Peak memory 249128 kb
Host smart-5e65aebe-80fd-4c3a-8824-04ecea9003f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44259
8812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.442598812
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2809937113
Short name T547
Test name
Test status
Simulation time 415110111 ps
CPU time 28.61 seconds
Started Jun 23 06:41:53 PM PDT 24
Finished Jun 23 06:42:22 PM PDT 24
Peak memory 255984 kb
Host smart-2005e047-b394-491a-b328-faf162719d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28099
37113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2809937113
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.4169757516
Short name T521
Test name
Test status
Simulation time 348278981 ps
CPU time 15.35 seconds
Started Jun 23 06:41:51 PM PDT 24
Finished Jun 23 06:42:06 PM PDT 24
Peak memory 249048 kb
Host smart-c6658451-2f26-4d33-ad1c-f628c842d805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41697
57516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.4169757516
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2426472366
Short name T395
Test name
Test status
Simulation time 1167251488 ps
CPU time 67.55 seconds
Started Jun 23 06:41:45 PM PDT 24
Finished Jun 23 06:42:53 PM PDT 24
Peak memory 249160 kb
Host smart-ed17b8d3-3dbe-43d0-938e-276e5b02b4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24264
72366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2426472366
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.121122698
Short name T590
Test name
Test status
Simulation time 27743353182 ps
CPU time 1388.06 seconds
Started Jun 23 06:41:55 PM PDT 24
Finished Jun 23 07:05:04 PM PDT 24
Peak memory 288884 kb
Host smart-fdf66101-2468-46e4-8a65-d03dc18f4aae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121122698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.121122698
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.3715990574
Short name T101
Test name
Test status
Simulation time 133865254859 ps
CPU time 1486.61 seconds
Started Jun 23 06:41:50 PM PDT 24
Finished Jun 23 07:06:37 PM PDT 24
Peak memory 288612 kb
Host smart-e1aed67f-83c5-4b8a-98fb-835e492509ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715990574 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.3715990574
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.119676702
Short name T203
Test name
Test status
Simulation time 132017945 ps
CPU time 3.72 seconds
Started Jun 23 06:41:54 PM PDT 24
Finished Jun 23 06:41:58 PM PDT 24
Peak memory 249240 kb
Host smart-f0247227-8aef-46e8-84c6-a9e5c80e9193
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=119676702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.119676702
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2748924814
Short name T587
Test name
Test status
Simulation time 69743825095 ps
CPU time 1849.11 seconds
Started Jun 23 06:41:54 PM PDT 24
Finished Jun 23 07:12:43 PM PDT 24
Peak memory 281800 kb
Host smart-a5d8c39d-1c06-4a10-96cf-c4b4bd6365a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748924814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2748924814
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3787807321
Short name T608
Test name
Test status
Simulation time 2394219286 ps
CPU time 25.62 seconds
Started Jun 23 06:41:56 PM PDT 24
Finished Jun 23 06:42:22 PM PDT 24
Peak memory 252000 kb
Host smart-a57af3db-e05c-4a9d-80b6-c722878577cb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3787807321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3787807321
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1320473992
Short name T498
Test name
Test status
Simulation time 153657854 ps
CPU time 8.11 seconds
Started Jun 23 06:41:50 PM PDT 24
Finished Jun 23 06:41:58 PM PDT 24
Peak memory 253204 kb
Host smart-fe3d059d-39a1-49ce-8dec-ae53383662b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13204
73992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1320473992
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.140074977
Short name T424
Test name
Test status
Simulation time 322625523 ps
CPU time 24.16 seconds
Started Jun 23 06:41:53 PM PDT 24
Finished Jun 23 06:42:17 PM PDT 24
Peak memory 249136 kb
Host smart-4b818192-ce7f-41f5-b8a0-e65628c31895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14007
4977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.140074977
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.150091068
Short name T559
Test name
Test status
Simulation time 207770588654 ps
CPU time 1053.59 seconds
Started Jun 23 06:41:54 PM PDT 24
Finished Jun 23 06:59:28 PM PDT 24
Peak memory 272360 kb
Host smart-207eae41-96c2-4fea-8652-b1df42b74fb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150091068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.150091068
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1335494119
Short name T311
Test name
Test status
Simulation time 6083120340 ps
CPU time 242.49 seconds
Started Jun 23 06:41:51 PM PDT 24
Finished Jun 23 06:45:54 PM PDT 24
Peak memory 248376 kb
Host smart-47c962ce-5be6-4213-ad28-c24efa786285
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335494119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1335494119
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3060650369
Short name T230
Test name
Test status
Simulation time 249840627 ps
CPU time 22.41 seconds
Started Jun 23 06:41:48 PM PDT 24
Finished Jun 23 06:42:11 PM PDT 24
Peak memory 256500 kb
Host smart-b7679640-3d75-4404-a9af-b38173a89d5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30606
50369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3060650369
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3676693704
Short name T97
Test name
Test status
Simulation time 189609239 ps
CPU time 18.4 seconds
Started Jun 23 06:41:48 PM PDT 24
Finished Jun 23 06:42:07 PM PDT 24
Peak memory 256208 kb
Host smart-a8b68dda-f763-4504-abef-a2f254a3c010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36766
93704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3676693704
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3371961897
Short name T45
Test name
Test status
Simulation time 10008873104 ps
CPU time 60.14 seconds
Started Jun 23 06:41:53 PM PDT 24
Finished Jun 23 06:42:53 PM PDT 24
Peak memory 257288 kb
Host smart-73262eaa-710a-441a-b7f5-1a868378f9dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33719
61897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3371961897
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3038632962
Short name T566
Test name
Test status
Simulation time 298028535 ps
CPU time 19.53 seconds
Started Jun 23 06:41:48 PM PDT 24
Finished Jun 23 06:42:08 PM PDT 24
Peak memory 249032 kb
Host smart-c4d55f8d-734a-437d-b4eb-7f85537ad53f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30386
32962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3038632962
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.478230919
Short name T548
Test name
Test status
Simulation time 7060874566 ps
CPU time 293.39 seconds
Started Jun 23 06:41:54 PM PDT 24
Finished Jun 23 06:46:48 PM PDT 24
Peak memory 257012 kb
Host smart-b9e84fff-fe26-4ada-891f-08f398b6b7bf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478230919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_han
dler_stress_all.478230919
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3732188672
Short name T201
Test name
Test status
Simulation time 222398311 ps
CPU time 3.45 seconds
Started Jun 23 06:42:00 PM PDT 24
Finished Jun 23 06:42:03 PM PDT 24
Peak memory 249284 kb
Host smart-b944da48-3b4d-475f-87cd-20a6f42386d7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3732188672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3732188672
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.224865684
Short name T619
Test name
Test status
Simulation time 135388307642 ps
CPU time 1809.89 seconds
Started Jun 23 06:41:57 PM PDT 24
Finished Jun 23 07:12:07 PM PDT 24
Peak memory 273124 kb
Host smart-44935307-a983-46aa-acaf-57807a1bbe6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224865684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.224865684
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1184052920
Short name T509
Test name
Test status
Simulation time 254309994 ps
CPU time 12.62 seconds
Started Jun 23 06:41:58 PM PDT 24
Finished Jun 23 06:42:11 PM PDT 24
Peak memory 240856 kb
Host smart-948aa3c9-9346-4f4a-b4da-ee2045fb672c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1184052920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1184052920
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3437389208
Short name T241
Test name
Test status
Simulation time 30894069831 ps
CPU time 231.67 seconds
Started Jun 23 06:41:54 PM PDT 24
Finished Jun 23 06:45:46 PM PDT 24
Peak memory 257304 kb
Host smart-e3697be7-0a24-49a6-87a5-3cc46a6a2436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34373
89208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3437389208
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3404671395
Short name T375
Test name
Test status
Simulation time 45173184 ps
CPU time 5.24 seconds
Started Jun 23 06:41:53 PM PDT 24
Finished Jun 23 06:41:58 PM PDT 24
Peak memory 252616 kb
Host smart-9e4fd74f-a815-477e-a5a8-83c80a40422a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34046
71395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3404671395
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1924613726
Short name T666
Test name
Test status
Simulation time 114816594139 ps
CPU time 1960.74 seconds
Started Jun 23 06:42:00 PM PDT 24
Finished Jun 23 07:14:41 PM PDT 24
Peak memory 282324 kb
Host smart-83df830d-3369-47a0-89c6-de933185956f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924613726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1924613726
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.616716097
Short name T8
Test name
Test status
Simulation time 20047766167 ps
CPU time 217.49 seconds
Started Jun 23 06:41:59 PM PDT 24
Finished Jun 23 06:45:37 PM PDT 24
Peak memory 256496 kb
Host smart-4f176ae3-a0a8-41ab-931a-3f6063f6ad16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616716097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.616716097
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3165151416
Short name T378
Test name
Test status
Simulation time 990258582 ps
CPU time 54.78 seconds
Started Jun 23 06:41:55 PM PDT 24
Finished Jun 23 06:42:50 PM PDT 24
Peak memory 257240 kb
Host smart-a017d7ce-65ad-44e3-a172-84b6d53c82b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31651
51416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3165151416
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.383215578
Short name T705
Test name
Test status
Simulation time 2228972987 ps
CPU time 39.82 seconds
Started Jun 23 06:41:55 PM PDT 24
Finished Jun 23 06:42:35 PM PDT 24
Peak memory 257332 kb
Host smart-98bb7da2-2c8a-4f8d-91c6-2eeeb3f971c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38321
5578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.383215578
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3530434275
Short name T283
Test name
Test status
Simulation time 219671925 ps
CPU time 20.53 seconds
Started Jun 23 06:41:53 PM PDT 24
Finished Jun 23 06:42:14 PM PDT 24
Peak memory 247888 kb
Host smart-3ff40d77-1e8c-4f34-8550-3dc3d622a4bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35304
34275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3530434275
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3695793534
Short name T477
Test name
Test status
Simulation time 671608565 ps
CPU time 40.71 seconds
Started Jun 23 06:41:52 PM PDT 24
Finished Jun 23 06:42:33 PM PDT 24
Peak memory 249076 kb
Host smart-6001e508-cc70-46a1-947a-aa825a141190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36957
93534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3695793534
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.749717349
Short name T405
Test name
Test status
Simulation time 5445710611 ps
CPU time 36.35 seconds
Started Jun 23 06:42:01 PM PDT 24
Finished Jun 23 06:42:38 PM PDT 24
Peak memory 257068 kb
Host smart-39e81b7f-ad7a-4b6d-bdf2-e022084e3d26
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749717349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.749717349
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.4160976393
Short name T205
Test name
Test status
Simulation time 166687642 ps
CPU time 3.44 seconds
Started Jun 23 06:41:59 PM PDT 24
Finished Jun 23 06:42:03 PM PDT 24
Peak memory 249284 kb
Host smart-7e776df8-2f53-46c2-8ffc-5b69727f7790
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4160976393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.4160976393
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1257530521
Short name T120
Test name
Test status
Simulation time 8782180331 ps
CPU time 1292.33 seconds
Started Jun 23 06:41:57 PM PDT 24
Finished Jun 23 07:03:30 PM PDT 24
Peak memory 285532 kb
Host smart-c5958dad-5952-4fed-8341-0cdf797ee3a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257530521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1257530521
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.944819799
Short name T426
Test name
Test status
Simulation time 656553251 ps
CPU time 10.35 seconds
Started Jun 23 06:42:04 PM PDT 24
Finished Jun 23 06:42:14 PM PDT 24
Peak memory 249072 kb
Host smart-e8927b17-6d22-42f7-9096-8ce3861c855e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=944819799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.944819799
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2149800951
Short name T80
Test name
Test status
Simulation time 1584901890 ps
CPU time 92.94 seconds
Started Jun 23 06:41:58 PM PDT 24
Finished Jun 23 06:43:31 PM PDT 24
Peak memory 257260 kb
Host smart-5402602f-a12c-477d-b0aa-33f09c008d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21498
00951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2149800951
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.783843766
Short name T410
Test name
Test status
Simulation time 703418069 ps
CPU time 39.78 seconds
Started Jun 23 06:42:01 PM PDT 24
Finished Jun 23 06:42:41 PM PDT 24
Peak memory 249020 kb
Host smart-1079ad79-86af-4479-88c5-7e3fedc72bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78384
3766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.783843766
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3334482973
Short name T339
Test name
Test status
Simulation time 75319143595 ps
CPU time 1801.6 seconds
Started Jun 23 06:42:00 PM PDT 24
Finished Jun 23 07:12:02 PM PDT 24
Peak memory 288484 kb
Host smart-c44e6b02-1f5b-45cd-adc1-596f18369567
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334482973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3334482973
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1629887544
Short name T554
Test name
Test status
Simulation time 159200553909 ps
CPU time 2508.31 seconds
Started Jun 23 06:42:04 PM PDT 24
Finished Jun 23 07:23:53 PM PDT 24
Peak memory 289456 kb
Host smart-4b06b51f-897e-4391-83f4-01f0799a0ce7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629887544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1629887544
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1042535241
Short name T35
Test name
Test status
Simulation time 4041927732 ps
CPU time 55.21 seconds
Started Jun 23 06:41:58 PM PDT 24
Finished Jun 23 06:42:53 PM PDT 24
Peak memory 257248 kb
Host smart-f2c9f6a1-a6db-4ce9-9be9-faf73e56d69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10425
35241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1042535241
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2675415112
Short name T648
Test name
Test status
Simulation time 984414508 ps
CPU time 23.85 seconds
Started Jun 23 06:41:59 PM PDT 24
Finished Jun 23 06:42:23 PM PDT 24
Peak memory 247816 kb
Host smart-3f5af1c5-671d-457b-aa84-64af8cd18076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26754
15112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2675415112
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3309387380
Short name T109
Test name
Test status
Simulation time 760482452 ps
CPU time 26.05 seconds
Started Jun 23 06:41:59 PM PDT 24
Finished Jun 23 06:42:25 PM PDT 24
Peak memory 249020 kb
Host smart-27d0d615-37de-40fa-835a-276a49aecacb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33093
87380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3309387380
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2706782285
Short name T86
Test name
Test status
Simulation time 135967767 ps
CPU time 8.56 seconds
Started Jun 23 06:42:00 PM PDT 24
Finished Jun 23 06:42:09 PM PDT 24
Peak memory 249016 kb
Host smart-14dab085-1aa2-49c6-81ae-cffbde8043e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27067
82285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2706782285
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2648186968
Short name T700
Test name
Test status
Simulation time 54736546782 ps
CPU time 1394.93 seconds
Started Jun 23 06:42:01 PM PDT 24
Finished Jun 23 07:05:17 PM PDT 24
Peak memory 289920 kb
Host smart-4f031d89-4063-4d0f-bd87-335e14a5dcfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648186968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2648186968
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.81026814
Short name T552
Test name
Test status
Simulation time 757466428 ps
CPU time 33.91 seconds
Started Jun 23 06:42:03 PM PDT 24
Finished Jun 23 06:42:37 PM PDT 24
Peak memory 240836 kb
Host smart-e4d69243-3fe6-41c6-a2ca-7c2a8764bcd0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=81026814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.81026814
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.791551232
Short name T402
Test name
Test status
Simulation time 1405276322 ps
CPU time 125.15 seconds
Started Jun 23 06:42:03 PM PDT 24
Finished Jun 23 06:44:08 PM PDT 24
Peak memory 257292 kb
Host smart-e7c07d21-b179-430d-b654-6d8500bab8e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79155
1232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.791551232
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3539669733
Short name T478
Test name
Test status
Simulation time 630560166 ps
CPU time 39.63 seconds
Started Jun 23 06:42:01 PM PDT 24
Finished Jun 23 06:42:41 PM PDT 24
Peak memory 249156 kb
Host smart-8fd2f689-3dac-4f4e-af2b-efd8ea605fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35396
69733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3539669733
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1009679880
Short name T419
Test name
Test status
Simulation time 66595167562 ps
CPU time 2355.16 seconds
Started Jun 23 06:42:01 PM PDT 24
Finished Jun 23 07:21:17 PM PDT 24
Peak memory 289208 kb
Host smart-e155c2e1-a4bc-485e-9d90-166d1bd39248
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009679880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1009679880
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.4282563185
Short name T295
Test name
Test status
Simulation time 2634856936 ps
CPU time 106.09 seconds
Started Jun 23 06:42:02 PM PDT 24
Finished Jun 23 06:43:48 PM PDT 24
Peak memory 248312 kb
Host smart-055437ae-4125-454f-b802-d8dcc331999d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282563185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.4282563185
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3172225566
Short name T182
Test name
Test status
Simulation time 675846350 ps
CPU time 9.79 seconds
Started Jun 23 06:42:01 PM PDT 24
Finished Jun 23 06:42:11 PM PDT 24
Peak memory 253220 kb
Host smart-b6d7402a-acef-4786-9eff-080783afdc30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31722
25566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3172225566
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.108364568
Short name T639
Test name
Test status
Simulation time 445633100 ps
CPU time 26.3 seconds
Started Jun 23 06:42:02 PM PDT 24
Finished Jun 23 06:42:29 PM PDT 24
Peak memory 249108 kb
Host smart-742cbe28-9192-4146-9b97-e365d5e90fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10836
4568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.108364568
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.566337688
Short name T578
Test name
Test status
Simulation time 217296801 ps
CPU time 28.11 seconds
Started Jun 23 06:42:02 PM PDT 24
Finished Jun 23 06:42:30 PM PDT 24
Peak memory 255944 kb
Host smart-06bf998c-22e3-40ae-afaf-c5e65426e495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56633
7688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.566337688
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1549576673
Short name T634
Test name
Test status
Simulation time 405456902 ps
CPU time 11.3 seconds
Started Jun 23 06:41:59 PM PDT 24
Finished Jun 23 06:42:10 PM PDT 24
Peak memory 255596 kb
Host smart-3d4e10cf-1df9-4337-9510-423d203f1cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15495
76673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1549576673
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.12966117
Short name T508
Test name
Test status
Simulation time 27519533389 ps
CPU time 1634.83 seconds
Started Jun 23 06:42:02 PM PDT 24
Finished Jun 23 07:09:17 PM PDT 24
Peak memory 289688 kb
Host smart-676cf7e9-4b81-40db-ba6f-fd32d3bc1efd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12966117 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.12966117
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3725500084
Short name T194
Test name
Test status
Simulation time 30066735 ps
CPU time 2.45 seconds
Started Jun 23 06:42:17 PM PDT 24
Finished Jun 23 06:42:20 PM PDT 24
Peak memory 249180 kb
Host smart-7d0bff7d-6909-43c4-ac6c-4da4d0a6e41e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3725500084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3725500084
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3203227670
Short name T236
Test name
Test status
Simulation time 1489505805 ps
CPU time 15.12 seconds
Started Jun 23 06:42:07 PM PDT 24
Finished Jun 23 06:42:23 PM PDT 24
Peak memory 249092 kb
Host smart-b8f61df7-4508-4e1a-b359-13e0337fb3b6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3203227670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3203227670
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.334595616
Short name T453
Test name
Test status
Simulation time 3963441023 ps
CPU time 118.51 seconds
Started Jun 23 06:42:07 PM PDT 24
Finished Jun 23 06:44:06 PM PDT 24
Peak memory 249880 kb
Host smart-ffe57e8a-5a81-40b9-a8c8-9843a583f783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33459
5616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.334595616
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.4178167993
Short name T73
Test name
Test status
Simulation time 1202481461 ps
CPU time 35.92 seconds
Started Jun 23 06:42:02 PM PDT 24
Finished Jun 23 06:42:38 PM PDT 24
Peak memory 249024 kb
Host smart-f62ed661-361f-499d-b7d5-07a2104b3619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41781
67993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.4178167993
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1370247797
Short name T289
Test name
Test status
Simulation time 21726960822 ps
CPU time 832.01 seconds
Started Jun 23 06:42:07 PM PDT 24
Finished Jun 23 06:56:00 PM PDT 24
Peak memory 273800 kb
Host smart-520cad6d-6fa3-46e0-9905-b78aef6bfdd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370247797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1370247797
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3337609212
Short name T626
Test name
Test status
Simulation time 18315015546 ps
CPU time 1229.93 seconds
Started Jun 23 06:42:18 PM PDT 24
Finished Jun 23 07:02:49 PM PDT 24
Peak memory 265528 kb
Host smart-add01a5d-0093-4de2-ae08-3898ede3753a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337609212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3337609212
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1104544778
Short name T516
Test name
Test status
Simulation time 437401341 ps
CPU time 25.68 seconds
Started Jun 23 06:42:04 PM PDT 24
Finished Jun 23 06:42:30 PM PDT 24
Peak memory 256584 kb
Host smart-4594aab7-a3bf-4638-a4b0-11703a7f408e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11045
44778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1104544778
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2104364348
Short name T696
Test name
Test status
Simulation time 444009692 ps
CPU time 42.16 seconds
Started Jun 23 06:42:03 PM PDT 24
Finished Jun 23 06:42:46 PM PDT 24
Peak memory 249196 kb
Host smart-d5066c66-6583-42fe-82db-84ac5532dcb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21043
64348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2104364348
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.275809036
Short name T58
Test name
Test status
Simulation time 652501527 ps
CPU time 20.21 seconds
Started Jun 23 06:42:18 PM PDT 24
Finished Jun 23 06:42:39 PM PDT 24
Peak memory 255588 kb
Host smart-c4c548a1-6a48-469d-99bc-cfcd95530e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27580
9036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.275809036
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3287807481
Short name T574
Test name
Test status
Simulation time 662167255 ps
CPU time 36.1 seconds
Started Jun 23 06:42:03 PM PDT 24
Finished Jun 23 06:42:39 PM PDT 24
Peak memory 256464 kb
Host smart-9f8c43f8-c152-472b-af35-177424e2dfd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32878
07481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3287807481
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2675941788
Short name T185
Test name
Test status
Simulation time 14259843897 ps
CPU time 1675.93 seconds
Started Jun 23 06:42:08 PM PDT 24
Finished Jun 23 07:10:04 PM PDT 24
Peak memory 290220 kb
Host smart-4dd89c9e-0315-45e7-bf94-9c01e9d86b06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675941788 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2675941788
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2796704973
Short name T195
Test name
Test status
Simulation time 23843074 ps
CPU time 2.61 seconds
Started Jun 23 06:42:09 PM PDT 24
Finished Jun 23 06:42:12 PM PDT 24
Peak memory 249288 kb
Host smart-1f300d85-3915-4e8a-8179-030ba4acd2e8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2796704973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2796704973
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1286914654
Short name T582
Test name
Test status
Simulation time 10682606127 ps
CPU time 956.06 seconds
Started Jun 23 06:42:07 PM PDT 24
Finished Jun 23 06:58:04 PM PDT 24
Peak memory 271688 kb
Host smart-1029c2a4-af7e-4dda-9986-cf8af2b091ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286914654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1286914654
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1534310761
Short name T616
Test name
Test status
Simulation time 329314822 ps
CPU time 14.74 seconds
Started Jun 23 06:42:08 PM PDT 24
Finished Jun 23 06:42:23 PM PDT 24
Peak memory 240828 kb
Host smart-955a254c-62d4-4add-b65d-f7dbb5b35664
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1534310761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1534310761
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.763691020
Short name T436
Test name
Test status
Simulation time 6653224161 ps
CPU time 194.56 seconds
Started Jun 23 06:42:06 PM PDT 24
Finished Jun 23 06:45:21 PM PDT 24
Peak memory 257384 kb
Host smart-f39b6d64-d348-4b0f-b5aa-c50296533743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76369
1020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.763691020
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.538959494
Short name T689
Test name
Test status
Simulation time 731009674 ps
CPU time 43.38 seconds
Started Jun 23 06:42:09 PM PDT 24
Finished Jun 23 06:42:53 PM PDT 24
Peak memory 256212 kb
Host smart-0a62bca8-7777-493d-af06-03970f5bd245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53895
9494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.538959494
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3685613535
Short name T288
Test name
Test status
Simulation time 10433324282 ps
CPU time 764.55 seconds
Started Jun 23 06:42:07 PM PDT 24
Finished Jun 23 06:54:52 PM PDT 24
Peak memory 272988 kb
Host smart-11fdc0a8-20c7-49b2-9494-a352e83d2499
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685613535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3685613535
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2159303731
Short name T435
Test name
Test status
Simulation time 152560545763 ps
CPU time 2508.02 seconds
Started Jun 23 06:42:09 PM PDT 24
Finished Jun 23 07:23:57 PM PDT 24
Peak memory 273736 kb
Host smart-c14465d9-84e1-40c0-b780-33733fc7fbad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159303731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2159303731
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1861048303
Short name T585
Test name
Test status
Simulation time 17903027788 ps
CPU time 187.83 seconds
Started Jun 23 06:42:08 PM PDT 24
Finished Jun 23 06:45:16 PM PDT 24
Peak memory 248592 kb
Host smart-a2bd6a4e-cc99-4b6b-bb05-21a132abcfe2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861048303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1861048303
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.16214665
Short name T414
Test name
Test status
Simulation time 913303368 ps
CPU time 61.34 seconds
Started Jun 23 06:42:18 PM PDT 24
Finished Jun 23 06:43:19 PM PDT 24
Peak memory 248984 kb
Host smart-f095807b-b576-4706-9b05-cee468c176f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16214
665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.16214665
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.920153283
Short name T682
Test name
Test status
Simulation time 3238241506 ps
CPU time 54.7 seconds
Started Jun 23 06:42:18 PM PDT 24
Finished Jun 23 06:43:13 PM PDT 24
Peak memory 248344 kb
Host smart-06e7e606-b28e-49d2-883f-56338fea0408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92015
3283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.920153283
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1318503512
Short name T461
Test name
Test status
Simulation time 6091702984 ps
CPU time 48.98 seconds
Started Jun 23 06:42:07 PM PDT 24
Finished Jun 23 06:42:56 PM PDT 24
Peak memory 256060 kb
Host smart-f8db38d2-1546-45e2-9f3e-85139d55fd50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13185
03512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1318503512
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2755235401
Short name T373
Test name
Test status
Simulation time 396280036 ps
CPU time 24.26 seconds
Started Jun 23 06:42:18 PM PDT 24
Finished Jun 23 06:42:43 PM PDT 24
Peak memory 249076 kb
Host smart-1744ba39-443b-4dcc-acdc-bb0b66da62ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27552
35401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2755235401
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.727709874
Short name T277
Test name
Test status
Simulation time 20229079606 ps
CPU time 1721.87 seconds
Started Jun 23 06:42:07 PM PDT 24
Finished Jun 23 07:10:50 PM PDT 24
Peak memory 289848 kb
Host smart-79167361-d59e-43e0-b497-4b47bf8bc424
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727709874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.727709874
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3360542371
Short name T196
Test name
Test status
Simulation time 32534165 ps
CPU time 2.99 seconds
Started Jun 23 06:42:11 PM PDT 24
Finished Jun 23 06:42:14 PM PDT 24
Peak memory 249228 kb
Host smart-0ecb904d-df06-4868-84c2-fb3fefa6daee
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3360542371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3360542371
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1944785838
Short name T401
Test name
Test status
Simulation time 63590769857 ps
CPU time 1433.64 seconds
Started Jun 23 06:42:13 PM PDT 24
Finished Jun 23 07:06:07 PM PDT 24
Peak memory 285884 kb
Host smart-f1b94854-cad2-4238-a365-f421a112fc85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944785838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1944785838
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2063246905
Short name T385
Test name
Test status
Simulation time 1318541799 ps
CPU time 16.34 seconds
Started Jun 23 06:42:13 PM PDT 24
Finished Jun 23 06:42:29 PM PDT 24
Peak memory 240928 kb
Host smart-17706459-26a6-46db-b9d8-20b21bc147df
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2063246905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2063246905
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2519365367
Short name T67
Test name
Test status
Simulation time 2425127289 ps
CPU time 51.56 seconds
Started Jun 23 06:42:11 PM PDT 24
Finished Jun 23 06:43:03 PM PDT 24
Peak memory 257328 kb
Host smart-bc604ffd-7fc2-402c-a8d8-3da869397990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25193
65367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2519365367
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.495637480
Short name T118
Test name
Test status
Simulation time 92979201 ps
CPU time 6.53 seconds
Started Jun 23 06:42:13 PM PDT 24
Finished Jun 23 06:42:20 PM PDT 24
Peak memory 249100 kb
Host smart-69a8a047-75ac-43c9-b4d3-43c31fca11f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49563
7480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.495637480
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2629548027
Short name T326
Test name
Test status
Simulation time 126266989861 ps
CPU time 1820.62 seconds
Started Jun 23 06:42:15 PM PDT 24
Finished Jun 23 07:12:36 PM PDT 24
Peak memory 273712 kb
Host smart-bc7c5e6a-b21f-41a6-addb-44a74a223dc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629548027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2629548027
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1899884460
Short name T589
Test name
Test status
Simulation time 13708054197 ps
CPU time 1228.25 seconds
Started Jun 23 06:42:12 PM PDT 24
Finished Jun 23 07:02:40 PM PDT 24
Peak memory 289896 kb
Host smart-db322985-8a0d-4227-afe7-24a14c17c99a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899884460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1899884460
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3145193516
Short name T229
Test name
Test status
Simulation time 77079761222 ps
CPU time 348.97 seconds
Started Jun 23 06:42:13 PM PDT 24
Finished Jun 23 06:48:03 PM PDT 24
Peak memory 248868 kb
Host smart-7f85d08f-a8b7-4db2-8de3-de0edb860533
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145193516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3145193516
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2387230967
Short name T421
Test name
Test status
Simulation time 270667120 ps
CPU time 16.05 seconds
Started Jun 23 06:42:14 PM PDT 24
Finished Jun 23 06:42:31 PM PDT 24
Peak memory 255688 kb
Host smart-94860e68-a981-42c1-9305-e9a8a64fdf0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23872
30967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2387230967
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.771263588
Short name T22
Test name
Test status
Simulation time 3201597027 ps
CPU time 19.33 seconds
Started Jun 23 06:42:13 PM PDT 24
Finished Jun 23 06:42:33 PM PDT 24
Peak memory 254572 kb
Host smart-40e83cac-8200-4728-bbb9-df4fcd5ceeb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77126
3588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.771263588
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.4120523638
Short name T383
Test name
Test status
Simulation time 9518517736 ps
CPU time 35.68 seconds
Started Jun 23 06:42:14 PM PDT 24
Finished Jun 23 06:42:50 PM PDT 24
Peak memory 249100 kb
Host smart-cf0af93d-db76-4110-8cde-c594038f29c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41205
23638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.4120523638
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.622572830
Short name T702
Test name
Test status
Simulation time 1745969827 ps
CPU time 52.47 seconds
Started Jun 23 06:42:16 PM PDT 24
Finished Jun 23 06:43:08 PM PDT 24
Peak memory 249084 kb
Host smart-059e41dc-b251-499b-a99c-ce37e8cbcd09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62257
2830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.622572830
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1315669725
Short name T108
Test name
Test status
Simulation time 37167771136 ps
CPU time 271 seconds
Started Jun 23 06:42:14 PM PDT 24
Finished Jun 23 06:46:46 PM PDT 24
Peak memory 257224 kb
Host smart-5fce36eb-f35d-490f-b272-c92620e2cce8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315669725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1315669725
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2961167549
Short name T55
Test name
Test status
Simulation time 16622671 ps
CPU time 2.66 seconds
Started Jun 23 06:41:19 PM PDT 24
Finished Jun 23 06:41:22 PM PDT 24
Peak memory 249268 kb
Host smart-70b3ca5b-8f1e-453c-87a5-6fdc427d582a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2961167549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2961167549
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.4167100465
Short name T480
Test name
Test status
Simulation time 27327643953 ps
CPU time 1559.67 seconds
Started Jun 23 06:41:16 PM PDT 24
Finished Jun 23 07:07:16 PM PDT 24
Peak memory 273688 kb
Host smart-e6fa5889-1946-4c44-8e5c-4b078252312b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167100465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.4167100465
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3761538041
Short name T510
Test name
Test status
Simulation time 111285976 ps
CPU time 6.91 seconds
Started Jun 23 06:41:16 PM PDT 24
Finished Jun 23 06:41:23 PM PDT 24
Peak memory 249060 kb
Host smart-cdf9b7ef-4286-4d9c-8f01-ded4da1321a6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3761538041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3761538041
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2804651537
Short name T500
Test name
Test status
Simulation time 671483994 ps
CPU time 39.08 seconds
Started Jun 23 06:41:17 PM PDT 24
Finished Jun 23 06:41:57 PM PDT 24
Peak memory 256636 kb
Host smart-45f36bb6-16dc-4d19-a474-db1ae2528028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28046
51537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2804651537
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2693015781
Short name T517
Test name
Test status
Simulation time 2566336817 ps
CPU time 40.12 seconds
Started Jun 23 06:41:19 PM PDT 24
Finished Jun 23 06:41:59 PM PDT 24
Peak memory 256604 kb
Host smart-ea1d0229-949e-4090-85fe-06bc28d16ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26930
15781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2693015781
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.945151282
Short name T628
Test name
Test status
Simulation time 67491773046 ps
CPU time 2088.45 seconds
Started Jun 23 06:41:20 PM PDT 24
Finished Jun 23 07:16:09 PM PDT 24
Peak memory 285096 kb
Host smart-56c80589-fabd-4a64-b7fa-7dea6f8d737e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945151282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.945151282
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.893980564
Short name T322
Test name
Test status
Simulation time 5746040986 ps
CPU time 64.76 seconds
Started Jun 23 06:41:19 PM PDT 24
Finished Jun 23 06:42:25 PM PDT 24
Peak memory 253624 kb
Host smart-1e69db2e-0a12-40d6-99d1-4be6022d6338
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893980564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.893980564
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.276682495
Short name T595
Test name
Test status
Simulation time 170509816 ps
CPU time 12.53 seconds
Started Jun 23 06:41:11 PM PDT 24
Finished Jun 23 06:41:24 PM PDT 24
Peak memory 249076 kb
Host smart-fc1e4cd9-e6d2-46ae-ae59-761ccc88a639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27668
2495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.276682495
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1247814518
Short name T573
Test name
Test status
Simulation time 216361903 ps
CPU time 17.1 seconds
Started Jun 23 06:41:19 PM PDT 24
Finished Jun 23 06:41:37 PM PDT 24
Peak memory 255488 kb
Host smart-d5a6991c-f41f-47ad-a2e2-f768f432fd8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12478
14518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1247814518
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.1300845080
Short name T32
Test name
Test status
Simulation time 1391060532 ps
CPU time 18.41 seconds
Started Jun 23 06:41:17 PM PDT 24
Finished Jun 23 06:41:36 PM PDT 24
Peak memory 270456 kb
Host smart-e3766cd1-d6ea-4a5e-bf87-565cfcb1abe0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1300845080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1300845080
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1087806035
Short name T69
Test name
Test status
Simulation time 235000634 ps
CPU time 12.14 seconds
Started Jun 23 06:41:10 PM PDT 24
Finished Jun 23 06:41:23 PM PDT 24
Peak memory 248720 kb
Host smart-4ae8fe17-7e58-4ef1-a8a8-c2eb10555fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10878
06035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1087806035
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2265815569
Short name T586
Test name
Test status
Simulation time 1998148561 ps
CPU time 32.39 seconds
Started Jun 23 06:41:12 PM PDT 24
Finished Jun 23 06:41:45 PM PDT 24
Peak memory 257332 kb
Host smart-9a10271b-2443-4523-bacb-ec3076b5849c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22658
15569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2265815569
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.613372346
Short name T87
Test name
Test status
Simulation time 132386108975 ps
CPU time 3711.71 seconds
Started Jun 23 06:41:19 PM PDT 24
Finished Jun 23 07:43:12 PM PDT 24
Peak memory 290144 kb
Host smart-a7da42e8-b062-450e-b14b-2113e3163ea7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613372346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.613372346
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1069226450
Short name T612
Test name
Test status
Simulation time 74697786143 ps
CPU time 7788.58 seconds
Started Jun 23 06:41:18 PM PDT 24
Finished Jun 23 08:51:08 PM PDT 24
Peak memory 338436 kb
Host smart-561fa1a6-803d-485f-8215-92d9b074c254
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069226450 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1069226450
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2539594859
Short name T680
Test name
Test status
Simulation time 121749076884 ps
CPU time 2814.36 seconds
Started Jun 23 06:42:14 PM PDT 24
Finished Jun 23 07:29:09 PM PDT 24
Peak memory 285276 kb
Host smart-b80309b5-bfeb-4836-b537-02c4c49fccef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539594859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2539594859
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.508866675
Short name T469
Test name
Test status
Simulation time 8735871018 ps
CPU time 268.71 seconds
Started Jun 23 06:42:16 PM PDT 24
Finished Jun 23 06:46:45 PM PDT 24
Peak memory 257352 kb
Host smart-d6933834-2e15-43cd-affc-4b22d2894ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50886
6675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.508866675
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.472587475
Short name T452
Test name
Test status
Simulation time 773472832 ps
CPU time 41.29 seconds
Started Jun 23 06:42:14 PM PDT 24
Finished Jun 23 06:42:56 PM PDT 24
Peak memory 255996 kb
Host smart-3221d60a-05a6-48ba-8db8-227640329244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47258
7475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.472587475
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1491082133
Short name T331
Test name
Test status
Simulation time 11105721849 ps
CPU time 889.77 seconds
Started Jun 23 06:42:12 PM PDT 24
Finished Jun 23 06:57:02 PM PDT 24
Peak memory 273756 kb
Host smart-d98902ea-4541-41af-a172-3beb1c2d6035
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491082133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1491082133
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2512108343
Short name T389
Test name
Test status
Simulation time 56244819425 ps
CPU time 1779.25 seconds
Started Jun 23 06:42:15 PM PDT 24
Finished Jun 23 07:11:55 PM PDT 24
Peak memory 282536 kb
Host smart-ad8fc430-5aa1-42fc-8f12-e4f592364cbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512108343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2512108343
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1577413950
Short name T316
Test name
Test status
Simulation time 5252887495 ps
CPU time 207.84 seconds
Started Jun 23 06:42:13 PM PDT 24
Finished Jun 23 06:45:42 PM PDT 24
Peak memory 248836 kb
Host smart-6e2905e2-06dd-47e8-97be-ade77ca07c65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577413950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1577413950
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3842337566
Short name T543
Test name
Test status
Simulation time 1266158606 ps
CPU time 39.06 seconds
Started Jun 23 06:42:14 PM PDT 24
Finished Jun 23 06:42:54 PM PDT 24
Peak memory 257304 kb
Host smart-da9763f9-2deb-4e2e-ab6d-1c4008954fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38423
37566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3842337566
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.167342055
Short name T712
Test name
Test status
Simulation time 4740836709 ps
CPU time 60.94 seconds
Started Jun 23 06:42:14 PM PDT 24
Finished Jun 23 06:43:15 PM PDT 24
Peak memory 256080 kb
Host smart-f432e8dc-c593-441b-a8b7-fbaa5483aa6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16734
2055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.167342055
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1590977376
Short name T442
Test name
Test status
Simulation time 873487099 ps
CPU time 53.28 seconds
Started Jun 23 06:42:12 PM PDT 24
Finished Jun 23 06:43:05 PM PDT 24
Peak memory 255384 kb
Host smart-0e07cc3c-0f1a-4275-9398-e86f6fd4b4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15909
77376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1590977376
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2209404617
Short name T692
Test name
Test status
Simulation time 7585577226 ps
CPU time 54.31 seconds
Started Jun 23 06:42:14 PM PDT 24
Finished Jun 23 06:43:09 PM PDT 24
Peak memory 249176 kb
Host smart-5a76db0b-9e21-4918-a1f9-aa24b684e592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22094
04617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2209404617
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1268206993
Short name T263
Test name
Test status
Simulation time 19010180067 ps
CPU time 1481.54 seconds
Started Jun 23 06:42:12 PM PDT 24
Finished Jun 23 07:06:54 PM PDT 24
Peak memory 289680 kb
Host smart-d713d52f-9483-4b37-af1e-a9ffa8ff32b2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268206993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1268206993
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3280402044
Short name T293
Test name
Test status
Simulation time 84195616229 ps
CPU time 1167.49 seconds
Started Jun 23 06:42:18 PM PDT 24
Finished Jun 23 07:01:46 PM PDT 24
Peak memory 289124 kb
Host smart-f59eae1d-1516-4d0c-a01a-868a99e8bd5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280402044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3280402044
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2136210731
Short name T607
Test name
Test status
Simulation time 323265714 ps
CPU time 33.41 seconds
Started Jun 23 06:42:27 PM PDT 24
Finished Jun 23 06:43:01 PM PDT 24
Peak memory 257212 kb
Host smart-37cab45f-68f8-4ee9-bc78-ffacb0db8ce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21362
10731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2136210731
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3594839361
Short name T456
Test name
Test status
Simulation time 877313589 ps
CPU time 12.85 seconds
Started Jun 23 06:42:27 PM PDT 24
Finished Jun 23 06:42:40 PM PDT 24
Peak memory 249112 kb
Host smart-02bf51f7-e92c-4e65-82b9-c57a71927d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35948
39361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3594839361
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2955228658
Short name T664
Test name
Test status
Simulation time 18583186781 ps
CPU time 987.74 seconds
Started Jun 23 06:42:22 PM PDT 24
Finished Jun 23 06:58:50 PM PDT 24
Peak memory 265612 kb
Host smart-e7d069b1-9977-47f8-ae3a-34b2bc133426
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955228658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2955228658
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.2776945568
Short name T6
Test name
Test status
Simulation time 54324377343 ps
CPU time 1862.08 seconds
Started Jun 23 06:42:17 PM PDT 24
Finished Jun 23 07:13:20 PM PDT 24
Peak memory 282576 kb
Host smart-8ecaae8c-0db9-4cce-95ed-5a8e4c73ea3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776945568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2776945568
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2971643863
Short name T309
Test name
Test status
Simulation time 6776784597 ps
CPU time 134.19 seconds
Started Jun 23 06:42:27 PM PDT 24
Finished Jun 23 06:44:41 PM PDT 24
Peak memory 248712 kb
Host smart-92ab11f9-a3d3-41f5-b8e9-feeb4cc04965
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971643863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2971643863
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.4054532317
Short name T523
Test name
Test status
Simulation time 1183108063 ps
CPU time 67.7 seconds
Started Jun 23 06:42:16 PM PDT 24
Finished Jun 23 06:43:24 PM PDT 24
Peak memory 257312 kb
Host smart-3dea8ae6-c974-40c7-b177-496a5c822005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40545
32317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.4054532317
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2357932358
Short name T676
Test name
Test status
Simulation time 995494779 ps
CPU time 49.08 seconds
Started Jun 23 06:42:21 PM PDT 24
Finished Jun 23 06:43:10 PM PDT 24
Peak memory 256584 kb
Host smart-d10dec02-1b63-4077-b618-4a488442f491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23579
32358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2357932358
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2229290525
Short name T254
Test name
Test status
Simulation time 514042987 ps
CPU time 19.92 seconds
Started Jun 23 06:42:25 PM PDT 24
Finished Jun 23 06:42:46 PM PDT 24
Peak memory 247912 kb
Host smart-3c313558-6c13-4091-b76c-171b7cd7206b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22292
90525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2229290525
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.3423957794
Short name T563
Test name
Test status
Simulation time 534312812 ps
CPU time 16.08 seconds
Started Jun 23 06:42:13 PM PDT 24
Finished Jun 23 06:42:30 PM PDT 24
Peak memory 249040 kb
Host smart-91dad0f7-0b39-4ee5-813a-23481a60ed89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34239
57794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3423957794
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1706014904
Short name T280
Test name
Test status
Simulation time 157087093809 ps
CPU time 2407.82 seconds
Started Jun 23 06:42:19 PM PDT 24
Finished Jun 23 07:22:28 PM PDT 24
Peak memory 289716 kb
Host smart-e47545b2-0ed3-4d03-bfbb-b493e502f27d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706014904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1706014904
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.449551716
Short name T493
Test name
Test status
Simulation time 3099792035 ps
CPU time 42.15 seconds
Started Jun 23 06:42:21 PM PDT 24
Finished Jun 23 06:43:04 PM PDT 24
Peak memory 256864 kb
Host smart-f3c18f56-9682-4694-8a17-ae60f70eaf84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44955
1716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.449551716
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.1161895935
Short name T601
Test name
Test status
Simulation time 1260142096 ps
CPU time 73.19 seconds
Started Jun 23 06:42:17 PM PDT 24
Finished Jun 23 06:43:31 PM PDT 24
Peak memory 256784 kb
Host smart-c14550e6-ce7d-47ec-b1ee-9498cfb621f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11618
95935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1161895935
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1207393067
Short name T333
Test name
Test status
Simulation time 53210995852 ps
CPU time 1311.66 seconds
Started Jun 23 06:42:18 PM PDT 24
Finished Jun 23 07:04:11 PM PDT 24
Peak memory 281912 kb
Host smart-bf1d42d1-30e1-4b87-a107-8966aea099b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207393067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1207393067
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2827916721
Short name T66
Test name
Test status
Simulation time 120569821048 ps
CPU time 1660.81 seconds
Started Jun 23 06:42:18 PM PDT 24
Finished Jun 23 07:09:59 PM PDT 24
Peak memory 273032 kb
Host smart-2d9a65cb-2590-47bb-947d-aacd2a07ccb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827916721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2827916721
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2139433968
Short name T459
Test name
Test status
Simulation time 3321438169 ps
CPU time 127.09 seconds
Started Jun 23 06:42:19 PM PDT 24
Finished Jun 23 06:44:27 PM PDT 24
Peak memory 255096 kb
Host smart-4ff99bfe-2c71-4436-88ab-1e693762e879
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139433968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2139433968
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.318346918
Short name T365
Test name
Test status
Simulation time 462087533 ps
CPU time 29.13 seconds
Started Jun 23 06:42:16 PM PDT 24
Finished Jun 23 06:42:46 PM PDT 24
Peak memory 256716 kb
Host smart-7ceb598d-1340-47f1-bb0d-27d66b2d9861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31834
6918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.318346918
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.437341076
Short name T106
Test name
Test status
Simulation time 1224389349 ps
CPU time 29.17 seconds
Started Jun 23 06:42:18 PM PDT 24
Finished Jun 23 06:42:48 PM PDT 24
Peak memory 247996 kb
Host smart-4e1d66ad-0756-4a14-895e-409b6847732a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43734
1076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.437341076
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2173804290
Short name T486
Test name
Test status
Simulation time 376831268 ps
CPU time 26.9 seconds
Started Jun 23 06:42:20 PM PDT 24
Finished Jun 23 06:42:47 PM PDT 24
Peak memory 249112 kb
Host smart-f17401d5-c5c2-4461-899c-f0e9247c447d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21738
04290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2173804290
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1287453965
Short name T581
Test name
Test status
Simulation time 435914296141 ps
CPU time 2369.39 seconds
Started Jun 23 06:42:26 PM PDT 24
Finished Jun 23 07:21:56 PM PDT 24
Peak memory 284912 kb
Host smart-97fd25ad-8814-48f3-afd9-82f820c9bb4d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287453965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1287453965
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.3929935438
Short name T512
Test name
Test status
Simulation time 12503212162 ps
CPU time 882.38 seconds
Started Jun 23 06:42:20 PM PDT 24
Finished Jun 23 06:57:03 PM PDT 24
Peak memory 273872 kb
Host smart-9d723485-61f0-4332-a681-e9c8562e58cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929935438 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.3929935438
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2844382991
Short name T711
Test name
Test status
Simulation time 3392711652 ps
CPU time 216.33 seconds
Started Jun 23 06:42:18 PM PDT 24
Finished Jun 23 06:45:55 PM PDT 24
Peak memory 250440 kb
Host smart-85d8bbbc-e7a1-41aa-900b-0e079f0d6bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28443
82991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2844382991
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.745232754
Short name T617
Test name
Test status
Simulation time 7244185342 ps
CPU time 64.95 seconds
Started Jun 23 06:42:21 PM PDT 24
Finished Jun 23 06:43:27 PM PDT 24
Peak memory 257372 kb
Host smart-e11bd308-ab8d-4c6b-a266-3f624aa8e41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74523
2754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.745232754
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.993776274
Short name T685
Test name
Test status
Simulation time 74274398648 ps
CPU time 1225.55 seconds
Started Jun 23 06:42:21 PM PDT 24
Finished Jun 23 07:02:47 PM PDT 24
Peak memory 265564 kb
Host smart-b87fb80e-4b7d-4d6e-a01f-e74f8e6f67f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993776274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.993776274
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.4201985704
Short name T29
Test name
Test status
Simulation time 116975113260 ps
CPU time 1749.69 seconds
Started Jun 23 06:42:19 PM PDT 24
Finished Jun 23 07:11:29 PM PDT 24
Peak memory 282304 kb
Host smart-6b18f003-6ed9-4ee7-825a-d731bf08daf7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201985704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.4201985704
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.881727903
Short name T305
Test name
Test status
Simulation time 113127937786 ps
CPU time 481.12 seconds
Started Jun 23 06:42:18 PM PDT 24
Finished Jun 23 06:50:20 PM PDT 24
Peak memory 248296 kb
Host smart-f2c1f21d-81a7-4298-914d-44c182053849
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881727903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.881727903
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3427962475
Short name T597
Test name
Test status
Simulation time 442015721 ps
CPU time 25.24 seconds
Started Jun 23 06:42:17 PM PDT 24
Finished Jun 23 06:42:43 PM PDT 24
Peak memory 254932 kb
Host smart-ed263082-9774-456e-9b9f-4e56c340b3d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34279
62475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3427962475
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.658675770
Short name T74
Test name
Test status
Simulation time 1290542459 ps
CPU time 31.16 seconds
Started Jun 23 06:42:26 PM PDT 24
Finished Jun 23 06:42:57 PM PDT 24
Peak memory 250060 kb
Host smart-ac38a4e0-5489-418f-a547-982bc15998b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65867
5770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.658675770
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1044032888
Short name T671
Test name
Test status
Simulation time 1652201780 ps
CPU time 27.21 seconds
Started Jun 23 06:42:20 PM PDT 24
Finished Jun 23 06:42:48 PM PDT 24
Peak memory 248288 kb
Host smart-428c1161-9103-477c-985b-5fd4f32281dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10440
32888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1044032888
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.396234951
Short name T393
Test name
Test status
Simulation time 239430040 ps
CPU time 8.35 seconds
Started Jun 23 06:42:15 PM PDT 24
Finished Jun 23 06:42:24 PM PDT 24
Peak memory 257276 kb
Host smart-70f1027c-9d99-44bc-9ed0-f19368c8d93f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39623
4951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.396234951
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3900103091
Short name T440
Test name
Test status
Simulation time 10244589604 ps
CPU time 162.25 seconds
Started Jun 23 06:42:19 PM PDT 24
Finished Jun 23 06:45:01 PM PDT 24
Peak memory 257248 kb
Host smart-418cad30-5d6d-49e4-bfa3-451ac9fbd2c6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900103091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3900103091
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1132419702
Short name T472
Test name
Test status
Simulation time 73955196652 ps
CPU time 1707.12 seconds
Started Jun 23 06:42:23 PM PDT 24
Finished Jun 23 07:10:50 PM PDT 24
Peak memory 289276 kb
Host smart-1f8c5b7f-160d-41c6-9b9a-9ad559a8107a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132419702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1132419702
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.647625996
Short name T598
Test name
Test status
Simulation time 4784978521 ps
CPU time 148.42 seconds
Started Jun 23 06:42:25 PM PDT 24
Finished Jun 23 06:44:54 PM PDT 24
Peak memory 252328 kb
Host smart-e09aac84-36e8-4af4-b575-c41da783951a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64762
5996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.647625996
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2555060872
Short name T61
Test name
Test status
Simulation time 1955863751 ps
CPU time 32.76 seconds
Started Jun 23 06:42:20 PM PDT 24
Finished Jun 23 06:42:53 PM PDT 24
Peak memory 256384 kb
Host smart-17d14cb5-c1ca-4c78-ab39-f117131563a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25550
60872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2555060872
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1527725651
Short name T637
Test name
Test status
Simulation time 179699549678 ps
CPU time 3149.21 seconds
Started Jun 23 06:42:24 PM PDT 24
Finished Jun 23 07:34:54 PM PDT 24
Peak memory 289516 kb
Host smart-74f582e1-f144-46c5-ae02-eaee3e8d25c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527725651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1527725651
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.856011327
Short name T698
Test name
Test status
Simulation time 175348537746 ps
CPU time 2806.09 seconds
Started Jun 23 06:42:25 PM PDT 24
Finished Jun 23 07:29:11 PM PDT 24
Peak memory 289832 kb
Host smart-63e0bb5f-eaed-431c-9eb4-673cb37f13c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856011327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.856011327
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.514813703
Short name T400
Test name
Test status
Simulation time 378582589 ps
CPU time 19.47 seconds
Started Jun 23 06:42:19 PM PDT 24
Finished Jun 23 06:42:39 PM PDT 24
Peak memory 256564 kb
Host smart-45f8fe90-4145-4fbc-aec6-26c25f4d400a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51481
3703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.514813703
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.210783047
Short name T646
Test name
Test status
Simulation time 680487684 ps
CPU time 33.63 seconds
Started Jun 23 06:42:22 PM PDT 24
Finished Jun 23 06:42:56 PM PDT 24
Peak memory 249436 kb
Host smart-342c244a-db07-492a-8bdb-9f1707aa6d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21078
3047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.210783047
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1395399106
Short name T630
Test name
Test status
Simulation time 357429243 ps
CPU time 14.9 seconds
Started Jun 23 06:42:23 PM PDT 24
Finished Jun 23 06:42:38 PM PDT 24
Peak memory 256460 kb
Host smart-592f43a4-a2c2-4d2e-b975-8c9f2202a3ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13953
99106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1395399106
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3329098632
Short name T115
Test name
Test status
Simulation time 524303369 ps
CPU time 29.34 seconds
Started Jun 23 06:42:18 PM PDT 24
Finished Jun 23 06:42:49 PM PDT 24
Peak memory 249148 kb
Host smart-a86f7209-0c68-41d8-8f93-5990d0d0e8a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33290
98632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3329098632
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.736443675
Short name T644
Test name
Test status
Simulation time 16783676717 ps
CPU time 1607.98 seconds
Started Jun 23 06:42:23 PM PDT 24
Finished Jun 23 07:09:12 PM PDT 24
Peak memory 287012 kb
Host smart-4cb2cbcd-a010-4663-9778-3b49250c7b31
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736443675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.736443675
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.4221894573
Short name T679
Test name
Test status
Simulation time 47882239968 ps
CPU time 953.98 seconds
Started Jun 23 06:42:26 PM PDT 24
Finished Jun 23 06:58:21 PM PDT 24
Peak memory 273700 kb
Host smart-492c527f-0db0-4b16-a435-70808b491dd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221894573 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.4221894573
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.4110038535
Short name T483
Test name
Test status
Simulation time 29144109733 ps
CPU time 1494.31 seconds
Started Jun 23 06:42:26 PM PDT 24
Finished Jun 23 07:07:21 PM PDT 24
Peak memory 273752 kb
Host smart-0af975b0-6bb8-47cb-85ec-add2e42e2b16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110038535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.4110038535
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3267565907
Short name T392
Test name
Test status
Simulation time 4108260603 ps
CPU time 218.32 seconds
Started Jun 23 06:42:26 PM PDT 24
Finished Jun 23 06:46:04 PM PDT 24
Peak memory 257324 kb
Host smart-a721aadc-fe40-4414-8801-56767d362df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32675
65907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3267565907
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.4203099812
Short name T220
Test name
Test status
Simulation time 369254540 ps
CPU time 24.53 seconds
Started Jun 23 06:42:27 PM PDT 24
Finished Jun 23 06:42:52 PM PDT 24
Peak memory 255952 kb
Host smart-acfca993-9a4a-4de9-b03b-7e9a0ee31fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42030
99812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.4203099812
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1716513142
Short name T568
Test name
Test status
Simulation time 10925581990 ps
CPU time 1122.73 seconds
Started Jun 23 06:42:23 PM PDT 24
Finished Jun 23 07:01:07 PM PDT 24
Peak memory 289212 kb
Host smart-3fe0a421-dbda-4bb2-b52a-61b331d83f61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716513142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1716513142
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3697213075
Short name T697
Test name
Test status
Simulation time 436357501 ps
CPU time 24.09 seconds
Started Jun 23 06:42:24 PM PDT 24
Finished Jun 23 06:42:48 PM PDT 24
Peak memory 249032 kb
Host smart-eacaef65-1a37-4263-9a9d-5dac0a6a77df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36972
13075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3697213075
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.4235544028
Short name T212
Test name
Test status
Simulation time 434949080 ps
CPU time 43.51 seconds
Started Jun 23 06:42:29 PM PDT 24
Finished Jun 23 06:43:13 PM PDT 24
Peak memory 248056 kb
Host smart-9778c13b-f5af-4d89-91b8-b8780f3b59f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42355
44028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.4235544028
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3855641843
Short name T219
Test name
Test status
Simulation time 1779905411 ps
CPU time 13.97 seconds
Started Jun 23 06:42:25 PM PDT 24
Finished Jun 23 06:42:40 PM PDT 24
Peak memory 249036 kb
Host smart-9eba0da8-86fe-4e62-960e-ff99bdfdb16e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38556
41843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3855641843
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3195280211
Short name T463
Test name
Test status
Simulation time 424228070265 ps
CPU time 1619.11 seconds
Started Jun 23 06:42:29 PM PDT 24
Finished Jun 23 07:09:29 PM PDT 24
Peak memory 273748 kb
Host smart-9e6a3468-32ac-4f0a-b141-e1f2995879cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195280211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3195280211
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.4034185032
Short name T379
Test name
Test status
Simulation time 114639574 ps
CPU time 10.82 seconds
Started Jun 23 06:42:23 PM PDT 24
Finished Jun 23 06:42:35 PM PDT 24
Peak memory 255388 kb
Host smart-5cd5422b-c127-4f94-9079-2feca43ca40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40341
85032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.4034185032
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1882176798
Short name T329
Test name
Test status
Simulation time 20090380366 ps
CPU time 1141.26 seconds
Started Jun 23 06:42:28 PM PDT 24
Finished Jun 23 07:01:30 PM PDT 24
Peak memory 273748 kb
Host smart-c4344874-d2d3-445b-978d-c9c59aa7b148
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882176798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1882176798
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1160498708
Short name T5
Test name
Test status
Simulation time 45033067759 ps
CPU time 1092.94 seconds
Started Jun 23 06:42:29 PM PDT 24
Finished Jun 23 07:00:42 PM PDT 24
Peak memory 286548 kb
Host smart-242e9f00-e0e3-4601-a2d0-2881a83bdfc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160498708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1160498708
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.628958064
Short name T321
Test name
Test status
Simulation time 9757386591 ps
CPU time 365.43 seconds
Started Jun 23 06:42:30 PM PDT 24
Finished Jun 23 06:48:36 PM PDT 24
Peak memory 248756 kb
Host smart-fe3ab78c-c084-4c07-8229-73133bdeb8f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628958064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.628958064
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3359456036
Short name T684
Test name
Test status
Simulation time 1369000961 ps
CPU time 26.78 seconds
Started Jun 23 06:42:27 PM PDT 24
Finished Jun 23 06:42:54 PM PDT 24
Peak memory 256808 kb
Host smart-3e853889-d833-41ac-92e7-5e34946d91a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33594
56036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3359456036
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.1171671583
Short name T114
Test name
Test status
Simulation time 126370808 ps
CPU time 16.44 seconds
Started Jun 23 06:42:24 PM PDT 24
Finished Jun 23 06:42:41 PM PDT 24
Peak memory 256436 kb
Host smart-151a35b6-ab25-4618-9ddc-892e5387b30f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11716
71583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1171671583
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.468885601
Short name T222
Test name
Test status
Simulation time 397666150 ps
CPU time 30.63 seconds
Started Jun 23 06:42:26 PM PDT 24
Finished Jun 23 06:42:57 PM PDT 24
Peak memory 256020 kb
Host smart-e1a74689-03a5-4ed4-92e2-8a6d9869e383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46888
5601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.468885601
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1250639049
Short name T694
Test name
Test status
Simulation time 2594155185 ps
CPU time 45.21 seconds
Started Jun 23 06:42:28 PM PDT 24
Finished Jun 23 06:43:14 PM PDT 24
Peak memory 256468 kb
Host smart-e3a15a0c-90c7-40df-8382-eb08fae9656a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12506
39049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1250639049
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2728395626
Short name T213
Test name
Test status
Simulation time 209193767474 ps
CPU time 2938.96 seconds
Started Jun 23 06:42:28 PM PDT 24
Finished Jun 23 07:31:28 PM PDT 24
Peak memory 297884 kb
Host smart-7925ff5b-d5a2-450a-875d-5c5a5bcd32e7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728395626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2728395626
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2600601270
Short name T675
Test name
Test status
Simulation time 73815724224 ps
CPU time 1792.86 seconds
Started Jun 23 06:42:30 PM PDT 24
Finished Jun 23 07:12:23 PM PDT 24
Peak memory 273168 kb
Host smart-2b169dc8-ad97-475b-b38e-83ee9f2767c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600601270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2600601270
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.183770965
Short name T242
Test name
Test status
Simulation time 1495737820 ps
CPU time 87.34 seconds
Started Jun 23 06:42:30 PM PDT 24
Finished Jun 23 06:43:58 PM PDT 24
Peak memory 257168 kb
Host smart-1d508f7c-92a7-4c8e-90e0-0786b32bc892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18377
0965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.183770965
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2976821577
Short name T633
Test name
Test status
Simulation time 2257900200 ps
CPU time 61 seconds
Started Jun 23 06:42:30 PM PDT 24
Finished Jun 23 06:43:31 PM PDT 24
Peak memory 257376 kb
Host smart-83f38fcc-f8d9-4e04-be62-72969ac494c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29768
21577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2976821577
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3168711377
Short name T343
Test name
Test status
Simulation time 57637394374 ps
CPU time 1159.37 seconds
Started Jun 23 06:42:30 PM PDT 24
Finished Jun 23 07:01:50 PM PDT 24
Peak memory 289348 kb
Host smart-1de82af4-9d6b-48a1-b522-3b02a0fc253d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168711377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3168711377
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.4248449189
Short name T260
Test name
Test status
Simulation time 27485560709 ps
CPU time 1491.47 seconds
Started Jun 23 06:42:31 PM PDT 24
Finished Jun 23 07:07:23 PM PDT 24
Peak memory 273252 kb
Host smart-97f11541-6baa-47ed-a65d-7234f321b872
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248449189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.4248449189
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3846377739
Short name T613
Test name
Test status
Simulation time 2464482308 ps
CPU time 97.64 seconds
Started Jun 23 06:42:29 PM PDT 24
Finished Jun 23 06:44:07 PM PDT 24
Peak memory 248828 kb
Host smart-1abdaa65-b89f-4514-bbbc-273ac7a77977
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846377739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3846377739
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1986674664
Short name T651
Test name
Test status
Simulation time 258695258 ps
CPU time 13.99 seconds
Started Jun 23 06:42:31 PM PDT 24
Finished Jun 23 06:42:46 PM PDT 24
Peak memory 257280 kb
Host smart-217830c9-fbff-40f9-9437-df2ec6d430b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19866
74664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1986674664
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2268494067
Short name T564
Test name
Test status
Simulation time 794808849 ps
CPU time 33.63 seconds
Started Jun 23 06:42:31 PM PDT 24
Finished Jun 23 06:43:05 PM PDT 24
Peak memory 256092 kb
Host smart-41793c63-07ab-43f6-97dc-b3e48ea8df68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22684
94067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2268494067
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2833895790
Short name T610
Test name
Test status
Simulation time 596343335 ps
CPU time 20.11 seconds
Started Jun 23 06:42:30 PM PDT 24
Finished Jun 23 06:42:51 PM PDT 24
Peak memory 255900 kb
Host smart-132da527-2007-443e-81c1-de0ba4e43576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28338
95790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2833895790
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2598188915
Short name T413
Test name
Test status
Simulation time 713363668 ps
CPU time 42.99 seconds
Started Jun 23 06:42:29 PM PDT 24
Finished Jun 23 06:43:13 PM PDT 24
Peak memory 249108 kb
Host smart-975f4519-8fd4-4538-a455-30cf2af68587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25981
88915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2598188915
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.1880462341
Short name T258
Test name
Test status
Simulation time 264999261241 ps
CPU time 6402.13 seconds
Started Jun 23 06:42:32 PM PDT 24
Finished Jun 23 08:29:15 PM PDT 24
Peak memory 323060 kb
Host smart-059107b3-5260-4462-aef3-108de2e52e9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880462341 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.1880462341
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2556564893
Short name T110
Test name
Test status
Simulation time 36065326322 ps
CPU time 1114.69 seconds
Started Jun 23 06:42:30 PM PDT 24
Finished Jun 23 07:01:06 PM PDT 24
Peak memory 265500 kb
Host smart-5c58a63e-91d5-4083-bc80-7a2504c43b91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556564893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2556564893
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.3431623885
Short name T529
Test name
Test status
Simulation time 3592849436 ps
CPU time 195.07 seconds
Started Jun 23 06:42:29 PM PDT 24
Finished Jun 23 06:45:45 PM PDT 24
Peak memory 257344 kb
Host smart-c1fb1d29-982f-47c4-9201-3b1e3aea043b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34316
23885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3431623885
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1248270838
Short name T279
Test name
Test status
Simulation time 732348994 ps
CPU time 47.52 seconds
Started Jun 23 06:42:29 PM PDT 24
Finished Jun 23 06:43:16 PM PDT 24
Peak memory 249116 kb
Host smart-bc4c52ea-4207-4e06-8f0e-96f0986544d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12482
70838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1248270838
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2576031966
Short name T30
Test name
Test status
Simulation time 5998066065 ps
CPU time 527.44 seconds
Started Jun 23 06:42:31 PM PDT 24
Finished Jun 23 06:51:18 PM PDT 24
Peak memory 273000 kb
Host smart-1eb450da-de71-43a9-9453-5e783a9014ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576031966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2576031966
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.890506631
Short name T454
Test name
Test status
Simulation time 4962840099 ps
CPU time 197.73 seconds
Started Jun 23 06:42:30 PM PDT 24
Finished Jun 23 06:45:48 PM PDT 24
Peak memory 248456 kb
Host smart-190bd94c-a038-45b6-b82d-0eb2b89eb33c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890506631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.890506631
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2666136675
Short name T48
Test name
Test status
Simulation time 242279903 ps
CPU time 14.31 seconds
Started Jun 23 06:42:28 PM PDT 24
Finished Jun 23 06:42:43 PM PDT 24
Peak memory 257108 kb
Host smart-1f2ba09f-f23e-45ba-807b-e61fd2c3613d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26661
36675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2666136675
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.620840043
Short name T217
Test name
Test status
Simulation time 1651159147 ps
CPU time 28.89 seconds
Started Jun 23 06:42:29 PM PDT 24
Finished Jun 23 06:42:59 PM PDT 24
Peak memory 256144 kb
Host smart-ce4f3527-c70a-42be-a40e-d35f0a0be8f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62084
0043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.620840043
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.4117830269
Short name T294
Test name
Test status
Simulation time 12824217895 ps
CPU time 48.77 seconds
Started Jun 23 06:42:30 PM PDT 24
Finished Jun 23 06:43:19 PM PDT 24
Peak memory 249332 kb
Host smart-ffffcaa2-b009-4974-a685-b2e4935f8064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41178
30269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.4117830269
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.737539506
Short name T487
Test name
Test status
Simulation time 291070772 ps
CPU time 27.52 seconds
Started Jun 23 06:42:32 PM PDT 24
Finished Jun 23 06:42:59 PM PDT 24
Peak memory 257288 kb
Host smart-4854991b-6115-4961-89eb-96b6bad6cea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73753
9506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.737539506
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.1230690726
Short name T100
Test name
Test status
Simulation time 252181998168 ps
CPU time 3869.83 seconds
Started Jun 23 06:42:36 PM PDT 24
Finished Jun 23 07:47:06 PM PDT 24
Peak memory 301084 kb
Host smart-bcc53ca9-63a0-4662-a1ca-5f91a7f9d518
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230690726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.1230690726
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3957555467
Short name T460
Test name
Test status
Simulation time 33622177347 ps
CPU time 2275.02 seconds
Started Jun 23 06:42:36 PM PDT 24
Finished Jun 23 07:20:32 PM PDT 24
Peak memory 289616 kb
Host smart-1ff79814-20c5-4290-881b-24d429a7d844
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957555467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3957555467
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2960812564
Short name T503
Test name
Test status
Simulation time 3414093468 ps
CPU time 31.73 seconds
Started Jun 23 06:42:35 PM PDT 24
Finished Jun 23 06:43:08 PM PDT 24
Peak memory 249136 kb
Host smart-f5197725-d2f5-4f20-b8b5-64b77578dc33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29608
12564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2960812564
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.882923841
Short name T701
Test name
Test status
Simulation time 607464315 ps
CPU time 10.25 seconds
Started Jun 23 06:42:35 PM PDT 24
Finished Jun 23 06:42:45 PM PDT 24
Peak memory 249124 kb
Host smart-05fa8e7e-2076-448d-b535-ca8fd53b914a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88292
3841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.882923841
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.401574349
Short name T57
Test name
Test status
Simulation time 17771388121 ps
CPU time 1264.88 seconds
Started Jun 23 06:42:34 PM PDT 24
Finished Jun 23 07:03:39 PM PDT 24
Peak memory 289932 kb
Host smart-01caec6b-b3cc-407f-bbc1-bbb1e677bce1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401574349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.401574349
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3564520217
Short name T104
Test name
Test status
Simulation time 37938923323 ps
CPU time 2541.27 seconds
Started Jun 23 06:42:33 PM PDT 24
Finished Jun 23 07:24:55 PM PDT 24
Peak memory 289148 kb
Host smart-38ee2cf7-dba5-4e83-9595-34cf088a77b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564520217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3564520217
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.4293553481
Short name T388
Test name
Test status
Simulation time 190359744 ps
CPU time 22.29 seconds
Started Jun 23 06:42:35 PM PDT 24
Finished Jun 23 06:42:58 PM PDT 24
Peak memory 249128 kb
Host smart-23ef510f-5873-4dfa-8ca8-dacc9eb97235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42935
53481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.4293553481
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1533933599
Short name T695
Test name
Test status
Simulation time 339059150 ps
CPU time 11.73 seconds
Started Jun 23 06:42:33 PM PDT 24
Finished Jun 23 06:42:45 PM PDT 24
Peak memory 251700 kb
Host smart-a6f2985b-6cb5-4dcb-b1e1-30408395a7a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15339
33599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1533933599
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1095093046
Short name T215
Test name
Test status
Simulation time 4496470036 ps
CPU time 71.3 seconds
Started Jun 23 06:42:34 PM PDT 24
Finished Jun 23 06:43:46 PM PDT 24
Peak memory 256152 kb
Host smart-10457a15-d23c-4649-8d82-4fa481256e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10950
93046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1095093046
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1530341519
Short name T81
Test name
Test status
Simulation time 287341266 ps
CPU time 14.16 seconds
Started Jun 23 06:42:35 PM PDT 24
Finished Jun 23 06:42:50 PM PDT 24
Peak memory 249112 kb
Host smart-57e5bdba-7152-472d-b012-d12e5c2bb9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15303
41519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1530341519
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2887318849
Short name T437
Test name
Test status
Simulation time 2444443314 ps
CPU time 153.27 seconds
Started Jun 23 06:42:34 PM PDT 24
Finished Jun 23 06:45:08 PM PDT 24
Peak memory 257308 kb
Host smart-dc28b8c6-cf53-499a-bb5c-37521018ced4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887318849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2887318849
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2380816771
Short name T193
Test name
Test status
Simulation time 19466688 ps
CPU time 2.33 seconds
Started Jun 23 06:41:17 PM PDT 24
Finished Jun 23 06:41:20 PM PDT 24
Peak memory 249296 kb
Host smart-ce8d4470-0f19-4f01-a522-a72798baab53
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2380816771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2380816771
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.4200151776
Short name T562
Test name
Test status
Simulation time 23277814116 ps
CPU time 1387.34 seconds
Started Jun 23 06:41:20 PM PDT 24
Finished Jun 23 07:04:28 PM PDT 24
Peak memory 273472 kb
Host smart-d176db75-e5ba-4f87-9738-ef9b040525af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200151776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.4200151776
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3163542928
Short name T479
Test name
Test status
Simulation time 229304172 ps
CPU time 12.59 seconds
Started Jun 23 06:41:17 PM PDT 24
Finished Jun 23 06:41:30 PM PDT 24
Peak memory 251916 kb
Host smart-fc92e0f7-cf19-463a-a288-66a3c60fc2c4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3163542928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3163542928
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1228106544
Short name T113
Test name
Test status
Simulation time 1458914816 ps
CPU time 100.48 seconds
Started Jun 23 06:41:20 PM PDT 24
Finished Jun 23 06:43:02 PM PDT 24
Peak memory 257316 kb
Host smart-3fe7c50c-38f1-4896-b202-eb59c7fd0f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12281
06544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1228106544
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2321815172
Short name T496
Test name
Test status
Simulation time 2239720421 ps
CPU time 28.58 seconds
Started Jun 23 06:41:15 PM PDT 24
Finished Jun 23 06:41:44 PM PDT 24
Peak memory 249196 kb
Host smart-efdf3699-899c-4e96-bed7-420caf2950bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23218
15172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2321815172
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2860453575
Short name T623
Test name
Test status
Simulation time 7549622410 ps
CPU time 679.29 seconds
Started Jun 23 06:41:20 PM PDT 24
Finished Jun 23 06:52:41 PM PDT 24
Peak memory 266596 kb
Host smart-75dcc34a-2cda-44f1-8db2-11132c0759bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860453575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2860453575
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.866067218
Short name T318
Test name
Test status
Simulation time 14075055945 ps
CPU time 580.75 seconds
Started Jun 23 06:41:21 PM PDT 24
Finished Jun 23 06:51:03 PM PDT 24
Peak memory 255844 kb
Host smart-01ee4cf2-c8cc-4680-beff-13f4967691d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866067218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.866067218
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1867843146
Short name T224
Test name
Test status
Simulation time 225546123 ps
CPU time 6.56 seconds
Started Jun 23 06:41:16 PM PDT 24
Finished Jun 23 06:41:23 PM PDT 24
Peak memory 249096 kb
Host smart-a4d7ecaf-3dad-42da-b5d3-f85279067ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18678
43146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1867843146
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1512925715
Short name T656
Test name
Test status
Simulation time 469127819 ps
CPU time 34.5 seconds
Started Jun 23 06:41:21 PM PDT 24
Finished Jun 23 06:41:56 PM PDT 24
Peak memory 249328 kb
Host smart-cd09ebb5-2cb5-4385-adb6-7f91f2a96c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15129
25715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1512925715
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1685028331
Short name T31
Test name
Test status
Simulation time 498222191 ps
CPU time 13.89 seconds
Started Jun 23 06:41:17 PM PDT 24
Finished Jun 23 06:41:32 PM PDT 24
Peak memory 269256 kb
Host smart-5e97f642-bce2-4d5d-8fe1-6e41805ec8bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1685028331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1685028331
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.514977712
Short name T90
Test name
Test status
Simulation time 130068766 ps
CPU time 14.28 seconds
Started Jun 23 06:41:21 PM PDT 24
Finished Jun 23 06:41:36 PM PDT 24
Peak memory 256220 kb
Host smart-4f1cb3a0-4053-4661-879d-ccab0b338f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51497
7712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.514977712
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2660621042
Short name T116
Test name
Test status
Simulation time 1546577453 ps
CPU time 7.85 seconds
Started Jun 23 06:41:19 PM PDT 24
Finished Jun 23 06:41:28 PM PDT 24
Peak memory 249104 kb
Host smart-64f3d5a2-6615-403a-ba06-8c239c7e7ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26606
21042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2660621042
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3312194263
Short name T533
Test name
Test status
Simulation time 403284676482 ps
CPU time 1399.3 seconds
Started Jun 23 06:41:23 PM PDT 24
Finished Jun 23 07:04:43 PM PDT 24
Peak memory 281620 kb
Host smart-d1a47811-5ad2-4888-9147-a92659ffb6e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312194263 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3312194263
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3752177858
Short name T670
Test name
Test status
Simulation time 112602361413 ps
CPU time 3181.51 seconds
Started Jun 23 06:42:40 PM PDT 24
Finished Jun 23 07:35:42 PM PDT 24
Peak memory 289772 kb
Host smart-66ca0b46-ab98-4c36-a98f-9647d06fd40c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752177858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3752177858
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1892325099
Short name T550
Test name
Test status
Simulation time 3071652266 ps
CPU time 190.26 seconds
Started Jun 23 06:42:35 PM PDT 24
Finished Jun 23 06:45:46 PM PDT 24
Peak memory 257364 kb
Host smart-b9e00893-7fe5-49c3-b762-57e15a2dc743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18923
25099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1892325099
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.265878995
Short name T420
Test name
Test status
Simulation time 156065279 ps
CPU time 7.75 seconds
Started Jun 23 06:42:34 PM PDT 24
Finished Jun 23 06:42:42 PM PDT 24
Peak memory 249024 kb
Host smart-66aa560a-33cf-45a7-8d27-c0516abc0fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26587
8995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.265878995
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.882969981
Short name T690
Test name
Test status
Simulation time 143767961571 ps
CPU time 2485.75 seconds
Started Jun 23 06:42:40 PM PDT 24
Finished Jun 23 07:24:06 PM PDT 24
Peak memory 289556 kb
Host smart-91f6cc09-46d9-4ce1-8338-012491b06e0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882969981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.882969981
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2614599364
Short name T261
Test name
Test status
Simulation time 72210093038 ps
CPU time 269.98 seconds
Started Jun 23 06:42:39 PM PDT 24
Finished Jun 23 06:47:09 PM PDT 24
Peak memory 248756 kb
Host smart-381c28ba-d74d-4c3a-9b26-2cca015001f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614599364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2614599364
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.42946744
Short name T425
Test name
Test status
Simulation time 938978280 ps
CPU time 18.95 seconds
Started Jun 23 06:42:33 PM PDT 24
Finished Jun 23 06:42:52 PM PDT 24
Peak memory 255800 kb
Host smart-9c6535ee-7784-4938-a10c-ce26bd3a4a0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42946
744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.42946744
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2024010035
Short name T655
Test name
Test status
Simulation time 3838208161 ps
CPU time 59.48 seconds
Started Jun 23 06:42:35 PM PDT 24
Finished Jun 23 06:43:35 PM PDT 24
Peak memory 249132 kb
Host smart-f6bf7d67-fb0e-4b8f-b527-9116a0abae10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20240
10035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2024010035
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1866154316
Short name T119
Test name
Test status
Simulation time 1482219825 ps
CPU time 26.1 seconds
Started Jun 23 06:42:41 PM PDT 24
Finished Jun 23 06:43:08 PM PDT 24
Peak memory 256084 kb
Host smart-ac8deac5-0d57-46ea-94f8-ab6042c0075b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18661
54316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1866154316
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2108823507
Short name T571
Test name
Test status
Simulation time 44779714 ps
CPU time 3.74 seconds
Started Jun 23 06:42:34 PM PDT 24
Finished Jun 23 06:42:38 PM PDT 24
Peak memory 240912 kb
Host smart-f6afbeca-ac3e-43a4-b8fe-cbcaa5b5589a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21088
23507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2108823507
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.3513639583
Short name T276
Test name
Test status
Simulation time 49039338627 ps
CPU time 1306.2 seconds
Started Jun 23 06:42:41 PM PDT 24
Finished Jun 23 07:04:27 PM PDT 24
Peak memory 289932 kb
Host smart-41652b45-efbf-4ed2-9c70-2919f052fa78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513639583 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.3513639583
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1997295706
Short name T92
Test name
Test status
Simulation time 49736989753 ps
CPU time 1769.16 seconds
Started Jun 23 06:42:46 PM PDT 24
Finished Jun 23 07:12:16 PM PDT 24
Peak memory 289428 kb
Host smart-0965f47a-94a7-4f13-bf84-408c66273c8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997295706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1997295706
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2516614599
Short name T18
Test name
Test status
Simulation time 725685471 ps
CPU time 33.42 seconds
Started Jun 23 06:42:45 PM PDT 24
Finished Jun 23 06:43:18 PM PDT 24
Peak memory 249100 kb
Host smart-8af5596f-da2a-49ea-a553-84aa4ba9c8e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25166
14599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2516614599
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1723081433
Short name T53
Test name
Test status
Simulation time 640898941 ps
CPU time 39.6 seconds
Started Jun 23 06:42:40 PM PDT 24
Finished Jun 23 06:43:20 PM PDT 24
Peak memory 257284 kb
Host smart-f767159e-213a-4d07-8fb2-80a70977e71f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17230
81433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1723081433
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.732397860
Short name T335
Test name
Test status
Simulation time 67164585646 ps
CPU time 671.7 seconds
Started Jun 23 06:42:44 PM PDT 24
Finished Jun 23 06:53:56 PM PDT 24
Peak memory 273672 kb
Host smart-5423a809-8b34-435f-9d44-35d900b5f8b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732397860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.732397860
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3484211133
Short name T534
Test name
Test status
Simulation time 33367908825 ps
CPU time 2009.06 seconds
Started Jun 23 06:42:44 PM PDT 24
Finished Jun 23 07:16:14 PM PDT 24
Peak memory 290144 kb
Host smart-072bc4b3-0ac9-40bc-b687-ba4fbce66e08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484211133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3484211133
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1970247476
Short name T304
Test name
Test status
Simulation time 13898057238 ps
CPU time 216.15 seconds
Started Jun 23 06:42:45 PM PDT 24
Finished Jun 23 06:46:22 PM PDT 24
Peak memory 255256 kb
Host smart-48d42763-1e84-4a8e-9ab8-25c19e27fc5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970247476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1970247476
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3399276832
Short name T468
Test name
Test status
Simulation time 436776018 ps
CPU time 23.49 seconds
Started Jun 23 06:42:40 PM PDT 24
Finished Jun 23 06:43:04 PM PDT 24
Peak memory 249232 kb
Host smart-a986543c-f9b4-4640-94b4-6e4617211d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33992
76832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3399276832
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.866906009
Short name T624
Test name
Test status
Simulation time 410915001 ps
CPU time 8.43 seconds
Started Jun 23 06:42:42 PM PDT 24
Finished Jun 23 06:42:51 PM PDT 24
Peak memory 252076 kb
Host smart-09c48711-c2f1-498b-baba-d4a7157dbe2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86690
6009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.866906009
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.181609760
Short name T75
Test name
Test status
Simulation time 1039688356 ps
CPU time 63.37 seconds
Started Jun 23 06:42:45 PM PDT 24
Finished Jun 23 06:43:49 PM PDT 24
Peak memory 255920 kb
Host smart-bb1a7ee0-3969-4028-bbea-c8ba1533c6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18160
9760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.181609760
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2237757031
Short name T621
Test name
Test status
Simulation time 593955501 ps
CPU time 28.08 seconds
Started Jun 23 06:42:40 PM PDT 24
Finished Jun 23 06:43:08 PM PDT 24
Peak memory 249048 kb
Host smart-3cb64fb7-e24c-4265-9b13-be6c823d46d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22377
57031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2237757031
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.4022623839
Short name T256
Test name
Test status
Simulation time 17045178878 ps
CPU time 1539.65 seconds
Started Jun 23 06:42:46 PM PDT 24
Finished Jun 23 07:08:26 PM PDT 24
Peak memory 290120 kb
Host smart-cc9639c9-f77b-4b87-9866-5801b77e4c34
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022623839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.4022623839
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3534417245
Short name T52
Test name
Test status
Simulation time 53375142972 ps
CPU time 2841.49 seconds
Started Jun 23 06:42:44 PM PDT 24
Finished Jun 23 07:30:06 PM PDT 24
Peak memory 289488 kb
Host smart-10c04b65-46b7-418e-b7b2-79dd11c4dd96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534417245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3534417245
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1998900319
Short name T492
Test name
Test status
Simulation time 16927299208 ps
CPU time 275.3 seconds
Started Jun 23 06:42:47 PM PDT 24
Finished Jun 23 06:47:22 PM PDT 24
Peak memory 257436 kb
Host smart-d03727f9-b5bc-41c5-b2c0-450b927c19fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19989
00319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1998900319
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.4031410313
Short name T658
Test name
Test status
Simulation time 141866584 ps
CPU time 6.21 seconds
Started Jun 23 06:42:46 PM PDT 24
Finished Jun 23 06:42:53 PM PDT 24
Peak memory 249452 kb
Host smart-3abec7a6-ceef-4e58-82fd-b8915012cfb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40314
10313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.4031410313
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3989491409
Short name T707
Test name
Test status
Simulation time 28759510371 ps
CPU time 1568.82 seconds
Started Jun 23 06:42:44 PM PDT 24
Finished Jun 23 07:08:54 PM PDT 24
Peak memory 273684 kb
Host smart-7c5cfe5a-c99d-4597-92a3-92fa3e7c83f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989491409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3989491409
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1067562313
Short name T262
Test name
Test status
Simulation time 103535550228 ps
CPU time 1301.27 seconds
Started Jun 23 06:42:48 PM PDT 24
Finished Jun 23 07:04:29 PM PDT 24
Peak memory 289796 kb
Host smart-5bcf3bd6-1401-49a1-af73-264a1b66dd9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067562313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1067562313
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.352633728
Short name T313
Test name
Test status
Simulation time 14469763875 ps
CPU time 586.89 seconds
Started Jun 23 06:42:45 PM PDT 24
Finished Jun 23 06:52:32 PM PDT 24
Peak memory 247592 kb
Host smart-f0090fb6-fea4-4b56-9e4e-664411e84ee7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352633728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.352633728
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1937957788
Short name T455
Test name
Test status
Simulation time 193790566 ps
CPU time 8.38 seconds
Started Jun 23 06:42:45 PM PDT 24
Finished Jun 23 06:42:53 PM PDT 24
Peak memory 253132 kb
Host smart-5c636d78-acdc-445d-a323-0aa75930afa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19379
57788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1937957788
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2975146739
Short name T98
Test name
Test status
Simulation time 497497405 ps
CPU time 36.22 seconds
Started Jun 23 06:42:43 PM PDT 24
Finished Jun 23 06:43:19 PM PDT 24
Peak memory 249064 kb
Host smart-f5e17e77-915a-4f48-b42a-b80f35aa2fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29751
46739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2975146739
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.995360492
Short name T231
Test name
Test status
Simulation time 717985501 ps
CPU time 43.01 seconds
Started Jun 23 06:42:45 PM PDT 24
Finished Jun 23 06:43:29 PM PDT 24
Peak memory 256584 kb
Host smart-6e2eb449-3aaf-4e19-9663-554216741aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99536
0492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.995360492
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.4270048429
Short name T618
Test name
Test status
Simulation time 184465586 ps
CPU time 5.07 seconds
Started Jun 23 06:42:45 PM PDT 24
Finished Jun 23 06:42:50 PM PDT 24
Peak memory 257264 kb
Host smart-b2c4b518-25d9-4a56-bb02-571b38e67999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42700
48429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.4270048429
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.46753386
Short name T266
Test name
Test status
Simulation time 51779999511 ps
CPU time 5443.64 seconds
Started Jun 23 06:42:52 PM PDT 24
Finished Jun 23 08:13:36 PM PDT 24
Peak memory 334336 kb
Host smart-703dac18-87b8-4a78-bd6d-6cbbff6ec8c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46753386 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.46753386
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2771362182
Short name T121
Test name
Test status
Simulation time 102868792381 ps
CPU time 1636.44 seconds
Started Jun 23 06:42:54 PM PDT 24
Finished Jun 23 07:10:11 PM PDT 24
Peak memory 289052 kb
Host smart-0123824f-2f07-4f3a-8878-9e7a98daea45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771362182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2771362182
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3691932255
Short name T538
Test name
Test status
Simulation time 822452113 ps
CPU time 51.89 seconds
Started Jun 23 06:42:51 PM PDT 24
Finished Jun 23 06:43:43 PM PDT 24
Peak memory 257264 kb
Host smart-e6ac8985-bae9-4081-a9d7-834739a8084e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36919
32255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3691932255
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.4153163311
Short name T76
Test name
Test status
Simulation time 247119373 ps
CPU time 17.02 seconds
Started Jun 23 06:42:50 PM PDT 24
Finished Jun 23 06:43:07 PM PDT 24
Peak memory 249316 kb
Host smart-2d0a285a-90f3-4347-bc7b-c46225f85e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41531
63311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.4153163311
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3039232768
Short name T693
Test name
Test status
Simulation time 200558660534 ps
CPU time 753.16 seconds
Started Jun 23 06:42:52 PM PDT 24
Finished Jun 23 06:55:26 PM PDT 24
Peak memory 273196 kb
Host smart-5f98de94-258c-4561-9f72-13d893e7c0ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039232768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3039232768
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2380552088
Short name T438
Test name
Test status
Simulation time 83069642554 ps
CPU time 2244.1 seconds
Started Jun 23 06:42:50 PM PDT 24
Finished Jun 23 07:20:15 PM PDT 24
Peak memory 283632 kb
Host smart-eb466bee-6ad9-433c-91c0-0df0ebd88d4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380552088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2380552088
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1723685355
Short name T308
Test name
Test status
Simulation time 151813380671 ps
CPU time 542.5 seconds
Started Jun 23 06:42:50 PM PDT 24
Finished Jun 23 06:51:54 PM PDT 24
Peak memory 255224 kb
Host smart-41c4eaa9-f2ea-4b0d-90d5-e688df4112d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723685355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1723685355
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.4168061655
Short name T417
Test name
Test status
Simulation time 1572780718 ps
CPU time 11.77 seconds
Started Jun 23 06:42:51 PM PDT 24
Finished Jun 23 06:43:04 PM PDT 24
Peak memory 252852 kb
Host smart-8516683c-7719-47f8-a121-b58987a18558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41680
61655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.4168061655
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.277625172
Short name T524
Test name
Test status
Simulation time 812340192 ps
CPU time 36.06 seconds
Started Jun 23 06:42:49 PM PDT 24
Finished Jun 23 06:43:26 PM PDT 24
Peak memory 249036 kb
Host smart-0603f942-886c-4a06-9967-dedfc4dcecdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27762
5172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.277625172
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1248392779
Short name T494
Test name
Test status
Simulation time 291912007 ps
CPU time 19.14 seconds
Started Jun 23 06:42:53 PM PDT 24
Finished Jun 23 06:43:12 PM PDT 24
Peak memory 248020 kb
Host smart-8b48104f-80ec-4eac-ad8a-486c675873bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12483
92779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1248392779
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1306423514
Short name T428
Test name
Test status
Simulation time 1122906813 ps
CPU time 23.1 seconds
Started Jun 23 06:42:50 PM PDT 24
Finished Jun 23 06:43:14 PM PDT 24
Peak memory 256824 kb
Host smart-ae964bcb-450c-4777-9b4f-b02b2c7c268f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13064
23514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1306423514
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.4199232422
Short name T46
Test name
Test status
Simulation time 77432206688 ps
CPU time 2161.93 seconds
Started Jun 23 06:42:53 PM PDT 24
Finished Jun 23 07:18:56 PM PDT 24
Peak memory 306076 kb
Host smart-76c98425-9ba7-4067-bf5f-31ef14767d2f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199232422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.4199232422
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1783434298
Short name T418
Test name
Test status
Simulation time 17520509586 ps
CPU time 717.11 seconds
Started Jun 23 06:42:54 PM PDT 24
Finished Jun 23 06:54:51 PM PDT 24
Peak memory 265580 kb
Host smart-0960a945-5379-4283-892f-f5bc7ada6034
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783434298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1783434298
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2560077792
Short name T444
Test name
Test status
Simulation time 671047373 ps
CPU time 41.07 seconds
Started Jun 23 06:42:51 PM PDT 24
Finished Jun 23 06:43:33 PM PDT 24
Peak memory 257296 kb
Host smart-1ae063a4-76f4-4b07-9cf7-b85414a639f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25600
77792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2560077792
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1313124331
Short name T569
Test name
Test status
Simulation time 51117365 ps
CPU time 4.18 seconds
Started Jun 23 06:42:51 PM PDT 24
Finished Jun 23 06:42:55 PM PDT 24
Peak memory 239832 kb
Host smart-1d27eb78-e17e-4ef9-a540-ec3eda313b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13131
24331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1313124331
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.70052652
Short name T709
Test name
Test status
Simulation time 21016272154 ps
CPU time 969.15 seconds
Started Jun 23 06:42:56 PM PDT 24
Finished Jun 23 06:59:06 PM PDT 24
Peak memory 273400 kb
Host smart-9263fff1-70cd-4904-9683-07831b38c9a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70052652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.70052652
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.4156583005
Short name T4
Test name
Test status
Simulation time 39040062729 ps
CPU time 908.6 seconds
Started Jun 23 06:42:54 PM PDT 24
Finished Jun 23 06:58:03 PM PDT 24
Peak memory 281960 kb
Host smart-f25bd1d3-35c4-4238-a688-88433bc2a27c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156583005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.4156583005
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2772571657
Short name T300
Test name
Test status
Simulation time 16269852131 ps
CPU time 342.92 seconds
Started Jun 23 06:42:55 PM PDT 24
Finished Jun 23 06:48:38 PM PDT 24
Peak memory 248452 kb
Host smart-aff60d75-7e62-448f-a4e7-94f0b97e7cb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772571657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2772571657
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.4158261056
Short name T642
Test name
Test status
Simulation time 4625255415 ps
CPU time 55.44 seconds
Started Jun 23 06:42:49 PM PDT 24
Finished Jun 23 06:43:45 PM PDT 24
Peak memory 257312 kb
Host smart-d2a01cb9-cf2d-4e12-a33b-b9ef3df85126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41582
61056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.4158261056
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.2334387857
Short name T659
Test name
Test status
Simulation time 681292779 ps
CPU time 35.13 seconds
Started Jun 23 06:42:50 PM PDT 24
Finished Jun 23 06:43:26 PM PDT 24
Peak memory 255512 kb
Host smart-5f153e45-2fa4-4dfc-8783-ea6980572b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23343
87857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2334387857
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3958278891
Short name T484
Test name
Test status
Simulation time 391125009 ps
CPU time 10.09 seconds
Started Jun 23 06:42:50 PM PDT 24
Finished Jun 23 06:43:01 PM PDT 24
Peak memory 249004 kb
Host smart-3045add4-0b5e-4f35-bf46-28b31583d90d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39582
78891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3958278891
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1034092936
Short name T497
Test name
Test status
Simulation time 31697097960 ps
CPU time 1387.18 seconds
Started Jun 23 06:42:54 PM PDT 24
Finished Jun 23 07:06:02 PM PDT 24
Peak memory 289584 kb
Host smart-b126eba6-9020-4718-8c5e-fbb4e9686520
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034092936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1034092936
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.773093869
Short name T39
Test name
Test status
Simulation time 60855211630 ps
CPU time 7031.54 seconds
Started Jun 23 06:42:55 PM PDT 24
Finished Jun 23 08:40:08 PM PDT 24
Peak memory 372000 kb
Host smart-2114fdf9-5141-49e2-b9c0-245fca7f1498
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773093869 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.773093869
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2024853070
Short name T42
Test name
Test status
Simulation time 17517068040 ps
CPU time 827.19 seconds
Started Jun 23 06:43:01 PM PDT 24
Finished Jun 23 06:56:49 PM PDT 24
Peak memory 273768 kb
Host smart-2a4e61d1-96be-473f-a75e-95dc7a2a57c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024853070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2024853070
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2473478903
Short name T570
Test name
Test status
Simulation time 16966212500 ps
CPU time 237.49 seconds
Started Jun 23 06:43:01 PM PDT 24
Finished Jun 23 06:46:58 PM PDT 24
Peak memory 251408 kb
Host smart-eda568b5-6af7-4f20-848b-c0a7450c407a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24734
78903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2473478903
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2621440538
Short name T83
Test name
Test status
Simulation time 5448375878 ps
CPU time 74.38 seconds
Started Jun 23 06:42:58 PM PDT 24
Finished Jun 23 06:44:13 PM PDT 24
Peak memory 249196 kb
Host smart-e192c07e-f37a-4de4-a916-a9fc5a7ed06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26214
40538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2621440538
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.4267233295
Short name T606
Test name
Test status
Simulation time 205738760102 ps
CPU time 2753.62 seconds
Started Jun 23 06:43:01 PM PDT 24
Finished Jun 23 07:28:55 PM PDT 24
Peak memory 289276 kb
Host smart-0785bb17-63c6-4e1b-954a-76222ae97477
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267233295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.4267233295
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1056997690
Short name T376
Test name
Test status
Simulation time 24036553840 ps
CPU time 1613.15 seconds
Started Jun 23 06:43:00 PM PDT 24
Finished Jun 23 07:09:53 PM PDT 24
Peak memory 273412 kb
Host smart-46be1a8f-8d96-46a4-8e4f-931fd184d3b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056997690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1056997690
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2184453414
Short name T314
Test name
Test status
Simulation time 8135060416 ps
CPU time 170.76 seconds
Started Jun 23 06:43:02 PM PDT 24
Finished Jun 23 06:45:53 PM PDT 24
Peak memory 256548 kb
Host smart-132530f2-e3ba-475e-a4e7-70e836e4df79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184453414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2184453414
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.493176029
Short name T464
Test name
Test status
Simulation time 3194679253 ps
CPU time 58.45 seconds
Started Jun 23 06:42:55 PM PDT 24
Finished Jun 23 06:43:54 PM PDT 24
Peak memory 257340 kb
Host smart-197efcd7-70c9-4f10-9d98-98e9bf9ca28b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49317
6029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.493176029
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.591152858
Short name T415
Test name
Test status
Simulation time 3135544805 ps
CPU time 39.79 seconds
Started Jun 23 06:42:56 PM PDT 24
Finished Jun 23 06:43:36 PM PDT 24
Peak memory 256264 kb
Host smart-ccea87a4-d6d7-455f-9349-46f313c4ccbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59115
2858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.591152858
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.228445306
Short name T70
Test name
Test status
Simulation time 581904796 ps
CPU time 34.61 seconds
Started Jun 23 06:43:01 PM PDT 24
Finished Jun 23 06:43:36 PM PDT 24
Peak memory 248312 kb
Host smart-03a0f6d8-d3ac-41f9-9d98-d91a6ffc572e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22844
5306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.228445306
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2494201715
Short name T412
Test name
Test status
Simulation time 2211434117 ps
CPU time 60.04 seconds
Started Jun 23 06:42:55 PM PDT 24
Finished Jun 23 06:43:56 PM PDT 24
Peak memory 249108 kb
Host smart-c771e60d-05a7-4a38-8284-a5f7ba6cc163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24942
01715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2494201715
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.823734806
Short name T112
Test name
Test status
Simulation time 127977705556 ps
CPU time 4397.07 seconds
Started Jun 23 06:43:02 PM PDT 24
Finished Jun 23 07:56:20 PM PDT 24
Peak memory 302172 kb
Host smart-9d021fe0-c897-48de-8bf8-e711a8bd014d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823734806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.823734806
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1619507448
Short name T520
Test name
Test status
Simulation time 2826225402 ps
CPU time 119.89 seconds
Started Jun 23 06:43:05 PM PDT 24
Finished Jun 23 06:45:05 PM PDT 24
Peak memory 256672 kb
Host smart-18a5a4de-ba34-49d7-940f-3e2e6e697063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16195
07448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1619507448
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3128935485
Short name T593
Test name
Test status
Simulation time 677726396 ps
CPU time 39.69 seconds
Started Jun 23 06:43:06 PM PDT 24
Finished Jun 23 06:43:46 PM PDT 24
Peak memory 256496 kb
Host smart-4b6330f1-2462-4859-a781-252d75bdbcba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31289
35485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3128935485
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1856260574
Short name T553
Test name
Test status
Simulation time 8858338372 ps
CPU time 647.88 seconds
Started Jun 23 06:43:07 PM PDT 24
Finished Jun 23 06:53:56 PM PDT 24
Peak memory 265516 kb
Host smart-638ed188-ab7a-4f71-b50f-d7de5c762acb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856260574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1856260574
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.503851019
Short name T255
Test name
Test status
Simulation time 50753797622 ps
CPU time 1075.36 seconds
Started Jun 23 06:43:06 PM PDT 24
Finished Jun 23 07:01:02 PM PDT 24
Peak memory 285532 kb
Host smart-add504e9-cde9-46de-8fa4-490b071d3db3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503851019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.503851019
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3039994199
Short name T591
Test name
Test status
Simulation time 26439686886 ps
CPU time 98.33 seconds
Started Jun 23 06:43:08 PM PDT 24
Finished Jun 23 06:44:47 PM PDT 24
Peak memory 248504 kb
Host smart-c949b9e1-db40-4271-9eb3-582d2bc343d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039994199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3039994199
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1573774930
Short name T594
Test name
Test status
Simulation time 227649261 ps
CPU time 14.44 seconds
Started Jun 23 06:43:01 PM PDT 24
Finished Jun 23 06:43:16 PM PDT 24
Peak memory 249280 kb
Host smart-d5140c32-fae3-43b6-bd8b-d24e2340a8cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15737
74930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1573774930
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1255413214
Short name T699
Test name
Test status
Simulation time 2350221124 ps
CPU time 53.51 seconds
Started Jun 23 06:43:06 PM PDT 24
Finished Jun 23 06:44:00 PM PDT 24
Peak memory 256408 kb
Host smart-a3a721bb-e6fd-4b5f-b39e-50f7666b99fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12554
13214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1255413214
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2830686694
Short name T56
Test name
Test status
Simulation time 3124862006 ps
CPU time 40.47 seconds
Started Jun 23 06:43:04 PM PDT 24
Finished Jun 23 06:43:45 PM PDT 24
Peak memory 249084 kb
Host smart-b0cce314-0ffb-4fab-97e5-24a61367ed58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28306
86694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2830686694
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2463041628
Short name T363
Test name
Test status
Simulation time 1957211235 ps
CPU time 17.15 seconds
Started Jun 23 06:43:00 PM PDT 24
Finished Jun 23 06:43:17 PM PDT 24
Peak memory 256640 kb
Host smart-0824da0b-c9e3-465e-97ca-274342448dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24630
41628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2463041628
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.3412854669
Short name T43
Test name
Test status
Simulation time 72470853656 ps
CPU time 2272.75 seconds
Started Jun 23 06:43:07 PM PDT 24
Finished Jun 23 07:21:01 PM PDT 24
Peak memory 290200 kb
Host smart-06f6e968-bbb7-41fe-b8e8-4e6f890c0175
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412854669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.3412854669
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.4159047463
Short name T674
Test name
Test status
Simulation time 139236767214 ps
CPU time 1634.89 seconds
Started Jun 23 06:43:13 PM PDT 24
Finished Jun 23 07:10:29 PM PDT 24
Peak memory 273764 kb
Host smart-0853bb0b-f73b-4e79-8ae7-c6fd34f218e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159047463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.4159047463
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1539958544
Short name T20
Test name
Test status
Simulation time 13043980874 ps
CPU time 226.34 seconds
Started Jun 23 06:43:06 PM PDT 24
Finished Jun 23 06:46:53 PM PDT 24
Peak memory 257348 kb
Host smart-451777ab-4b2c-46a7-ad6a-409bcea5b5f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15399
58544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1539958544
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1459512398
Short name T382
Test name
Test status
Simulation time 3218809665 ps
CPU time 46.58 seconds
Started Jun 23 06:43:05 PM PDT 24
Finished Jun 23 06:43:51 PM PDT 24
Peak memory 249160 kb
Host smart-9130bebf-6608-4147-834f-662c9d021801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14595
12398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1459512398
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3573769648
Short name T324
Test name
Test status
Simulation time 124178934206 ps
CPU time 1677.88 seconds
Started Jun 23 06:43:11 PM PDT 24
Finished Jun 23 07:11:09 PM PDT 24
Peak memory 273692 kb
Host smart-c7d50107-9ca6-4cf9-91ba-4c7a75dd5c42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573769648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3573769648
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1488736621
Short name T681
Test name
Test status
Simulation time 23656857534 ps
CPU time 1552.61 seconds
Started Jun 23 06:43:19 PM PDT 24
Finished Jun 23 07:09:12 PM PDT 24
Peak memory 273156 kb
Host smart-18419ae0-326f-4b17-817e-b02f0a77d304
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488736621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1488736621
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3378038801
Short name T549
Test name
Test status
Simulation time 13308860931 ps
CPU time 290.22 seconds
Started Jun 23 06:43:12 PM PDT 24
Finished Jun 23 06:48:03 PM PDT 24
Peak memory 247740 kb
Host smart-087ebc33-efc6-4d7a-bb37-9515c9057b7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378038801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3378038801
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3918358738
Short name T397
Test name
Test status
Simulation time 901172096 ps
CPU time 45.9 seconds
Started Jun 23 06:43:05 PM PDT 24
Finished Jun 23 06:43:51 PM PDT 24
Peak memory 256664 kb
Host smart-7e02d6f1-95c1-4668-84de-8f189bd80d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39183
58738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3918358738
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1995365198
Short name T615
Test name
Test status
Simulation time 142645135 ps
CPU time 3.75 seconds
Started Jun 23 06:43:05 PM PDT 24
Finished Jun 23 06:43:09 PM PDT 24
Peak memory 239860 kb
Host smart-3e54cc39-d148-4b7f-8fbb-9e1889956a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19953
65198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1995365198
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3381638396
Short name T107
Test name
Test status
Simulation time 153168802 ps
CPU time 6.79 seconds
Started Jun 23 06:43:14 PM PDT 24
Finished Jun 23 06:43:21 PM PDT 24
Peak memory 251372 kb
Host smart-6bbe4f0d-ddcc-43ed-b409-69b700b49017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33816
38396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3381638396
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1724731733
Short name T592
Test name
Test status
Simulation time 354879429 ps
CPU time 12.59 seconds
Started Jun 23 06:43:05 PM PDT 24
Finished Jun 23 06:43:18 PM PDT 24
Peak memory 249040 kb
Host smart-8ccdf2cf-f639-468d-b2cd-ae293b78bbce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17247
31733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1724731733
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2593887257
Short name T44
Test name
Test status
Simulation time 35598659386 ps
CPU time 999.51 seconds
Started Jun 23 06:43:22 PM PDT 24
Finished Jun 23 07:00:02 PM PDT 24
Peak memory 289640 kb
Host smart-3fd36d03-3063-441c-8dee-eb3bfd397d79
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593887257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2593887257
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.198110597
Short name T16
Test name
Test status
Simulation time 144542668143 ps
CPU time 2424.5 seconds
Started Jun 23 06:43:19 PM PDT 24
Finished Jun 23 07:23:44 PM PDT 24
Peak memory 290000 kb
Host smart-c84c00d5-b82f-4c9f-a3cc-d19b0875841c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198110597 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.198110597
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2510099497
Short name T504
Test name
Test status
Simulation time 25335980223 ps
CPU time 1246.54 seconds
Started Jun 23 06:43:19 PM PDT 24
Finished Jun 23 07:04:06 PM PDT 24
Peak memory 289096 kb
Host smart-dedcb43b-377a-4e2e-9713-523c69ff8dff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510099497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2510099497
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3642734060
Short name T374
Test name
Test status
Simulation time 38135808712 ps
CPU time 200.85 seconds
Started Jun 23 06:43:20 PM PDT 24
Finished Jun 23 06:46:41 PM PDT 24
Peak memory 257348 kb
Host smart-4afd0f0e-741b-4678-b1b8-95407d00206e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36427
34060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3642734060
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.729527840
Short name T713
Test name
Test status
Simulation time 4388441576 ps
CPU time 65.2 seconds
Started Jun 23 06:43:19 PM PDT 24
Finished Jun 23 06:44:25 PM PDT 24
Peak memory 256372 kb
Host smart-49356b0b-1df7-4da8-9d83-0fa9157789e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72952
7840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.729527840
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2870276570
Short name T227
Test name
Test status
Simulation time 23171573416 ps
CPU time 1233.04 seconds
Started Jun 23 06:43:20 PM PDT 24
Finished Jun 23 07:03:53 PM PDT 24
Peak memory 290108 kb
Host smart-f3ee6ae4-b28a-4cf8-8e44-4ffec35a0eed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870276570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2870276570
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.428653919
Short name T457
Test name
Test status
Simulation time 20882870258 ps
CPU time 1165.81 seconds
Started Jun 23 06:43:18 PM PDT 24
Finished Jun 23 07:02:44 PM PDT 24
Peak memory 285852 kb
Host smart-d9d85528-7dd9-41d1-8315-c89ab6a74cfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428653919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.428653919
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1294750421
Short name T298
Test name
Test status
Simulation time 53329957295 ps
CPU time 527.1 seconds
Started Jun 23 06:43:18 PM PDT 24
Finished Jun 23 06:52:06 PM PDT 24
Peak memory 248716 kb
Host smart-cb21e8c7-7232-4282-96e6-03285be0dacd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294750421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1294750421
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.491114235
Short name T491
Test name
Test status
Simulation time 66193693 ps
CPU time 5.17 seconds
Started Jun 23 06:43:21 PM PDT 24
Finished Jun 23 06:43:26 PM PDT 24
Peak memory 240928 kb
Host smart-c1f5b01f-4b6c-496c-ad3c-1c597c0b1ec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49111
4235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.491114235
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3072421095
Short name T537
Test name
Test status
Simulation time 258352059 ps
CPU time 14.8 seconds
Started Jun 23 06:43:19 PM PDT 24
Finished Jun 23 06:43:34 PM PDT 24
Peak memory 254680 kb
Host smart-0fa5353f-760d-4a48-84da-342783676b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30724
21095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3072421095
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2361264522
Short name T89
Test name
Test status
Simulation time 4192325201 ps
CPU time 67.05 seconds
Started Jun 23 06:43:19 PM PDT 24
Finished Jun 23 06:44:26 PM PDT 24
Peak memory 250184 kb
Host smart-8e808e60-5ae3-4fe7-9726-5cef5e90310d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23612
64522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2361264522
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1047045991
Short name T403
Test name
Test status
Simulation time 554996290 ps
CPU time 16.3 seconds
Started Jun 23 06:43:19 PM PDT 24
Finished Jun 23 06:43:36 PM PDT 24
Peak memory 249040 kb
Host smart-63f69407-0dab-4382-9761-89e0c7df7a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10470
45991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1047045991
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3233775974
Short name T531
Test name
Test status
Simulation time 23376075736 ps
CPU time 1445.74 seconds
Started Jun 23 06:43:29 PM PDT 24
Finished Jun 23 07:07:35 PM PDT 24
Peak memory 287928 kb
Host smart-0fb36688-a9cd-46d2-b503-dd769c5be7e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233775974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3233775974
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.774395815
Short name T544
Test name
Test status
Simulation time 17145297999 ps
CPU time 247.79 seconds
Started Jun 23 06:43:20 PM PDT 24
Finished Jun 23 06:47:28 PM PDT 24
Peak memory 257360 kb
Host smart-15cddf64-d721-4042-8e33-b580b087fd8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77439
5815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.774395815
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.170770638
Short name T218
Test name
Test status
Simulation time 224285990 ps
CPU time 6.34 seconds
Started Jun 23 06:43:21 PM PDT 24
Finished Jun 23 06:43:28 PM PDT 24
Peak memory 252584 kb
Host smart-c0058cd3-2529-4c64-938a-9ff3fae80948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17077
0638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.170770638
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1858368183
Short name T650
Test name
Test status
Simulation time 12521448940 ps
CPU time 1370.24 seconds
Started Jun 23 06:43:24 PM PDT 24
Finished Jun 23 07:06:15 PM PDT 24
Peak memory 281948 kb
Host smart-388144b4-e7e0-4815-9780-2971ecee018a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858368183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1858368183
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1160694098
Short name T600
Test name
Test status
Simulation time 150962167745 ps
CPU time 1525.62 seconds
Started Jun 23 06:43:24 PM PDT 24
Finished Jun 23 07:08:50 PM PDT 24
Peak memory 273272 kb
Host smart-5d7c2770-117d-4fea-95fe-b51ec1c90fab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160694098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1160694098
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.4237867128
Short name T301
Test name
Test status
Simulation time 12568062707 ps
CPU time 491.51 seconds
Started Jun 23 06:43:23 PM PDT 24
Finished Jun 23 06:51:35 PM PDT 24
Peak memory 248728 kb
Host smart-53d889d5-b933-4f5e-b1d1-03980ac36643
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237867128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.4237867128
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3913143984
Short name T429
Test name
Test status
Simulation time 1934085991 ps
CPU time 52.02 seconds
Started Jun 23 06:43:22 PM PDT 24
Finished Jun 23 06:44:14 PM PDT 24
Peak memory 256516 kb
Host smart-e98452f4-bf0d-4807-b090-ba6d2b85052c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39131
43984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3913143984
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2689269428
Short name T387
Test name
Test status
Simulation time 312527259 ps
CPU time 22.65 seconds
Started Jun 23 06:43:20 PM PDT 24
Finished Jun 23 06:43:43 PM PDT 24
Peak memory 249156 kb
Host smart-208be2c5-27e9-4e10-a574-eea4fe4319fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26892
69428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2689269428
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1002989435
Short name T577
Test name
Test status
Simulation time 203196217 ps
CPU time 4.68 seconds
Started Jun 23 06:43:23 PM PDT 24
Finished Jun 23 06:43:28 PM PDT 24
Peak memory 239604 kb
Host smart-805a624e-5594-404a-bc83-a62afa87cdb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10029
89435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1002989435
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.1740978946
Short name T641
Test name
Test status
Simulation time 2324687817 ps
CPU time 39.63 seconds
Started Jun 23 06:43:18 PM PDT 24
Finished Jun 23 06:43:58 PM PDT 24
Peak memory 249168 kb
Host smart-6defce49-5dc8-468e-a981-632a65116407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17409
78946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1740978946
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3529304034
Short name T199
Test name
Test status
Simulation time 45815185 ps
CPU time 4.16 seconds
Started Jun 23 06:41:19 PM PDT 24
Finished Jun 23 06:41:24 PM PDT 24
Peak memory 249288 kb
Host smart-d33d3fb7-f09d-43f6-a0e4-908e08d2c71b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3529304034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3529304034
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1006938880
Short name T443
Test name
Test status
Simulation time 46090223604 ps
CPU time 1327.69 seconds
Started Jun 23 06:41:20 PM PDT 24
Finished Jun 23 07:03:28 PM PDT 24
Peak memory 273252 kb
Host smart-6cc283ec-e9cc-4f34-86b7-0c37a100657d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006938880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1006938880
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1524414303
Short name T183
Test name
Test status
Simulation time 594980023 ps
CPU time 9.28 seconds
Started Jun 23 06:41:21 PM PDT 24
Finished Jun 23 06:41:31 PM PDT 24
Peak memory 249124 kb
Host smart-b6345ec1-c0ff-48db-b8cc-e15ec1ef6935
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1524414303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1524414303
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3740557880
Short name T364
Test name
Test status
Simulation time 924940798 ps
CPU time 57.1 seconds
Started Jun 23 06:41:20 PM PDT 24
Finished Jun 23 06:42:18 PM PDT 24
Peak memory 256612 kb
Host smart-90bf4823-f84c-4d9b-bd30-4a43f235b8d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37405
57880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3740557880
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2665997822
Short name T632
Test name
Test status
Simulation time 1102794200 ps
CPU time 30.5 seconds
Started Jun 23 06:41:19 PM PDT 24
Finished Jun 23 06:41:50 PM PDT 24
Peak memory 249120 kb
Host smart-3ae8e69a-1d47-4143-8aac-ef841ad620fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26659
97822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2665997822
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1411932910
Short name T708
Test name
Test status
Simulation time 41744881501 ps
CPU time 2575.32 seconds
Started Jun 23 06:41:22 PM PDT 24
Finished Jun 23 07:24:19 PM PDT 24
Peak memory 289728 kb
Host smart-550fcf78-5ba3-4a50-bfde-fce308ea8f90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411932910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1411932910
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2382322361
Short name T434
Test name
Test status
Simulation time 218663219494 ps
CPU time 3339.57 seconds
Started Jun 23 06:41:21 PM PDT 24
Finished Jun 23 07:37:02 PM PDT 24
Peak memory 290172 kb
Host smart-aba9a57e-c795-45de-8887-bcd1ac148b4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382322361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2382322361
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3958201280
Short name T303
Test name
Test status
Simulation time 7338014206 ps
CPU time 297.61 seconds
Started Jun 23 06:41:20 PM PDT 24
Finished Jun 23 06:46:19 PM PDT 24
Peak memory 248280 kb
Host smart-217d18de-d71c-49fb-9dc1-1fbdbdfaa45e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958201280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3958201280
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1960959488
Short name T476
Test name
Test status
Simulation time 440675898 ps
CPU time 11.64 seconds
Started Jun 23 06:41:18 PM PDT 24
Finished Jun 23 06:41:31 PM PDT 24
Peak memory 249164 kb
Host smart-482b7b44-3597-49a0-9d95-b0f1e98b5b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19609
59488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1960959488
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.577536193
Short name T686
Test name
Test status
Simulation time 124910321 ps
CPU time 8.56 seconds
Started Jun 23 06:41:15 PM PDT 24
Finished Jun 23 06:41:24 PM PDT 24
Peak memory 251476 kb
Host smart-dfe60884-4cc2-4b4d-9f92-c404a9723713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57753
6193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.577536193
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.68872072
Short name T12
Test name
Test status
Simulation time 2198457648 ps
CPU time 25.92 seconds
Started Jun 23 06:41:23 PM PDT 24
Finished Jun 23 06:41:49 PM PDT 24
Peak memory 276256 kb
Host smart-684ae583-0464-4613-b6e9-6e59ce6626eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=68872072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.68872072
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.4282625005
Short name T643
Test name
Test status
Simulation time 9571322671 ps
CPU time 55.05 seconds
Started Jun 23 06:41:20 PM PDT 24
Finished Jun 23 06:42:17 PM PDT 24
Peak memory 255868 kb
Host smart-dd6dcc2d-05aa-4ec4-b1a3-5fdcad22c5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42826
25005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.4282625005
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1249463789
Short name T471
Test name
Test status
Simulation time 1580556665 ps
CPU time 48.99 seconds
Started Jun 23 06:41:16 PM PDT 24
Finished Jun 23 06:42:06 PM PDT 24
Peak memory 249092 kb
Host smart-5317f0b3-25eb-4b6d-b0be-935783ded47d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12494
63789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1249463789
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1975341541
Short name T78
Test name
Test status
Simulation time 8751870731 ps
CPU time 51.37 seconds
Started Jun 23 06:41:21 PM PDT 24
Finished Jun 23 06:42:13 PM PDT 24
Peak memory 256492 kb
Host smart-59a9e47f-1e5c-489c-8889-925c362985b7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975341541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1975341541
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1239728738
Short name T706
Test name
Test status
Simulation time 141311734521 ps
CPU time 2050.38 seconds
Started Jun 23 06:43:27 PM PDT 24
Finished Jun 23 07:17:38 PM PDT 24
Peak memory 287748 kb
Host smart-96b6a32f-b949-4070-b54a-826e74baa3be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239728738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1239728738
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3373689203
Short name T485
Test name
Test status
Simulation time 2259245357 ps
CPU time 58.01 seconds
Started Jun 23 06:43:28 PM PDT 24
Finished Jun 23 06:44:26 PM PDT 24
Peak memory 256660 kb
Host smart-c2608f10-44a4-4201-8d3b-31c8ed3e20c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33736
89203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3373689203
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1579221233
Short name T657
Test name
Test status
Simulation time 411136038 ps
CPU time 8.79 seconds
Started Jun 23 06:43:24 PM PDT 24
Finished Jun 23 06:43:33 PM PDT 24
Peak memory 249052 kb
Host smart-1b859537-f134-45de-87ab-2a6f310e1d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15792
21233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1579221233
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3787879641
Short name T341
Test name
Test status
Simulation time 22662828992 ps
CPU time 883.43 seconds
Started Jun 23 06:43:25 PM PDT 24
Finished Jun 23 06:58:09 PM PDT 24
Peak memory 273548 kb
Host smart-879a5ec4-96af-43cb-a78e-06a59aa848b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787879641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3787879641
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2637435668
Short name T432
Test name
Test status
Simulation time 5675633935 ps
CPU time 603.93 seconds
Started Jun 23 06:43:24 PM PDT 24
Finished Jun 23 06:53:28 PM PDT 24
Peak memory 273156 kb
Host smart-14a7d39d-06c3-454d-951e-e1cc0275c917
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637435668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2637435668
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3347525704
Short name T233
Test name
Test status
Simulation time 8291071558 ps
CPU time 317.76 seconds
Started Jun 23 06:43:27 PM PDT 24
Finished Jun 23 06:48:45 PM PDT 24
Peak memory 248328 kb
Host smart-0dad170b-1eb2-4876-8c22-686ef66db2e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347525704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3347525704
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.446818902
Short name T423
Test name
Test status
Simulation time 175506527 ps
CPU time 12.97 seconds
Started Jun 23 06:43:23 PM PDT 24
Finished Jun 23 06:43:36 PM PDT 24
Peak memory 253652 kb
Host smart-2bfae93e-4fd1-42a2-b6ca-68a4da3b22f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44681
8902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.446818902
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2018123957
Short name T660
Test name
Test status
Simulation time 1568709249 ps
CPU time 18.21 seconds
Started Jun 23 06:43:23 PM PDT 24
Finished Jun 23 06:43:42 PM PDT 24
Peak memory 249092 kb
Host smart-b33c97b6-bb9c-41ea-8a16-90b0b6e49892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20181
23957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2018123957
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1728714004
Short name T635
Test name
Test status
Simulation time 931144019 ps
CPU time 57.52 seconds
Started Jun 23 06:43:25 PM PDT 24
Finished Jun 23 06:44:22 PM PDT 24
Peak memory 256312 kb
Host smart-9f71302a-07d0-482e-989b-bb707dc489b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17287
14004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1728714004
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1373842862
Short name T513
Test name
Test status
Simulation time 315982847 ps
CPU time 23.12 seconds
Started Jun 23 06:43:25 PM PDT 24
Finished Jun 23 06:43:48 PM PDT 24
Peak memory 249120 kb
Host smart-af94294b-6d07-4ddf-8980-2eb171c3e6ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13738
42862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1373842862
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3797625980
Short name T576
Test name
Test status
Simulation time 12982818213 ps
CPU time 1405.31 seconds
Started Jun 23 06:43:27 PM PDT 24
Finished Jun 23 07:06:53 PM PDT 24
Peak memory 289260 kb
Host smart-08d8d9c7-6fdc-401a-84fd-c7ad7fecb831
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797625980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3797625980
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3714223101
Short name T458
Test name
Test status
Simulation time 147810947109 ps
CPU time 2130.78 seconds
Started Jun 23 06:43:32 PM PDT 24
Finished Jun 23 07:19:03 PM PDT 24
Peak memory 289584 kb
Host smart-30d217cf-4392-4298-bdce-073cace8857b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714223101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3714223101
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1674144797
Short name T522
Test name
Test status
Simulation time 1616793612 ps
CPU time 24.76 seconds
Started Jun 23 06:43:30 PM PDT 24
Finished Jun 23 06:43:55 PM PDT 24
Peak memory 256480 kb
Host smart-33cdc2ea-5eed-49ac-aa7b-a2079fc1986f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16741
44797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1674144797
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2508555166
Short name T84
Test name
Test status
Simulation time 4968836492 ps
CPU time 68.31 seconds
Started Jun 23 06:43:35 PM PDT 24
Finished Jun 23 06:44:44 PM PDT 24
Peak memory 249280 kb
Host smart-20536b48-02c1-4b3d-8ae8-ef996771582b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25085
55166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2508555166
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.386542038
Short name T620
Test name
Test status
Simulation time 107938830859 ps
CPU time 2043.47 seconds
Started Jun 23 06:43:31 PM PDT 24
Finished Jun 23 07:17:35 PM PDT 24
Peak memory 273768 kb
Host smart-0cbe3fc0-f6d9-4a8e-af1a-552b94b287d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386542038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.386542038
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.809192802
Short name T59
Test name
Test status
Simulation time 71392146813 ps
CPU time 1731.9 seconds
Started Jun 23 06:43:28 PM PDT 24
Finished Jun 23 07:12:21 PM PDT 24
Peak memory 289808 kb
Host smart-3876ad36-5434-49b6-a4b9-2984a6e182a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809192802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.809192802
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2146285315
Short name T528
Test name
Test status
Simulation time 3834863780 ps
CPU time 152.19 seconds
Started Jun 23 06:43:31 PM PDT 24
Finished Jun 23 06:46:04 PM PDT 24
Peak memory 248748 kb
Host smart-31aff66e-c705-47a6-b201-7cd9522321b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146285315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2146285315
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.319499407
Short name T673
Test name
Test status
Simulation time 479043503 ps
CPU time 26.07 seconds
Started Jun 23 06:43:30 PM PDT 24
Finished Jun 23 06:43:56 PM PDT 24
Peak memory 255800 kb
Host smart-1f07ff77-d369-4aca-8c7e-ca24aa75be0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31949
9407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.319499407
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3033582561
Short name T37
Test name
Test status
Simulation time 3636769417 ps
CPU time 56.04 seconds
Started Jun 23 06:43:35 PM PDT 24
Finished Jun 23 06:44:32 PM PDT 24
Peak memory 256264 kb
Host smart-aeeb52a8-0b97-4faf-9280-1d95ca62271c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30335
82561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3033582561
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1016284162
Short name T539
Test name
Test status
Simulation time 1941445288 ps
CPU time 53.02 seconds
Started Jun 23 06:43:30 PM PDT 24
Finished Jun 23 06:44:23 PM PDT 24
Peak memory 249112 kb
Host smart-94c68891-0bf5-4663-a40a-0a89ac0767bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10162
84162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1016284162
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.701391046
Short name T654
Test name
Test status
Simulation time 1581041988 ps
CPU time 49.96 seconds
Started Jun 23 06:43:29 PM PDT 24
Finished Jun 23 06:44:19 PM PDT 24
Peak memory 256592 kb
Host smart-75fd816e-783c-4924-880e-65a6709f04fc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701391046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.701391046
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1179992813
Short name T575
Test name
Test status
Simulation time 17406030119 ps
CPU time 2095.25 seconds
Started Jun 23 06:43:31 PM PDT 24
Finished Jun 23 07:18:27 PM PDT 24
Peak memory 290288 kb
Host smart-8f1ca1f3-9fbb-40b4-906a-70eca06c74ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179992813 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1179992813
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1312750911
Short name T296
Test name
Test status
Simulation time 41163513971 ps
CPU time 2407.71 seconds
Started Jun 23 06:43:36 PM PDT 24
Finished Jun 23 07:23:44 PM PDT 24
Peak memory 289584 kb
Host smart-539b60cb-ae86-48c2-a958-207ffa374d62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312750911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1312750911
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1868547326
Short name T391
Test name
Test status
Simulation time 800411580 ps
CPU time 74.35 seconds
Started Jun 23 06:43:30 PM PDT 24
Finished Jun 23 06:44:44 PM PDT 24
Peak memory 249140 kb
Host smart-cbb8e220-d948-4278-b0a0-807c177725ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18685
47326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1868547326
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3970015291
Short name T638
Test name
Test status
Simulation time 1028121707 ps
CPU time 29.55 seconds
Started Jun 23 06:43:36 PM PDT 24
Finished Jun 23 06:44:06 PM PDT 24
Peak memory 256428 kb
Host smart-9249f0ad-1e23-4df2-b765-92d3c5e0f730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39700
15291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3970015291
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3808851570
Short name T334
Test name
Test status
Simulation time 81235905996 ps
CPU time 1740.7 seconds
Started Jun 23 06:43:34 PM PDT 24
Finished Jun 23 07:12:35 PM PDT 24
Peak memory 289644 kb
Host smart-6538215b-cc9c-4b30-87c5-c95ae7c77ff0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808851570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3808851570
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.917926552
Short name T540
Test name
Test status
Simulation time 42181576901 ps
CPU time 2132.67 seconds
Started Jun 23 06:43:35 PM PDT 24
Finished Jun 23 07:19:09 PM PDT 24
Peak memory 284648 kb
Host smart-040eb88b-9b2f-4982-8d82-5c30d7c08c56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917926552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.917926552
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2977682266
Short name T703
Test name
Test status
Simulation time 16558875434 ps
CPU time 330.58 seconds
Started Jun 23 06:43:29 PM PDT 24
Finished Jun 23 06:49:00 PM PDT 24
Peak memory 248836 kb
Host smart-11465f6c-d8e4-44c0-a8c4-293054b9ffd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977682266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2977682266
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1943096923
Short name T367
Test name
Test status
Simulation time 394073422 ps
CPU time 30.63 seconds
Started Jun 23 06:43:31 PM PDT 24
Finished Jun 23 06:44:02 PM PDT 24
Peak memory 256904 kb
Host smart-c19a7b6c-723a-4e2f-bec2-2665ae92a3b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19430
96923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1943096923
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2742304674
Short name T465
Test name
Test status
Simulation time 1725840611 ps
CPU time 23.46 seconds
Started Jun 23 06:43:32 PM PDT 24
Finished Jun 23 06:43:56 PM PDT 24
Peak memory 247936 kb
Host smart-631ee496-b548-4cf2-b0a8-13c595c0df37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27423
04674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2742304674
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2955553870
Short name T268
Test name
Test status
Simulation time 265003819 ps
CPU time 17.34 seconds
Started Jun 23 06:43:31 PM PDT 24
Finished Jun 23 06:43:48 PM PDT 24
Peak memory 253916 kb
Host smart-ae6202cb-f39e-487c-ab5c-4b6cc8550b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29555
53870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2955553870
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.407904925
Short name T614
Test name
Test status
Simulation time 93144758 ps
CPU time 6.68 seconds
Started Jun 23 06:43:35 PM PDT 24
Finished Jun 23 06:43:42 PM PDT 24
Peak memory 257272 kb
Host smart-c9180b7c-db27-4447-ab31-bc84426ebc3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40790
4925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.407904925
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.417701847
Short name T407
Test name
Test status
Simulation time 73807668006 ps
CPU time 2130.54 seconds
Started Jun 23 06:43:36 PM PDT 24
Finished Jun 23 07:19:07 PM PDT 24
Peak memory 285148 kb
Host smart-e389fdb1-34a9-4f2b-a28e-81d41cda9506
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417701847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.417701847
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2692269252
Short name T527
Test name
Test status
Simulation time 341287307324 ps
CPU time 1755.38 seconds
Started Jun 23 06:43:34 PM PDT 24
Finished Jun 23 07:12:50 PM PDT 24
Peak memory 289696 kb
Host smart-32606ebb-46cf-4f5a-a893-b36a737c2dfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692269252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2692269252
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.266098613
Short name T470
Test name
Test status
Simulation time 437427682 ps
CPU time 13.01 seconds
Started Jun 23 06:43:33 PM PDT 24
Finished Jun 23 06:43:46 PM PDT 24
Peak memory 253672 kb
Host smart-8f50bb4a-daee-4e0b-a02e-fc7f3c47def4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26609
8613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.266098613
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2904937885
Short name T448
Test name
Test status
Simulation time 279894063 ps
CPU time 21.53 seconds
Started Jun 23 06:43:36 PM PDT 24
Finished Jun 23 06:43:58 PM PDT 24
Peak memory 255980 kb
Host smart-5447c63f-79d9-4aa8-895d-28e6725332ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29049
37885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2904937885
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2057012956
Short name T662
Test name
Test status
Simulation time 20768905308 ps
CPU time 1550.03 seconds
Started Jun 23 06:43:39 PM PDT 24
Finished Jun 23 07:09:29 PM PDT 24
Peak memory 290012 kb
Host smart-32f5d146-0bdc-476d-bc89-b94350187e04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057012956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2057012956
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2312491920
Short name T530
Test name
Test status
Simulation time 1522210034 ps
CPU time 26.56 seconds
Started Jun 23 06:43:34 PM PDT 24
Finished Jun 23 06:44:01 PM PDT 24
Peak memory 256360 kb
Host smart-70d17d83-72ae-4d7c-943f-fbc47ae33340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23124
91920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2312491920
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3388207179
Short name T71
Test name
Test status
Simulation time 187996560 ps
CPU time 13.4 seconds
Started Jun 23 06:43:36 PM PDT 24
Finished Jun 23 06:43:50 PM PDT 24
Peak memory 254724 kb
Host smart-c422c50c-0b81-442e-8ae8-b6d2780ef6f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33882
07179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3388207179
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1775523447
Short name T282
Test name
Test status
Simulation time 190252662 ps
CPU time 13.46 seconds
Started Jun 23 06:43:48 PM PDT 24
Finished Jun 23 06:44:02 PM PDT 24
Peak memory 247928 kb
Host smart-236f7dac-2435-4b71-b064-1baa54baf64f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17755
23447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1775523447
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3537499838
Short name T661
Test name
Test status
Simulation time 3473046912 ps
CPU time 27.6 seconds
Started Jun 23 06:43:37 PM PDT 24
Finished Jun 23 06:44:05 PM PDT 24
Peak memory 257352 kb
Host smart-1f9082ac-4162-45a1-b267-182ee773f7fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35374
99838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3537499838
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2126135978
Short name T449
Test name
Test status
Simulation time 32261066575 ps
CPU time 1847.7 seconds
Started Jun 23 06:43:39 PM PDT 24
Finished Jun 23 07:14:27 PM PDT 24
Peak memory 288200 kb
Host smart-9f367260-510f-4e2f-850e-e0820c6d4ebe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126135978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2126135978
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.892244666
Short name T467
Test name
Test status
Simulation time 157803803184 ps
CPU time 5970.37 seconds
Started Jun 23 06:43:41 PM PDT 24
Finished Jun 23 08:23:12 PM PDT 24
Peak memory 322852 kb
Host smart-9849d717-0e2d-4d24-b336-dbecd858c68b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892244666 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.892244666
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.856553621
Short name T404
Test name
Test status
Simulation time 5814457789 ps
CPU time 664.33 seconds
Started Jun 23 06:43:40 PM PDT 24
Finished Jun 23 06:54:45 PM PDT 24
Peak memory 267580 kb
Host smart-1f5a72b7-a963-4558-a284-d30e0a78e336
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856553621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.856553621
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.4151183906
Short name T17
Test name
Test status
Simulation time 5678201621 ps
CPU time 143.07 seconds
Started Jun 23 06:43:40 PM PDT 24
Finished Jun 23 06:46:03 PM PDT 24
Peak memory 257212 kb
Host smart-a96a5b73-1e7c-4a92-869f-e634e3ad2989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41511
83906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.4151183906
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2159313548
Short name T611
Test name
Test status
Simulation time 166645862 ps
CPU time 16.57 seconds
Started Jun 23 06:43:44 PM PDT 24
Finished Jun 23 06:44:01 PM PDT 24
Peak memory 249516 kb
Host smart-73292f15-5741-4b58-9ff3-1444fe794e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21593
13548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2159313548
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2457734286
Short name T223
Test name
Test status
Simulation time 89794028554 ps
CPU time 1386.7 seconds
Started Jun 23 06:43:48 PM PDT 24
Finished Jun 23 07:06:55 PM PDT 24
Peak memory 273744 kb
Host smart-33e2bf52-dc17-4da1-b203-8b449a997347
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457734286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2457734286
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3287348282
Short name T91
Test name
Test status
Simulation time 63892188655 ps
CPU time 1136.05 seconds
Started Jun 23 06:43:44 PM PDT 24
Finished Jun 23 07:02:41 PM PDT 24
Peak memory 265656 kb
Host smart-3fafe2a1-530e-4989-9b0f-3c3fcb027e9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287348282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3287348282
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.400858738
Short name T599
Test name
Test status
Simulation time 28885833128 ps
CPU time 291.5 seconds
Started Jun 23 06:43:47 PM PDT 24
Finished Jun 23 06:48:38 PM PDT 24
Peak memory 248700 kb
Host smart-3a5ee8fa-b0ac-42e5-805b-ac13e1a8394d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400858738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.400858738
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.405470189
Short name T380
Test name
Test status
Simulation time 459068269 ps
CPU time 31.85 seconds
Started Jun 23 06:43:41 PM PDT 24
Finished Jun 23 06:44:13 PM PDT 24
Peak memory 249132 kb
Host smart-866f022c-4b08-4396-bdf9-7cb6d659202c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40547
0189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.405470189
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1500310767
Short name T501
Test name
Test status
Simulation time 1270117871 ps
CPU time 49.13 seconds
Started Jun 23 06:43:41 PM PDT 24
Finished Jun 23 06:44:30 PM PDT 24
Peak memory 249012 kb
Host smart-fecf625a-7e6a-46c9-bf33-6220e510a71c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15003
10767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1500310767
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.4256784625
Short name T431
Test name
Test status
Simulation time 198312431 ps
CPU time 13.45 seconds
Started Jun 23 06:43:38 PM PDT 24
Finished Jun 23 06:43:51 PM PDT 24
Peak memory 249060 kb
Host smart-51c17b4f-91ee-43f6-bfae-fce5330ba862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42567
84625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.4256784625
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3594382053
Short name T572
Test name
Test status
Simulation time 133386125 ps
CPU time 9.75 seconds
Started Jun 23 06:43:40 PM PDT 24
Finished Jun 23 06:43:50 PM PDT 24
Peak memory 251212 kb
Host smart-905815dd-f0d6-45c4-b504-0371998ffef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35943
82053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3594382053
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2829061088
Short name T284
Test name
Test status
Simulation time 48625836346 ps
CPU time 2884.72 seconds
Started Jun 23 06:43:44 PM PDT 24
Finished Jun 23 07:31:49 PM PDT 24
Peak memory 301268 kb
Host smart-ff2ed912-c6e4-48c0-98a4-2fdce0569db1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829061088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2829061088
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2894790365
Short name T596
Test name
Test status
Simulation time 28197851192 ps
CPU time 1494.72 seconds
Started Jun 23 06:43:44 PM PDT 24
Finished Jun 23 07:08:39 PM PDT 24
Peak memory 265636 kb
Host smart-1715fbbe-a4ac-4f05-955a-765fab2b8c45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894790365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2894790365
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.352942985
Short name T526
Test name
Test status
Simulation time 35848393016 ps
CPU time 243.89 seconds
Started Jun 23 06:43:46 PM PDT 24
Finished Jun 23 06:47:50 PM PDT 24
Peak memory 257348 kb
Host smart-8679a976-08eb-433c-8dc5-183edb468e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35294
2985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.352942985
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2567271692
Short name T583
Test name
Test status
Simulation time 733541343 ps
CPU time 19.03 seconds
Started Jun 23 06:43:45 PM PDT 24
Finished Jun 23 06:44:04 PM PDT 24
Peak memory 249304 kb
Host smart-0b9a6984-be45-4061-ab78-9f2c77b47899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25672
71692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2567271692
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.788370628
Short name T68
Test name
Test status
Simulation time 33909351092 ps
CPU time 1956.55 seconds
Started Jun 23 06:43:51 PM PDT 24
Finished Jun 23 07:16:28 PM PDT 24
Peak memory 282420 kb
Host smart-def5abcb-d23d-438d-8664-122a4c269008
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788370628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.788370628
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1843717173
Short name T446
Test name
Test status
Simulation time 24008962690 ps
CPU time 1699.3 seconds
Started Jun 23 06:43:50 PM PDT 24
Finished Jun 23 07:12:09 PM PDT 24
Peak memory 273132 kb
Host smart-a842876b-1adb-4fd3-8265-05744f505b25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843717173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1843717173
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.15554639
Short name T306
Test name
Test status
Simulation time 4954101300 ps
CPU time 205.99 seconds
Started Jun 23 06:43:44 PM PDT 24
Finished Jun 23 06:47:11 PM PDT 24
Peak memory 248420 kb
Host smart-7f0d15d6-6745-476b-82be-f86b35218911
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15554639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.15554639
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2131935979
Short name T704
Test name
Test status
Simulation time 733436369 ps
CPU time 37.79 seconds
Started Jun 23 06:43:47 PM PDT 24
Finished Jun 23 06:44:25 PM PDT 24
Peak memory 256800 kb
Host smart-d4669b4f-12d4-4ba2-9b6a-e413a94e0426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21319
35979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2131935979
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3839171428
Short name T506
Test name
Test status
Simulation time 129179070 ps
CPU time 9.67 seconds
Started Jun 23 06:43:48 PM PDT 24
Finished Jun 23 06:43:58 PM PDT 24
Peak memory 252292 kb
Host smart-70fb7456-b9c7-4215-9eda-27c9ad1d3560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38391
71428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3839171428
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.971355345
Short name T377
Test name
Test status
Simulation time 540005644 ps
CPU time 32.39 seconds
Started Jun 23 06:43:46 PM PDT 24
Finished Jun 23 06:44:19 PM PDT 24
Peak memory 256556 kb
Host smart-878ba2a4-0040-4720-9d98-e6150427b03c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97135
5345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.971355345
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.797171464
Short name T645
Test name
Test status
Simulation time 15304865525 ps
CPU time 217.72 seconds
Started Jun 23 06:43:50 PM PDT 24
Finished Jun 23 06:47:29 PM PDT 24
Peak memory 257308 kb
Host smart-29467f6f-86ea-4027-b856-8207bbc4a47c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797171464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.797171464
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.3479019865
Short name T269
Test name
Test status
Simulation time 101140646536 ps
CPU time 5220.25 seconds
Started Jun 23 06:43:50 PM PDT 24
Finished Jun 23 08:10:51 PM PDT 24
Peak memory 331276 kb
Host smart-b8bd2e86-7a87-4fc2-8487-41ffcd0fc1c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479019865 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.3479019865
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.649063944
Short name T515
Test name
Test status
Simulation time 544399886522 ps
CPU time 1843.38 seconds
Started Jun 23 06:43:49 PM PDT 24
Finished Jun 23 07:14:33 PM PDT 24
Peak memory 286264 kb
Host smart-9ac6e1bb-5a19-4744-bd3b-4ef6ee49a160
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649063944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.649063944
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3429005494
Short name T535
Test name
Test status
Simulation time 3392532374 ps
CPU time 105.77 seconds
Started Jun 23 06:43:51 PM PDT 24
Finished Jun 23 06:45:37 PM PDT 24
Peak memory 257232 kb
Host smart-9a3514fb-e3ef-412f-806f-51c33927b7ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34290
05494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3429005494
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3421646224
Short name T609
Test name
Test status
Simulation time 335245970 ps
CPU time 30.11 seconds
Started Jun 23 06:43:52 PM PDT 24
Finished Jun 23 06:44:22 PM PDT 24
Peak memory 256000 kb
Host smart-0b5c3391-6519-49cc-aef7-80896fd0fb91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34216
46224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3421646224
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2847558632
Short name T338
Test name
Test status
Simulation time 120535471613 ps
CPU time 1917.38 seconds
Started Jun 23 06:43:51 PM PDT 24
Finished Jun 23 07:15:49 PM PDT 24
Peak memory 271708 kb
Host smart-f3b32fc8-bf12-4f67-8d6a-f20825e614ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847558632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2847558632
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.873308234
Short name T246
Test name
Test status
Simulation time 53828813234 ps
CPU time 1137.48 seconds
Started Jun 23 06:43:51 PM PDT 24
Finished Jun 23 07:02:49 PM PDT 24
Peak memory 272152 kb
Host smart-10c70903-de21-4755-9d40-72fafc993215
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873308234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.873308234
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.291561787
Short name T9
Test name
Test status
Simulation time 13848744442 ps
CPU time 549.32 seconds
Started Jun 23 06:43:51 PM PDT 24
Finished Jun 23 06:53:01 PM PDT 24
Peak memory 248748 kb
Host smart-34e4a63f-2110-4fba-8153-e2808b52bccf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291561787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.291561787
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.4274063365
Short name T372
Test name
Test status
Simulation time 407852837 ps
CPU time 19.72 seconds
Started Jun 23 06:43:50 PM PDT 24
Finished Jun 23 06:44:10 PM PDT 24
Peak memory 249276 kb
Host smart-0bd66259-7291-4891-b99d-d177bef1735c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42740
63365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.4274063365
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.862875008
Short name T488
Test name
Test status
Simulation time 928035550 ps
CPU time 40.56 seconds
Started Jun 23 06:43:50 PM PDT 24
Finished Jun 23 06:44:30 PM PDT 24
Peak memory 255520 kb
Host smart-302a0569-4ac0-4a22-9ec4-128a008d077a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86287
5008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.862875008
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2583833726
Short name T54
Test name
Test status
Simulation time 972059522 ps
CPU time 29.42 seconds
Started Jun 23 06:43:51 PM PDT 24
Finished Jun 23 06:44:21 PM PDT 24
Peak memory 249108 kb
Host smart-e187d513-5d8b-4722-a64c-3f5d70c1d756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25838
33726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2583833726
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2153140919
Short name T398
Test name
Test status
Simulation time 6017814109 ps
CPU time 346.6 seconds
Started Jun 23 06:43:50 PM PDT 24
Finished Jun 23 06:49:37 PM PDT 24
Peak memory 257388 kb
Host smart-5607f5b3-1815-4e54-a132-5416fd2f0cda
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153140919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2153140919
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3487293888
Short name T560
Test name
Test status
Simulation time 14891049496 ps
CPU time 1071.51 seconds
Started Jun 23 06:43:55 PM PDT 24
Finished Jun 23 07:01:47 PM PDT 24
Peak memory 265492 kb
Host smart-1555a439-18d3-4c54-aa3f-e7feaac2f922
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487293888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3487293888
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2248785491
Short name T604
Test name
Test status
Simulation time 3605081376 ps
CPU time 91.02 seconds
Started Jun 23 06:43:56 PM PDT 24
Finished Jun 23 06:45:27 PM PDT 24
Peak memory 257308 kb
Host smart-0321d649-fb45-47b6-88c2-c7a5c75a17ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22487
85491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2248785491
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3578960992
Short name T668
Test name
Test status
Simulation time 357857990 ps
CPU time 23.87 seconds
Started Jun 23 06:43:55 PM PDT 24
Finished Jun 23 06:44:19 PM PDT 24
Peak memory 249344 kb
Host smart-98e046bf-b32d-4e14-a1e8-fc3c63473059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35789
60992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3578960992
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2263637395
Short name T287
Test name
Test status
Simulation time 76200578322 ps
CPU time 1124.15 seconds
Started Jun 23 06:43:55 PM PDT 24
Finished Jun 23 07:02:40 PM PDT 24
Peak memory 271832 kb
Host smart-5c288722-ba2a-4672-9afd-20a5e493c316
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263637395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2263637395
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.949360295
Short name T13
Test name
Test status
Simulation time 48094494022 ps
CPU time 2960.93 seconds
Started Jun 23 06:43:57 PM PDT 24
Finished Jun 23 07:33:19 PM PDT 24
Peak memory 288676 kb
Host smart-da1b02f7-9698-4cb8-a296-7c01d70c4d6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949360295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.949360295
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2410928697
Short name T319
Test name
Test status
Simulation time 142287303625 ps
CPU time 372.29 seconds
Started Jun 23 06:43:56 PM PDT 24
Finished Jun 23 06:50:08 PM PDT 24
Peak memory 248152 kb
Host smart-227c5e45-2621-4e0c-8b33-e469c083013e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410928697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2410928697
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1293786008
Short name T710
Test name
Test status
Simulation time 1938763278 ps
CPU time 29.75 seconds
Started Jun 23 06:43:54 PM PDT 24
Finished Jun 23 06:44:24 PM PDT 24
Peak memory 249040 kb
Host smart-ca3d0569-2b6c-44b4-9dc6-2206b92d2f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12937
86008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1293786008
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2307486482
Short name T629
Test name
Test status
Simulation time 501091985 ps
CPU time 9.18 seconds
Started Jun 23 06:43:56 PM PDT 24
Finished Jun 23 06:44:05 PM PDT 24
Peak memory 247988 kb
Host smart-d9ff2c7c-3e60-4a48-9536-ae87d5c4bf61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23074
86482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2307486482
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1314579175
Short name T545
Test name
Test status
Simulation time 106277677 ps
CPU time 13.68 seconds
Started Jun 23 06:43:57 PM PDT 24
Finished Jun 23 06:44:11 PM PDT 24
Peak memory 256348 kb
Host smart-168bbcad-1f9c-4c1a-a4b2-064888dfd695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13145
79175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1314579175
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3628191146
Short name T214
Test name
Test status
Simulation time 442006853 ps
CPU time 26.27 seconds
Started Jun 23 06:43:57 PM PDT 24
Finished Jun 23 06:44:23 PM PDT 24
Peak memory 256008 kb
Host smart-2b634f32-6cd3-44ed-89d8-24c6317fa5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36281
91146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3628191146
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.3543759423
Short name T237
Test name
Test status
Simulation time 198450375723 ps
CPU time 2247.44 seconds
Started Jun 23 06:44:02 PM PDT 24
Finished Jun 23 07:21:30 PM PDT 24
Peak memory 289336 kb
Host smart-638cf8a1-6d75-4657-a06c-be3ef6a3b0bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543759423 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.3543759423
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1885202692
Short name T687
Test name
Test status
Simulation time 67275355731 ps
CPU time 1261.87 seconds
Started Jun 23 06:44:05 PM PDT 24
Finished Jun 23 07:05:07 PM PDT 24
Peak memory 273036 kb
Host smart-63d31332-e63f-4966-8dfe-3c4d39106aec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885202692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1885202692
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2740936926
Short name T505
Test name
Test status
Simulation time 3811292998 ps
CPU time 221.61 seconds
Started Jun 23 06:44:06 PM PDT 24
Finished Jun 23 06:47:48 PM PDT 24
Peak memory 257376 kb
Host smart-0d2c2ead-f973-4995-a993-9940aae6fdfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27409
36926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2740936926
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2738011334
Short name T430
Test name
Test status
Simulation time 408901162 ps
CPU time 24.94 seconds
Started Jun 23 06:44:00 PM PDT 24
Finished Jun 23 06:44:26 PM PDT 24
Peak memory 256236 kb
Host smart-bda8cb9c-c195-4610-8632-f9f7f6eee813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27380
11334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2738011334
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1193154735
Short name T344
Test name
Test status
Simulation time 23375280188 ps
CPU time 1400.08 seconds
Started Jun 23 06:44:08 PM PDT 24
Finished Jun 23 07:07:29 PM PDT 24
Peak memory 273268 kb
Host smart-6b9ef930-c88c-48ce-8280-40894ba45e78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193154735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1193154735
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3387117214
Short name T105
Test name
Test status
Simulation time 47862854703 ps
CPU time 2887.04 seconds
Started Jun 23 06:44:05 PM PDT 24
Finished Jun 23 07:32:13 PM PDT 24
Peak memory 289548 kb
Host smart-e3932fb8-1c76-4616-8f45-02aa34cfb8e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387117214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3387117214
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.4276544631
Short name T310
Test name
Test status
Simulation time 5054253889 ps
CPU time 216.73 seconds
Started Jun 23 06:44:05 PM PDT 24
Finished Jun 23 06:47:42 PM PDT 24
Peak memory 247588 kb
Host smart-99fa855f-c1d6-4703-b710-15d586c13489
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276544631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.4276544631
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.621685251
Short name T490
Test name
Test status
Simulation time 374434189 ps
CPU time 23.85 seconds
Started Jun 23 06:44:02 PM PDT 24
Finished Jun 23 06:44:26 PM PDT 24
Peak memory 256456 kb
Host smart-b14a1e8d-2dee-49d0-a8f2-e337e1b1ef3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62168
5251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.621685251
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1997068953
Short name T368
Test name
Test status
Simulation time 453499783 ps
CPU time 34.24 seconds
Started Jun 23 06:43:59 PM PDT 24
Finished Jun 23 06:44:33 PM PDT 24
Peak memory 249116 kb
Host smart-0861eaee-cd4e-4cc7-a50f-a4d49c27efc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19970
68953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1997068953
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2341535841
Short name T557
Test name
Test status
Simulation time 772359641 ps
CPU time 25.19 seconds
Started Jun 23 06:44:05 PM PDT 24
Finished Jun 23 06:44:30 PM PDT 24
Peak memory 248008 kb
Host smart-f2e9b6cd-1a85-45fc-80ec-cf54f2df3de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23415
35841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2341535841
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3491788293
Short name T536
Test name
Test status
Simulation time 675563167 ps
CPU time 28.6 seconds
Started Jun 23 06:44:00 PM PDT 24
Finished Jun 23 06:44:29 PM PDT 24
Peak memory 257288 kb
Host smart-cae2132c-f8b2-4f45-9f03-8aa2328398ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34917
88293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3491788293
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.4219685162
Short name T561
Test name
Test status
Simulation time 40597382795 ps
CPU time 1850.43 seconds
Started Jun 23 06:44:09 PM PDT 24
Finished Jun 23 07:14:59 PM PDT 24
Peak memory 300816 kb
Host smart-bac420f8-6243-410e-a29f-a26382c79836
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219685162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.4219685162
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.238702033
Short name T406
Test name
Test status
Simulation time 27875437776 ps
CPU time 2020.79 seconds
Started Jun 23 06:44:09 PM PDT 24
Finished Jun 23 07:17:51 PM PDT 24
Peak memory 285692 kb
Host smart-bdf438fc-4b82-4323-8812-32da7fa1f491
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238702033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.238702033
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.240352886
Short name T678
Test name
Test status
Simulation time 3049433068 ps
CPU time 75.75 seconds
Started Jun 23 06:44:11 PM PDT 24
Finished Jun 23 06:45:27 PM PDT 24
Peak memory 257308 kb
Host smart-87f16c30-6deb-4cf2-9858-0996609600bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24035
2886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.240352886
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.393703757
Short name T653
Test name
Test status
Simulation time 1570336244 ps
CPU time 39.45 seconds
Started Jun 23 06:44:11 PM PDT 24
Finished Jun 23 06:44:50 PM PDT 24
Peak memory 257312 kb
Host smart-9415d188-2845-4a26-9ec0-7f007cb3673e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39370
3757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.393703757
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3801463062
Short name T337
Test name
Test status
Simulation time 111799734323 ps
CPU time 1608.2 seconds
Started Jun 23 06:44:13 PM PDT 24
Finished Jun 23 07:11:01 PM PDT 24
Peak memory 281964 kb
Host smart-a680f56b-eab3-4f8c-9dbe-5d3c936510bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801463062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3801463062
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1933766945
Short name T433
Test name
Test status
Simulation time 36612496198 ps
CPU time 2299.51 seconds
Started Jun 23 06:44:10 PM PDT 24
Finished Jun 23 07:22:30 PM PDT 24
Peak memory 288956 kb
Host smart-8f51dd11-a7c7-42ba-b24a-bd1ba8c35a21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933766945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1933766945
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3187637650
Short name T447
Test name
Test status
Simulation time 210655525 ps
CPU time 9.13 seconds
Started Jun 23 06:44:06 PM PDT 24
Finished Jun 23 06:44:15 PM PDT 24
Peak memory 249056 kb
Host smart-f0295269-5cb2-4a7e-9731-948a30a4b001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31876
37650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3187637650
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2894803273
Short name T366
Test name
Test status
Simulation time 54666019 ps
CPU time 4.39 seconds
Started Jun 23 06:44:08 PM PDT 24
Finished Jun 23 06:44:13 PM PDT 24
Peak memory 239592 kb
Host smart-bed0e1a0-3767-4683-ae10-d75e272c600c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28948
03273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2894803273
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1035554478
Short name T565
Test name
Test status
Simulation time 159235164 ps
CPU time 11.04 seconds
Started Jun 23 06:44:09 PM PDT 24
Finished Jun 23 06:44:20 PM PDT 24
Peak memory 254832 kb
Host smart-892fb3c0-5cf6-4298-8fb6-abdf5999e9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10355
54478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1035554478
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.4179518603
Short name T416
Test name
Test status
Simulation time 689047748 ps
CPU time 39.82 seconds
Started Jun 23 06:44:05 PM PDT 24
Finished Jun 23 06:44:45 PM PDT 24
Peak memory 256472 kb
Host smart-33bb4c21-2659-4a01-9137-c5287172b7bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41795
18603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.4179518603
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3367516164
Short name T41
Test name
Test status
Simulation time 68610422567 ps
CPU time 1820.8 seconds
Started Jun 23 06:44:09 PM PDT 24
Finished Jun 23 07:14:30 PM PDT 24
Peak memory 306356 kb
Host smart-b5451f4e-e39e-4183-bf75-752d7132632a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367516164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3367516164
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.2986526014
Short name T473
Test name
Test status
Simulation time 125991199264 ps
CPU time 4459.48 seconds
Started Jun 23 06:44:08 PM PDT 24
Finished Jun 23 07:58:29 PM PDT 24
Peak memory 297692 kb
Host smart-187685eb-2688-4592-a9cc-3b0f6796d505
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986526014 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.2986526014
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.308525947
Short name T206
Test name
Test status
Simulation time 179562128 ps
CPU time 3.7 seconds
Started Jun 23 06:41:24 PM PDT 24
Finished Jun 23 06:41:28 PM PDT 24
Peak memory 249408 kb
Host smart-c180a143-ae04-499b-9a02-be7a6ecff2b6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=308525947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.308525947
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1170991106
Short name T652
Test name
Test status
Simulation time 107194641813 ps
CPU time 861.36 seconds
Started Jun 23 06:41:21 PM PDT 24
Finished Jun 23 06:55:44 PM PDT 24
Peak memory 273740 kb
Host smart-3fd4b41d-6da1-4bc8-b4d2-71fc31411d38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170991106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1170991106
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.738624513
Short name T502
Test name
Test status
Simulation time 842452296 ps
CPU time 17.72 seconds
Started Jun 23 06:41:21 PM PDT 24
Finished Jun 23 06:41:40 PM PDT 24
Peak memory 249104 kb
Host smart-752fd9ca-8407-4756-bcca-b18fd42c6ecd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=738624513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.738624513
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.2703999961
Short name T451
Test name
Test status
Simulation time 396184278 ps
CPU time 35.04 seconds
Started Jun 23 06:41:22 PM PDT 24
Finished Jun 23 06:41:58 PM PDT 24
Peak memory 256532 kb
Host smart-29576871-92fc-4520-8c55-a36970bb45b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27039
99961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2703999961
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1295161183
Short name T381
Test name
Test status
Simulation time 7652777075 ps
CPU time 67.66 seconds
Started Jun 23 06:41:22 PM PDT 24
Finished Jun 23 06:42:31 PM PDT 24
Peak memory 249300 kb
Host smart-4ddd2f5d-a9c8-4ab4-b50d-685f3249cd16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12951
61183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1295161183
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1444137498
Short name T327
Test name
Test status
Simulation time 37879891633 ps
CPU time 1007.32 seconds
Started Jun 23 06:41:22 PM PDT 24
Finished Jun 23 06:58:10 PM PDT 24
Peak memory 283388 kb
Host smart-758df8bd-8112-46db-9cb2-fe7fe4578ce5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444137498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1444137498
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2540755452
Short name T370
Test name
Test status
Simulation time 149242317751 ps
CPU time 2587.79 seconds
Started Jun 23 06:41:18 PM PDT 24
Finished Jun 23 07:24:26 PM PDT 24
Peak memory 289552 kb
Host smart-5e2e0db3-680b-4fa8-8c5f-4e87113b4644
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540755452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2540755452
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1452676207
Short name T667
Test name
Test status
Simulation time 33645432704 ps
CPU time 319.42 seconds
Started Jun 23 06:41:21 PM PDT 24
Finished Jun 23 06:46:41 PM PDT 24
Peak memory 248884 kb
Host smart-f2b4c34e-9522-4969-8fd3-ab368f198b9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452676207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1452676207
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3691788289
Short name T40
Test name
Test status
Simulation time 211509522 ps
CPU time 22.34 seconds
Started Jun 23 06:41:20 PM PDT 24
Finished Jun 23 06:41:43 PM PDT 24
Peak memory 257288 kb
Host smart-aeea6331-05f9-4c74-beca-eb1e11a7f657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36917
88289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3691788289
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1316473743
Short name T511
Test name
Test status
Simulation time 220783960 ps
CPU time 15.37 seconds
Started Jun 23 06:41:22 PM PDT 24
Finished Jun 23 06:41:38 PM PDT 24
Peak memory 255500 kb
Host smart-010bffd4-170e-4f05-a187-c53b9ac773ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13164
73743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1316473743
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3237662827
Short name T117
Test name
Test status
Simulation time 187071300 ps
CPU time 8.61 seconds
Started Jun 23 06:41:22 PM PDT 24
Finished Jun 23 06:41:32 PM PDT 24
Peak memory 247904 kb
Host smart-5286e4c6-6954-490b-a9f9-8f8059b8ca8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32376
62827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3237662827
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3078358417
Short name T408
Test name
Test status
Simulation time 260341872 ps
CPU time 23.38 seconds
Started Jun 23 06:41:19 PM PDT 24
Finished Jun 23 06:41:44 PM PDT 24
Peak memory 256944 kb
Host smart-75ea287f-6adc-43b6-8042-061676052fc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30783
58417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3078358417
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1797534022
Short name T271
Test name
Test status
Simulation time 107506005484 ps
CPU time 1436.56 seconds
Started Jun 23 06:41:21 PM PDT 24
Finished Jun 23 07:05:19 PM PDT 24
Peak memory 282912 kb
Host smart-289fc698-a7bf-42f0-8e8c-27f6448bf56b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797534022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1797534022
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.34039052
Short name T209
Test name
Test status
Simulation time 46484829 ps
CPU time 3.38 seconds
Started Jun 23 06:41:25 PM PDT 24
Finished Jun 23 06:41:29 PM PDT 24
Peak memory 249216 kb
Host smart-febb51de-5c98-4711-bd09-53ae36c6746f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=34039052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.34039052
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3423458664
Short name T99
Test name
Test status
Simulation time 24737833253 ps
CPU time 1697.41 seconds
Started Jun 23 06:41:25 PM PDT 24
Finished Jun 23 07:09:43 PM PDT 24
Peak memory 273000 kb
Host smart-8e67e8fc-d0fd-4a01-a37e-699eb891c6b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423458664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3423458664
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1818464479
Short name T445
Test name
Test status
Simulation time 1479128649 ps
CPU time 17.89 seconds
Started Jun 23 06:41:31 PM PDT 24
Finished Jun 23 06:41:49 PM PDT 24
Peak memory 249136 kb
Host smart-276d3494-b776-403b-809a-049c3e31e401
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1818464479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1818464479
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3515741244
Short name T244
Test name
Test status
Simulation time 2420477458 ps
CPU time 146.92 seconds
Started Jun 23 06:41:36 PM PDT 24
Finished Jun 23 06:44:03 PM PDT 24
Peak memory 257312 kb
Host smart-f66f4ea8-e719-4caa-8513-81a2af094851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35157
41244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3515741244
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.315361915
Short name T541
Test name
Test status
Simulation time 649921050 ps
CPU time 41.61 seconds
Started Jun 23 06:41:36 PM PDT 24
Finished Jun 23 06:42:18 PM PDT 24
Peak memory 249140 kb
Host smart-217d78d7-10fe-4a0c-a122-4fc9597fc8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31536
1915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.315361915
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.826099685
Short name T290
Test name
Test status
Simulation time 138553902726 ps
CPU time 2018.19 seconds
Started Jun 23 06:41:27 PM PDT 24
Finished Jun 23 07:15:06 PM PDT 24
Peak memory 268016 kb
Host smart-1deb4ed5-ff4c-4733-90a5-923f4296149f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826099685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.826099685
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1725850984
Short name T665
Test name
Test status
Simulation time 37419737378 ps
CPU time 728.44 seconds
Started Jun 23 06:41:24 PM PDT 24
Finished Jun 23 06:53:33 PM PDT 24
Peak memory 273240 kb
Host smart-7c699c7c-539f-41ef-8df8-8ab0f0e1171b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725850984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1725850984
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1343450934
Short name T3
Test name
Test status
Simulation time 11832751885 ps
CPU time 251.52 seconds
Started Jun 23 06:41:25 PM PDT 24
Finished Jun 23 06:45:37 PM PDT 24
Peak memory 248780 kb
Host smart-96cf9687-02c5-4304-8a48-4e9520e2cf9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343450934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1343450934
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2209171903
Short name T514
Test name
Test status
Simulation time 850990021 ps
CPU time 23.48 seconds
Started Jun 23 06:41:23 PM PDT 24
Finished Jun 23 06:41:47 PM PDT 24
Peak memory 256676 kb
Host smart-a216905d-2339-4ee3-a890-87e23ad45a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22091
71903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2209171903
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3282429021
Short name T542
Test name
Test status
Simulation time 655134392 ps
CPU time 13.14 seconds
Started Jun 23 06:41:25 PM PDT 24
Finished Jun 23 06:41:38 PM PDT 24
Peak memory 247828 kb
Host smart-6d8d5896-6d95-4ff3-91f0-23945eb4aa89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32824
29021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3282429021
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.4275932161
Short name T278
Test name
Test status
Simulation time 908308486 ps
CPU time 26.78 seconds
Started Jun 23 06:41:24 PM PDT 24
Finished Jun 23 06:41:51 PM PDT 24
Peak memory 248132 kb
Host smart-8605736a-d00d-41f0-a9de-e7b115eb46b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42759
32161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.4275932161
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2379933905
Short name T558
Test name
Test status
Simulation time 535308590 ps
CPU time 9.39 seconds
Started Jun 23 06:41:36 PM PDT 24
Finished Jun 23 06:41:46 PM PDT 24
Peak memory 249116 kb
Host smart-2cfe88fb-100e-4972-85d7-e6fc9f10a9e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23799
33905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2379933905
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3760885243
Short name T111
Test name
Test status
Simulation time 46112928317 ps
CPU time 2813.53 seconds
Started Jun 23 06:41:36 PM PDT 24
Finished Jun 23 07:28:31 PM PDT 24
Peak memory 287932 kb
Host smart-7a4b9471-afc0-49ae-975e-203e38232d37
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760885243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3760885243
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1005714278
Short name T204
Test name
Test status
Simulation time 132786902 ps
CPU time 3.42 seconds
Started Jun 23 06:41:31 PM PDT 24
Finished Jun 23 06:41:35 PM PDT 24
Peak memory 249288 kb
Host smart-d879e022-f3ea-4beb-a3e6-13f5d9cb28bd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1005714278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1005714278
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3739749400
Short name T14
Test name
Test status
Simulation time 180903475246 ps
CPU time 2752.68 seconds
Started Jun 23 06:41:32 PM PDT 24
Finished Jun 23 07:27:25 PM PDT 24
Peak memory 284116 kb
Host smart-c6c6575b-953e-416f-898c-f1b5f0262ca0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739749400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3739749400
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.397638030
Short name T450
Test name
Test status
Simulation time 416928715 ps
CPU time 7.15 seconds
Started Jun 23 06:41:31 PM PDT 24
Finished Jun 23 06:41:39 PM PDT 24
Peak memory 249096 kb
Host smart-20708f84-82d1-4b6e-9657-7e83909db13b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=397638030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.397638030
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2678035247
Short name T386
Test name
Test status
Simulation time 1819922717 ps
CPU time 45 seconds
Started Jun 23 06:41:24 PM PDT 24
Finished Jun 23 06:42:10 PM PDT 24
Peak memory 249144 kb
Host smart-6dee4852-52a4-4a5e-9ac0-d608f589578c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26780
35247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2678035247
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1136168222
Short name T525
Test name
Test status
Simulation time 676683535 ps
CPU time 23.16 seconds
Started Jun 23 06:41:28 PM PDT 24
Finished Jun 23 06:41:51 PM PDT 24
Peak memory 249232 kb
Host smart-f104bd31-bc9d-4586-ab0c-2d93e791ce85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11361
68222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1136168222
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3178004324
Short name T409
Test name
Test status
Simulation time 11422446792 ps
CPU time 1221.61 seconds
Started Jun 23 06:41:32 PM PDT 24
Finished Jun 23 07:01:54 PM PDT 24
Peak memory 282992 kb
Host smart-e04d7d53-1cfc-4599-bb71-fa29796a8968
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178004324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3178004324
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2522421872
Short name T96
Test name
Test status
Simulation time 69293719474 ps
CPU time 322.79 seconds
Started Jun 23 06:41:31 PM PDT 24
Finished Jun 23 06:46:54 PM PDT 24
Peak memory 248744 kb
Host smart-ada48ebe-6c12-4341-b1b2-01f44a4c53d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522421872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2522421872
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.452322999
Short name T441
Test name
Test status
Simulation time 2056594452 ps
CPU time 26.45 seconds
Started Jun 23 06:41:26 PM PDT 24
Finished Jun 23 06:41:52 PM PDT 24
Peak memory 249120 kb
Host smart-aee2c6dd-7079-455f-8cd9-7230e3a067ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45232
2999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.452322999
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1020869405
Short name T427
Test name
Test status
Simulation time 618326522 ps
CPU time 16.18 seconds
Started Jun 23 06:41:26 PM PDT 24
Finished Jun 23 06:41:43 PM PDT 24
Peak memory 248004 kb
Host smart-ca140792-fd9a-44cf-8004-7a9abd3a2f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10208
69405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1020869405
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.347676645
Short name T257
Test name
Test status
Simulation time 410565832 ps
CPU time 12.55 seconds
Started Jun 23 06:41:36 PM PDT 24
Finished Jun 23 06:41:49 PM PDT 24
Peak memory 256668 kb
Host smart-4317d572-188c-4fef-804c-0b15fcfd47de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34767
6645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.347676645
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.983666067
Short name T251
Test name
Test status
Simulation time 256647125 ps
CPU time 23.19 seconds
Started Jun 23 06:41:25 PM PDT 24
Finished Jun 23 06:41:49 PM PDT 24
Peak memory 257136 kb
Host smart-fcca0089-6909-4c15-af2f-d721d87cc9d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98366
6067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.983666067
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2340802961
Short name T555
Test name
Test status
Simulation time 24600349967 ps
CPU time 1837.3 seconds
Started Jun 23 06:41:36 PM PDT 24
Finished Jun 23 07:12:14 PM PDT 24
Peak memory 288528 kb
Host smart-0af758d3-aecd-43c4-a53b-26692fbed4d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340802961 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2340802961
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1181488943
Short name T202
Test name
Test status
Simulation time 101799618 ps
CPU time 3.14 seconds
Started Jun 23 06:41:35 PM PDT 24
Finished Jun 23 06:41:38 PM PDT 24
Peak memory 249216 kb
Host smart-433df762-12c2-4e6a-ba51-dba884b176e9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1181488943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1181488943
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3016392615
Short name T495
Test name
Test status
Simulation time 66826621971 ps
CPU time 1737.93 seconds
Started Jun 23 06:41:36 PM PDT 24
Finished Jun 23 07:10:35 PM PDT 24
Peak memory 273104 kb
Host smart-1a63c683-e98a-46c2-9cdf-246921e3bf3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016392615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3016392615
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1297826680
Short name T688
Test name
Test status
Simulation time 1766107960 ps
CPU time 18.41 seconds
Started Jun 23 06:41:32 PM PDT 24
Finished Jun 23 06:41:51 PM PDT 24
Peak memory 249140 kb
Host smart-856e8f2e-3d2f-486b-a27d-09b9f043a2ab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1297826680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1297826680
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1326508062
Short name T252
Test name
Test status
Simulation time 967379590 ps
CPU time 86.61 seconds
Started Jun 23 06:41:31 PM PDT 24
Finished Jun 23 06:42:58 PM PDT 24
Peak memory 257260 kb
Host smart-01e552ca-237a-4ea9-8564-bc987de91de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13265
08062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1326508062
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.1425121148
Short name T663
Test name
Test status
Simulation time 1792949065 ps
CPU time 32.44 seconds
Started Jun 23 06:41:32 PM PDT 24
Finished Jun 23 06:42:05 PM PDT 24
Peak memory 249096 kb
Host smart-3e750b69-dedc-4618-b4a1-2912f6c166c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14251
21148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1425121148
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2896423611
Short name T345
Test name
Test status
Simulation time 105740435967 ps
CPU time 1664.51 seconds
Started Jun 23 06:41:34 PM PDT 24
Finished Jun 23 07:09:19 PM PDT 24
Peak memory 272820 kb
Host smart-404bd922-ea4c-4fbe-9158-25f3299d97f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896423611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2896423611
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.652144393
Short name T63
Test name
Test status
Simulation time 334339758429 ps
CPU time 1444.72 seconds
Started Jun 23 06:41:32 PM PDT 24
Finished Jun 23 07:05:37 PM PDT 24
Peak memory 272912 kb
Host smart-7526318b-713d-4224-bcfa-38c799759586
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652144393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.652144393
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2656157699
Short name T315
Test name
Test status
Simulation time 73321561586 ps
CPU time 623.56 seconds
Started Jun 23 06:41:31 PM PDT 24
Finished Jun 23 06:51:55 PM PDT 24
Peak memory 248488 kb
Host smart-6ab5abd4-edee-40dd-bd41-8a6916bfb9b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656157699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2656157699
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3351555798
Short name T567
Test name
Test status
Simulation time 642880941 ps
CPU time 13.01 seconds
Started Jun 23 06:41:30 PM PDT 24
Finished Jun 23 06:41:43 PM PDT 24
Peak memory 254904 kb
Host smart-d64496b4-f565-4176-9798-2ada5d8a94fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33515
55798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3351555798
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.4110863779
Short name T25
Test name
Test status
Simulation time 2802026120 ps
CPU time 37.67 seconds
Started Jun 23 06:41:31 PM PDT 24
Finished Jun 23 06:42:09 PM PDT 24
Peak memory 249120 kb
Host smart-728a254f-88cb-4249-8653-ce9a3dbe816a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41108
63779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.4110863779
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.4148028497
Short name T384
Test name
Test status
Simulation time 4903663735 ps
CPU time 37.5 seconds
Started Jun 23 06:41:33 PM PDT 24
Finished Jun 23 06:42:11 PM PDT 24
Peak memory 249120 kb
Host smart-59075f8e-260e-454c-ba25-be1eaf9fc003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41480
28497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.4148028497
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3021559273
Short name T532
Test name
Test status
Simulation time 820931295 ps
CPU time 26.33 seconds
Started Jun 23 06:41:33 PM PDT 24
Finished Jun 23 06:42:00 PM PDT 24
Peak memory 249044 kb
Host smart-b39e22a9-9d5f-4b5a-a455-dff81024c968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30215
59273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3021559273
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.86553813
Short name T669
Test name
Test status
Simulation time 233750694609 ps
CPU time 3736.98 seconds
Started Jun 23 06:41:32 PM PDT 24
Finished Jun 23 07:43:49 PM PDT 24
Peak memory 289692 kb
Host smart-d650af93-9a60-4faf-9edf-c40122ea5e4e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86553813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handl
er_stress_all.86553813
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.1230247449
Short name T273
Test name
Test status
Simulation time 34176288887 ps
CPU time 2348.08 seconds
Started Jun 23 06:41:32 PM PDT 24
Finished Jun 23 07:20:41 PM PDT 24
Peak memory 289880 kb
Host smart-8b77e342-bf3f-43e1-8d4c-9ef3af521a16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230247449 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.1230247449
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3152200584
Short name T200
Test name
Test status
Simulation time 62986410 ps
CPU time 3.12 seconds
Started Jun 23 06:41:36 PM PDT 24
Finished Jun 23 06:41:40 PM PDT 24
Peak memory 249260 kb
Host smart-dd8355d6-8a13-461e-9817-e97cafd99273
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3152200584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3152200584
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3078436622
Short name T47
Test name
Test status
Simulation time 32249599528 ps
CPU time 2030.96 seconds
Started Jun 23 06:41:35 PM PDT 24
Finished Jun 23 07:15:26 PM PDT 24
Peak memory 286080 kb
Host smart-8d4c2da4-99b2-44e5-8cf6-7850bfb94c8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078436622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3078436622
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2426612273
Short name T353
Test name
Test status
Simulation time 359867640 ps
CPU time 17.01 seconds
Started Jun 23 06:41:35 PM PDT 24
Finished Jun 23 06:41:52 PM PDT 24
Peak memory 240932 kb
Host smart-cb412745-3639-4b93-b728-59bf726ce458
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2426612273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2426612273
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.325299403
Short name T499
Test name
Test status
Simulation time 1983399228 ps
CPU time 41.04 seconds
Started Jun 23 06:41:31 PM PDT 24
Finished Jun 23 06:42:13 PM PDT 24
Peak memory 256644 kb
Host smart-fcec3ba0-e299-4f8d-a486-6e150b68fd90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32529
9403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.325299403
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3442511382
Short name T221
Test name
Test status
Simulation time 860798415 ps
CPU time 58.94 seconds
Started Jun 23 06:41:32 PM PDT 24
Finished Jun 23 06:42:32 PM PDT 24
Peak memory 249356 kb
Host smart-e3de781e-2915-42a2-ad17-d2b7b47a1050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34425
11382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3442511382
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2385483752
Short name T683
Test name
Test status
Simulation time 39233811596 ps
CPU time 879.15 seconds
Started Jun 23 06:41:34 PM PDT 24
Finished Jun 23 06:56:13 PM PDT 24
Peak memory 273200 kb
Host smart-b182e50f-6f6b-4da7-aa6f-1e890ae0a76b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385483752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2385483752
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2949212281
Short name T371
Test name
Test status
Simulation time 10704073409 ps
CPU time 1053.75 seconds
Started Jun 23 06:41:35 PM PDT 24
Finished Jun 23 06:59:09 PM PDT 24
Peak memory 273372 kb
Host smart-013eaa22-0211-4c85-bc1c-14aa84346dd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949212281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2949212281
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3508509180
Short name T228
Test name
Test status
Simulation time 712796812 ps
CPU time 12.69 seconds
Started Jun 23 06:41:33 PM PDT 24
Finished Jun 23 06:41:46 PM PDT 24
Peak memory 253612 kb
Host smart-678a5462-92f1-4450-82e9-ce3015828669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35085
09180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3508509180
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2714165328
Short name T474
Test name
Test status
Simulation time 303697352 ps
CPU time 20.64 seconds
Started Jun 23 06:41:30 PM PDT 24
Finished Jun 23 06:41:51 PM PDT 24
Peak memory 249068 kb
Host smart-3bca7306-80fa-48b8-9782-27da56cc5502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27141
65328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2714165328
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.244156248
Short name T297
Test name
Test status
Simulation time 713409125 ps
CPU time 20.01 seconds
Started Jun 23 06:41:34 PM PDT 24
Finished Jun 23 06:41:55 PM PDT 24
Peak memory 249028 kb
Host smart-28d0b3a6-95a0-4883-a3d9-1434df7095d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24415
6248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.244156248
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.583873481
Short name T482
Test name
Test status
Simulation time 896598231 ps
CPU time 19.55 seconds
Started Jun 23 06:41:32 PM PDT 24
Finished Jun 23 06:41:52 PM PDT 24
Peak memory 249116 kb
Host smart-4a9ac204-187c-47f8-bf11-c966b3fcbd8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58387
3481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.583873481
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1484260465
Short name T77
Test name
Test status
Simulation time 3334435276 ps
CPU time 274.24 seconds
Started Jun 23 06:41:35 PM PDT 24
Finished Jun 23 06:46:10 PM PDT 24
Peak memory 265580 kb
Host smart-1de6a3b8-e615-4bef-aad7-afa15491e2ef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484260465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1484260465
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.4002445831
Short name T579
Test name
Test status
Simulation time 44916365451 ps
CPU time 2507.17 seconds
Started Jun 23 06:41:38 PM PDT 24
Finished Jun 23 07:23:25 PM PDT 24
Peak memory 323032 kb
Host smart-5f20df21-8721-407c-8a73-03fe85ad4efd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002445831 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.4002445831
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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