Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	58647	1			T2	4008		T4	1828		T13	156
class_i[0x1]	53574	1			T4	3		T14	26		T25	175
class_i[0x2]	49970	1			T1	2146		T2	6		T13	11
class_i[0x3]	43714	1			T2	1		T4	1577		T13	86

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	52037	1			T1	1133		T2	928		T4	1252
alert[0x1]	48649	1			T1	355		T2	1107		T4	438
alert[0x2]	49871	1			T1	658		T2	1014		T4	516
alert[0x3]	55348	1			T2	966		T4	1202		T13	114

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

205652

1

T1

2146

T2

4015

T4

3408

esc_ping_fail

253

1

T7

4

T8

10

T9

5

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	51962	1			T1	1133		T2	928		T4	1252
esc_integrity_fail	alert[0x1]	48582	1			T1	355		T2	1107		T4	438
esc_integrity_fail	alert[0x2]	49807	1			T1	658		T2	1014		T4	516
esc_integrity_fail	alert[0x3]	55301	1			T2	966		T4	1202		T13	114
esc_ping_fail	alert[0x0]	75	1			T8	4		T9	2		T297	2
esc_ping_fail	alert[0x1]	67	1			T7	1		T8	2		T297	2
esc_ping_fail	alert[0x2]	64	1			T7	2		T8	1		T9	2
esc_ping_fail	alert[0x3]	47	1			T7	1		T8	3		T9	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	58589	1			T2	4008		T4	1828		T13	156
esc_integrity_fail	class_i[0x1]	53489	1			T4	3		T14	26		T25	175
esc_integrity_fail	class_i[0x2]	49919	1			T1	2146		T2	6		T13	11
esc_integrity_fail	class_i[0x3]	43655	1			T2	1		T4	1577		T13	86
esc_ping_fail	class_i[0x0]	58	1			T8	1		T297	7		T92	1
esc_ping_fail	class_i[0x1]	85	1			T7	4		T9	5		T92	2
esc_ping_fail	class_i[0x2]	51	1			T8	9		T320	1		T303	3
esc_ping_fail	class_i[0x3]	59	1			T297	1		T230	3		T231	8