Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	659886278	0	0	625
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	659886278	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	659886278	659724741	0	0
tb.dut.CheckAccuCntDw	0	0	625	625	0	0
tb.dut.CheckEscCntDw	0	0	625	625	0	0
tb.dut.CheckNAlerts	0	0	625	625	0	0
tb.dut.CheckNClasses	0	0	625	625	0	0
tb.dut.CheckNEscSev	0	0	625	625	0	0
tb.dut.CrashdumpKnownO_A	0	0	659886278	659724741	0	0
tb.dut.EdnKnownO_A	0	0	659886278	659724741	0	0
tb.dut.EscPKnownO_A	0	0	659886278	659724741	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	659886278	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	659886278	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	659886278	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	659886278	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	659886278	70	0	0
tb.dut.IrqAKnownO_A	0	0	659886278	659724741	0	0
tb.dut.IrqBKnownO_A	0	0	659886278	659724741	0	0
tb.dut.IrqCKnownO_A	0	0	659886278	659724741	0	0
tb.dut.IrqDKnownO_A	0	0	659886278	659724741	0	0
tb.dut.TlAReadyKnownO_A	0	0	659886278	659724741	0	0
tb.dut.TlDValidKnownO_A	0	0	659886278	659724741	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	683847747	3053617	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	683847747	14491	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	683847747	14746	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	683847747	14585	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	683847747	14785	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	683847747	14557	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	683847747	14468	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	683847747	14743	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	683847747	14749	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	683847747	14959	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	683847747	14746	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	683847747	14721	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	683847747	14533	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	683847747	15093	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	683847747	14603	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	683847747	14733	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	683847747	14730	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	683847747	14666	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	683847747	14791	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	683847747	14719	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	683847747	15052	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	683847747	14535	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	683847747	14719	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	683847747	14753	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	683847747	14722	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	683847747	14668	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	683847747	14739	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	683847747	15048	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	683847747	14774	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	683847747	14434	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	683847747	14825	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	683847747	14740	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	683847747	15001	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	683847747	14781	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	683847747	14690	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	683847747	14704	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	683847747	14482	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	683847747	14482	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	683847747	14795	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	683847747	14776	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	683847747	14300	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	683847747	14625	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	683847747	14634	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	683847747	14620	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	683847747	14529	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	683847747	14820	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	683847747	14746	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	683847747	14635	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	683847747	15026	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	683847747	14625	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	683847747	14916	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	683847747	14940	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	683847747	14806	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	683847747	14659	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	683847747	14968	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	683847747	14616	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	683847747	14560	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	683847747	14873	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	683847747	14794	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	683847747	14974	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	683847747	14577	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	683847747	14858	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	683847747	14861	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	683847747	14728	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	683847747	14518	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	683847747	14663	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	683847747	14683	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	683847747	14414	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	683847747	14959	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	683847747	14609	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	683847747	26405	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	683847747	14880	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	683847747	14526	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	683847747	14833	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	683847747	14785	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	683847747	14899	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	683847747	14763	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	683847747	14798	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	683847747	14680	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	659886278	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	659886278	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	659886278	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	659886278	4780	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	659886278	213431	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	659886278	338777771	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	659886278	225	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	659886278	911	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	659886278	48	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	659886278	455	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	659742880	242527431	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	659886278	1013	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	659886278	993	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	659886278	974	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	659886278	946	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	659886278	1053	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	659886278	132993	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	659886278	932	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	659886278	70	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	659886278	1269	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	659886278	1059	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	659741468	659669365	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	659886278	659724741	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	659886278	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	659886278	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	659886278	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	659886278	2702	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	659886278	228235	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	659886278	328783776	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	659886278	277	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	659886278	537	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	659886278	24	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	659886278	253	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	659742880	270866877	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	659886278	616	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	659886278	597	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	659886278	585	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	659886278	570	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	659886278	1209	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	659886278	149003	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	659886278	1114	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	659886278	69	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	659886278	1260	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	659886278	1050	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	659741468	659669365	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	659886278	659724741	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	659886278	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	659886278	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	659886278	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	659886278	2051	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	659886278	202248	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	659886278	389969752	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	659886278	204	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	659886278	517	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	659886278	24	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	659886278	231	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	659742880	317814401	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	659886278	580	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	659886278	571	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	659886278	560	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	659886278	552	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	659886278	670	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	659886278	86900	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	659886278	597	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	659886278	49	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	659886278	1220	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	659886278	1010	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	659741468	659669365	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	659886278	659724741	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	659886278	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	659886278	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	659886278	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	659886278	4467	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	659886278	190945	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	659886278	351049982	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	659886278	231	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	659886278	497	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	659886278	24	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	659886278	234	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	659742880	285749098	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	659886278	576	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	659886278	559	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	659886278	545	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	659886278	528	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	659886278	989	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	659886278	121546	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	659886278	893	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	659886278	69	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	659886278	1245	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	659886278	1035	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	659741468	659669365	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	659886278	659724741	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	683847747	128893502	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	683847747	683154023	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	683847747	683154023	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	683847747	176520740	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	683847747	683154023	0	0
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tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	830	830	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	830	830	0	0

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