Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	3	41	93.18

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	3	41	93.18	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	170	1			T21	1		T14	1		T66	1
index[0x1]	182	1			T2	3		T13	1		T15	1
index[0x2]	217	1			T1	1		T4	2		T22	3
index[0x3]	161	1			T1	1		T20	1		T13	4

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	229	1			T4	1		T21	1		T13	2
lens_less_than_1000[1]	115	1			T1	2		T2	3		T15	1
lens_less_than_1000[2]	96	1			T4	1		T13	1		T22	1
lens_less_than_1000[3]	66	1			T70	2		T75	1		T101	1
lens_less_than_1000[4]	83	1			T14	1		T94	1		T47	1
lens_less_than_1000[5]	60	1			T13	1		T46	2		T33	8
lens_less_than_1000[6]	44	1			T13	1		T107	2		T109	1
lens_less_than_1000[7]	21	1			T73	1		T246	1		T28	1
lens_less_than_1000[8]	9	1			T247	1		T248	1		T249	1
lens_less_than_1000[9]	2	1			T29	1		T84	1		-	-
len_2	5	1			T20	1		T97	1		T250	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	3	41	93.18	3

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[9]]	0	1	1
[index[0x2]]	[len_2]	0	1	1
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	66	1			T21	1		T68	1		T251	1
index[0x0]	lens_less_than_1000[1]	26	1			T38	1		T252	1		T253	1
index[0x0]	lens_less_than_1000[2]	23	1			T66	1		T47	1		T92	1
index[0x0]	lens_less_than_1000[3]	13	1			T93	1		T56	2		T99	1
index[0x0]	lens_less_than_1000[4]	15	1			T14	1		T230	1		T41	1
index[0x0]	lens_less_than_1000[5]	14	1			T56	5		T254	1		T99	2
index[0x0]	lens_less_than_1000[6]	6	1			T107	1		T255	1		T236	1
index[0x0]	lens_less_than_1000[7]	2	1			T60	1		T256	1		-	-
index[0x0]	lens_less_than_1000[8]	3	1			T248	1		T249	1		T257	1
index[0x0]	len_2	2	1			T250	1		T258	1		-	-
index[0x1]	lens_less_than_1000[0]	42	1			T47	1		T259	1		T55	1
index[0x1]	lens_less_than_1000[1]	34	1			T2	3		T15	1		T260	1
index[0x1]	lens_less_than_1000[2]	29	1			T43	1		T51	1		T261	1
index[0x1]	lens_less_than_1000[3]	18	1			T70	1		T262	1		T26	1
index[0x1]	lens_less_than_1000[4]	24	1			T33	1		T32	6		T56	1
index[0x1]	lens_less_than_1000[5]	12	1			T33	1		T43	1		T263	1
index[0x1]	lens_less_than_1000[6]	12	1			T13	1		T109	1		T123	1
index[0x1]	lens_less_than_1000[7]	6	1			T28	1		T264	1		T258	4
index[0x1]	lens_less_than_1000[8]	3	1			T265	1		T266	1		T267	1
index[0x1]	lens_less_than_1000[9]	1	1			T29	1		-	-		-	-
index[0x1]	len_2	1	1			T97	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	73	1			T4	1		T22	2		T25	1
index[0x2]	lens_less_than_1000[1]	36	1			T1	1		T25	1		T92	1
index[0x2]	lens_less_than_1000[2]	18	1			T4	1		T22	1		T110	1
index[0x2]	lens_less_than_1000[3]	18	1			T70	1		T92	1		T51	1
index[0x2]	lens_less_than_1000[4]	33	1			T47	1		T29	1		T268	1
index[0x2]	lens_less_than_1000[5]	19	1			T46	2		T33	7		T260	1
index[0x2]	lens_less_than_1000[6]	12	1			T86	1		T26	1		T248	3
index[0x2]	lens_less_than_1000[7]	5	1			T73	1		T89	1		T113	1
index[0x2]	lens_less_than_1000[8]	2	1			T247	1		T269	1		-	-
index[0x2]	lens_less_than_1000[9]	1	1			T84	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	48	1			T13	2		T22	1		T14	1
index[0x3]	lens_less_than_1000[1]	19	1			T1	1		T42	1		T270	1
index[0x3]	lens_less_than_1000[2]	26	1			T13	1		T14	1		T68	2
index[0x3]	lens_less_than_1000[3]	17	1			T75	1		T101	1		T26	1
index[0x3]	lens_less_than_1000[4]	11	1			T94	1		T41	1		T48	1
index[0x3]	lens_less_than_1000[5]	15	1			T13	1		T271	1		T53	1
index[0x3]	lens_less_than_1000[6]	14	1			T107	1		T87	1		T26	1
index[0x3]	lens_less_than_1000[7]	8	1			T246	1		T272	1		T273	1
index[0x3]	lens_less_than_1000[8]	1	1			T258	1		-	-		-	-
index[0x3]	len_2	2	1			T20	1		T266	1		-	-